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Si 5 3 1 5 - EVB
SI5315-EVB USER 'S G UIDE
Description
The Si5315 Evaluation Board User's Guide provides for a complete and simple evaluation of the functions, features, and performance of the SI5315-EVB. The Si5315 Synchronous Ethernet/Telecom jitter attenuating clock multiplier has a comprehensive feature set, including any-rate frequency synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input clocks, and programmable output clock signal format (LVPECL, LVDS, CML, CMOS). For more details, consult the Silicon Labs timing products website at: www.silabs.com/timing. TheSI5315-EVB has two differential clock input and output ports that are AC terminated to 50 ohms and then AC coupled to the Si5315. The XA-XB reference is usually a 40 MHz crystal; however, there are provisions for an external XA-XB reference clock (either differential or single ended). The evaluation board (EVB) can be powered using two different approaches: external power supplies or by USB. Jumper plugs are provided to select between these two options. Jumper plugs are used to strap the device pins for the various pin value options. Status outputs are available on a ribbon connector header. SMA connectors are used for the clock input, output, and XA-XB reference signals.
Features
The SI5315-EVB includes the following:

Evaluation board
CD with the Si5315 documentation and the Si5315EVB User's Guide
Function Block Diagram
Ext RefClk
Input SMAs
Terminate
CKOUT1
Output SMAs
Si5315
CKOUT2
USB
+3.3V Vreg
LEDs
+3.3V DUT PWR
1.8V to 3.3V
LED power To DUT Jumper Headers Control signals status signals
Rev. 0.2 6/09
Copyright (c) 2009 by Silicon Laboratories
SI5315-EVB
SI5315-EVB
1. Introduction
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL(R) technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level. Refer to the Si5315 data sheet for technical details of the device.
Front
Figure 1. Si5315 EVB
Back
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Preliminary Rev. 0.2
SI5315-EVB
2. Si53315-EVB Input and Output Clocks
Refer to the schematics, diagrams, and tables while reading this section.
2.1. Input Clocks
The Si5315 has two differential clock inputs that are AC terminated and AC coupled before being presented to the Si5315. If the input clock frequencies are low (below 1 MHz), there are extra considerations that should be taken into account. The Si5315 has a maximum clock input rise time specification of 11 ns that must be met (see CKNtrf in the Si5315 data sheet). Also, if the input clock is LVCMOS, it might be advantageous to replace the input coupling capacitors (C7, C12, C16, and C18) with zero ohm resistors. Regardless of the input format, if the clock inputs are not roughly 50% duty cycle, it is highly recommended to avoid AC coupling. For input clocks that are far off of 50% duty cycle, the average value of the signal that passes through the coupling capacitor will be significantly off of the midpoint between the maximum and minimum value of the clock signal, resulting in a mismatch with the common mode input threshold voltage (see VICM in Table 2 of the Si5315 data sheet).
2.2. XA-XB Reference
To achieve very low jitter generation and for stability during holdover, the Si5315 requires a stable, low jitter reference at its XA-XB pins. To that end, the EVB is configured with a 40 MHz fundamental mode crystal connected between pins 6 and 7 of the Si5315. However, the SI5315-EVB is capable of using an external XA-XB reference oscillator, either differential or single ended. J1 and J2 are the SMA connectors with AC termination. AC coupling is also provided that needs to be installed at C6 and C8. Table 1 explains the changes of components that are needed to implement an external XA-XB reference oscillator.
Table 1. XA-XB Reference Mode of Operation
Mode Xtal Ext Ref In+ Ext Ref InC6, C8 R8 XTAL/CLOCK (J12 jumper, see Table 3.)
Notes: 1. Xtal is 40 MHz. 2. NC - no connect. 3. NOPOP - do not install.
Ext Ref J1 J2 install NOPOP M
NC NC NOPOP install L
2.3. Output Clocks
The clock outputs are AC coupled and are available on SMA's J5, J7, J9, and J11. For LVCMOS outputs, it might be desirable to replace the AC coupling capacitors (C9, C14, C17, and C 20) with zero ohm resistors. Also, if greater drive strength is desired for LVCMOS outputs, R6 and R10 can be installed.
Preliminary Rev. 0.2
3
SI5315-EVB
2.4. Pin Configuration
J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the Si5315. Each pin can be strapped to be either H, M or L. H is achieved by installing a jumper plug between the appropriate middle row pin and its VDD row pin. L is achieved by installing a jumper plug between the appropriate middle row pin and its GND row pin. M is achieved by not installing a jumper plug.
2.5. Evaluation Board Power Options
The EVB can be powered from two possible sources: USB or external supplies. A 3.3 V supply is required to run the LEDs because of their large forward drop. The Si5315 power supply can be separated from the 3.3 V supply so that the Si5315 can be evaluated at voltages other than 3.3 V. It is important to note that when the USB supply is being used, the EVB uses the USB port only for power and that the resulting power supply is strictly 3.3 V. Here are the instructions for the various possibilities: 2.5.1. Two External Power Supplies 1. Install a jumper between J16.1 and J16.2 (labeled EXT). 2. No USB connection. 3. If the Si5315 is not being operated at 3.3 V, two different supplies should be connected to J14. Connect the 3.3 V supply to J14.1 and J14.2 (labeled 3.3 V and GND). Connect the SI5315 power supply between J14.2 and J14.3 (labeled GND and DUT). 4. If the Si5315 is to be operated at 3.3 V, J15 (labeled ONE PWR) can be installed, requiring only one external supply. Connect 3.3 V power between J14.2 and J14.3 (labeled GND and DUT). 2.5.2. USB Power 1. With a USB cable, plug the EVB into a powered USB port. 2. Install a jumper between J16.2 and J16.3 (labeled USB). 3. Install a jumper at J15 (labeled ONE PWR). 2.5.3. USB 3.3 V Power, External Si5315 Power 1. Install a jumper between J16.2 and J16.3 (labeled USB). 2. No jumper at J15 (labeled ONE PWR). 3. Connect the Si5315 power supply between J14.2 and J14.3 (labeled GND and DUT).
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SI5315-EVB
3. Connectors and LEDs
3.1. LEDs
Table 2. LED Descriptions
LED D1 D2 D3 D4 D5 D6 Color Yellow Red Red Red Green Green Label CS_CA LOS2 LOS1 LOL DUT_PWR 3.3V Significance ON = clock input 2 selected, else clock 1 ON = no valid clock input 2 ON = no valid clock input 1 ON = Si5315 is not locked ON = Si5315 power is present ON = 3.3V power is present
3.2. Connectors, Headers, and Jumpers
Refer to Figure 2 to locate the items described in this section.
C7, C12, C16, C18
J12
R8 U1, Si5315
J16 J13 J15
Figure 2. Connectors, Headers, and Jumper Locations
Preliminary Rev. 0.2
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SI5315-EVB
Table 3. Configuration Header, J12
J12 J12.1 J12.2 J12.3 J12.4 J12.5 J12.6 J12.7 J12.8 J12.9 J12.10 J12.11 J12.12 J12.13 J12.14 Pin Not used* SFOUT0 SFOUT1 FRQTBL FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 BWSEL0 BSWEL1 DBL2_BY AUTOSEL XTAL/CLOCK Not used*
*Note: Unused header pin locations should be left open.
Table 4. Status Indication Header, J13
J13 J13.1 J13.3 J13.5 J13.7 J13.9 Signal LOS1 LOS2 CS_CA LOL RST_B
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Preliminary Rev. 0.2
Ext Ref In +
DUT_PWR L1 NOPOP 100 R1 Ferrite R2 0 ohm R3 49.9 C1 10NF 49.9 C3 10NF C6 10NF NOPOP C8 10NF NOPOP C9 100N J5 SMA_EDGE 1 C4 100N C5 1UF R5 C2 10NF FILT_DUT_PWR 49.9 R4 J3 NOPOP
J1 SMA_EDGE 1
2
3
1
2
to measure DUT supply
Ext Ref In 1 2
J2 SMA_EDGE 1
2
3
4. Schematics
to power plane
CKIN1+
100N C7
J4 SMA_EDGE 1
2
3
CKOUT1+
3
NOPOP C10 100N 0 ohm 100N C12 100N C14 X1 C13 10NF R8 49.9 R7 R6 0 ohm C11 100N
CKIN1-
J6 SMA_EDGE 1
2
3
40 MHz for SI5315-EVB
2
J7 SMA_EDGE 1
CKOUT13 2
15
11
Rate1
Rate0
2
3
6 7 XA XB CKIN1+ CKIN1CKIN_2+ CKIN_2CKOUT1+ CKOUT128 29 35 34 16 17 12 13
VDD1 VDD2 VDD3
CKIN2+
100N C16
J8 SMA_EDGE 1 49.9 R9 C15
2 GND
114.285 MHz
4
5 10 32
1
3
10NF
install for CMOS outputs
C17 100N NOPOP R10 0 ohm J9 SMA_EDGE 1
NOPOP for Si5317-EVB
100N C18 C19 10NF 49.9 R11 NOPOP R12 0 ohm U1
CKOUT2+
3 2
CKIN2-
J10 SMA_EDGE 1
2
3
NOPOP for Si5317-EVB
J11 SMA_EDGE 1
3
NOPOP for Si5317-EVB
C20 100N
14C
RATE1 RATE0 AUTOSEL
0 ohm
R13
13C 9 AUTOSEL
12C
DBL2_BY BWSEL1 BWSEL0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 FRQTBL SFOUT1 DUT_PWR SFOUT0 TP1
NOPOP for SI5315-EVB
2
J12
Si5315/17
30 SFOUT1 SFOUT0 14 DBL2_BY BWSEL1 BWSEL0 23 22 LOS1 LOS2 33 3 4
CKOUT2+ CKOUT2-
CKOUT2-
LOS2 LOS1 10_M_Header
11C
1C
DUT_PWR R15 10k R14 10
14x3_M_HDR_THRU
TP2
2 1
SI5315-EVB
Figure 3. Si5315/17-EVB
8 31 20 19 37
14A 14B 13A 13B 12A 12B 11A 11B 10A 10B 9A 9B 8A 8B 7A 7B 6A 6B 5A 5B 4A 4B 3A 3B 2A 2B 1A 1B 27 26 25 24 2 36 2 1 1 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 FRQTBL GND1 GND2 GND3 GND4 GND5 NC RST
Preliminary Rev. 0.2
CS_CA 21 LOL 18
10C
9C
Jumper Plugs
8C
LOS1 LOS2 CS_CA LOL RST_B
1 3 5 7 9
J13
2 4 6 8 10
Status
7C
6C
5C
CS_CA
4C
3C
LOL
2C
7
1
1
1
DUT_PWR + C21 220UF C22 1UF
EVB main power
mounting holes
Single 3.3V supply
J14
J15
SI5315-EVB
DUT_PWR
3
GND
U2 FAN1540B
1 2
2 1 1 2 3 NC1 VOUT PAD VIN GND NC3 NC2 7
USB_3P3V J16
Power Source Selection
6 5 4 2
3.3V
* * *
Ferrite
1
Phoenix_3_screw
PHOENIX_3P3V
1
S2
S1
6
RAW_3P3V
LED_PWR
150 A CS_CA Q1 CS_CA
R17
Yel 2C
D1 1
3
1 2
BSS138 Red Q2
150
R18
1C
A D2
2
LOS2
3
LOS2
1 2
BSS138 Red
1C
A D3
2
LOS1
5
3
2
Q4 LOL
3
2
DUT_PWR
Q5
1
R20 10k
2
BSS138
3
8
DUT Power
H1 #4 #4 #4 #4 H2 H3 H4 DUT_PWR
USB power
+ C23 33UF
3
L2 1
2
J17 USB
V3P3 VBUS +
C25 1UF
C24 220UF +
2 DD+ Gnd 4 V 3
0 ohm R16
1
C26 33UF
1
J18
Preliminary Rev. 0.2
1C
Red A D4
2
LOL
ground pins
1 1 1
J19 J20 J21
Q3
1 2 3 4 2
C Grn D5 A
8 7 6 5 1
DUT_PWR R150x4 R19
1 1 1
J22 J23 J24
LOS1 BSS138
1
2
C D6 Grn
A
1
3.3V
1 1
J25 J26
1
BSS138
Figure 4. Power and LED
SI5315-EVB
5. Bill of Materials
Table 5. SI5315-EVB Bill of Materials
Item 1 2 3 5 6 7 8 9 11 13 14 15 16 17 18 19 20 21 23 24 26 27 28 29 31 Qty 6 11 3 2 2 1 3 2 10 1 1 1 1 1 1 9 2 5 4 6 1 2 2 1 1 Reference C1,C2,C3,C13,C15,C19 C4,C7,C9,C10,C11,C12,C14, C16,C17,C18,C20 C5,C22,C25 C21,C24 C23,C26 D1 D2,D3,D4 D5,D6 J1,J2,J4,J5,J6,J7, J8,J9,J10,J11 J12 J13 J14 J15 J16 J17 J18,J19,J20,J21, J22,J23,J24,J25,J26 L1,L2 Q1,Q2,Q3,Q4,Q5 R2,R8,R12,R16 R3,R4,R5,R7,R9,R11 R14 R15,R20 R17,R18 R19 U1 Part 10NF 100N 1UF 220UF 33UF Yel Red Grn SMA_EDGE 14x3_M_HDR_THRU 10_M_Header Phoenix_3_screw Jmpr_2pin Jmpr_3pin USB Jmpr_1pin Ferrite BSS138 0 ohm 49.9 10 10k 150 R150x4 Si5315 Venkel On Semi Venkel Venkel Venkel Venkel Venkel Panasonic Silicon Labs FBC1206-471H BSS138LT1G CR0603-16W-000T CR0603-16W-49R9FT CR0603-16W-10R0FT CR603-16W-1002FT CR0603-16W-1500FT EXB-38V151JV Si5315A-C-GM FCI 61729-0010BLF Mfr Venkel Venkel Venkel Kemet Venkel Panasonic Lumex Panasonic Johnson -- 3M Phoenix N2510-6002RB MKDSN 1.5/3-5.08 Manufacturer Part No. C0603X7R160-103KNE C0603X7R160-104KNE C0603X7R6R3-105KNE T494B227M004AT TA006TCM336MBR LN1471YTR LN1271RAL LN1371G 142-0701-801
Preliminary Rev. 0.2
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SI5315-EVB
Table 5. SI5315-EVB Bill of Materials
Item 32 33 Qty 1 1 Reference U2 X1 Part FAN1540B 40 MHz Not Populated 4 12 22 25 2 1 1 3 C6,C8 J3 R1 R6,R10,R13 10NF Jmpr_2pin 100 0 ohm Venkel Venkel CR0603-16W-1000FT CR0603-16W-000T Venkel C0603X7R160-103KNE Mfr Fairchild Abracon Manufacturer Part No. FAN1540BPMX ABM8-40.000 MHz-BZT
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Preliminary Rev. 0.2
SI5315-EVB
6. Layout
Figure 5. Silkscreen Top
Preliminary Rev. 0.2
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SI5315-EVB
Figure 6. Layer 1
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Preliminary Rev. 0.2
SI5315-EVB
Figure 7. Layer 2--Ground Plane
Preliminary Rev. 0.2
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SI5315-EVB
Figure 8. Layer 3
14
Preliminary Rev. 0.2
SI5315-EVB
Figure 9. Layer 4
Preliminary Rev. 0.2
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SI5315-EVB
Figure 10. Layer 5, FILT_DUT_PWR
16
Preliminary Rev. 0.2
SI5315-EVB
Figure 11. Layer 6, Bottom
Preliminary Rev. 0.2
17
SI5315-EVB
Figure 12. Bottom Silkscreen
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Preliminary Rev. 0.2
SI5315-EVB
7. Factory Default Configuration
Table 6. Factory Default Jumper Settings
J12 J12.1 J12.2 J12.3 J12.4 J12.5 J12.6 J12.7 J12.8 J12.9 J12.10 J12.11 J12.12 J12.13 J12.14 Pin Not used SFOUT0 SFOUT1 FRQTBL FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 BWSEL0 BSWEL1 DBL2_BY AUTOSEL XTAL/CLOCK Not used Jumper -- H M H L H M L H H L H L --
The jumper settings in Table 6 result in the following: SFOUT = LVPECL outputs 19.44 MHz input clocks 155.52 MHz output clocks BW = 112 Hz DBL2_BY = CKOUT2 enabled AUTOSEL = automatic revertive clock selection XTAL/CLOCK = 40 MHz crystal Refer to Table 7 in the Si5315 Data Sheet for other frequency plans. The factory configuration for the board is to use only USB power by using the following jumper configuration: Jumper between J16.2 and J16.3 (labeled PWR, USB) Jumper installed on J15 (labeled ONE POWER)
Preliminary Rev. 0.2
19
SI5315-EVB
NOTES:
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Preliminary Rev. 0.2
SI5315-EVB
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Removed SI5315-EVB from Appendix of Si5315EVB, Si5316-EVB, Si5319-EVB, Si532/23-EVB, Si5325/26-EVB with SI5315-EVB Appendix B User's Guide Revised Revision 0.2 as a stand-alone SI5315-EVB User's Guide
Preliminary Rev. 0.2
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SI5315-EVB
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.2

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