View XR-T5684IJ_389173.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

XR-T5684
...the analog plus company TM
Low Power T1 Analog Interface
June 1997-3
FEATURES D Fully Integrated T1 Transceiver D Low Power Consumption (normally 225mW) D Recovered Data and Clock Outputs D Driver Performance Monitor D Internal Transmit LBO for Line Lengths Between 0 to 655 Feet D Compliance with TR-TSY-000499, 43802 and 43801 Input Jitter Tolerance Specifications
APPLICATIONS D Interfacing T1 Network Equipment such as Multiplexers, Channel Banks and DSX-1 Switching Systems D Interfacing Customer Premises Equipment such as CSUs, PBXs, T1 Measurement and Test Equipment
GENERAL DESCRIPTION The XR-T5684 is a fully integrated PCM line transceiver intended for DSX-1 digital cross-connect applications. It combines both transmit and receive circuitry in a 28 pin PLCC or PDIP package. The receiver extracts data from AMI coded input signal, and outputs synchronized clock and unipolar RPOS and RNEG data by means of an external 8X or 16X oversampling clock. The oversampling clock is necessary only for applications where the clock recovery feature is required. The transmitter of the device pre-shapes the transmit pulse internally, providing the appropriate pulse shape at the cross-connect for line lengths ranging from 0 to 655 feet. The XR-T5684 is manufactured using advanced CMOS technology and requires only a single +5V power supply.
ORDERING INFORMATION
Operating Temperature Range -40 to + 85C -40 to + 85C
Part No. XR-T5684IJ XR-T5684IP
Package
28 Lead PLCC 28 Lead 600 Mil PDIP
Rev. 1.01
E1997
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-T5684
BLOCK DIAGRAM
12 LOS Loss of Signal Detection
Data Comparators + - 19 RTIP 20 RRING Peak Det. + - Data Retiming Circuit 7 RNEG 6 RPOS
Clock Recovery
8
RCLK
1 LCLK MODE PD CLKDIS RVDD RGND 5 9 10 21 22 +5
Figure 1. XR-T5684 Receive Side
Rev 1.01 2
XR-T5684
2 TCLK TPOS TNEG 4 3 Transmit Control Logic Output Pulse Shaper Output Driver
13 TTIIP 16 TRING
26 TEST TAOS LEN0 LEN1 LEN2 25 23 24 28
17 MTIP MRING TVDD GND NC 18 15 14 27
Driver Performance Monitor +5
11 DPM
Figure 2. XR-T5684 Transmit Side
Rev. 1.01 3
XR-T5684
PIN CONFIGURATION
TNEG TPOS TCLK TAOS LCLK TSET N/C
4
3
2
1
28
27
26
MODE RPOS RNEG RCLK PD CLKDS DPM
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23 22 21 20 19
LEN2 LEN1 LEN0 RGND RVDD RRING RTIP
LCLK TCLK TPOS TNEG MODE RPOS RNEG RCLK PD CLKDS DPM LOS TTIP TGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
TAOS N/C TEST LEN2 LEN1 LEN0 RGND RVDD RRING RTIP MRING MTIP TRING TVDD
28 Lead PLCC
MRNG
TGND
TRNG
TVDD
MTIP
TTIP
LOS
28 Lead PDIP (0.600")
PIN DESCRIPTION
Pin # 1 2 3 4 5 Symbol LCLK TCLK TPOS TNEG MODE Type I I I I I Description Oversampling Clock. 8X or 16X input clock for receive clock recovery circuit. 8X=12.352MHz200ppm with pin 9 set to low. 16X=24.704MHz 200ppm with pin 9 set to high. Transmit Clock. T1=1.544MHz50ppm. Transmit Positive Data. A positive NRZ data on this pin causes a positive pulse to be transmitted on TTIP. TPOS is sampled on the falling edge of TCLK. Transmit Negative Data. A positive NRZ data on this pin causes a negative pulse to be transmitted on TRING. TNEG is sampled on the falling edge of TCLK. Receive Output Data Select. With this pin set to high, the extracted data at RPOS and RNEG are re-timed using the recovered clock RCLK. With this pin set to low, the received data have no relation to RCLK and are typically stretched by 80nS before being sent to the output. This pin is pulled down internally. Receive Positive Data Output. A positive pulse on this pin corresponds to a positive pulse on RTIP. Receive Negative Data Output. A positive pulse on this pin corresponds to a positive pulse on RRING. Receive Clock Output. Recovered clock using oversampling clock applied to pin 1. See MODE select of pin 5 and PD of pin 9. Programmable Divider. The state of this pin determines the oversampling clock applied to pin 1. When LCLK=16X1.544MHz, set PD to high. When LCLK=8X1.544MHz, set PD to low. This pin is pulled down internally. Clock Disable. With this pin set to high, the recovered clock at pin 8 is disabled. This function is provided for applications where upon input data loss, the output clock can be inhibited by connecting LOS to CLKDS externally. This pin is pulled down internally. Driver Performance Monitor. Used as an early warning signal on non-functioning T1 links. If no signal is present on MTIP and MRING for 63 clock cycles. DPM goes high until a next pulse is detected.
6 7 8 9
RPOS RNEG RCLK PD
O O O I
10
CLKDS
I
11
DPM
O
Rev 1.01 4
XR-T5684
PIN DESCRIPTION (CONT'D)
Pin # 12 Symbol LOS Type O Description Loss of Signal. This pin goes high either when the input signal at RTIP and RRING drops to below 0.4V peak or after 175 zeros are detected. The 175 zeros detection is active only when LCLK is applied. Transmit Positive Data. Transmit AMI signal is driven to the line via a step-up transformer from this pin. Transmitter Supply Ground. This pin can be connected to RGND externally. O O I I I I 5 V 5% Transmitter Supply. Transmit Negative Data. Transmit AMI signal is driven to the line via a step-up transformer from this pin. Driver Performance Monitor Input. This pin is normally connected to TTIP for monitoring the driver's activity. It is pulled high internally. Driver Performance Monitor Input. This pin is normally connected to TRING for monitoring the driver's activity. It is pulled high internally. Receive Tip Input. The AMI receive signal is input to this pin via a centre-tapped transformer. Receive Ring Input. The AMI receive signal is input to this pin via a centre-tapped transformer. 5 V 5% Receive Supply. This pin can be connected to TVDD externally. Receive Supply Ground. This pin is also connected to the substrate of the device. I I I I I Pulse Shaper Select Pin. Least significant bit. Pulse Shaper Select Pin. Second significant bit. Pulse Shaper Select Pin. Most significant bit. Factory Test Pin. This pin must be grounded for normal operation. No Connection Pin. This pin can be grounded or left floating. Transmit All Ones Select. Setting TAOS high causes continuous AMI ones to be transmitted to the line at the frequency set by TCLK.
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TTIP TGND TVDD TRING MTIP MRING RTIP RRING RVDD RGND LEN0 LEN1 LEN2 TEST N/C TAOS
O
Rev. 1.01 5
XR-T5684
ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test Conditions: TA = -40 to + 85_C, RVDD and TVDD = 5V 5%, RGND and TGND = 0V.
Min. Typ. Max. Unit Conditions DC ELECTRICAL CHARACTERISTICS Recommended Operating Conditions VDD/TVDD PD DC Supply Voltage Total Power Disapation 4.75 5 5.25 400 V mW 100% ones density & max. line length @ 5.25V and with 16X oversampling clock running. 50% ones density & 300 feet line length @5.0V and with over-sampling clock disabled.
PD
Normal Power Dissipation
225
mW
Inputs VIH VIL IIL Outputs VOH VOL VPA High Level Output2 Low Level Output2 2.4 3.0 2.4 0.4 3.6 V V V Measured at DSX-1 using a 1:1.36 step up transformer with all line length select as shown in Table 1. High Level Input1 Low Level Input1 Input Leakage Current 2.0 0.8
10
V V mA Pins = TCLK, TPOS, TNEG, LEN0/1/2.
Analog Specifications AMI Output Pulse Amplitudes
TXJA
Jitter added by the transmitter 10Hz - 40KHz3 Broad Band3 6 0.4 160 175 70 190 % of peak MHz 60 % MHz MHz 200 35 50 65 ppm % 0.025 0.05 UI UI dB V
RXS RLOS
Receiver Sensitivity Below DSX(0dB=2.4V) Receiver Loss of Signal Threshold Number of Consecutive Zeros before LOS
RTH
Receiver Data Slicing Threshold Clock Frequency TCLK Clock Duty Cycle 40 Frequency 8X 16X LCLK Clock Tolerance LCLK Clock Duty Cycle
AC CHARACTERISTICS TCLKf LCLKf LCLKf 1.544 50 12.352 24.704
Notes 1 All input pins except RTIP, RRING, MTIP and MRING. 2 All output pins except TTIP and TRING. 3 Input clock to TCLK is jitter free. 4 Pin 5 Set to low.
Rev 1.01 6
XR-T5684
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: TA = -40 to + 85_C, RVDD and TVDD = 5V 5%, RGND and TGND = 0V.
Symbol tsu tho tdr tdf Parameter TPOS/TNEG to TCLK Setup Time TCLK to TPOS/TNEG Hold Time RTIP/RRING Rising to RPOS/ RNEG Rising4 RTIP/RRING Falling to RPOS/ RNEG Falling4 RCLK Duty Cycle tsu tho RPOS/RNEG to RCLK Falling Setup Time RCLK Falling to RPOS/RNEG Hold Time Min. 25 25 15 60 30 120 50 300 324 120 250 Typ. Max. Unit ns ns ns ns % ns ns Conditions
Notes 1 All input pins except RTIP, RRING, MTIP and MRING. 2 All output pins except TTIP and TRING. 3 Input clock to TCLK is jitter free. 4 Pin 5 Set to low.
ABSOLUTE MAXIMUM RATINGS Supply Voltage (continuous) . . . . . . . . . . . . -0.5V, +7V Supply Current (continuous) . . . . . . . 20mA to -20mA Storage Temperature . . . . . . . . . . . . -65C to + 150C
Rev. 1.01 7
XR-T5684
SYSTEM DESCRIPTION The device consists of receiver and transmitter circuitry with separate power supplies to reduce crosstalk between the two sections. RECEIVER The receiver is sensitive to the entire cable length from the cross-connect and requires no external equalization networks. The receive AMI input signal is applied to RTIP and RRING through a center-grounded transformer. The positive pulse is input to RTIP and the negative pulse is input to RRING. Comparators are used to slice the data on RTIP and RRING. The slicing level of the comparators are dynamically set at around 70% of peak level of the input signal to ensure optimum signal-to-noise ratio. With Mode Select (pin 5) set to low, the clock recovery feature is bypassed and the output data from the comparators are typically stretched by 80nS before output to RPOS and RNEG respectively. A positive data at RPOS corresponds to a positive pulse received at RTIP and a positive data at RNEG corresponds to a positive pulse received at RRING. With Mode Select (pin 5) set to high and an oversampling clock applied to pin 1, the recovered data can be synchronized with RCLK at pin 8. The clock recovery circuit extracts the timing contents from the incoming data transitions by means of an 8X or 16X divider. If there is no data on the input, the divider operates in its free running mode, generating a equal mark-and-space ratio output clock. This free running mode will be interrupted if a positive pulse is detected; the resultant mark-and-space ratio of the output clock is then determined by the position of the occurrence of the positive data relative to its free running position. See timing diagram in Figure 3 and Figure 4. In all cases, the output data RPOS and RNEG remains stable on the falling edge of RCLK so as to be sampled correctly. The input jitter tolerance with an 8X oversampling clock is shown in Figure 6 and that with a 16X oversampling clock is shown in Figure 5.
8X OVERSAMPLING RTIP RRING 648nS RCLK RPOS RNEG
6 Clk Cycles
tsu
tho
6 Clk Cycles
Figure 3. Receiver Clock and Data Switching Characteristics
16 X OVERSAMPLING RTIP RRING RCLK 8 Clk Cycles RPOS RNEG tsu tho 8 Clk Cycles
Figure 4. Typical Receive Timing Diagram Using 8X Oversampling Clock.
Rev 1.01 8
XR-T5684
-20db / Decade Sinusodial Input Jitter Amplitude (PK-PK UI)
10 UI
TR-TSY-000499 Issue 2 Dec., 1988
10 UI
1.5 UI 0.6 UI 0.4 UI
0.3 UI 10 Hz 640 Hz 6430 Hz 20 KHz 40 KHz
Jitter Frequency
Figure 5. Typical Receive Timing Diagram Using 16X Oversampling Clock
-20db / Decade Sinusoidal Input Jitter Amplitude (PK-PK UI)
10 UI
TR-TSY-000499 Issue 2 Dec., 1988
10 UI
1.9 UI 0.7 UI 0.5 UI
0.3 UI 10 Hz 640 Hz 6430 Hz 20 KHz 40 KHz
Jitter Frequency
Figure 6. XR-T5684 Input Jitter Tolerance Using 8X Oversampling Clock
Rev. 1.01 9
XR-T5684
Another function of the receiver is the signal quality monitor that reports loss of signal when the input level on RTIP and RRING falls below 0.4V or upon detection of 175 15 consecutive zeros in the incoming data stream. The zero detection circuit is active only when LCLK clock is applied. In both cases, the receiver reports loss of signal by setting LOS high, and at the same time, RPOS and RNEG are forced to low. Under the loss of signal conditions, the receiver will continue to recover data and will return to its normal operation if a valid data is detected on RTIP and RRING. TRANSMITTER The transmitter is designed to take dual rail NRZ data, plus a synchronized input clock and produces a bipolar signal with the appropriate shape for transmission to the line. After sampling by the falling edge of TCLK, TPOS and TNEG data are processed by a digital to analog converter together with a slew-control circuit to generate output pulses at TTIP and TRING with the appropriate amplitude and shape to meet the cross-connect template specified in CB 119. A typical output pulse is shown in Figure 7. In order to meet the amplitude requirement with a single +5V supply, the transmit signal is driven to the line differentially via a 1:1.36 step-up transformer. Table 1. ABAM or ALVYN Cable Type Line Length Selection The transmitter can be set to transmit a continuous AMI encoded all ones signal to the line by forcing TAOS high. In this mode, input data TPOS and TNEG are ignored and the frequency of the transmitted signal is determined by TCLK. With TTIP connected to MTIP and TRING connected to MRING, the driver monitor can detect a non-functional T1 transmitter by monitoring the activity at its input. If no signal is presented on MTIP and MRING for 63 TCLK clock cycles, DPM goes high until the next AMI signal is detected. Pulse shaping is selectable through input control pins LEN2, LEN1 and LEN0 for line lengths ranging from 0 to 655 feet of ABAM cable as illustrated in Table 1. LEN2 0 1 1 1 1 LEN1 1 0 0 1 1 LEN0 1 0 1 0 1 Line Length Selected (ft.) 0 - 133 133 - 266 266 - 399 399 - 533 533 - 655
T5684 Output Pulse Shape Normalized Amplitude 1.0 0.5 0 CB119 Specification
-0.5
250
500
750
1000
Time (Nanoseconds)
Figure 7. Receiver Clock and Data Switching Characteristics
Rev 1.01 10
Rev. 1.01
TNEG TPOS TCLK 10K SWITCH 2 R6 75 LEN2 LEN1 LEN0 X5 SIP2 1 2 3 4 5 XR-T5684 XFMR 2 PE64944 R2 220 R1 220 10 9 8 7 6 RX: SCHOTT 67121040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C3 0.47mF XFMR 1 PE64937 LCLK TCLK TPOS TNEG MODE RPOS RNEG RCLK PD CLKDS DPM LOS TTIP TGND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TAOS N/C TEST LEN2 LEN1 LEN0 RGND RVDD RRING RTIP MRING MTIP TRING TVDD SWITCH 1 X8 1 2 3 4 5 TAOS RETIME X16 CLKDS C1 + C2 10K X5 SIP1 10 9 8 7 6 TX: SCHOTT 67121050 22mF 16V RPOS RNEG RCLK GND 0.22mF VCC (5V 5%)
12.35MHz or 24.07MHz
R5 75
Drive Performance Monitor Pin
Loss of Signal Monitor Pin
11
XR-T5684
Figure 1. Application Schematic Diagram
XR-T5684
RRING, RTIP tdr tdf
RPOS, RNEG
Figure 2. Receiver Clock and Data Switching Characteristics
TCLK
tsu
tho
TPOS, TTNEG
Figure 3. Receiver Clock and Data Switching Characteristics
Rev 1.01 12
Preliminary
28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
XR-T5684
D D1 45 x H2 2 1 28 45 x H1
C
Seating Plane A2
B1
D
D1
D3
B
D2
e
D3 A1 A
R
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.485 0.450 0.390 MAX 0.180 0.120 ---. 0.021 0.032 0.013 0.495 0.456 0.430
MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 12.32 11.43 9.91 MAX 4.57 3.05 --- 0.53 0.81 0.32 12.57 11.58 10.92
0.300 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
7.62 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
Note: The control dimension is the inch column
Rev. 13
XR-T5684
28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP)
Rev. 1.00
28
15 E1
1 D
14 E A2 A1
Seating Plane
A L B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.380 0.600 0.485 MAX 0.250 0.070 0.195 0.024 0.070 0.014 1.565 0.625 0.580
MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 35.05 15.24 12.32 MAX 6.35 1.78 4.95 0.56 1.78 0.38 39.75 15.88 14.73
0.100 BSC 0.600 BSC 0.600 0.115 0.700 0.200
2.54 BSC 15.24 BSC 15.24 2.92 17.78 5.08 15
0 15 0 Note: The control dimension is the inch column
Rev 1.01 14
Preliminary
XR-T5684
Notes
Rev. 15
XR-T5684
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1997 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev 1.01 16

▲Up To Search▲

Price & Availability of XR-T5684IJ

	To Download XR-T5684IJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .