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Blackfin(R) Embedded Processor
Preliminary Technical Data
FEATURES
Up to 600 MHz high-performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a wide range of supply voltages for internal and I/O operations. See Operating Conditions for ADSP-BF523/525/527 on Page 29 and Operating Conditions for ADSP-BF522/524/526 on Page 27 Programmable on-chip voltage regulator (ADSP-BF523/525/527 processors only) 289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm) CSP_BGA packages
ADSP-BF522/523/524/525/526/527
PERIPHERALS
USB 2.0 high speed on-the-go (OTG) with Integrated PHY IEEE 802.3-compliant 10/100 Ethernet MAC Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Host DMA port (HOSTDP) Two dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo I2S channels 12 peripheral DMAs, 2 mastered by the Ethernet MAC Two memory-to-memory DMAs with external request lines Event handler with 54 interrupt inputs Serial peripheral interface (SPI) compatible port Two UARTs with IrDA(R) support Two-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 32-bit up/down counter with rotary support Real-time clock (RTC) and watchdog timer 32-bit core timer 48 general-purpose I/Os (GPIOs), with programmable hysteresis NAND flash controller (NFC) Debug/JTAG interface On-chip PLL capable of 0.5 to 64 frequency multiplication
MEMORY
132K bytes of on-chip memory: (See Table 1 on Page 3 for L1 and L3 memory size details) External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Flexible booting options from external flash, SPI, and TWI memory or from host devices including SPI, TWI, and UART Code Security with LockboxTM Secure Technology One-Time-Programmable (OTP) Memory Memory management unit providing memory protection
WATCHDOG TIMER
OTP MEMORY RTC
VOLTAGE REGULATOR*
JTAG TEST AND EMULATION PERIPHERAL
COUNTER SPORT0
ACCESS BUS
B
L1 INSTRUCTION MEMORY EAB USB 16 L1 DATA MEMORY
SPORT1 INTERRUPT CONTROLLER UART1 UART0 NFC DMA CONTROLLER DCB DEB DMA ACCESS BUS PPI SPI TIMER7-1 TIMER0 GPIO PORT H GPIO PORT G GPIO PORT F
EXTERNAL PORT FLASH, SDRAM CONTROL
BOOT ROM
EMAC HOST DMA
*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY
TWI
PORT J
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADSP-BF522/523/524/525/526/527
TABLE OF CONTENTS
General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 System Integration ................................................ 3 Processor Peripherals ............................................. 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 9 Host DMA Port .................................................... 9 Real-Time Clock ................................................. 10 Watchdog Timer ................................................ 10 Timers ............................................................. 10 Up/Down Counter and Thumbwheel Interface .......... 10 Serial Ports ........................................................ 11 Serial Peripheral Interface (SPI) Port ....................... 11 UART Ports ...................................................... 11 TWI Controller Interface ...................................... 12 10/100 Ethernet MAC .......................................... 12 Ports ................................................................ 12 Parallel Peripheral Interface (PPI) ........................... 13 USB On-the-go dual-role device controller ............... 14 Code Security with Lockbox Secure Technology ......... 14 Dynamic Power Management ................................ 14 ADSP-BF523/525/527 Voltage Regulation ................ 15 ADSP-BF522/524/526 Voltage Regulation ................ 16 Clock Signals ..................................................... 16
Preliminary Technical Data
Booting Modes ................................................... 18 Instruction Set Description .................................... 20 Development Tools .............................................. 21 Designing an Emulator-Compatible Processor Board (Target) ................................... 21 Related Documents .............................................. 21 Lockbox Secure Technology Disclaimer .................... 21 Signal Descriptions ................................................. 22 Specifications ........................................................ 27 Operating Conditions for ADSP-BF522/524/526 ......... 27 Operating Conditions for ADSP-BF523/525/527 ......... 29 Electrical Characteristics ....................................... 31 Absolute Maximum Ratings ................................... 36 ESD Sensitivity ................................................... 37 Package Information ............................................ 37 Timing Specifications ........................................... 38 Output Drive Currents ......................................... 64 Test Conditions .................................................. 67 Environmental Conditions .................................... 71 289-Ball CSP_BGA Ball assignment ............................ 72 208-Ball CSP_BGA Ball assignment ............................ 75 Outline Dimensions ................................................ 78 Surface Mount Design .......................................... 79 Ordering Guide ..................................................... 80
REVISION HISTORY
2/09--Revision PrG: Numerous small clarifications and corrections throughout document. Updated external crystal connections guidelines in Figure 6 ...................................................... Page 17 Added electrical characteristics ............................ Page 31 Added total power dissipation data ....................... Page 33 Added maximum total source/sink (IOH/IOL) current to absolute maximum ratings .............................. Page 36 Added capacitive loading data ............................. Page 68
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Preliminary Technical Data GENERAL DESCRIPTION
The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-ofthe-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors are completely code compatible with other Blackfin processors. The ADSP-BF523/525/527 processors offer performance up to 600 MHz. The ADSP-BF522/524/526 processors offer performance up to 400 MHz and reduced static power consumption. Differences with respect to peripheral combinations are shown in Table 1. Table 1. Processor Comparison
ADSP-BF522 ADSP-BF524 ADSP-BF526 ADSP-BF523 ADSP-BF525 ADSP-BF527
ADSP-BF522/523/524/525/526/527
By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors are highly integrated system-on-a-chip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB 2.0 high speed OTG controller, a TWI controller, a NAND flash controller, two UART ports, an SPI port, two serial ports (SPORTs), eight general purpose 32bit timers with PWM capability, a core timer, a real-time clock, a watchdog timer, a Host DMA (HOSTDP) interface, and a parallel peripheral interface (PPI).
Feature Host DMA USB Ethernet MAC Internal Voltage Regulator TWI SPORTs UARTs SPI GP Timers Watchdog Timers RTC Parallel Peripheral Interface GPIOs L1 Instruction SRAM L1 Instruction SRAM/Cache L1 Data SRAM L1 Data SRAM/Cache L1 Scratchpad L3 Boot ROM Maximum Speed Grade1 Maximum System Clock Speed Package Options Memory (bytes)
1
111111 -11-11 - -1- -1 ---111 111111 222222 222222 111111 888888 111111 111111 111111 48 48 48 48 48 48 48K 48K 48K 48K 48K 48K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 400 MHz 600 MHz 80 MHz 133 MHz 289-Ball CSP_BGA 208-Ball CSP_BGA
PROCESSOR PERIPHERALS
The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). These Blackfin processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for the general-purpose I/O, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
Maximum speed grade is not available with every possible SCLK selection.
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ADSP-BF522/523/524/525/526/527
The ADSP-BF523/525/527 processors include an on-chip voltage regulator in support of the processor's dynamic power management capability. The voltage regulator provides a range of core voltage levels when supplied from VDDEXT. The voltage regulator can be bypassed at the user's discretion.
Preliminary Technical Data
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing
ADDRESS ARITHMETIC UNIT
I3 I2 I1 I0 DA1 DA0
TO MEMORY
L3 L2 L1 L0
B3 B2 B1 B0
M3 M2 M1 M0 DAG1 DAG0
SP FP P5 P4 P3 P2 P1 P0
32 32
32 RAB
32 PREG
SD LD1 LD0
32 32 32
32 32
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER 16 8 8 8 16 8 DECODE ALIGN
40 40 40
40
LOOP BUFFER
A0
A1
CONTROL UNIT
32
32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
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Preliminary Technical Data
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
ADSP-BF522/523/524/525/526/527
0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTES) 0xFFA1 0000 0xFFA0 C000 INSTRUCTION BANK B SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK A SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTES) 0xFF90 4000 DATA BANK B SRAM (16K BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES) 0xFF80 4000 DATA BANK A SRAM (16K BYTES) 0xFF80 0000 RESERVED 0xEF00 8000 BOOT ROM (32K BYTES) RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTES) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTES) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTES) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTES) 0x2000 0000 RESERVED 0x08 00 0000 SDRAM MEMORY (16M BYTES - 128M BYTES) 0x0000 0000
EXTERNAL MEMORY MAP INTERNAL MEMORY MAP
RESERVED
0xEF00 0000
Figure 3. Internal/External Memory Map
Internal (On-Chip) Memory
The processor has three blocks of on-chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3. The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external
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External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices.
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ADSP-BF522/523/524/525/526/527
The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory.
Preliminary Technical Data
ID, MAC address, etc. Hence generic parts can be shipped which are then programmed and protected by the developer within this non-volatile memory.
I/O Memory Space
The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.
NAND Flash Controller (NFC)
The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors provide a NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for read-only code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as SDRAM or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. Hardware features of the NFC include: * Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries. * Error checking and correction (ECC) hardware that facilitates error detection and correction. * A single 8-bit external bus interface for commands, addresses and data. * Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 and 512 bytes. Larger page sizes can be supported in software. * Capability of releasing external bus interface pins during long accesses. * Support for internal bus requests of 16-bits * DMA engine to transfer data between internal memory and NAND flash device.
Booting
The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 18.
Event Handling
The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. * RESET - This event resets the processor. * Nonmaskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. * Exceptions - Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt
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One-Time Programmable Memory
The processor has 64K bits of one-time programmable non-volatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as customer ID, product
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Preliminary Technical Data
controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC.
ADSP-BF522/523/524/525/526/527
Table 2. Core Event Controller (CEC)
Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control RESET Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General-Purpose Interrupt 7 General-Purpose Interrupt 8 General-Purpose Interrupt 9 General-Purpose Interrupt 10 General-Purpose Interrupt 11 General-Purpose Interrupt 12 General-Purpose Interrupt 13 General-Purpose Interrupt 14 General-Purpose Interrupt 15 EVT Entry EMU RST NMI EVX -- IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event PLL Wakeup Interrupt DMA Error 0 (generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error PPI Error MAC Status SPORT0 Status SPORT1 Status Reserved Reserved UART0 Status UART1 Status RTC DMA Channel 0 (PPI/NFC) DMA 3 Channel (SPORT0 RX) DMA 4 Channel (SPORT0 TX) DMA 5 Channel (SPORT1 RX) DMA 6 Channel (SPORT1 TX) TWI DMA 7 Channel (SPI) DMA8 Channel (UART0 RX) DMA9 Channel (UART0 TX) General Purpose Interrupt (at RESET) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10
Peripheral Interrupt ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Default Core Interrupt ID SIC Registers 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR0 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 0 IAR1 IMASK0, ISR0, IWR0 1 IAR1 IMASK0, ISR0, IWR0 1 IAR1 IMASK0, ISR0, IWR0 2 IAR2 IMASK0, ISR0, IWR0 2 IAR2 IMASK0, ISR0, IWR0 2 IAR2 IMASK0, ISR0, IWR0 2 IAR2 IMASK0, ISR0, IWR0 3 IAR2 IMASK0, ISR0, IWR0 3 IAR2 IMASK0, ISR0, IWR0 3 IAR2 IMASK0, ISR0, IWR0 3 IAR2 IMASK0, ISR0, IWR0
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Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event DMA10 Channel (UART1 RX) DMA11 Channel (UART1 TX) OTP Memory Interrupt GP Counter DMA1 Channel (MAC RX/HOSTDP) Port H Interrupt A DMA2 Channel (MAC TX/NFC) Port H Interrupt B Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Port G Interrupt A Port G Interrupt B MDMA Stream 0 MDMA Stream 1 Software Watchdog Timer Port F Interrupt A Port F Interrupt B SPI Status NFC Status HOSTDP Status Host Read Done USB_EINT Interrupt USB_INT0 Interrupt USB_INT1 Interrupt USB_INT2 Interrupt USB_DMAINT Interrupt General Purpose Interrupt (at RESET) IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13 IVG7 IVG7 IVG7 IVG7 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt ID 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Preliminary Technical Data
Default Core Interrupt ID SIC Registers 3 IAR3 IMASK0, ISR0, IWR0 3 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 4 IAR3 IMASK0, ISR0, IWR0 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR4 IMASK1, ISR1, IWR1 5 IAR5 IMASK1, ISR1, IWR1 5 IAR5 IMASK1, ISR1, IWR1 6 IAR5 IMASK1, ISR1, IWR1 6 IAR5 IMASK1, ISR1, IWR1 6 IAR5 IMASK1, ISR1, IWR1 6 IAR5 IMASK1, ISR1, IWR1 6 IAR5 IMASK1, ISR1, IWR1 0 IAR5 IMASK1, ISR1, IWR1 0 IAR6 IMASK1, ISR1, IWR1 0 IAR6 IMASK1, ISR1, IWR1 0 IAR6 IMASK1, ISR1, IWR1 3 IAR6 IMASK1, ISR1, IWR1 3 IAR6 IMASK1, ISR1, IWR1 3 IAR6 IMASK1, ISR1, IWR1 3 IAR6 IMASK1, ISR1, IWR1 3 IAR6 IMASK1, ISR1, IWR1
Event Control
The processor provides a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide. * CEC interrupt latch register (ILAT) - Indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. * CEC interrupt mask register (IMASK) - Controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) * CEC interrupt pending register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.
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Preliminary Technical Data
The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7. * SIC interrupt mask registers (SIC_IMASKx) - Control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. * SIC interrupt status registers (SIC_ISRx) - As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. * SIC interrupt wakeup enable registers (SIC_IWRx) - By enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. For more information see Dynamic Power Management on Page 14. Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
ADSP-BF522/523/524/525/526/527
The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the processor DMA controller include: * A single, linear buffer that stops upon completion * A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer * 1-D or 2-D DMA using a linked list of descriptors * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The processor also has an external DMA controller capability via dual external DMA request pins when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core.
HOST DMA PORT
The host port interface allows an external host to be a DMA master to transfer data in and out of the device. The host device masters the transactions and the Blackfin is the DMA slave. The host port is enabled through the PAB interface. Once enabled, the DMA is controlled by the external host, which can then program the DMA to send/receive data to any valid internal or external memory location. The host port interface controller has the following features. * Allows external master to configure DMA read/write data transfers and read port status. * Uses asynchronous memory protocol for external interface. * 8-/16-bit external data interface to host device. * Half duplex operation * Little-/big-endian data transfer. * Acknowledge mode allows flow control on host transactions. * Interrupt mode guarantees a burst of FIFO depth host transactions.
February 2009
DMA CONTROLLERS
The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, NFC, HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The processor DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.
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REAL-TIME CLOCK
The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state. Connect RTC pins RTXI and RTXO with external components as shown in Figure 4.
RTXI R1 RTXO
Preliminary Technical Data
expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK.
TIMERS
There are nine general-purpose programmable timer units in the processors. Eight timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
X1 C1 C2
UP/DOWN COUNTER AND THUMBWHEEL INTERFACE
A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input pin or by two edge detectors. A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded.
SUGGESTED COMPONENTS: X1 = ECL IPTEK EC38J (THROUGH-HOLE PACKAGE) OR EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 4. External Components for RTC
WATCHDOG TIMER
The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer
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Preliminary Technical Data
SERIAL PORTS
The processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. * Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.
ADSP-BF522/523/524/525/526/527
SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port's baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI's DMA channel can only service unidirectional accesses at any given time. The SPI port's clock rate is calculated as: f SCLK SPI Clock Rate = ----------------------------------2 x SPI_BAUD Where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORTS
The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. Each UART port supports two modes of operation: * PIO (programmed I/O) - The processor sends or receives data by writing or reading I/O mapped UART registers. The data is double-buffered on both transmit and receive. * DMA (direct memory access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: * Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK/16) bits per second. * Supporting data formats from seven to 12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port's clock rate is calculated as: f SCLK UART Clock Rate = ---------------------------------------------16 x UART_Divisor Where the 16-bit UART_Divisor comes from the UART_DLH (most significant 8 bits) and UART_DLL (least significant 8 bits) registers.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The processors have an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7-1) let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the
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In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UARTs are further extended with support for the infrared data association (IrDA(R)) serial infrared physical layer link specification (SIR) protocol.
Preliminary Technical Data
* Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software. * Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations. * Convenient frame alignment modes support even 32-bit alignment of encapsulated Rx or Tx IP packet data in memory after the 14-byte MAC header. * Programmable Ethernet event interrupt supports any combination of: * Any selected Rx or Tx frame status conditions. * PHY interrupt condition. * Wakeup frame detected. * Any selected MAC management counter(s) at halffull. * DMA descriptor error. * 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value. * Programmable Rx address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames. * Advanced power management supporting unattended transfer of Rx and Tx frames and status to/from external memory via DMA during low-power sleep mode. * System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters. * Support for 802.3Q tagged VLAN frames. * Programmable MDC clock rate and preamble suppression. * In RMII operation, seven unused pins may be configured as GPIO pins for other purposes.
TWI CONTROLLER INTERFACE
The processors include a two wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C(R) bus standard. The TWI module offers the capabilities of simultaneous master and slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices.
10/100 ETHERNET MAC
The ADSP-BF526 and ADSP-BF527 processors offer the capability to directly connect to a network by way of an embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are: * Support of MII and RMII protocols for external PHYs. * Full duplex and half duplex modes. * Data framing and encapsulation: generation and detection of preamble, length padding, and FCS. * Media access management (in half-duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing. * Flow control (in full-duplex operation): generation and detection of PAUSE frames. * Station management: generation of MDC/MDIO frames for read-write access to PHY registers. * SCLK operating range down to 25 MHz (active and sleep operating modes). * Internal loopback from Tx to Rx. Some advanced features are: * Buffered crystal output to external PHY for support of a single crystal system. * Automatic checksum computation of IP header and IP payload fields of Rx frames. * Independent 32-bit descriptor-driven Rx and Tx DMA channels.
PORTS
Because of the rich set of peripherals, the processor groups the many peripheral signals to four ports--Port F, Port G, Port H, and Port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 48 bidirectional, general-purpose I/O (GPIO) pins allocated across three separate GPIO modules--PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by
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Preliminary Technical Data
default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: * GPIO direction control register - Specifies the direction of each individual GPIO pin as input or output. * GPIO control and status registers - The processor employs a "write one to modify" mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins. * GPIO interrupt mask registers - The two GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. * GPIO interrupt sensitivity registers - The two GPIO interrupt sensitivity registers specify whether individual pins are level- or edge-sensitive and specify--if edge-sensitive-- whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
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General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: 1. Input mode - Frame syncs and data are inputs into the PPI. 2. Frame capture mode - Frame syncs are outputs from the PPI, but data are inputs. 3. Output mode - Frame syncs and data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF522/524/526 and ADSP-BF523/525/527 processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling.
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that can connect directly to parallel A/D and D/A converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bidirectional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct submodes are supported: 1. Active video only mode 2. Vertical blanking only mode 3. Entire field mode Active Video Mode Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register).
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Vertical Blanking Interval Mode In this mode, the PPI only transfers vertical blanking interval (VBI) data. Entire Field Mode In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core.
Preliminary Technical Data
processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.
Full-On Operating Mode--Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.
Active Operating Mode--Moderate Dynamic Power Savings
In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories. In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl(). If disabled, the PLL control input must be re-enabled before transitioning to the full-on or sleep modes. Table 4. Power Settings
PLL Mode/State PLL Bypassed Full On Enabled No Active Enabled/ Yes Disabled Sleep Enabled -- Deep Sleep Disabled -- Hibernate Disabled -- Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power On On
USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
The USB clock (USB_XI) is provided through a dedicated external crystal or crystal oscillator. See Universal Serial Bus (USB) On-The-Go--Receive and Transmit Timing on Page 54 for related timing requirements. If using a crystal to provide the USB clock, use a parallel-resonant, fundamental mode, microprocessor-grade crystal. The USB on-the-go dual-role device controller includes a phase locked loop with programmable multipliers to generate the necessary internal clocking frequency for USB. The multiplier value should be programmed based on the USB_XI frequency to achieve the necessary 480 MHz internal clock for USB high speed operation. For example, for a USB_XI crystal frequency of 24 MHz, the USB_PLLOSC_CTRL register should be programmed with a multiplier value of 20 to generate a 480 MHz internal clock.
CODE SECURITY WITH LOCKBOX SECURE TECHNOLOGY
A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code security features with Lockbox secure technology. Key features include: * OTP memory * Unique chip ID * Code authentication * Secure mode of operation The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. See Lockbox Secure Technology Disclaimer on Page 21.
Disabled Enabled On Disabled Disabled On Disabled Disabled Off
For more information about PLL controls, see the "Dynamic Power Management" chapter in the ADSP-BF542x Blackfin Processor Hardware Reference.
Sleep Operating Mode--High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity wakes up the processor. When in the sleep mode, asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full on mode. If BYPASS is enabled, the processor transitions to the active mode. System DMA access to L1 memory is not supported in sleep mode.
DYNAMIC POWER MANAGEMENT
The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 volt core supply voltage, the
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Preliminary Technical Data
Deep Sleep Operating Mode--Maximum Dynamic Power Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode.
ADSP-BF522/523/524/525/526/527
the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor Operating Conditions; even if the feature/peripheral is not used. Table 5. Power Domains
Power Domain All internal logic, except RTC, Memory, USB, OTP RTC internal logic and crystal I/O Memory logic USB PHY logic OTP logic All other I/O VDD Range VDDINT VDDRTC VDDMEM VDDUSB VDDOTP VDDEXT
Hibernate State--Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all of the synchronous peripherals (SCLK). The internal voltage regulator (ADSP-BF523/525/527 only) for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This setting sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (for example, memory contents, register contents, and other information) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Writing b#00 to the FREQ bits also causes EXT_WAKE0 and EXT_WAKE1 to transition low, which can be used to signal an external voltage regulator to shut down. Since VDDEXT and VDDMEM can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. The Ethernet or USB modules can wake up the internal supply regulator (ADSP-BF525 and ADSP-BF527 only) or signal an external regulator to wake up using EXT_WAKE0 or EXT_WAKE1. If PG15 does not connect as a PHYINT signal to an external PHY device, PG15 can be pulled low by any other device to wake the processor up. The processor can also be woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wakeup events initiate the hardware reset sequence. Individual sources are enabled by the VR_CTL register. The EXT_WAKEx signals are provided to indicate the occurrence of wakeup events. As long as VDDEXT is applied, the VR_CTL register maintains its state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state. State variables may be held in external SRAM or SDRAM. The SCKELOW bit in the VR_CTL register controls whether or not SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence.
The dynamic power management feature of the processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. Power Savings Factor V DDINTRED 2 f CCLKRED T RED = ------------------------- x ------------------------------- x -------------- T NOM f CCLKNOM V DDINTNOM % Power Savings = ( 1 - Power Savings Factor ) x 100% where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage TNOM is the duration running at fCCLKNOM TRED is the duration running at fCCLKRED
ADSP-BF523/525/527 VOLTAGE REGULATION
The ADSP-BF523/525/527 provides an on-chip voltage regulator that can generate processor core voltage levels from an external supply. Figure 5 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power
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Power Savings
As shown in Table 5, the processor supports six different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating
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consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in the hibernate state, all external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) can still be applied, eliminating the need for external buffers. VDDRTC must be applied at all times for correct hibernate operation. The voltage regulator can be activated from this power down state either through an RTC wakeup, a USB wakeup, an ethernet wakeup, or by asserting the RESET pin, each of which then initiates a boot sequence. The regulator can also be disabled and bypassed at the user's discretion.
SET OF DECOUPLING CAPACITORS
Preliminary Technical Data
ADSP-BF522/524/526 VOLTAGE REGULATION
The ADSP-BF522/524/526 processor requires an external voltage regulator to power the VDDINT domain. To reduce standby power consumption, the external voltage regulator can be signaled through EXT_WAKE0 or EXT_WAKE1 to remove power from the processor core. These identical signals are high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. While in the hibernate state, all external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) can still be applied, eliminating the need for external buffers. VDDRTC must be applied at all times for correct hibernate operation. The external voltage regulator can be activated from this power down state either through an RTC wakeup, a USB wakeup, an ethernet wakeup, or by asserting the RESET pin, each of which then initiates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a wakeup to the external voltage regulator. The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of the Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference.
2.25V TO 3.6V INPUT VOLTAGE RANGE
VDDEXT (LOW-INDUCTANCE)
+ 100F 100F + FDS9431A 10 F LOW ESR ZHCS1000 100F 100nF 10H
VDDEXT
VDDINT +
SS/PG
CLOCK SIGNALS
VROUT EXT_WAKE1
SHORT AND LOWINDUCTANCE WIRE SEE H/W REFERENCE, SYSTEM DESIGN CHAPTER, TO DETERMINE VALUE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
VRSEL GND
The processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 6. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins. The onchip resistance between CLKIN and the XTAL pin is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in Figure 6 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 6 are typical values only. The capacitor values are dependent upon the crystal manufacturers' load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level
Figure 5. ADSP-BF523/525/527 Voltage Regulator Circuit
The voltage regulator has two modes set by the VRSEL pin--the normal pulse width control of an external FET and the external supply mode which can signal a power down during hibernate to an external regulator. Set VRSEL to VDDEXT to use an external regulator or set VRSEL to GND to use the internal regulator. In the external mode VROUT becomes EXT_WAKE1. If the internal regulator is used, EXT_WAKE0 can control other power sources in the system during the hibernate state. Both signals are high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. The mode of the SS/PG (Soft Start/Power Good) signal also changes according to the state of VRSEL. When using an internal regulator, the SS/PG pin is Soft Start, and when using an external regulator, it is Power Good. The Soft Start feature is recommended to reduce the inrush currents and to reduce VDDINT voltage overshoot when coming out of hibernate or changing voltage levels. The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of Soft Start and Power Good functionality, refer to the ADSPBF52x Blackfin Processor Hardware Reference.
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Preliminary Technical Data
specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range.
BLACKFIN CLKOUT TO PLL CIRCUITRY EN CLKBUF 560 EN CLKIN 330 * XTAL FOR OVERTONE OPERATION ONLY:
ADSP-BF522/523/524/525/526/527
SDRAM interface, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers.
"FINE" ADJUSTMENT REQUIRES PLL SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
/ 1, 2, 4, 8 CLKIN PLL 0.5x to 64x
CCLK
VCO / 1 to 15 SCLK
SCLK CCLK SCLK 133 MHz
18 pF *
18 pF *
Figure 7. Frequency Modification Methods
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 .
Figure 6. External Crystal Connections
A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)--use site search on "EE-168." The CLKBUF pin is an output pin, which is a buffered version of the input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. If instead of a crystal, an external oscillator is used at CLKIN, CLKBUF will not have the 40/60 duty cycle required by some devices. The CLKBUF output is active by default and can be disabled for power savings reasons using the VR_CTL register. The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 7, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable 0.5x to 64x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. The maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT, VDDEXT, and VDDMEM; the VCO is always permitted to run up to the frequency specified by the part's speed grade. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It is part of the
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All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). Table 6. Example System Clock Ratios
Example Frequency Ratios (MHz) VCO SCLK 100 100 300 50 500 50
Signal Name SSEL3-0 0001 0110 1010
Divider Ratio VCO/SCLK 1:1 6:1 10:1
The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1-0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 7. This programmable core clock capability is useful for fast core frequency modifications. Table 7. Core Clock Ratios
Example Frequency Ratios (MHz) VCO CCLK 300 300 300 150 500 125 200 25
Signal Name CSEL1-0 00 01 10 11
Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1
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The maximum CCLK frequency not only depends on the part's speed grade (see Page 80), it also depends on the applied VDDINT voltage. See Table 12 and Table 15 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 14 and Table 17).
Preliminary Technical Data
kernel performs an 8- or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). The ARDY is not enabled by default, but it can be enabled through OTP programming. Similarly, all interface behavior and timings can be customized through OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all asynchronous interface signals are enabled at the port muxing level. * Boot from 16-bit asynchronous FIFO (BMODE = 0x2) -- In this mode, the boot kernel starts booting from address 0x2030 0000. Every 16-bit word that the boot kernel has to read from the FIFO must be requested by placing a low pulse on the DMAR1 pin. * Boot from serial SPI memory, EEPROM or flash (BMODE = 0x3) -- 8-, 16-, 24-, or 32-bit addressable devices are supported. The processor uses the PG1 GPIO pin to select a single SPI EEPROM/flash device and submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SPISEL1 and MISO pins. By default, a value of 0x85 is written to the SPI_BAUD register. * Boot from SPI host device (BMODE = 0x4) -- The processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. The HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the SPISS input. A pull-down on the serial clock (SCK) may improve signal quality and booting robustness. * Boot from serial TWI memory, EEPROM/flash (BMODE = 0x5) -- The processor operates in master mode and selects the TWI slave connected to the TWI with the unique ID 0xA0. The processor submits successive read commands to the memory device starting at internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with the Philips I2C(R) Bus Specification version 2.1 and should be able to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. By default, a PRESCALE value of 0xA and a TWI_CLKDIV value of 0x0811 are used. Unless altered by OTP settings, an I2C memory that takes two address bytes is assumed. The development tools ensure that data booted to memories that cannot be accessed by the Blackfin core is written to an intermediate storage location and then copied to the final destination via memory DMA. * Boot from TWI host (BMODE = 0x6) -- The TWI host selects the slave with the unique ID 0x5F. The processor replies with an acknowledgement and the host then downloads the boot stream. The TWI host agent should comply with the Philips I2C Bus Specification
BOOTING MODES
The processor has several mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. The boot mode is defined by four BMODE input pins dedicated to this purpose. There are two categories of boot modes. In master boot modes the processor actively loads data from parallel or serial memories. In slave boot modes the processor receives data from external host devices. The boot modes listed in Table 8 provide a number of mechanisms for automatically loading the processor's internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. The BMODE pins of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes shown in Table 8. Table 8. Booting Modes
BMODE3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Idle - No boot Boot from 8- or 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial SPI memory (EEPROM or flash) Boot from SPI host device Boot from serial TWI memory (EEPROM/flash) Boot from TWI host Boot from UART0 Host Boot from UART1 Host Reserved Boot from SDRAM Boot from OTP memory Boot from 8-bit NAND flash via NFC using PORTF data pins Boot from 8-bit NAND flash via NFC using PORTH data pins Boot from 16-Bit Host DMA Boot from 8-Bit Host DMA
* Idle/no boot mode (BMODE = 0x0) -- In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the OTP memory has been misconfigured. * Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1) -- In this mode, the boot kernel loads the first block header from address 0x2000 0000, and (depending on instructions contained in the header) the boot
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Preliminary Technical Data
version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. * Boot from UART0 host on Port G (BMODE = 0x7) -- Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities. When performing the autobaud, the UART expects a "@" (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the UART0RX pin to determine the bit rate. The UART then replies with an acknowledgement composed of 4 bytes (0xBF, the value of UART0_DLL, the value of UART0_DLH, then 0x00). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte. * Boot from UART1 host on Port F (BMODE = 0x8). Same as BMODE = 0x7 except that the UART1 port is used. * Boot from SDRAM (BMODE = 0xA) This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings. * Boot from OTP memory (BMODE = 0xB) -- This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default, the boot stream is expected to start from OTP page 0x40 and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes. Table 9. Fourth Byte for Large Page Devices
Bit Parameter Value Meaning 00 01 10 11 00 01 00 01 10 11 00 01 1K byte 2K byte 4K byte 8K byte 8 byte/512 byte 16 byte/512 byte 64K byte 128K byte 256K byte 512K byte x8 not supported
ADSP-BF522/523/524/525/526/527
* Boot from 8-bit external NAND flash memory (BMODE = 0xC and BMODE = 0xD) -- In this mode, auto detection of the NAND flash device is performed. BMODE = 0xC, the processor configures PORTF GPIO pins PF7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals. BMODE = 0xD, the processor configures PORTH GPIO pins PH7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals. For correct device operation pull-up resistors are required on both ND_CE (PH10) and ND_BUSY (PH13) signals. By default, a value of 0x0033 is written to the NFC_CTL register. The booting procedure always starts by booting from byte 0 of block 0 of the NAND flash device. NAND flash boot supports the following features: --Device Auto Detection --Error Detection & Correction for maximum reliability --No boot stream size limitation --Peripheral DMA providing efficient transfer of all data (excluding the ECC parity data) --Software-configurable boot mode for booting from boot streams spanning multiple blocks, including bad blocks --Software-configurable boot mode for booting from multiple copies of the boot stream, allowing for handling of bad blocks and uncorrectable errors --Configurable timing via OTP memory Small page NAND flash devices must have a 512-byte page size, 32 pages per block, a 16-byte spare area size, and a bus configuration of 8 bits. By default, all read requests from the NAND flash are followed by four address cycles. If the NAND flash device requires only three address cycles, the device must be capable of ignoring the additional address cycles. The small page NAND flash device must comply with the following command set: --Reset: 0xFF --Read lower half of page: 0x00 --Read upper half of page: 0x01 --Read spare area: 0x50 For large-page NAND-flash devices, the four-byte electronic signature is read in order to configure the kernel for booting, which allows support for multiple large-page devices. The fourth byte of the electronic signature must comply with the specification in Table 9. Any NAND flash array configuration from Table 9, excluding 16-bit devices, that also complies with the command set listed below are directly supported by the boot kernel. There are no restrictions on the page size or block size as imposed by the small-page boot kernel.
D1:D0 Page Size (excluding spare area)
D2
Spare Area Size
D5:D4 Block Size (excluding spare area)
D6
Bus width
D3, D7 Not Used for configuration
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For devices consisting of a five-byte signature, only four are read. The fourth must comply as outlined above. Large page devices must support the following command set: --Reset: 0xFF --Read Electronic Signature: 0x90 --Read: 0x00, 0x30 (confirm command) Large-page devices must not support or react to NAND flash command 0x50. This is a small-page NAND flash command used for device auto detection. By default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the additional address cycles. * Boot from 16-Bit Host DMA (BMODE = 0xE) -- In this mode, the host DMA port is configured in 16-bit Acknowledge mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the configuration, the host is required to poll the READY bit in HOST_STATUS before beginning to transfer data. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure that valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel. * Boot from 8-Bit Host DMA (BMODE = 0xF) -- In this mode, the Host DMA port is configured in 8-bit interrupt mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. The host will receive an interrupt from the HOST_ACK signal every time it is allowed to send the next FIFO depths worth (sixteen 32-bit words) of information. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM con-
Preliminary Technical Data
troller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel. For each of the boot modes, a 16-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the address stored in the EVT1 register. Prior to booting, the pre-boot routine interrogates the OTP memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware, especially booting hosts, may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts the boot process. By programming OTP memory, the user can also instruct the pre-boot routine to customize the PLL, Internal Voltage Regulator (ADSP-BF523/525/527 only), SDRAM Controller, and Asynchronous Memory Controller. The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case. Bits 6-4 in the system reset configuration (SYSCR) register can be used to bypass the pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case. The boot process can be further customized by "initialization code." This is a piece of code that is loaded and executed prior to the regular application boot. Typically, this is used to configure the SDRAM controller or to speed up booting by managing the PLL, clock frequencies, wait states, or serial bit rates. The boot ROM also features C-callable function that can be called by the user application at run time. This enables secondstage boot or boot management schemes to be implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.
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Preliminary Technical Data
The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. * A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. * All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. * Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.
ADSP-BF522/523/524/525/526/527
Reference on the Analog Devices website (www.analog.com)-- use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the ADSPBF522/524/526 and ADSP-BF523/525/527 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: * Getting Started With Blackfin Processors * ADSP-BF52x Blackfin Processor Hardware Reference (volumes 1 and 2) * Blackfin Processor Programming Reference * ADSP-BF522/524/526 Blackfin Processor Anomaly List * ADSP-BF523/525/527 Blackfin Processor Anomaly List
LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices products containing Lockbox Secure Technology are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowledge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifications, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY OR INTELLECTUAL PROPERTY.
DEVELOPMENT TOOLS
The processor is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF522/524/526 and ADSP-BF523/525/527 processors.
EZ-KIT Lite(R) Evaluation Board
For evaluation of ADSP-BF522/524/526 and ADSP-BF523/525/527 processors, use the EZ-KIT Lite boards available from Analog Devices. Order using part numbers ADZS-BF526-EZLITE or ADZS-BF527-EZLITE. The boards come with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (EE-68) Analog Devices JTAG Emulation Technical
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SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF522/524/526 and ADSP-BF523/525/527 processors are listed in Table 10. In order to maintain maximum function and reduce package size and ball count, some balls have dual, multiplexed functions. In cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. All pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL output pin (CLKBUF). On the external memory interface, the control and address lines are driven high, with the exception of CLKOUT, which toggles at the system clock rate. All I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs, as noted in Table 10. Table 10. Signal Descriptions
Signal Name EBIU ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 AMS3-0 ARDY AOE ARE AWE SRAS SCAS SWE SCKE CLKOUT SA10 SMS O I/O O O I O O O O O O O O O O Address Bus Data Bus Byte Enables/Data Mask Bank Select Hardware Ready Control Output Enable Read Enable Write Enable SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Clock Enable SDRAM Clock Output SDRAM A10 Signal SDRAM Bank Select Type Function
Preliminary Technical Data
It is strongly advised to use the available IBIS models to ensure that a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it is strongly recommended to add series resistor terminations for all Driver Types A, C and D. The termination resistors should be placed near the processor to reduce transients and improve signal integrity. The resistance value, typically 33 or 47 , should be chosen to match the average board trace impedance. Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware.
Driver Type1 A A A A A A A A A A A B A A
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Preliminary Technical Data
Table 10. Signal Descriptions (Continued)
Signal Name USB 2.0 HS OTG USB_DP USB_DM USB_XI USB_XO USB_ID USB_VREF USB_RSET USB_VBUS I/O I/O I O I I I Type Function
ADSP-BF522/523/524/525/526/527
Driver Type1
Data + (This ball should be pulled low when USB is unused or not present.) F Data - (This ball should be pulled low when USB is unused or not present.) USB Crystal Input (This ball should be pulled low when USB is unused or not present.) USB Crystal Output (This ball should be left unconnected when USB is unused F or not present.) USB OTG mode (This ball should be pulled low when USB is unused or not present.) USB voltage reference (Connect to GND through a 0.1 F capacitor, or leave unconnected if USB is unused or not present.) USB resistance set. (This ball should be left unconnected when USB is unused or not present.) F
F I/O 5V USB VBUS (USB_VBUS is an output only during initialization of USB OTG session request pulses. Host mode or OTG type A mode require that an external voltage source of 5V, at 8mA or more-per the OTG specification-be applied to VBUS. Other OTG modes require that this external voltage be disabled. This ball should be pulled low when USB is unused or not present.) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/PPI Data 0/SPORT0 Primary Receive Data /NAND Alternate Data 0 GPIO/PPI Data 1/SPORT0 Receive Frame Sync /NAND Alternate Data 1 GPIO/PPI Data 2/SPORT0 Receive Serial Clock /NAND Alternate Data 2/Alternate Capture Input 0 GPIO/PPI Data 3/SPORT0 Transmit Primary Data /NAND Alternate Data 3 GPIO/PPI Data 4/SPORT0 Transmit Frame Sync /NAND Alternate Data 4/Alternate Timer Clock 0 GPIO/PPI Data 5/SPORT0 Transmit Serial Clock /NAND Alternate Data 5/Alternate Timer Clock 1 GPIO/PPI Data 6/SPORT0 Transmit Secondary Data /NAND Alternate Data 6/Alternate Capture Input 0 GPIO/PPI Data 7/SPORT0 Receive Secondary Data /NAND Alternate Data 7/Alternate Capture Input 1 GPIO/PPI Data 8/SPORT1 Primary Receive Data GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6 GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7 GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter Down Gate C C D C C D C C C D C C C
Port F: GPIO and Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A PF1/PPI D1/RFS0/ND_D1A PF2/PPI D2/RSCLK0/ND_D2A PF3/PPI D3/DT0PRI/ND_D3A PF4/PPI D4/TFS0/ND_D4A/TACLK0 PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 PF6/PPI D6/DT0SEC/ND_D6A/TACI0 PF7/PPI D7/DR0SEC/ND_D7A/TACI1 PF8/PPI D8/DR1PRI PF9/PPI D9/RSCLK1/SPISEL6 PF10/PPI D10/RFS1/SPISEL7 PF11/PPI D11/TFS1/CZM PF12/PPI D12/DT1PRI/SPISEL2/CDG PF13/PPI D13/TSCLK1/SPISEL3/CUD PF14/PPI D14/DT1SEC/UART1TX PF15/PPI D15/DR1SEC/UART1RX/TACI3 Port G: GPIO and Multiplexed Peripherals
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up D Direction GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit GPIO/PPI Data 15/SPORT1 Receive Secondary Data /UART1 Receive /Alternate Capture Input 3 C C
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ADSP-BF522/523/524/525/526/527
Table 10. Signal Descriptions (Continued)
Signal Name PG0/HWAIT PG1/SPISS/SPISEL1 PG2/SCK PG3/MISO/DR0SECA PG4/MOSI/DT0SECA PG5/TMR1/PPI_FS2 PG6/DT0PRIA/TMR2/PPI_FS3 PG7/TMR3/DR0PRIA/UART0TX PG8/TMR4/RFS0A/UART0RX/TACI4 PG9/TMR5/RSCLK0A/TACI5 PG10/TMR6/TSCLK0A/TACI6 PG11/TMR7/HOST_WR PG12/DMAR1/UART1TXA/HOST_ACK PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 PG14/TSCLK0A1/MDC/HOST_RD Type Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/Boot Host Wait2
Preliminary Technical Data
Driver Type1 C C D C C C C C C D D C C C D
GPIO/SPI Slave Select Input/SPI Slave Select 1 GPIO/SPI Clock GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary GPIO/Timer1/PPI Frame Sync2 GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3 GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync /UART0 Receive/Alternate Capture Input 4 GPIO/Timer5/Sport 0 Alternate Receive Clock /Alternate Capture Input 5 GPIO/Timer 6 /Sport 0 Alternate Transmit /Alternate Capture Input 6 GPIO/Timer7/Host DMA Write Enable GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate Capture Input 2 GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock /Host DMA Read Enable
PG153/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O Port H: GPIO and Multiplexed Peripherals PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 PH1/ND_D1/ERxER/HOST_D1 PH2/ND_D2/MDIO/HOST_D2 PH3/ND_D3/ETxEN/HOST_D3 PH5/ND_D5/ETxD0/HOST_D5 PH6/ND_D6/ERxD0/HOST_D6 PH7/ND_D7/ETxD1/HOST_D7 PH8/SPISEL4/ERxD1/HOST_D8/TACLK2 PH9/SPISEL5/ETxD2/HOST_D9/TACLK3 PH10/ND_CE/ERxD2/HOST_D10 PH11/ND_WE/ETxD3/HOST_D11 PH12/ND_RE/ERxD3/HOST_D12 PH13/ND_BUSY/ERxCLK/HOST_D13 PH14/ND_CLE/ERxDV/HOST_D14 PH15/ND_ALE/COL/HOST_D15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII C Management Channel Data Interrupt/Host DMA Chip Enable GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0 GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1 GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2 GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3 GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4 GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5 GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6 GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7 C C C C C C C C
PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O
GPIO/Alternate Capture Input 2/Ethernet MII or RMII Receive D1/Host DMA D8 C /SPI Slave Select 4 GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9 /Alternate Timer Clock 3 GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10 GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11 GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12 GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13 GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/Host DMA D14 GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15 C C C C C C C
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February 2009
Preliminary Technical Data
Table 10. Signal Descriptions (Continued)
Signal Name Port J: Multiplexed Peripherals PJ0: PPI_FS1/TMR0 PJ1: PPI_CLK/TMRCLK PJ2: SCL PJ3: SDA Real Time Clock RTXI RTXO JTAG Port TCK TDO TDI TMS TRST EMU Clock CLKIN XTAL CLKBUF Mode Controls RESET NMI BMODE3-0 ADSP-BF523/525/527 Voltage Regulation I/F VRSEL VROUT/EXT_WAKE1 EXT_WAKE0 SS/PG ADSP-BF522/524/526 Voltage Regulation I/F EXT_WAKE1 EXT_WAKE0 PG O O I Wake up Indication 1 Wake up Indication 0 Power Good I O O I I I I Reset I O O Clock/Crystal Input Crystal Output Buffered XTAL Output I O I I I O JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select I O I/O I PPI Frame Sync1/Timer0 PPI Clock/Timer Clock Type Function
ADSP-BF522/523/524/525/526/527
Driver Type1 C E E
I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up resistor.4) I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up resistor.4) RTC Crystal Input (This ball should be pulled low when not used.) RTC Crystal Output
C
JTAG Reset (This ball should be pulled low if the JTAG port is not used.) Emulation Output C
C
Nonmaskable Interrupt (This ball should be pulled high when not used.) Boot Mode Strap 3-0 Internal/External Voltage Regulator Select External FET Drive/Wake up Indication 1 Wake up Indication 0 Soft Start/Power Good C C G C
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ADSP-BF522/523/524/525/526/527
Table 10. Signal Descriptions (Continued)
Signal Name Power Supplies Type Function
Preliminary Technical Data
Driver Type1
ALL SUPPLIES MUST BE POWERED See Operating Conditions for ADSP-BF523/525/527 on Page 29, and see Operating Conditions for ADSP-BF522/524/526 on Page 27. P P P P P P P G I/O Power Supply Internal Power Supply Real Time Clock Power Supply 3.3 V USB Phy Power Supply MEM Power Supply OTP Power Supply OTP Programming Voltage Ground for All Supplies
VDDEXT VDDINT VDDRTC VDDUSB VDDMEM VDDOTP VPPOTP VSS
1
See Output Drive Currents on Page 64 for more information about each driver type. 2 HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page 18. 3 When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor. 4 Consult version 2.1 of the I2C specification for the proper resistor value.
Rev. PrG
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February 2009
Preliminary Technical Data SPECIFICATIONS
Specifications are subject to change without notice.
ADSP-BF522/523/524/525/526/527
OPERATING CONDITIONS FOR ADSP-BF522/524/526
Parameter VDDINT VDDEXT1 VDDRTC2 VDDMEM3 VDDOTP VPPOTP Conditions Internal Supply Voltage External Supply Voltage RTC Power Supply Voltage MEM Supply Voltage OTP Supply Voltage OTP Programming Voltage For Reads For Writes4 USB Supply Voltage5 High Level Input Voltage6, 7 High Level Input Voltage6, 7 High Level Input Voltage6, 7 High Level Input Voltage Low Level Input Voltage6, 7 Low Level Input Voltage6, 7 Low Level Input Voltage6, 7 Low Level Input Voltage Junction Temperature Junction Temperature Junction Temperature Min tbd 1.70 2.25 1.70 2.25 2.25 6.9 3.0 1.1 1.7 2.0 0.7 x VBUSTWI -0.3 -0.3 -0.3 -0.3 0 0 -40 Nominal tbd 1.8, 2.5 or 3.3 1.8, 2.5 or 3.3 2.5 2.5 7.0 3.3 Max tbd 3.6 3.6 3.6 2.75 2.75 7.1 3.6 3.6 3.6 3.6 VBUSTWI8 0.6 0.7 0.8 0.3 x VBUSTWI9 +105 +105 +105 Unit V V V V V V V V V V V V V V V V C C C
VDDUSB VIH VIH VIH VIHTWI VIL VIL VIL VILTWI TJ TJ TJ
1 2
VDDEXT/VDDMEM = 1.90 V VDDEXT/VDDMEM = 2.75 V VDDEXT/VDDMEM = 3.6 V VDDEXT = 1.90 V/2.75 V/3.6 V VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = minimum 289-Ball CSP_BGA @ TAMBIENT = 0C to +70C 208-Ball CSP_BGA @ TAMBIENT = 0C to +70C 208-Ball CSP_BGA @ TAMBIENT = -40C to +85C
Must remain powered (even if the associated function is not used). If not used, power with VDDEXT. 3 Balls that use VDDMEM are DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant to voltages higher than VDDMEM. 4 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. Please see Table 27 on Page 36 for details. 5 When not using the USB peripheral on the ADSP-BF524/BF526 or terminating VDDUSB on the ADSP-BF522, VDDUSB must be powered by VDDEXT. 6 Bidirectional balls (PF15-0, PG15-0, PH15-0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3-0) of the ADSPBF522/523/524/525/526/527 processors are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 7 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 8 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 11. 9 SDA and SCL are pulled up to VBUSTWI. See Table 11.
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 11. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT 000 (default)1 001 010 011 100 101 110 111 (reserved)
1
Preliminary Technical Data
VDDEXT Nominal 3.3 1.8 2.5 1.8 3.3 1.8 2.5 -
VBUSTWI Minimum 2.97 1.7 2.97 2.97 4.5 2.25 2.25 -
VBUSTWI Nominal 3.3 1.8 3.3 3.3 5 2.5 2.5 -
VBUSTWI Maximum 3.63 1.98 3.63 3.63 5.5 2.75 2.75 -
Unit V V V V V V V -
Designs must comply with the VDDEXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
ADSP-BF522/524/526 Clock Related Operating Conditions
Table 12 describes the core clock timing requirements for the ADSP-BF522/524/526 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 14). Table 13 describes phaselocked loop operating conditions. Table 12. Core Clock (CCLK) Requirements--ADSP-BF522/524/526 Processors--All Speed Grades1
Parameter fCCLK fCCLK fCCLK fCCLK fCCLK
1 2
Core Clock Frequency (VDDINT =tbd2 V minimum) Core Clock Frequency (VDDINT =tbd4 V minimum) Core Clock Frequency (VDDINT = tbd5 V minimum) Core Clock Frequency (VDDINT = tbd V minimum) Core Clock Frequency (VDDINT = tbd V minimum)
Max 4003 350 300 TBD TBD
Unit MHz MHz MHz MHz MHz
See the Ordering Guide on Page 80. Preliminary data indicates a value of 1.33 V. 3 Applies only to 400 MHz speed grade only. See the Ordering Guide on Page 80. 4 Preliminary data indicates a value of 1.235 V. 5 Preliminary data indicates a value of 1.14 V.
Table 13. Phase-Locked Loop Operating Conditions
Parameter fVCO
1
Voltage Controlled Oscillator (VCO) Frequency
Minimum 50
Maximum Speed Grade1
Unit MHz
See the Ordering Guide on Page 80.
Table 14. ADSP-BF522/524/526 Processors Maximum SCLK Conditions
Parameter fSCLK fSCLK
1
CLKOUT/SCLK Frequency (VDDINT tbd V)1 CLKOUT/SCLK Frequency (VDDINT < tbd V)
VDDEXT/VDDMEM = 1.8 V/2.5 V/3.3 V Nominal 80 tbd
Unit MHz MHz
fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44.
Rev. PrG
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February 2009
Preliminary Technical Data
OPERATING CONDITIONS FOR ADSP-BF523/525/527
Parameter VDDINT VDDEXT VDDEXT VDDRTC VDDMEM VDDOTP VPPOTP VDDUSB VIH VIH VIH VIHTWI VIL VIL VIL VILTWI TJ TJ TJ
1
ADSP-BF522/523/524/525/526/527
Conditions Internal Supply Voltage1 External Supply Voltage2, 3 External Supply Voltage2, 3 RTC Power Supply Voltage4 MEM Supply Voltage2, 5 OTP Supply Voltage2 OTP Programming Voltage2 USB Supply Voltage6 High Level Input Voltage7, 8 High Level Input Voltage7, 8 High Level Input Voltage7, 8 High Level Input Voltage Low Level Input Voltage7, 8 Low Level Input Voltage7, 8 Low Level Input Voltage7, 8 Low Level Input Voltage Junction Temperature Junction Temperature Junction Temperature Internal Voltage Regulator Disabled Internal Voltage Regulator Enabled
Min 0.95 1.70 2.25 2.25 1.70 2.25 2.25 3.0 1.1 1.7 2.0 0.7 x VBUSTWI -0.3 -0.3 -0.3 -0.3 0 0 -40
Nominal 1.8, 2.5 or 3.3 2.5 or 3.3
Max 1.26 3.6 3.6 3.6 3.6 2.75 2.75 3.6 3.6 3.6 3.6 VBUSTWI9 0.6 0.7 0.8 0.3 x VBUSTWI10 +105 +105 +105
Unit V V V V V V V V V V V V V V V V C C C
1.8, 2.5 or 3.3 2.5 2.5 3.3
VDDEXT/VDDMEM = 1.90 V VDDEXT/VDDMEM = 2.75 V VDDEXT/VDDMEM = 3.6 V VDDEXT = 1.90 V/2.75 V/3.6 V VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = minimum 289-Ball CSP_BGA @ TAMBIENT = 0C to +70C 208-Ball CSP_BGA @ TAMBIENT = 0C to +70C 208-Ball CSP_BGA @ TAMBIENT = -40C to +85C
The voltage regulator can generate VDDINT at levels of 1.00 V to 1.20 V with -5% to +5% tolerance when VRCTL is programmed with the sysctl API. This specification is only guaranteed when the API is used. 2 Must remain powered (even if the associated function is not used). 3 VDDEXT is the supply to the voltage regulator and GPIO. 4 If not used, power with VDDEXT. 5 Balls that use VDDMEM are DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant to voltages higher than VDDMEM. 6 When not using the USB peripheral on the ADSP-BF525/BF527 or terminating VDDUSB on the ADSP-BF523, VDDUSB must be powered by VDDEXT. 7 Bidirectional balls (PF15-0, PG15-0, PH15-0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3-0) of the ADSPBF522/523/524/525/526/527 processors are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 8 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 9 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 11 on Page 28. 10 SDA and SCL are pulled up to VBUSTWI. See Table 11 on Page 28.
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
ADSP-BF523/525/527 Clock Related Operating Conditions
Table 15 describes the core clock timing requirements for the ADSP-BF523/525/527 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 17). Table 16 describes phaselocked loop operating conditions.
Preliminary Technical Data
Table 15. Core Clock (CCLK) Requirements--ADSP-BF523/525/527 Processors--All Speed Grades1
Parameter fCCLK fCCLK fCCLK
1 2
Core Clock Frequency (VDDINT =1.14 V minimum)2 Core Clock Frequency (VDDINT =1.093 V minimum)3 Core Clock Frequency (VDDINT = 0.95 V minimum)
Internal Regulator Setting 1.20 V 1.15 V 1.0 V
Max 600 533 400
Unit MHz MHz MHz
See the Ordering Guide on Page 80. Applies only to 600 MHz speed grades. See the Ordering Guide on Page 80. 3 Applies only to 533 MHz and 600 MHz speed grades. See the Ordering Guide on Page 80.
Table 16. Phase-Locked Loop Operating Conditions
Parameter fVCO
1
Voltage Controlled Oscillator (VCO) Frequency
Minimum 50
Maximum Speed Grade1
Unit MHz
See the Ordering Guide on Page 80.
Table 17. ADSP-BF523/525/527 Processors Maximum SCLK Conditions
Parameter fSCLK fSCLK
1 2
CLKOUT/SCLK Frequency (VDDINT 1.14 V)2 CLKOUT/SCLK Frequency (VDDINT < 1.14 V)2
VDDEXT/VDDMEM = 1.8 V Nominal1 100 100
VDDEXT/VDDMEM = 2.5 V/3.3 V Nominal Unit 3 133 MHz 100 MHz
If either VDDEXT or VDDMEM are operating at 1.8V nominal, fSCLK is constrained to 100MHz. fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44. 3 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 34 on Page 44.
Rev. PrG
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February 2009
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
ADSP-BF522/523/524/525/526/527
Table 18. Common Electrical Characteristics For All ADSP-BF522/523/524/525/526/527 Processors
Parameter VOH VOH VOH VOL IIH IIL IIHP IOZH IOZHTWI IOZL CIN
1 2
Test Conditions High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current1 Low Level Input Current1 VDDEXT /VDDMEM = 1.7 V, IOH = -0.5 mA VDDEXT /VDDMEM = 2.25 V, IOH = -0.5 mA VDDEXT /VDDMEM = 3.0 V, IOH = -0.5 mA VDDEXT /VDDMEM = 1.7/2.25/3.0 V, IOL = 2.0 mA VDDEXT /VDDMEM =3.6 V, VIN = 3.6 V VDDEXT /VDDMEM =3.6 V, VIN = 0 V
Min 1.35 2.0 2.4
Typical
Max
Unit V V V
0.4 10.0 10.0 75.0 10.0 10.0 10.0 5 8
6
V A A A A A A pF
High Level Input Current JTAG2 VDDEXT = 3.6 V, VIN = 3.6 V Three-State Leakage Current3 VDDEXT /VDDMEM= 3.6 V, VIN = 3.6 V Three-State Leakage Current4 VDDEXT =3.0 V, VIN = 5.5 V Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 0 V Input Capacitance
5 3
fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V
Applies to input balls. Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3 Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls. 6 Guaranteed, but not tested.
Table 19. Electrical Characteristics For ADSP-BF522/524/526 Processors
Parameter IDDDEEPSLEEP
1
Test Conditions VDDINT Current in Deep Sleep Mode VDDINT = 1.0 V, fCCLK = 0 MHz, fSCLK = 0 MHz, TJ = 25C, ASF = 0.00
Min
Typical TBD
Max
Unit mA
IDDSLEEP IDD-IDLE IDD-TYP IDD-TYP IDD-TYP
VDDINT Current in Sleep Mode VDDINT = 1.0 V, fSCLK = 25 MHz, TJ = 25C VDDINT Current in Idle VDDINT Current VDDINT Current VDDINT Current VDDINT = 1.0 V, fCCLK = 50 MHz, TJ = 25C, ASF = 0.44 VDDINT = 1.0 V, fCCLK = 400 MHz, TJ = 25C, ASF = 1.00 VDDINT = 1.15 V, fCCLK = 533 MHz, TJ = 25C, ASF = 1.00 VDDINT = 1.2 V, fCCLK = 600 MHz, TJ = 25C, ASF = 1.00
TBD TBD TBD TBD TBD
mA mA mA mA mA
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Table 19. Electrical Characteristics For ADSP-BF522/524/526 Processors (Continued)
Parameter IDDHIBERNATE
1, 2
Preliminary Technical Data
Min Typical TBD Max Unit A
Test Conditions Hibernate State Current VDDEXT =VDDMEM =VDDRTC = VDDUSB = 3.30 V, VDDOTP =VPPOTP =2.5 V, TJ = 25C, CLKIN = 0 MHz with voltage regulator off (VDDINT = 0 V) VDDRTC = 3.3 V, TJ = 25C VDDUSB = 3.3 V, TJ = 25C, Full Speed USB Transmit
IDDRTC IDDUSB-FS IDDUSB-HS IDDSLEEP1, 3
VDDRTC Current VDDUSB Current in Full/Low Speed Mode
TBD TBD TBD Table 22 + (TBD x VDDINT x fSCLK)4 Table 22
A mA mA mA4
VDDUSB Current in High Speed VDDUSB = 3.3 V, TJ = 25C, High Mode Speed USB Transmit VDDINIT Current in Sleep Mode fCCLK = 0 MHz, fSCLK > 0 MHz
IDDDEEPSLEEP1, 3 IDDINT3, 5
VDDINT Current in Deep Sleep Mode VDDINT Current
fCCLK = 0 MHz, fSCLK = 0 MHz fCCLK > 0 MHz, fSCLK 0 MHz
mA
mA Table 22 + (Table 24 x ASF) + (TBD x VDDINT x fSCLK)
1 2
See the ADSP-BF522/523/524/525/526/527 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. Includes current on VDDEXT, VDDUSB, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 3 Guaranteed maximum specifications. 4 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder. 5 See Table 21 for the list of IDDINT power vectors covered.
Table 20. Electrical Characteristics For ADSP-BF523/525/527 Processors
Parameter IDDDEEPSLEEP1 VDDINT Current in Deep Sleep Mode Test Conditions VDDINT = 1.0 V, fCCLK = 0 MHz, fSCLK = 0 MHz, TJ = 25C, ASF = 0.00 Min Typical 10 Max Unit mA
IDDSLEEP IDD-IDLE IDD-TYP IDD-TYP
VDDINT Current in Sleep Mode VDDINT = 1.0 V, fSCLK = 25 MHz, TJ = 25C VDDINT Current in Idle VDDINT Current VDDINT Current VDDINT = 1.0 V, fCCLK = 50 MHz, TJ = 25C, ASF = 0.44 VDDINT = 1.0 V, fCCLK = 400 MHz, TJ = 25C, ASF = 1.00 VDDINT = 1.15 V, fCCLK = 533 MHz, TJ = 25C, ASF = 1.00 VDDINT = 1.2 V, fCCLK = 600 MHz, TJ = 25C, ASF = 1.00
15 49 98 149
mA mA mA mA
IDD-TYP
VDDINT Current
176
mA
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Preliminary Technical Data
Parameter IDDHIBERNATE
1, 2
ADSP-BF522/523/524/525/526/527
Test Conditions Min Typical 40 Max Unit A
Table 20. Electrical Characteristics For ADSP-BF523/525/527 Processors (Continued)
Hibernate State Current
VDDEXT =VDDMEM =VDDRTC = VDDUSB = 3.30 V, VDDOTP =VPPOTP =2.5 V, TJ = 25C, CLKIN = 0 MHz with voltage regulator off (VDDINT = 0 V) VDDRTC = 3.3 V, TJ = 25C VDDUSB = 3.3 V, TJ = 25C, Full Speed USB Transmit
IDDRTC IDDUSB-FS IDDUSB-HS IDDSLEEP1, 3
VDDRTC Current VDDUSB Current in Full/Low Speed Mode
20 9 25 Table 23 + (0.43 x VDDINT x fSCLK)4 Table 23
A mA mA mA4
VDDUSB Current in High Speed VDDUSB = 3.3 V, TJ = 25C, Mode High Speed USB Transmit VDDINIT Current in Sleep Mode fCCLK = 0 MHz, fSCLK > 0 MHz
IDDDEEPSLEEP1, 3 IDDINT3, 5
VDDINT Current in Deep Sleep Mode VDDINT Current
fCCLK = 0 MHz, fSCLK = 0 MHz fCCLK > 0 MHz, fSCLK 0 MHz
mA
mA Table 23 + (Table 25 x ASF) + (0.43 x VDDINT x fSCLK)
1 2
See the ADSP-BF522/523/524/525/526/527 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. Includes current on VDDEXT, VDDUSB, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 3 Guaranteed maximum specifications. 4 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder. 5 See Table 21 for the list of IDDINT power vectors covered.
Total Power Dissipation
Total power dissipation has two components: 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 31 shows the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 22 or Table 23), and IDDINT specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (VDDINT) and frequency (Table 24 or Table 25). There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain. This part is subject to an Activity Scaling Factor (ASF) which represents application code running on the processor core and L1/L2 memories (Table 21). The ASF is combined with the CCLK Frequency and VDDINT dependent data in Table 24 or Table 25 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Table 21. Activity Scaling Factors (ASF)1
IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE
1
Activity Scaling Factor (ASF) 1.29 1.26 1.00 0.88 0.72 0.44
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF52x processors.
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ADSP-BF522/523/524/525/526/527
Table 22. ADSP-BF522/524/526 Static Current - IDD-DEEPSLEEP (mA)1
TJ (C) -40 -20 0 25 40 55 70 85 100 105
1 2
Preliminary Technical Data
2
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Voltage (VDDINT)2 TBD V TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Values are guaranteed maximum IDDDEEPSLEEP for non-automotive 400 MHz speed-grade devices. Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/524/526 on Page 27.
Table 23. ADSP-BF523/525/527 Static Current - IDD-DEEPSLEEP (mA)1
TJ (C) -40 -20 0 25 40 55 70 85 100 105
1 2
2
0.95 V 6.5 9.0 13.2 22.3 30.8 42.9 59.1 80.4 109.3 120.8
1.00 V 7.8 10.6 15.2 25.4 34.8 47.9 65.6 88.6 118.7 132.1
1.05 V 9.3 12.4 17.7 28.9 39.2 53.6 72.9 97.9 130.5 144.7
Voltage (VDDINT)2 1.10 V 1.15 V 11.1 13.1 14.6 17.0 20.4 23.5 32.8 37.2 44.1 49.6 59.9 66.9 80.8 89.7 107.8 119.2 143.2 157.4 158.8 174.2
1.20 V 15.4 19.8 27.0 42.1 55.7 74.6 99.4 131.5 172.8 190.9
1.25 V 18.0 22.9 30.9 47.6 62.5 83.2 110.2 145.1 189.7 209.3
1.30 V 21.0 26.4 35.3 53.7 70.0 92.6 122.0 159.8 208.1 229.2
Values are guaranteed maximum IDDDEEPSLEEP for non-automotive 400 MHz speed-grade devices. Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/525/527 on Page 29.
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Preliminary Technical Data
fCCLK (MHz)2 400 300 200 100
1 2
ADSP-BF522/523/524/525/526/527
Voltage (VDDINT)2 TBD V TBD V TBD TBD TBD TBD TBD TBD TBD TBD
Table 24. ADSP-BF522/524/526 Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
TBD V TBD TBD TBD TBD
TBD V TBD TBD TBD TBD
TBD V TBD TBD TBD TBD
TBD V TBD TBD TBD TBD
TBD V TBD TBD TBD TBD
TBD V TBD TBD TBD TBD
The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 31. Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/524/526 on Page 27.
Table 25. ADSP-BF523/525/527 Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
fCCLK (MHz)2 600 533 500 400 300 200 100
1 2
0.95 V n/a n/a n/a 69.8 53.4 36.9 20.5
1.00 V n/a n/a n/a 74.3 56.9 39.4 22.0
1.05 V n/a n/a 97.3 78.9 60.4 41.9 23.6
Voltage (VDDINT)2 1.10 V 1.15 V n/a 130.4 110.3 116.7 103.1 109.1 83.6 88.5 64.1 68.0 44.6 47.4 25.3 27.0
1.20 V 137.6 123.3 115.0 93.5 71.8 50.1 28.8
1.25 V 145.1 129.8 121.3 98.6 75.8 53.0 30.6
1.30 V 152.5 136.4 127.7 103.9 80.0 56.0 32.5
The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 31. Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/525/527 on Page 29.
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ADSP-BF522/523/524/525/526/527
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Rating
Preliminary Technical Data
time for the ADSP-BF522/524/526 processors is shown in Table 27. The ADSP-BF523/525/527 processors do not have a similar restriction. Table 27. Maximum OTP Memory Programming Time for ADSP-BF522/524/526 Processors
Temperature (TJ) VPPOTP Voltage (V) 6.9 7.0 7.1 25C tbd sec 2400 sec 1000 sec 85C tbd sec tbd sec tbd sec 110C tbd sec tbd sec tbd sec 125C tbd sec tbd sec tbd sec
-0.3 V to +1.26 V Internal Supply Voltage (VDDINT), for ADSP-BF523/525/527 processors TBD V to TBD V Internal Supply Voltage (VDDINT), for ADSP-BF522/524/526 processors External (I/O) Supply Voltage (VDDEXT/VDDMEM) Input Voltage1, 2 Input Voltage
1, 2, 3
-0.3 V to +3.8 V -0.5 V to +3.6 V -0.5 V to +5.5 V -0.5 V to +5.25 V -0.5 V to VDDEXT /VDDMEM+0.5 V 200 pF 80 mA (max) -65C to +150C +110C
Input Voltage1, 2, 4 Output Voltage Swing Load Capacitance5 IOH/IOL Current per Pin Group6 Storage Temperature Range Junction Temperature Underbias
1
The Absolute Maximum Ratings table specifies the maximum total source/sink (IOH/IOL) current for a group of pins. Permanent damage can occur if this value is exceeded. To understand this specification, if pins PH4, PH3, PH2, PH1, and PH0 from group 1 in the Total Current Pin Groups table, each were sourcing or sinking 2 mA each, the total current for those pins would be 10 mA. This would allow up to 70 mA total that could be sourced or sunk by the remaining pins in the group without damaging the device. For a list of all groups and their pins, see the Total Current Pin Groups table. Note that the VOL and VOL specifications have separate per-pin maximum current requirements, see the Electrical Characteristics For ADSPBF522/524/526 Processors and Electrical Characteristics For ADSP-BF523/525/527 Processors tables. Table 28. Total Current Pin Groups
Group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pins in Group PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13 PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7 PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1 PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9 PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1 BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU, TCK, TRST, TMS, DATA15, DATA14, DATA13, DATA12, DATA11, DATA10 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4 DATA3, , DATA2, , DATA1, , DATA0, ADDR19, ADDR18 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1 ABE1, ABE0, SA10, SWE, SCAS, SRAS SMS, SCKE, ARDY, AWE, ARE, AOE AMS3, AMS2, AMS1, AMS0, CLKOUT
Applies to 100% transient duty cycle. For other duty cycles see Table 26. 2 Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT 0.2 Volts. 3 Applies to balls SCL and SDA. 4 Applies to balls USB_DP, USB_DM, and USB_VBUS. 5 For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS. 6 For more information, see description preceeding Table 28.
Table 26. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V) TBD TBD TBD TBD TBD
1
VIN Max (V) TBD TBD TBD TBD TBD
Maximum Duty Cycle 100 % 40% 25% 15% 10%
Applies to all signal balls with the exception of CLKIN, XTAL, VROUT/EXT_WAKE1.
When programming OTP memory on the ADSPBF522/524/526 processors, the VPPOTP ball must be set to the write value specified in the Operating Conditions for ADSPBF522/524/526 on Page 27. There is a finite amount of cumulative time that the write voltage may be applied (dependent on voltage and junction temperature) to VPPOTP over the lifetime of the part. Therefore, maximum OTP memory programming
Rev. PrG
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February 2009
Preliminary Technical Data
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
ADSP-BF522/523/524/525/526/527
PACKAGE INFORMATION
The information presented in Figure 8 and Table 29 provides details about the package branding for the ADSPBF522/524/526 and ADSP-BF523/525/527 processors. For a complete listing of product availability, see Ordering Guide on Page 80.
a
ADSP-BF52x tppZccc vvvvvv.x n.n yyww country_of_origin
B
Figure 8. Product Information on Package
Table 29. Package Brand Information
Brand Key ADSP-BF52x t pp Z ccc vvvvvv.x n.n yyww
1
Field Description Product Name1 Temperature Range Package Type RoHS Compliant Designation See Ordering Guide Assembly Lot Code Silicon Revision Date Code
See product names in the Ordering Guide on Page 80.
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ADSP-BF522/523/524/525/526/527
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 30 and Figure 9 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 12 to Table 17, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's speed grade. Table 30. Clock and Reset Timing
Parameter Timing Requirements CLKIN Period tCKIN tCKINL CLKIN Low Pulse1 tCKINH CLKIN High Pulse1 tWRST RESET Asserted Pulse Width Low2 Switching Characteristic tBUFDLAY CLKIN to CLKBUF Delay
1
Preliminary Technical Data
Min 20.0 10.0 10.0 11 x tCKIN
Max 100.0
Unit ns ns ns ns ns
10
Applies to bypass mode and non-bypass mode. 2 Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH tBUFDLAY tBUFDLAY
CLKBUF
tWRST
RESET
Figure 9. Clock and Reset Timing
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February 2009
Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 31. Asynchronous Memory Read Cycle Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 tDO tHO Output Hold After CLKOUT 1
1
VDDMEM = 1.8 V Min Max 2.1 0.9 4.0 0.2 6.0 0.8
VDDMEM = 2.5/3.3 V Min Max 2.1 0.8 4.0 0.2 6.0 0.8
Unit ns ns ns ns ns ns
Output balls include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP 2 CYCLES
PROGRAMMED READ ACCESS 4 CYCLES
ACCESS EXTENDED 3 CYCLES
HOLD 1 CYCLE
CLKOUT
tDO
AMSx
tHO
ABE1-0
ADDR19-1
ABE, ADDRESS
AOE
tDO
ARE
tHO
tSARDY
ARDY
tHARDY tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure 10. Asynchronous Memory Read Cycle Timing
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February 2009
ADSP-BF522/523/524/525/526/527
Asynchronous Memory Write Cycle Timing
Table 32. Asynchronous Memory Write Cycle Timing
Preliminary Technical Data
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 tDO tHO Output Hold After CLKOUT 1
1
VDDMEM = 1.8 V Min Max 4.0 0.2 6.0 0.0 6.0 0.8
VDDMEM = 2.5/3.3 V Min Max 4.0 0.2 6.0 0.0 6.0 0.8
Unit ns ns ns ns ns ns
Output balls include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
SETUP 2 CYCLES
PROGRAMMED WRITE ACCESS 2 CYCLES
ACCESS EXTENDED 1 CYCLE
HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
ABE, ADDRESS
tDO
AWE
tHO
t SARDY
ARDY
t HARDY
tSARDY t ENDAT
DATA15-0 WRITE DATA
t DDAT
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. PrG
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February 2009
Preliminary Technical Data
NAND Flash Controller Interface Timing
Table 33 and Figure 12 on Page 41 through Figure 16 on Page 43 describe NAND Flash Controller Interface operations. Table 33. NAND Flash Controller Interface Timing
Parameter Write Cycle Switching Characteristics tCWL ND_CE Setup Time to AWE Low tCH ND_CE Hold Time From AWE High tCLEWL ND_CLE Setup Time to AWE Low tCLH ND_CLE Hold Time From AWE high tALEWL ND_ALE Setup Time to AWE Low tALH ND_ALE Hold Time From AWE High tWP1 AWE Low to AWE high tWHWL AWE High to AWE Low tWC1 AWE Low to AWE Low tDWS1 Data Setup Time for a Write Access tDWH Data Hold Time for a Write Access Read Cycle Switching Characteristics tCRL ND_CE Setup Time to ARE Low tCRH ND_CE Hold Time From ARE High 1 tRP ARE Low to ARE High tRHRL ARE High to ARE Low tRC1 ARE Low to ARE Low Timing Requirements tDRS Data Setup Time for a Read Transaction tDRH Data Hold Time for a Read Transaction Write Followed by Read Switching Characteristics tWHRL AWE High to ARE Low
1 2
ADSP-BF522/523/524/525/526/527
Min
Max
Unit
1.0 x tSCLK - 4 3.0 x tSCLK - 4 0.0 2.5 x tSCLK - 4 0.0 2.5 x tSCLK - 4 (WR_DLY +1.0) x tSCLK - 4 4.0 x tSCLK - 4 (WR_DLY +5.0) x tSCLK - 4 (WR_DLY +1.5) x tSCLK - 4 2.5 x tSCLK - 4
ns ns ns ns ns ns ns ns ns ns ns
1.0 x tSCLK - 4 3.0 x tSCLK - 4 (RD_DLY +1.0) x tSCLK - 4 4.0 x tSCLK - 4 (RD_DLY +5.0) x tSCLK - 4 8.02 0.0
ns ns ns ns ns ns ns
5.0 x tSCLK - 4
ns
WR_DLY and RD_DLY are defined in the NFC_CTL register. The only parameter that differs from 1.8V to 2.5/3.3V operation is tDRS, which is 8.0ns at 2.5/3.3V and is 11ns at 1.8V.
tCWL ND_CE tCH
ND_CLE tCLEWL tALEWL ND_ALE tWP AWE
tCLH tALH
tDWS ND_D0-D7
tDWH
Figure 12. NAND Flash Controller Interface Timing - Command Write Cycle
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
tCWL ND_CE tCLEWL ND_CLE
ND_ALE tALEWL tWP AWE tWC tDWS tDWH tDWS tDWH tALH tWHWL tALEWL tWP tALH
ND_D0-D7
Figure 13. NAND Flash Controller Interface Timing - Address Write Cycle
tCWL
ND_CE tCLEWL ND_CLE tALEWL ND_ALE tWP tWP
tWHWL
AWE tWC ARE tDWS tDWH
tDWS
tDWH
ND_D0-D7
Figure 14. NAND Flash Controller Interface Timing - Data Write Operation
Rev. PrG
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February 2009
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
tCRL
tCRH
ND_CE
ND_CLE
ND_ALE
AWE tRC tRP ARE tRHRL tRP
tDRS ND_D0-D7
tDRH
tDRS
tDRH
Figure 15. NAND Flash Controller Interface Timing - Data Read Operation
tCWL ND_CE
ND_CLE
tCLEWL
tCLH
ND_ALE tWP AWE tWHRL ARE tDWS tDWH tDRS tDWH tRP
ND_D0-D7
Figure 16. NAND Flash Controller Interface Timing - Write Followed by Read Operation
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February 2009
ADSP-BF522/523/524/525/526/527
SDRAM Interface Timing
Table 34. SDRAM Interface Timing
Preliminary Technical Data
ADSP-BF522/524/526 VDDMEM = 1.8 V Parameter Timing Requirements tSSDAT tHSDAT tSCLK tSCLKH tSCLKL tDCAD tHCAD tDSDAT tENSDAT
1 2
ADSP-BF523/525/527 VDDMEM = 1.8 V Min 1.5 1.0 10 2.5 2.5 Max VDDMEM = 2.5/3.3 V Min 1.5 0.8 7.5 2.5 2.5 4.0 1.0 1.0 5.0 0.0 0.0 4.0 4.0 Max Unit ns ns ns ns ns ns ns ns ns
VDDMEM = 2.5/3.3 V Min 1.5 0.8 12.5 2.5 2.5 Max
Min Data Setup Before CLKOUT Data Hold After CLKOUT CLKOUT Period1 CLKOUT Width High CLKOUT Width Low Command, Address, Data Delay After CLKOUT Command, Address, Data Hold After CLKOUT Data Disable After CLKOUT Data Enable After CLKOUT 0.0
2 2
Max
1.5 0.8 12.5 2.5 2.5 4.4 1.0 5.0
Switching Characteristics
4.4 1.0 5.0 0.0
The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here. Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
tSSDAT tHSDAT
DATA (IN)
tSCLKL
tDCAD tENSDAT
DATA (OUT)
tDSDAT tHCAD
tDCAD
COMMAND, ADDRESS (OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 17. SDRAM Interface Timing
Rev. PrG
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February 2009
Preliminary Technical Data
External DMA Request Timing
Table 35 and Figure 18 describe the External DMA Request operations. Table 35. External DMA Request Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Parameters tDR tDH tDMARACT tDMARINACT
1
VDDEXT/VDDMEM = 1.8 V1 Min Max DMARx Asserted to CLKOUT High Setup CLKOUT High to DMARx Deasserted Hold Time DMARx Active Pulse Width DMARx Inactive Pulse Width 8.0 0.0 1.0 x tSCLK 1.75 x tSCLK
VDDEXT/VDDMEM = 2.5/3.3 V Min Max Unit 6.0 0.0 1.0 x tSCLK 1.75 x tSCLK ns ns ns ns
Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and VDDMEM are NOT equal may require level shifting logic for correct operation.
CLKOUT
tDR
DMAR0/1 (Active Low)
tDH tDMARINACT
tDMARACT
DMAR0/1 (Active High)
tDMARACT
tDMARINACT
Figure 18. External DMA Request Timing
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Parallel Peripheral Interface Timing
Table 36 and Figure 19 on Page 46, Figure 23 on Page 50, and Figure 25 on Page 51 describe parallel peripheral interface operations. Table 36. Parallel Peripheral Interface Timing
Preliminary Technical Data
Parameter Timing Requirements tPCLKW PPI_CLK Width1 tPCLK PPI_CLK Period1 Timing Requirements - GP Input and Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK (Nonsampling Edge for Rx, Sampling Edge for Tx) tHFSPE External Frame Sync Hold After PPI_CLK tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics - GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK
1
ADSP-BF522/524/526 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max 6.4 25.0 6.7 1.0 3.5 1.5 8.8 1.7 8.8 1.8 1.8 1.7 8.8 6.4 25.0 6.7 1.0 3.5 1.5 8.8
ADSP-BF523/525/527 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max Unit 6.0 15.0 6.7 1.0 3.5 1.6 8.0 1.7 8.0 1.8 1.8 1.7 8.0 6.0 15.0 6.7 1.0 3.5 1.5 8.0 ns ns ns ns ns ns ns ns ns ns
PPI_CLK frequency cannot exceed fSCLK/2
DATA0 IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1
DATA1 IS SAMPLED
tSFSPE POLS = 1 PPI_FS1 POLS = 0
t
HFSPE
POLS = 1 PPI_FS2 POLS = 0 tSDRPE PPI_DATA t
HDRPE
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrG
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February 2009
Preliminary Technical Data
DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPI_CLK POLC = 0 PPI_CLK POLC = 1 t t POLS = 1 PPI_FS1 POLS = 0
SFSPE HFSPE
ADSP-BF522/523/524/525/526/527
DATA DRIVING/ FRAME SYNC SAMPLING EDGE
POLS = 1 PPI_FS2 POLS = 0 t t PPI_DATA
DDTPE
HDTPE
Figure 20. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC IS DRIVEN OUT POLC = 0 PPI_CLK
DATA0 IS SAMPLED
PPI_CLK POLC = 1 tDFSPE tHOFSPE POLS = 1 PPI_FS1 POLS = 0
POLS = 1 PPI_FS2 POLS = 0 tSDRPE tHDRPE
PPI_DATA
Figure 21. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
FRAME SYNC IS DRIVEN OUT
Preliminary Technical Data
DATA0 IS DRIVEN OUT
PPI_CLK POLC = 0 PPI_CLK POLC = 1 t tHOFSPE POLS = 1 PPI_FS1 POLS = 0
DFSPE
POLS = 1 PPI_FS2 POLS = 0 tDDTPE t
HDTPE
PPI_DATA
DATA0
Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrG
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February 2009
Preliminary Technical Data
Serial Ports
Table 37 through Table 40 on Page 51 and Figure 23 on Page 50 through Figure 25 on Page 51 describe serial port operations. Table 37. Serial Ports--External Clock
ADSP-BF522/523/524/525/526/527
ADSP-BF522/524/526 VDDEXT = 1.8 V Parameter Timing Requirements tSFSE tHFSE tSDRE tHDRE tSCLKEW tSCLKE tDFSE tHOFSE tDDTE tHDTE
1
ADSP-BF523/525/527 VDDEXT = 1.8 V Min 3.0 3.0 3.0 3.5 7.0 20.0 Max VDDEXT = 2.5/3.3 V Min 3.0 3.0 3.0 3.0 4.5 15.0 10.0 0.0 0.0 10.0 0.0 0.0 Max Unit ns ns ns ns ns ns 10.0 ns ns 10.0 ns ns
VDDEXT = 2.5/3.3 V Min 3.0 3.0 3.0 3.6 5.4 18.0 Max
Min TFSx/RFSx Setup Before TSCLKx/RSCLKx1 TFSx/RFSx Hold After TSCLKx/RSCLKx1 Receive Data Setup Before RSCLKx Receive Data Hold After RSCLKx TSCLKx/RSCLKx Width TSCLKx/RSCLKx Period TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 Transmit Data Delay After TSCLKx1 Transmit Data Hold After TSCLKx
1 1 1
Max
3.0 3.0 3.0 3.6 5.4 18.0 12.0 0.0 12.0 0.0
Switching Characteristics 12.0 0.0 12.0 0.0
Referenced to sample edge. 2 Referenced to drive edge.
Table 38. Serial Ports--Internal Clock
ADSP-BF522/524/526 VDDEXT = 1.8 V Parameter Timing Requirements tSFSI tHFSI tSDRI tHDRI tSCLKIW tSCLKI tDFSI tHOFSI tDDTI tHDTI
1 2
ADSP-BF523/525/527 VDDEXT = 1.8 V Min 11.0 -1.5 11.0 -1.5 4.5 20.0 Max VDDEXT = 2.5/3.3 V Min 9.6 -1.5 9.6 -1.5 4.5 15.0 3.0 -1.0 -1.0 3.0 -1.8 -1.5 3.0 3.0 Max Unit ns ns ns ns ns ns ns ns ns ns
VDDEXT = 2.5/3.3 V Min 11.3 -1.5 11.3 -1.5 5.4 18.0 Max
Min TFSx/RFSx Setup Before TSCLKx/RSCLKx1 TFSx/RFSx Hold After TSCLKx/RSCLKx Receive Data Setup Before RSCLKx1 Receive Data Hold After RSCLKx1 TSCLKx/RSCLKx Width TSCLKx/RSCLKx Period TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 Transmit Data Delay After TSCLKx1 Transmit Data Hold After TSCLKx
1 1
Max
11.3 -1.5 11.3 -1.5 5.4 18.0 3.0 -4.0 3.0 -1.8
Switching Characteristics
3.0 -4.0 3.0 -1.8
Referenced to sample edge. Referenced to drive edge.
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
DATA RECEIVE--INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE
Preliminary Technical Data
DATA RECEIVE--EXTERNAL CLOCK SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
DRx
tHDRI
DRx
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT--INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT--EXTERNAL CLOCK DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
DTx DTx
tDDTE tHDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 23. Serial Ports
Table 39. Serial Ports--Enable and Three-State
ADSP-BF522/524/526 VDDEXT = 1.8 V Parameter Switching Characteristics tDTENE tDDTTE tDTENI tDDTTI
1
ADSP-BF523/525/527 VDDEXT = 1.8 V Min 0.0 Max VDDEXT = 2.5/3.3 V Min 0.0 tSCLK+1 -2.0 -2.0 tSCLK+1 Max Unit ns tSCLK+1 ns ns tSCLK+1 ns
VDDEXT = 2.5/3.3 V Min 0.0 Max
Min Data Enable Delay from External TSCLKx1 Data Disable Delay from External TSCLKx1 Data Enable Delay from Internal TSCLKx1 Data Disable Delay from Internal TSCLKx
1
Max
0.0 10.0 -2.0 3.0
10.0 -2.0 3.0
Referenced to drive edge.
DRIVE TSCLKx DRIVE
tDTENE/I
DTx
tDDTTE/I
Figure 24. Serial Ports -- Enable and Three-State
Rev. PrG
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February 2009
Preliminary Technical Data
Table 40. Serial Ports -- External Late Frame Sync
ADSP-BF522/523/524/525/526/527
ADSP-BF522/524/526 VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max 10.0 0.0 0.0 ADSP-BF523/525/527 VDDEXT = 1.8 V Min Max 12.0 0.0 VDDEXT = 2.5/3.3 V Min Max Unit 10.0 ns ns
Parameter Switching Characteristics tDDTLFSE tDTENLFSE
1 2
Min Data Delay from Late External TFSx or External RFSx in multi-channel mode with MFD = 01, 2 Data Enable from External RFSx in multi-channel mode with MFD = 01, 2 0.0
Max 10.0
When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE. If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE WITH MCE = 1 DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFSE
DTx
1ST BIT
tDDTLFSE
LATE EXTERNAL TFSx DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
DTx
1ST BIT
tDDTLFSE
Figure 25. Serial Ports -- External Late Frame Sync
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Serial Peripheral Interface (SPI) Port--Master Timing
Table 41 and Figure 26 describe SPI port master operations. Table 41. Serial Peripheral Interface (SPI) Port--Master Timing
ADSP-BF522/524/526 VDDEXT = 2.5/3.3 V VDDEXT = 1.8 V Min Max Min Max 11.6 -1.5 11.6 -1.5
Preliminary Technical Data
Parameter Timing Requirements Data Input Valid to SCK Edge (Data tSSPIDM Input Setup) tHSPIDM SCK Sampling Edge to Data Input Invalid Switching Characteristics SPISELx low to First SCK Edge tSDSCIM Serial Clock High Period tSPICHM Serial Clock Low Period tSPICLM tSPICLK Serial Clock Period Last SCK Edge to SPISELx High tHDSM Sequential Transfer Delay tSPITDM tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold)
SPISELx (OUTPUT)
ADSP-BF523/525/527 VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max Min Max Unit 11.6 -1.5 9.6 -1.5 ns ns
2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 4 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 6 -1.0
2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 4 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 6 -1.0
2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 4 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 6 -1.0
2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 4 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 6 -1.0
ns ns ns ns ns ns ns ns
tSDSCIM
SCK (CPOL = 0) (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCK (CPOL = 1) (OUTPUT)
tSPICHM
tHDSPIDM
MOSI (OUTPUT) CPHA = 1 MISO (INPUT) MSB
tDDSPIDM
LSB
tSSPIDM
MSB VALID LSB VALID
tHSPIDM
tHDSPIDM
MOSI (OUTPUT) CPHA = 0 MISO (INPUT) MSB
tDDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port--Master Timing
Rev. PrG
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February 2009
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port--Slave Timing
Table 42 and Figure 27 describe SPI port slave operations. Table 42. Serial Peripheral Interface (SPI) Port--Slave Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirements Serial Clock High Period tSPICHS tSPICLS Serial Clock Low Period Serial Clock Period tSPICLK tHDS tSPITDS tSDSCI tSSPID Last SCK Edge to SPISS Not Asserted Sequential Transfer Delay SPISS Assertion to First SCK Edge Data Input Valid to SCK Edge (Data Input Setup) SCK Sampling Edge to Data Input Invalid tHSPID Switching Characteristics SPISS Assertion to Data Out Active tDSOE SPISS Deassertion to Data High Impedance tDSDHI SCK Edge to Data Out Valid (Data Out Delay) tDDSPID tHDSPID SCK Edge to Data Out Invalid (Data Out Hold)
ADSP-BF522/524/526 VDDEXT = 2.5/3.3 V VDDEXT = 1.8 V Min Max Min Max 2 x tSCLK -1.5 2 x tSCLK -1.5 4x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 1.6 1.6 0 0 0 12.0 8.5 10 2 x tSCLK -1.5 2 x tSCLK -1.5 4x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 1.6 1.6 0 0 0 12.0 8.5 10
ADSP-BF523/525/527 VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max Min Max Unit 2 x tSCLK -1.5 2 x tSCLK -1.5 4x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 1.6 1.6 0 0 0 12.0 8.5 10 2 x tSCLK -1.5 2 x tSCLK -1.5 4x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 2 x tSCLK -1.5 1.6 1.6 0 0 0 ns ns ns ns ns ns ns ns 10.3 ns 8 ns 10 ns ns
SPISS (INPUT)
tSPICHS
SCKx (CPOL = 0) (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCKx (CPOL = 1) (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
LSB
MISOx (OUTPUT) CPHA = 1 MOSIx (INPUT)
MSB
tSSPID
MSB VALID
tHSPID
LSB VALID
tDSOE
MISOx (OUTPUT) CPHA = 0 MOSIx (INPUT)
tHDSPID
MSB
tDDSPID
LSB
tDSDHI
tHSPID tSSPID
MSB VALID LSB VALID
Figure 27. Serial Peripheral Interface (SPI) Port--Slave Timing
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Universal Serial Bus (USB) On-The-Go--Receive and Transmit Timing
Table 43 describes the USB On-The-Go receive and transmit operations. Table 43. USB On-The-Go--Receive and Transmit Timing
Preliminary Technical Data
Parameter Timing Requirements fUSBS USB_XI Frequency FSUSB USB_XI Clock Frequency Stability
ADSP-BF522/524/526 ADSP-BF523/525/527 VDDEXT = VDDEXT = 1.8 V VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V 2.5/3.3 V Min Max Min Max Min Max Min Max Unit 9 -50 33.3 50 9 -50 33.3 50 9 -50 33.3 50 9 -50 33.3 MHz 50 ppm
Universal Asynchronous Receiver-Transmitter (UART) Ports--Receive and Transmit Timing
Figure 28 describes the UART ports receive and transmit operations. The maximum baud rate is SCLK/16. There is some latency between the generation of internal UART interrupts
CLKOUT (SAMPLE CLOCK)
and the external data operations. These latencies are negligible at the data transmission rates for the UART.
UARTx Rx RECEIVE INTERNAL UART RECEIVE INTERRUPT START UARTx Tx TRANSMIT INTERNAL UART TRANSMIT INTERRUPT
DATA(5-8) STOP
UART RECEIVE BIT SET BY DATA STOP ; CLEARED BY FIFO READ DATA(5-8) STOP (1-2)
UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT
Figure 28. UART Ports--Receive and Transmit Timing
Rev. PrG
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February 2009
Preliminary Technical Data
General-Purpose Port Timing
Table 44 and Figure 29 describe general-purpose port operations. Table 44. General-Purpose Port Timing
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirement General-Purpose Port Ball Input Pulse Width tSCLK + 1 tWFI Switching Characteristics General-Purpose Port Ball Output Delay from 0 tGPOD CLKOUT Low
ADSP-BF522/524/526 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max tSCLK + 1 9.66 0 9.66
ADSP-BF523/525/527 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max tSCLK + 1 0 8.2 tSCLK + 1 0 6.5
Unit ns ns
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 29. General-Purpose Port Timing
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Timer Cycle Timing
Table 45 and Figure 30 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 45. Timer Cycle Timing
ADSP-BF522/524/526 VDDEXT = 1.8 V Parameter Timing Characteristics tWL Timer Pulse Width Input Low (Measured In SCLK Cycles)1 Timer Pulse Width Input High (Measured In SCLK Cycles)1 Timer Input Setup Time Before CLKOUT Low2 Timer Input Hold Time After CLKOUT Low2 Timer Pulse Width Output (Measured In SCLK Cycles) Timer Output Update Delay After CLKOUT High tSCLK tSCLK tSCLK Min Max VDDEXT = 2.5/3.3 V Min Max Min
Preliminary Technical Data
ADSP-BF523/525/527 VDDEXT = 1.8 V Max VDDEXT = 2.5/3.3 V Min tSCLK Max Unit ns
tWH
tSCLK
tSCLK
tSCLK
tSCLK
ns
tTIS tTIH
5 -2
5 -2
8.1 -2
6.2 -2
ns ns
Switching Characteristics tHTO tTOD
1 2
tSCLK
(232-1)tSCLK 8.1
tSCLK
(232-1)tSCLK 8.1
tSCLK-1
(232-1)tSCLK 6
tSCLK-1
(232-1)tSCLK ns 6 ns
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode. Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRX OUTPUT
tHTO tTIS
TMRx INPUT
tTIH
tWH, tWL
Figure 30. Timer Cycle Timing
Rev. PrG
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February 2009
Preliminary Technical Data
Timer Clock Timing
Table 46 and Figure 31 describe timer clock timing. Table 46. Timer Clock Timing
ADSP-BF522/523/524/525/526/527
VDDEXT = 1.8 V Parameter Switching Characteristic tTODP Timer Output Update Delay After PPI_CLK High 12.0 Min Max
VDDEXT = 2.5/3.3 V Min Max 12.0 Unit ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 31. Timer Clock Timing
Up/Down Counter/Rotary Encoder Timing
Table 47. Up/Down Counter/Rotary Encoder Timing
VDDEXT = 1.8 V Min Max tSCLK + 1 4.0 4.0 VDDEXT = 2.5/3.3 V Min Max tSCLK + 1 4.0 4.0
Parameter Timing Requirements tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width tCIS Counter Input Setup Time Before CLKOUT Low1 Counter Input Hold Time After CLKOUT Low1 tCIH
1
Unit ns ns ns
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLK OUT
tCIS
CUD/CDG/CZM
tCIH
tWCOUNT
Figure 32. Up/Down Counter/Rotary Encoder Timing
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
HOSTDP A/C Timing- Host Read Cycle
Table 48 describe the HOSTDP A/C Host Read Cycle timing requirements. Table 48. Host Read Cycle Timing Requirements
ADSP-BF522/524/526, VDDEXT = 2.5/3.3 V VDDEXT = 1.8 V Min Max Min Max 4 2.5 4 2.5
Preliminary Technical Data
tDRDYRDL + tDRDYRDL + tDRDYRDL + tDRDYRDL + tRDYPRD + tRDYPRD + tRDYPRD + tRDYPRD + tDRDHRDY tDRDHRDY tDRDHRDY tDRDHRDY tRDWL HOST_RD pulse width low 1.5 x tSCLK 1.5 x tSCLK 1.5 x tSCLK 1.5 x tSCLK (INT mode) + 8.7 + 8.7 + 8.7 + 8.7 tRDWH HOST_RD pulse width high or time 2 x tSCLK 2 x tSCLK 2 x tSCLK 2 x tSCLK between HOST_RD rising edge and HOST_WR falling edge tDRDHRDY HOST_RD rising edge delay after 0 0 0 0 HOST_ACK rising edge (ACK mode) Switching Characteristics tSDATRDY Data valid prior HOST_ACK rising 4.5 3.5 4.5 3.5 edge (ACK mode) 1.5 x tSCLK tDRDYRDL Host_ACK assertion delay after 1.5 x tSCLK 1.5 x tSCLK 1.5 x tSCLK HOST_RD/HOST_CE (ACK mode) tRDYPRD HOST_ACK low pulse-width for NM1 NM1 NM1 NM1 Read access (ACK mode) tDDARWH Data disable after HOST_RD 9.0 9.0 9.0 9.0 tACC Data valid after HOST_RD falling 1.5 x tSCLK 1.5 x tSCLK 1.5 x tSCLK 1.5 x tSCLK edge (INT mode) tHDARWH Data hold after HOST_RD rising 1.0 1.0 1.0 1.0 edge
1
Parameter Timing Requirements tSADRDL HOST_ADDR and HOST_CE Setup before HOST_RD falling edge tHADRDH HOST_ADDR and HOST_CE Hold after HOST_RD rising edge tRDWL HOST_RD pulse width low (ACK mode)
ADSP-BF523/525/527 VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max Min Max Unit 4 2.5 4 2.5 ns ns ns
ns ns
ns
ns ns ns ns ns ns
NM (Not Measured) -- This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
HOST_ADDR HOST_CE
tSADRDL
HOST_RD
tHADRDH tRDWL tRDWH
HOST_ACK
tDRDYRDL
tRDYPRD
tDRDHRDY tDDARWH tHDARWH
tSDATRDY
HOST_D15-0
tACC
Figure 33. HOSTDP A/C- Host Read Cycle
Rev. PrG
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February 2009
Preliminary Technical Data
HOSTDP A/C Timing- Host Write Cycle
Table 49 describes the HOSTDP A/C Host Write Cycle timing requirements. Table 49. Host Write Cycle Timing Requirements
ADSP-BF522/523/524/525/526/527
Parameter Timing Requirements tSADWRL HOST_ADDR/HOST_CE Setup before HOST_WR falling edge tHADWRH HOST_ADDR/HOST_CE Hold after HOST_WR rising edge tWRWL HOST_WR pulse width low (ACK mode) HOST_WR pulse width low (INT mode) tWRWH HOST_WR pulse width high or time between HOST_WR rising edge and HOST_RD falling edge tDWRHRDY HOST_WR rising edge delay after HOST_ACK rising edge (ACK mode) tHDATWH Data Hold after HOST_WR rising edge tSDATWH Data Setup before HOST_WR rising edge Switching Characteristics tDRDYWRL HOST_ACK low delay after HOST_WR/HOST_CE asserted (ACK mode) tRDYPWR HOST_ACK low pulse-width for Write access (ACK mode)
1
ADSP-BF522/524/526 VDDEXT = 2.5/3.3 V VDDEXT = 1.8 V Min Max Min Max 4 2.5 tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 x tSCLK + 8.7 2 x tSCLK 4 2.5 tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 x tSCLK + 8.7 2 x tSCLK
ADSP-BF523/525/527 VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max Min Max Unit 4 2.5 tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 x tSCLK + 8.7 2 x tSCLK 4 2.5 tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 x tSCLK + 8.7 2 x tSCLK ns ns ns
ns ns
0
0
0
0
ns
2.5 2.5
2.5 2.5
2.5 2.5
2.5 2.5
ns ns
1.5 x tSCLK
1.5 x tSCLK
1.5 x tSCLK
1.5 x tSCLK ns
NM1
NM1
NM1
NM1
ns
NM (Not Measured) -- This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
HOST_ADDR HOST_CE
tSADWRL
HOST_WR
tHADWRH tWRWL tWRWH
HOST_ACK
tDRDYWRL
tRDYPWR
tDWRHRDY tHDATWH
tSDATWH
HOST_D15-0
Figure 34. HOSTDP A/C- Host Write Cycle
Rev. PrG
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Page 59 of 80 |
February 2009
ADSP-BF522/523/524/525/526/527
10/100 Ethernet MAC Controller Timing
Table 50 through Table 55 and Figure 35 through Figure 40 describe the 10/100 Ethernet MAC Controller operations. Table 50. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter tERXCLKF tERXCLKW tERXCLKIS tERXCLKIH
1
Preliminary Technical Data
1
ERxCLK Frequency (fSCLK = SCLK Frequency) ERxCLK Width (tERxCLK = ERxCLK Period) Rx Input Valid to ERxCLK Rising Edge (Data In Setup) ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
VDDEXT = 1.8 V Min Max None 25 + 1% fSCLK + 1% tERxCLK x 40% tERxCLK x 60% 7.5 7.5
VDDEXT = 2.5/3.3 V Min Max None 25 + 1% fSCLK + 1% tERxCLK x 35% tERxCLK x 65% 7.5 7.5
Unit MHz ns ns ns
MII inputs synchronous to ERxCLK are ERxD3-0, ERxDV, and ERxER.
Table 51. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter tETXCLKF tETXCLKW tETXCLKOV tETXCLKOH
1
1
VDDEXT = 1.8 V Min Max ETxCLK Frequency (fSCLK = SCLK Frequency) None 25 + 1% fSCLK + 1% ETxCLK Width (tETxCLK = ETxCLK Period) tETxCLK x 40% tETxCLK x 60% ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) 20 ETxCLK Rising Edge to Tx Output Invalid (Data Out 0 Hold)
VDDEXT = 2.5/3.3 V Min Max None 25 + 1% fSCLK + 1% tETxCLK x 35% tETxCLK x 65% 20 0
Unit MHz ns ns ns
MII outputs synchronous to ETxCLK are ETxD3-0.
Table 52. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter1 tEREFCLKF tEREFCLKW tEREFCLKIS tEREFCLKIH
1
REF_CLK Frequency (fSCLK = SCLK Frequency) EREF_CLK Width (tEREFCLK = EREFCLK Period) Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup) RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min Max Min Max None 50 + 1% None 50 + 1% 2 x fSCLK + 1% 2 x fSCLK + 1% tEREFCLK x 40% tEREFCLK x 60% tEREFCLK x 35% tEREFCLK x 65% 4 4 2 2
Unit MHz ns ns ns
RMII inputs synchronous to RMII REF_CLK are ERxD1-0, RMII CRS_DV, and ERxER.
Table 53. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
ADSP-BF522/524/526 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max 8.1 8.1 2 2 ADSP-BF523/525/527 VDDEXT = VDDEXT = 1.8 V 2.5/3.3 V Min Max Min Max Unit 7.5 7.5 ns 2 2 ns
Parameter1 tEREFCLKOV tEREFCLKOH
1
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid) RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
RMII outputs synchronous to RMII REF_CLK are ETxD1-0.
Rev. PrG
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Page 60 of 80 |
February 2009
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
VDDEXT = 1.8 V VDDEXT = 2.5/3.3 V Min tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tETxCLK x 1.5 Max Unit ns ns ns ns
Table 54. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter tECOLH tECOLL tECRSH tECRSL
1
1, 2
Min COL Pulse Width High COL Pulse Width Low CRS Pulse Width High CRS Pulse Width Low tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tERxCLK x 1.5 tETxCLK x 1.5 tETxCLK x 1.5
Max
MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks. 2 The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 55. 10/100 Ethernet MAC Controller Timing: MII Station Management
ADSP-BF522/524/526 VDDEXT = 1.8 V Parameter1 tMDIOS tMDCIH tMDCOV tMDCOH
1
ADSP-BF523/525/527 VDDEXT = 1.8 V Min 10 10 25 -1 Max VDDEXT = 2.5/3.3 V Min 10 10 25 -1 Max Unit ns ns ns ns
VDDEXT = 2.5/3.3 V Min 11.5 11.5 25 -1 Max
Min MDIO Input Valid to MDC Rising Edge (Setup) MDC Rising Edge to MDIO Input Invalid (Hold) MDC Falling Edge to MDIO Output Valid MDC Falling Edge to MDIO Output Invalid (Hold) 11.5 11.5 25 -1
Max
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. MDIO is a bidirectional data line.
tERXCLK
ERx_CLK
tERXCLKW
ERxD3-0 ERxDV ERxER
tERXCLKIS
tERXCLKIH
Figure 35. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLK
MII TxCLK
tETXCLKW tETXCLKOH
ETxD3-0 ETxEN
tETXCLKOV
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
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ADSP-BF522/523/524/525/526/527
tREFCLK
RMII _REF_CLK
Preliminary Technical Data
tREFCLKW
ERxD1-0 ERxDV ERxER
tREFCLKIS
tREFCLKIH
Figure 37. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
tREFCLK
RMII _REF_CLK
tREFCLKOH
ETxD1-0 ETxEN
tREFCLKOV
Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
MII CRS, COL
tECRSH tECOLH
tECRSL tECOLL
Figure 39. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
MDC (OUTPUT)
tMDCOH
MDIO (OUTPUT)
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 40. 10/100 Ethernet MAC Controller Timing: MII Station Management
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Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 56 and Figure 41 describe JTAG port operations. Table 56. JTAG Port Timing
ADSP-BF522/523/524/525/526/527
VDDEXT = 1.8 V Parameter Timing Parameters tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW tDTDO tDSYS
1 2
VDDEXT = 2.5/3.3 V Min 20 4 4 12 5 4 Max Unit ns ns ns ns ns TCK 10 12 ns ns
Min TCK Period TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High System Inputs Setup Before TCK High System Inputs Hold After TCK High
2 1 1
Max
20 4 4 12 5 4 10
3
TRST Pulse Width (measured in TCK cycles) TDO Delay from TCK Low System Outputs Delay After TCK Low
Switching Characteristics 12
System Inputs = DATA15-0, ARDY, SCL, SDA, PF15-0, PG15-0, PH15-0, TCK, TRST, RESET, NMI, BMODE3-0. 50 MHz Maximum 3 System Outputs = DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15-0, PG15-0, PH15-0, TDO, EMU.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 41. JTAG Port Timing
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ADSP-BF522/523/524/525/526/527
OUTPUT DRIVE CURRENTS
Figure 42 through Figure 56 show typical current-voltage characteristics for the output drivers of the ADSP-BF523/525/527 and ADSP-BF522/524/526 processors.
200 160 120
SOURCE CURRENT (mA)
Preliminary Technical Data
The curves represent the current drive capability of the output drivers. See Table 10 on Page 22 for information about which driver type corresponds to a particular ball.
240 VDDEXT = 3.6V @ - 40C VDDEXT = 3.3V @ 25C VDDEXT = 3.0V @ 105C
VDDEXT = 3.6V @ - 40C VDDEXT = 3.3V @ 25C VDDEXT = 3.0V @ 105C
SOURCE CURRENT (mA)
200 160 120 80 40 0 - 40 - 80 - 120 - 160 - 200 - 240
80 40 0 - 40 - 80 - 120 - 160 - 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) VOL VOH
VOH
VOL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 42. Driver Type A Current (3.3V VDDEXT/VDDMEM)
160 VDDEXT = 2.75V @ - 40C 120 80
SOURCE CURRENT (mA) SOURCE CURRENT (mA)
Figure 45. Driver Type B Current (3.3V VDDEXT/VDDMEM)
160 VDDEXT = 2.75V @ - 40C 120 80 40 VOH 0 - 40 - 80 VOL - 120 - 160 - 200 VDDEXT = 2.5V @ 25C VDDEXT = 2.25V @ 105C
VDDEXT = 2.5V @ 25C VDDEXT = 2.25V @ 105C
40 VOH 0 - 40 - 80 VOL - 120 - 160 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 43. Driver Type A Current (2.5V VDDEXT/VDDMEM)
80 VDDEXT = 1.9V @ - 40C 60 40
SOURCE CURRENT (mA) SOURCE CURRENT (mA)
Figure 46. Driver Type B Current (2.5V VDDEXT/VDDMEM)
80 VDDEXT = 1.9V @ - 40C 60 40 20 0 - 20 - 40 - 60 - 80 - 100 VDDEXT = 1.8V @ 25C VDDEXT = 1.7V @ 105C VOH
VDDEXT = 1.8V @ 25C VDDEXT = 1.7V @ 105C VOH
20 0 - 20 - 40 - 60 - 80 0 0.5 1.0 SOURCE VOLTAGE (V) 1.5
VOL
VOL
0
0.5
1.0 SOURCE VOLTAGE (V)
1.5
Figure 44. Driver Type A Current (1.8V VDDEXT/VDDMEM)
Figure 47. Driver Type B Current (1.8V VDDEXT/VDDMEM)
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Preliminary Technical Data
100 80 60
SOURCE CURRENT (mA)
ADSP-BF522/523/524/525/526/527
160 VDDEXT = 3.6V @ - 40C VDDEXT = 3.3V @ 25C VDDEXT = 3.0V @ 105C
SOURCE CURRENT (mA)
VDDEXT = 3.6V @ - 40C 120 80 40 0 - 40 - 80 VOL - 120 - 160 VDDEXT = 3.3V @ 25C VDDEXT = 3.0V @ 105C VOH
40 VOH 20 0 - 20 - 40 - 60 - 80 - 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) VOL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 48. Driver Type C Current (3.3V VDDEXT/VDDMEM)
80 VDDEXT = 2.75V @ - 40C 60 40
SOURCE CURRENT (mA) SOURCE CURRENT (mA)
Figure 51. Driver Type D Current (3.3V VDDEXT/VDDMEM)
120 100 80 60 40 20 0 - 20 - 40 - 60 - 80 - 100 VOL VOH VDDEXT = 2.75V @ - 40C VDDEXT = 2.5V @ 25C VDDEXT = 2.25V @ 105C
VDDEXT = 2.5V @ 25C VDDEXT = 2.25V @ 105C
20 VOH 0 - 20 - 40 VOL - 60 - 80 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V)
- 120 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V)
Figure 49. Drive Type C Current (2.5V VDDEXT/VDDMEM)
40 VDDEXT = 1.9V @ - 40C 30 20
SOURCE CURRENT (mA)
Figure 52. Driver Type D Current (2.5V VDDEXT/VDDMEM)
60 VDDEXT = 1.9V @ - 40C 40
SOURCE CURRENT (mA)
VDDEXT = 1.8V @ 25C VDDEXT = 1.7V @ 105C VOH
VDDEXT = 1.8V @ 25C VDDEXT = 1.7V @ 105C
10 0 - 10
20 VOH 0
VOL - 20 - 30 - 40 0 0.5 1.0 SOURCE VOLTAGE (V) 1.5
- 20 VOL - 40
- 60 0 0.5 1.0 SOURCE VOLTAGE (V) 1.5
Figure 50. Driver Type C Current (1.8V VDDEXT/VDDMEM)
Figure 53. Driver Type D Current (1.8V VDDEXT/VDDMEM)
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ADSP-BF522/523/524/525/526/527
60 50 40 30
SOURCE CURRENT (mA)
Preliminary Technical Data
VDDEXT = 3.6V @ - 40C VDDEXT = 3.3V @ 25C VDDEXT = 3.0V @ 105C
20 10 0 - 10 - 20 - 30 - 40 - 50 - 60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) VOL
Figure 54. Driver Type E Current (3.3V VDDEXT/VDDMEM)
40 VDDEXT = 2.75V @ - 40C 30 20
SOURCE CURRENT (mA)
VDDEXT = 2.5V @ 25C VDDEXT = 2.25V @ 105C
10 0 -10 VOL - 20 - 30 - 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V)
Figure 55. Driver Type E Current (2.5V VDDEXT/VDDMEM)
20 VDDEXT = 1.9V @ - 40C 15 10
SOURCE CURRENT (mA)
VDDEXT = 1.8V @ 25C VDDEXT = 1.7V @ 105C
5 0 -5 VOL - 10 - 15 - 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V)
Figure 56. Driver Type E Current (1.8V VDDEXT/VDDMEM)
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Preliminary Technical Data
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 57 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/2.5 V/3.3 V.
ADSP-BF522/523/524/525/526/527
Output Disable Time Measurement
Output balls are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 58. t DIS = t DIS_MEASURED - t DECAY The time for the voltage on the bus to decay by V is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: t DECAY = ( C L V ) I L
INPUT OR OUTPUT
V MEAS
VMEAS
Figure 57. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8V. The time tDIS_MEASURED is the interval from when the reference signal switches, to when the output voltage decays V from the measured output high or output low voltage.
Output Enable Time Measurement
Output balls are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 58.
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the processor's output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on Page 38 (for example tDSDAT for an SDRAM write cycle as shown in SDRAM Interface Timing on Page 44).
REFERENCE SIGNAL
tDIS_MEASURED tDIS
VOH (MEASURED) VOL (MEASURED)
tENA_MEASURED tENA
VOH (MEASURED)
V
VOH(MEASURED) VTRIP (HIGH) VTRIP (LOW) VOL (MEASURED)
VOL (MEASURED) + V
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE
Figure 58. Output Enable/Disable
The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or VTRIP(low). For VDDEXT/VDDMEM (nominal) = 1.8V, VTRIP (high) is 1.05V, and VTRIP (low) is 0.75V. For VDDEXT/VDDMEM (nominal) = 2.5V, VTRIP (high) is 1.5V and VTRIP (low) is 1.0V. For VDDEXT/VDDMEM (nominal) = 3.3V, VTRIP (high) is 1.9V, and VTRIP (low) is 1.4V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED - t TRIP If multiple balls (such as the data bus) are enabled, the measurement value is that of the first ball to start driving.
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ADSP-BF522/523/524/525/526/527
Capacitive Loading
Output delays and holds are based on standard capacitive loads of an average of 6 pF on all balls (see Figure 59). VLOAD is equal to (VDDEXT/VDDMEM) /2. The graphs of Figure 60 through Figure 71 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.
TESTER PIN ELECTRONICS 50 VLOAD 45 70 ZO = 50 (impedance) TD = 4.04 1.18 ns 0.5pF 2pF 400 T1 DUT OUTPUT
Preliminary Technical Data
50 4pF
NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 59. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
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Preliminary Technical Data
12
RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%)
ADSP-BF522/523/524/525/526/527
9 8 tRISE 7 6 tFALL 5 4 3 2 1 0 tRISE = 1.8V @ 25C tFALL = 1.8V @ 25C 0 50 100 150 200
10 tRISE 8 tFALL 6
4
2
tRISE = 1.8V @ 25C tFALL = 1.8V @ 25C
0 0 50 100 150 200 LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 60. Driver Type A Typical Rise and Fall Times (10%-90%) versus Load Capacitance (1.8V VDDEXT/VDDMEM)
8 7 6 5 tFALL 4 3 2 1 0 0 50 100 150 200 LOAD CAPACITANCE (pF) tRISE = 2.5V @ 25C tFALL = 2.5V @ 25C
Figure 63. Driver Type B Typical Rise and Fall Times (10%-90%) versus Load Capacitance (1.8V VDDEXT/VDDMEM)
7 6 5 tRISE 4 tFALL 3 2 1
RISE AND FALL TIME (10% TO 90%)
tRISE
RISE AND FALL TIME (10% TO 90%)
tRISE = 2.5V @ 25C tFALL = 2.5V @ 25C
0 0 50 100 150 200 LOAD CAPACITANCE (pF)
Figure 61. Driver Type A Typical Rise and Fall Times (10%-90%) versus Load Capacitance (2.5V VDDEXT/VDDMEM)
6
Figure 64. Driver Type B Typical Rise and Fall Times (10%-90%) versus Load Capacitance (2.5V VDDEXT/VDDMEM)
6
RISE AND FALL TIME (10% TO 90%)
5 tRISE 4 tFALL 3
RISE AND FALL TIME (10% TO 90%)
5 tRISE 4 tFALL 3
2
2
1 tRISE = 3.3V @ 25C 0 0 50 100 150 tFALL = 3.3V @ 25C
1 tRISE = 3.3V @ 25C 0 tFALL = 3.3V @ 25C 0 50 100 150 200
200
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 62. Driver Type A Typical Rise and Fall Times (10%-90%) versus Load Capacitance (3.3V VDDEXT/VDDMEM)
Figure 65. Driver Type B Typical Rise and Fall Times (10%-90%) versus Load Capacitance (3.3V VDDEXT/VDDMEM)
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ADSP-BF522/523/524/525/526/527
25 14 12
RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%)
Preliminary Technical Data
20 tRISE 15
tRISE 10 tFALL 8 6 4 2
tFALL
10
5 tRISE = 1.8V @ 25C tFALL = 1.8V @ 25C 0 0 50 100 150 200 LOAD CAPACITANCE (pF)
tRISE = 1.8V @ 25C tFALL = 1.8V @ 25C
0 0 50 100 150 200 LOAD CAPACITANCE (pF)
Figure 66. Driver Type C Typical Rise and Fall Times (10%-90%) versus Load Capacitance (1.8V VDDEXT/VDDMEM)
16
Figure 69. Driver Type D Typical Rise and Fall Times (10%-90%) versus Load Capacitance (1.8V VDDEXT/VDDMEM)
10 9
RISE AND FALL TIME (10% TO 90%)
RISE AND FALL TIME (10% TO 90%)
14 12 tRISE 10 tFALL 8 6 4 2 0 0 50 100 150 200 LOAD CAPACITANCE (pF) tRISE = 2.5V @ 25C tFALL = 2.5V @ 25C
8 7 6 5 4 3 2 1 0 0 50 100 150 200 LOAD CAPACITANCE (pF) tRISE = 2.5V @ 25C tFALL = 2.5V @ 25C tRISE tFALL
Figure 67. Driver Type C Typical Rise and Fall Times (10%-90%) versus Load Capacitance (2.5V VDDEXT/VDDMEM)
14 12 tRISE 10 8 tFALL 6 4 2
Figure 70. Driver Type D Typical Rise and Fall Times (10%-90%) versus Load Capacitance (2.5V VDDEXT/VDDMEM)
8 7 6 5 tFALL 4 3 2 1 0 tRISE = 3.3V @ 25C tFALL = 3.3V @ 25C 0 50 100 150 200
RISE AND FALL TIME (10% TO 90%)
RISE AND FALL TIME (10% TO 90%)
tRISE
tRISE = 3.3V @ 25C tFALL = 3.3V @ 25C 0 50 100 150 200
0
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 68. Driver Type C Typical Rise and Fall Times (10%-90%) versus Load Capacitance (3.3V VDDEXT/VDDMEM)
Figure 71. Driver Type D Typical Rise and Fall Times (10%-90%) versus Load Capacitance (3.3V VDDEXT/VDDMEM)
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Preliminary Technical Data
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( JT x P D ) where: TJ = Junction temperature ( C) TCASE = Case temperature ( C) measured by customer at top center of package.
ADSP-BF522/523/524/525/526/527
Table 58. Thermal Characteristics (BC-289-2)
Parameter JA JMA JMA JB JC JT JT JT Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 34.5 31.1 29.8 20.3 8.8 0.24 0.44 0.53 Unit C/W C/W C/W C/W C/W C/W C/W C/W
JT = From Table 58
PD = Power dissipation -- For a description, see Total Power Dissipation on Page 33. Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + ( JA x P D ) where: TA = Ambient temperature ( C) Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. Values of JB are provided for package comparison and printed circuit board design considerations. In Table 58, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 57. Thermal Characteristics (BC-208-1)
Parameter JA JMA JMA JB JC JT JT JT Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 23.20 20.20 19.20 13.05 6.92 0.18 0.27 0.32 Unit C/W C/W C/W C/W C/W C/W C/W C/W
0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow
0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow
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Preliminary Technical Data 289-BALL CSP_BGA BALL ASSIGNMENT
Table 59 lists the CSP_BGA balls by signal mnemonic.
ADSP-BF522/523/524/525/526/527
Table 60 on Page 73 lists the CSP_BGA by ball number.
Table 59. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal No. No. No. No. No. No. ABE0/SDQM0 AB9 DATA9 P1 GND N9 VPPOTP AB11 PH12 M23 VDDEXT N17 VDDMEM ABE1/SDQM1 AC9 DATA10 P2 GND N10 PF0 A7 PH13 N22 VDDEXT P17 VDDMEM ADDR1 AB8 DATA11 R2 GND N11 PF1 B8 PH14 N23 VDDEXT R17 VDDMEM ADDR2 AC8 DATA12 N1 GND N12 PF2 A8 PH15 P22 VDDEXT T17 VDDMEM ADDR3 AB7 DATA13 N2 GND N13 PF3 B9 PPI_CLK/TMRCLK A6 VDDEXT U17 VDDMEM ADDR4 AC7 DATA14 M2 GND N14 PF4 B11 PPI_FS1/TMR0 B7 VDDINT B5 VDDMEM ADDR5 AC6 DATA15 M1 GND N15 PF5 B10 RESET V22 VDDINT H8 VDDMEM ADDR6 AB6 EMU J2 GND P9 PF6 B12 RTXI U23 VDDINT H9 VDDMEM ADDR7 AB4 EXT_WAKE0 AC19 GND P10 PF7 B13 RTXO V23 VDDINT H10 VDDMEM ADDR8 AB5 GND A1 GND P11 PF8 B16 SA10 AC10 VDDINT H11 VDDMEM ADDR9 AC5 GND A23 GND P12 PF9 A20 SCAS AC11 VDDINT H12 VDDMEM ADDR10 AC4 GND B6 GND P13 PF10 B15 SCKE AB13 VDDINT H13 VDDOTP ADDR11 AB3 GND1 G16 GND P14 PF11 B17 SCL B22 VDDINT H14 VDDRTC ADDR12 AC3 GND G17 GND P15 PF12 B18 SDA C22 VDDINT H15 VDDUSB ADDR13 AB2 GND1 H17 GND R9 PF13 B19 SMS AC13 VDDINT H16 VDDUSB ADDR14 AC2 GND H22 GND R10 PF14 A9 SRAS AB12 VDDINT J8 NC ADDR15 AA2 GND1 J22 GND R11 PF15 A10 SS/PG AC20 VDDINT J16 VROUT/EXT_WAKE1 ADDR16 W2 GND J9 GND R12 PG0 H2 SWE AB10 VDDINT K8 VRSEL/VDDEXT ADDR17 Y2 GND J10 GND R13 PG1 G1 TCK L1 VDDINT K16 XTAL ADDR18 AA1 GND J11 GND R14 PG2 H1 TDI J1 VDDINT L8 ADDR19 AB1 GND J12 GND R15 PG3 F1 TDO K1 VDDINT L16 AMS0 AC17 GND J13 GND T22 PG4 D1 TMS L2 VDDINT M8 AMS1 AB16 GND J14 GND AC1 PG5 D2 TRST K2 VDDINT M16 AMS2 AC16 GND J15 GND AC23 PG6 C2 USB_DM AB21 VDDINT N8 AMS3 AB15 GND K9 NC A15 PG7 B1 USB_DP AA22 VDDINT N16 AOE AC15 GND K10 NC A16 PG8 C1 USB_ID Y22 VDDINT P8 ARDY AC14 GND K11 NC A17 PG9 B2 USB_RSET AC21 VDDINT P16 ARE AB17 GND K12 NC A18 PG10 B4 USB_VBUS AB20 VDDINT R8 AWE AB14 GND K13 NC A19 PG11 B3 USB_VREF AC22 VDDINT R16 BMODE0 G2 GND K14 NC A21 PG12 A2 USB_XI AB23 VDDINT T8 BMODE1 F2 GND K15 NC A22 PG13 A3 USB_XO AA23 VDDINT T9 BMODE2 E1 GND L9 NC B20 PG14 A4 VDDEXT G7 VDDINT T10 BMODE3 E2 GND L10 NC B21 PG15 A5 VDDEXT G8 VDDINT T11 CLKBUF AB19 GND L11 NC B23 PH0 A11 VDDEXT G9 VDDINT T12 CLKIN R23 GND L12 NC C23 PH1 A12 VDDEXT G10 VDDINT T13 CLKOUT AB18 GND L13 NC D22 PH2 A13 VDDEXT G11 VDDINT T14 DATA0 Y1 GND L14 NC D23 PH3 B14 VDDEXT G12 VDDINT T15 DATA1 V2 GND L15 NC E22 PH4 A14 VDDEXT G13 VDDINT T16 DATA2 W1 GND M9 NC E23 PH5 K23 VDDEXT G14 VDDMEM J7 DATA3 U2 GND M10 NC F22 PH6 K22 VDDEXT G15 VDDMEM K7 DATA4 V1 GND M11 NC F23 PH7 L23 VDDEXT H7 VDDMEM L7 DATA5 U1 GND M12 NC G22 PH8 L22 VDDEXT J17 VDDMEM M7 DATA6 T2 GND M13 NC H23 PH9 T23 VDDEXT K17 VDDMEM N7 DATA7 T1 GND M14 NC J23 PH10 M22 VDDEXT L17 VDDMEM P7 DATA8 R1 GND M15 NMI U22 PH11 R22 VDDEXT M17 VDDMEM R7 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.
For ADSP-BF52xC compatibility, connect this ball to VDDEXT.
Ball No. T7 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 AC12 W23 W22 Y23 G23 AC18 AB22 P23
1
Rev. PrG
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Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
Table 60. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal No. No. No. No. No. No. No. A1 GND B23 NC H22 GND L22 PH8 P22 PH15 U22 NMI AC5 ADDR9 A2 PG12 C1 PG8 H23 NC L23 PH7 P23 XTAL U23 RTXI AC6 ADDR5 A3 PG13 C2 PG6 J1 TDI M1 DATA15 R1 DATA8 V1 DATA4 AC7 ADDR4 A4 PG14 C22 SDA J2 EMU M2 DATA14 R2 DATA11 V2 DATA1 AC8 ADDR2 A5 PG15 C23 NC J7 VDDMEM M7 VDDMEM R7 VDDMEM V22 RESET AC9 ABE1/SDQM1 A6 PPI_CLK/TMRCLK D1 PG4 J8 VDDINT M8 VDDINT R8 VDDINT V23 RTXO AC10 SA10 A7 PF0 D2 PG5 J9 GND M9 GND R9 GND W1 DATA2 AC11 SCAS A8 PF2 D22 NC J10 GND M10 GND R10 GND W2 ADDR16 AC12 VDDOTP A9 PF14 D23 NC J11 GND M11 GND R11 GND W22 VDDUSB AC13 SMS A10 PF15 E1 BMODE2 J12 GND M12 GND R12 GND W23 VDDRTC AC14 ARDY A11 PH0 E2 BMODE3 J13 GND M13 GND R13 GND Y1 DATA0 AC15 AOE A12 PH1 E22 NC J14 GND M14 GND R14 GND Y2 ADDR17 AC16 AMS2 A13 PH2 E23 NC J15 GND M15 GND R15 GND Y22 USB_ID AC17 AMS0 A14 PH4 F1 PG3 J16 VDDINT M16 VDDINT R16 VDDINT Y23 VDDUSB AC18 VROUT/EXT_WAKE1 A15 NC F2 BMODE1 J17 VDDEXT M17 VDDEXT R17 VDDEXT AA1 ADDR18 AC19 EXT_WAKE0 A16 NC F22 NC J22 GND1 M22 PH10 R22 PH11 AA2 ADDR15 AC20 SS/PG A17 NC F23 NC J23 NC M23 PH12 R23 CLKIN AA22 USB_DP AC21 USB_RSET A18 NC G1 PG1 K1 TDO N1 DATA12 T1 DATA7 AA23 USB_XO AC22 USB_VREF A19 NC G2 BMODE0 K2 TRST N2 DATA13 T2 DATA6 AB1 ADDR19 AC23 GND A20 PF9 G7 VDDEXT K7 VDDMEM N7 VDDMEM T7 VDDMEM AB2 ADDR13 A21 NC G8 VDDEXT K8 VDDINT N8 VDDINT T8 VDDINT AB3 ADDR11 A22 NC G9 VDDEXT K9 GND N9 GND T9 VDDINT AB4 ADDR7 A23 GND G10 VDDEXT K10 GND N10 GND T10 VDDINT AB5 ADDR8 B1 PG7 G11 VDDEXT K11 GND N11 GND T11 VDDINT AB6 ADDR6 B2 PG9 G12 VDDEXT K12 GND N12 GND T12 VDDINT AB7 ADDR3 B3 PG11 G13 VDDEXT K13 GND N13 GND T13 VDDINT AB8 ADDR1 B4 PG10 G14 VDDEXT K14 GND N14 GND T14 VDDINT AB9 ABE0/SDQM0 B5 VDDINT G15 VDDEXT K15 GND N15 GND T15 VDDINT AB10 SWE B6 GND G16 GND1 K16 VDDINT N16 VDDINT T16 VDDINT AB11 VPPOTP B7 PPI_FS1/TMR0 G17 GND K17 VDDEXT N17 VDDEXT T17 VDDEXT AB12 SRAS B8 PF1 G22 NC K22 PH6 N22 PH13 T22 GND AB13 SCKE B9 PF3 G23 NC K23 PH5 N23 PH14 T23 PH9 AB14 AWE B10 PF5 H1 PG2 L1 TCK P1 DATA9 U1 DATA5 AB15 AMS3 B11 PF4 H2 PG0 L2 TMS P2 DATA10 U2 DATA3 AB16 AMS1 B12 PF6 H7 VDDEXT L7 VDDMEM P7 VDDMEM U7 VDDMEM AB17 ARE B13 PF7 H8 VDDINT L8 VDDINT P8 VDDINT U8 VDDMEM AB18 CLKOUT B14 PH3 H9 VDDINT L9 GND P9 GND U9 VDDMEM AB19 CLKBUF B15 PF10 H10 VDDINT L10 GND P10 GND U10 VDDMEM AB20 USB_VBUS B16 PF8 H11 VDDINT L11 GND P11 GND U11 VDDMEM AB21 USB_DM B17 PF11 H12 VDDINT L12 GND P12 GND U12 VDDMEM AB22 VRSEL/VDDEXT B18 PF12 H13 VDDINT L13 GND P13 GND U13 VDDMEM AB23 USB_XI B19 PF13 H14 VDDINT L14 GND P14 GND U14 VDDMEM AC1 GND B20 NC H15 VDDINT L15 GND P15 GND U15 VDDMEM AC2 ADDR14 B21 NC H16 VDDINT L16 VDDINT P16 VDDINT U16 VDDMEM AC3 ADDR12 B22 SCL H17 GND1 L17 VDDEXT P17 VDDEXT U17 VDDEXT AC4 ADDR10 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.
1
For ADSP-BF52xC compatibility, connect this ball to VDDEXT.
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
Figure 72 shows the top view of the BC-289-2 CSP_BGA ball configuration. Figure 73 shows the bottom view of the BC-2892 CSP_BGA ball configuration.
A1 BALL PAD CORNER
Preliminary Technical Data
A B C D E F G H J K TOP VIEW L M N KEY: P R V DDINT GND NC T U V V DDEXT I/O V DDMEM W Y AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 72. 289-Ball CSP_BGA Ball Configuration (Top View)
A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y AA AB AC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V DDINT GND NC KEY: BOTTOM VIEW
V
DDEXT
I/O
V
DDMEM
Figure 73. 289-Ball CSP_BGA Ball Configuration (Bottom View)
Rev. PrG
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February 2009
Preliminary Technical Data 208-BALL CSP_BGA BALL ASSIGNMENT
Table 61 lists the CSP_BGA balls by signal mnemonic.
ADSP-BF522/523/524/525/526/527
Table 62 on Page 76 lists the CSP_BGA by ball number.
Table 61. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal ABE0/SDQM0 ABE1/SDQM1 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BMODE0 BMODE1 BMODE2 BMODE3 CLKBUF CLKIN CLKOUT DATA0 DATA1 Ball Signal No. V19 V20 DATA2 DATA3 Ball Signal No. Y7 W7 Y6 W6 Y5 W5 Y4 W4 Y3 W3 Y2 W2 W1 V1 T2 J20 A1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND NMI PF0 Ball Signal No. L12 L13 M9 PG6 PG7 PG8 Ball Signal No. M2 L1 L2 K1 K2 J1 J2 H1 H2 G1 A7 B7 A8 B8 A9 B9 B10 B11 B12 B13 B14 B15 B16 B17 G2 F2 B18 SS/PG SWE TCK TDI TDO TMS TRST USB_DM USB_DP USB_ID USB_RSET USB_VBUS USB_VREF USB_XI USB_XO VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT Ball Signal No. G19 VDDINT T20 V2 R1 T1 U2 U1 F20 E20 C20 E19 VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDOTP Ball No. P14 L8 M7 M8 N7 N8 P7 P8 P9 P10 P11 R20 A16 D19 G20 H20 F19 A10
W20 DATA4 W19 DATA5 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 J19 K19 L20 P19 DATA6 DATA8 DATA10 DATA12 DATA14 EMU GND GND GND GND GND GND GND W18 DATA7 W17 DATA9 W16 DATA11 W15 DATA13 W14 DATA15 W13 EXT_WAKE0 W12 GND W11 GND
M10 PG9 M11 PG10 M12 PG11 M13 PG12 N9 PG13 N10 PG14 N11 PG15 N12 PH0 N13 PH1 Y1 Y20 B19 F1 E1 E2 D1 D2 C1 C2 B1 B2 A2 B3 A3 B5 A5 B6 A6 R2 P1 P2 N1 N2 M1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PPI_CLK/TMRCLK PPI_FS1/TMR0 RESET RTXI RTXO SA10 SCAS SCKE SCL SDA SMS SRAS
D20 VDDMEM H19 VDDRTC A19 VDDUSB A18 VDDUSB G7 G8 G9 G10 G11 H7 H8 J7 J8 K7 K8 L7 G12 G13 G14 H14 J14 K14 L14 M14 N14 P12 P13 VROUT/EXT_WAKE1 VRSEL/VDDEXT XTAL
VPPOTP L19
A17 PF1 A20 PF2 B20 H9 PF3 PF4
A12 VDDEXT A13 VDDEXT
H10 PF5 H11 PF6 H12 PF7 H13 PF8 J9 J10 J11 J12 J13 K9 K10 K11 K12 K13 L9 L10 L11 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3 PG4 PG5
M19 GND N20 GND M20 GND N19 GND Y10 Y9 W9 C19 K20 Y8 W8 GND GND GND GND GND GND GND W10 GND
A14 VDDINT A15 VDDINT U19 VDDINT U20 VDDINT P20 A4 B4 R19 T19 VDDINT VDDINT VDDINT VDDINT VDDINT
A11 GND
NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.
Rev. PrG
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ADSP-BF522/523/524/525/526/527
Table 62. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Signal GND PF9 PF11 SCL PF13 PF15 PH0 PH2 PH4 XTAL CLKIN PH8 PH10 RTXI RTXO VDDRTC GND USB_XO USB_XI GND PF7 PF8 PF10 SDA PF12 PF14 PH1 PH3 PH5 PH6 PH7 PH9 PH11 PH12 PH13 PH14 PH15 RESET Ball No. B19 B20 C1 C2 C19 C20 D1 D2 D19 D20 E1 E2 E19 E20 F1 F2 F19 F20 G1 G2 G7 G8 G9 G10 G11 G12 G13 G14 G19 G20 H1 H2 H7 H8 H9 H10 H11 H12 Signal NMI GND PF5 PF6 CLKBUF USB_ID PF3 PF4 VDDUSB USB_RSET PF1 PF2 USB_VBUS USB_DP PF0 PPI_FS1/TMR0 VRSEL/VDDEXT USB_DM PG15 PPI_CLK/TMRCLK VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT SS/PG VDDUSB PG13 PG14 VDDEXT VDDEXT GND GND GND GND Ball No. H13 H14 H19 H20 J1 J2 J7 J8 J9 J10 J11 J12 J13 J14 J19 J20 K1 K2 K7 K8 K9 K10 K11 K12 K13 K14 K19 K20 L1 L2 L7 L8 L9 L10 L11 L12 L13 L14 Signal GND VDDINT USB_VREF VROUT/EXT_WAKE1 PG11 PG12 VDDEXT VDDEXT GND GND GND GND GND VDDINT AMS0 EXT_WAKE0 PG9 PG10 VDDEXT VDDEXT GND GND GND GND GND VDDINT AMS1 CLKOUT PG7 PG8 VDDEXT VDDMEM GND GND GND GND GND VDDINT Ball No. L19 L20 M1 M2 M7 M8 M9 Signal VPPOTP AMS3 PG5 PG6 VDDMEM VDDMEM GND
Preliminary Technical Data
Ball No. R1 R2 R19 R20 T1 T2 T19 T20 U1 U2 U19 U20 V1 V2 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 Signal TDI PG0 SMS VDDOTP TDO EMU SRAS SWE TRST TMS SA10 SCAS DATA15 TCK ABE0/SDQM0 ABE1/SDQM1 DATA14 DATA13 DATA11 DATA9 DATA7 DATA5 DATA3 DATA1 BMODE3 Ball No. Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal DATA10 DATA8 DATA6 DATA4 DATA2 DATA0 BMODE2 BMODE0 ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR9 ADDR7 ADDR5 ADDR3 GND
M10 GND M11 GND M12 GND M13 GND M14 VDDINT M19 AMS2 M20 ARE N1 N2 N7 N8 N9 N10 N11 N12 N13 N14 N19 N20 P1 P2 P7 P8 P9 P10 P11 P12 P13 P14 P19 P20 PG3 PG4 VDDMEM VDDMEM GND GND GND GND GND VDDINT AWE AOE PG1 PG2 VDDMEM VDDMEM VDDMEM VDDMEM VDDMEM VDDINT VDDINT VDDINT ARDY SCKE
W10 BMODE1 W11 ADDR18 W12 ADDR16 W13 ADDR14 W14 ADDR12 W15 ADDR10 W16 ADDR8 W17 ADDR6 W18 ADDR4 W19 ADDR2 W20 ADDR1 Y1 Y2 GND DATA12
NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.
Rev. PrG
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Page 76 of 80 |
February 2009
Preliminary Technical Data
Figure 74 shows the top view of the CSP_BGA ball configuration. Figure 75 shows the bottom view of the CSP_BGA ball configuration.
A1 BALL PAD CORNER
ADSP-BF522/523/524/525/526/527
KEY: VDDINT GND
VDDEXT
I/O
A B C D E F G H J K L M N P R T U V W Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TOP VIEW
VDDMEM
Figure 74. 208-Ball CSP_BGA Ball Configuration (Top View)
A1 BALL PAD CORNER
A B C D E F G H J K L M N P R T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
KEY: VDDINT GND
VDDEXT
I/O
VDDMEM
Figure 75. 208-Ball CSP_BGA Ball Configuration (Bottom View)
Rev. PrG
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February 2009
ADSP-BF522/523/524/525/526/527
OUTLINE DIMENSIONS
Dimensions in Figure 76, 289-Ball CSP_BGA (BC-289-2) are shown in millimeters.
Preliminary Technical Data
12.00 BSC SQ
0.5 BSC BALL PITCH
A B C D E F G H J K L M N P R T U V W Y AA AB AC
11.00 BSC SQ CL
A1 BALL PAD CORNER
A1 BALL PAD CORNER
CL
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TOP VIEW
BOTTOM VIEW
1.40 1.26 1.11 SIDE VIEW
0.20 MIN DETAIL A
NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT AND BALL HEIGHT. 3. MINIMUM BALL HEIGHT 0.20
0.08 MAX COPLANARITY SEATING PLANE DETAIL A
0.35 BALL DIAMETER 0.30 0.25
Figure 76. 289-Ball CSP_BGA (BC-289-2)
Rev. PrG
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Page 78 of 80 |
February 2009
Preliminary Technical Data
17.10 17.00 SQ 16.90
ADSP-BF522/523/524/525/526/527
A1 CORNER INDEX AREA
A B C D E F G H J K L M N P R T U V W Y
20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 75 31
A1 BALL CORNER
15.20 BSC SQ
0.80 BSC
TOP VIEW *1.75 1.61 1.46 DETAIL A
BOTTOM VIEW 1.36 1.26 1.16 0.35 NOM 0.30 MIN *0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12
DETAIL A
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.
Figure 77. 208-Ball CSP_BGA (BC-208-2)
SURFACE MOUNT DESIGN
Table 63 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 63. Surface Mount Design Supplement
Package 289-Ball CSP_BGA 208-Ball CSP_BGA Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.26 mm diameter 0.40 mm diameter Ball Pad Size 0.35 mm diameter 0.50 mm diameter
Rev. PrG
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ADSP-BF522/523/524/525/526/527
ORDERING GUIDE
Table 64. ADSP-BF523/525/527 Processors
Model ADSP-BF523KBCZ-6 ADSP-BF523KBCZ-5 ADSP-BF525KBCZ-6 ADSP-BF525KBCZ-5 ADSP-BF527KBCZ-6 ADSP-BF527KBCZ-5 ADSP-BF523KBCZ-6A ADSP-BF523BBCZ-5A ADSP-BF525KBCZ-6A ADSP-BF525BBCZ-5A ADSP-BF527KBCZ-6A ADSP-BF527BBCZ-5A
1 2
Preliminary Technical Data
Package Description 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) 0C to +70C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40C to +85C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
Temperature Range1 0C to +70C
Package Instruction Operating Voltage Option Rate (Max) (Nom) BC-289-2 600 MHz 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O BC-289-2 533 MHz BC-289-2 600 MHz BC-289-2 533 MHz BC-289-2 600 MHz BC-289-2 533 MHz BC-208-2 600 MHz BC-208-2 533 MHz BC-208-2 600 MHz BC-208-2 533 MHz BC-208-2 600 MHz BC-208-2 533 MHz 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.2 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O 1.15 V internal2, 1.8 V, 2.5 V, or 3.3 V I/O
Referenced temperature is ambient temperature. is is the nominal voltage required to run at the nominal instruction rate. Lesser frequencies may require lower operating voltages. Please see Table 12 and Table 15 for details.
Table 65. ADSP-BF522/524/526 Processors
Model ADSP-BF526KBCZ-4X Package Description 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) ADSP-BF526BBCZ-4AX -40C to +85C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) ADSP-BF526BBCZ-3AX -40C to +85C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
Referenced temperature is ambient temperature.
Temperature Range1 0C to +70C
Package Instruction Operating Voltage Option Rate (Max) (Nom) BC-289-2 400 MHz tbd V internal, 1.8 V, 2.5 V, or 3.3 V I/O BC-208-2 400 MHz BC-208-2 300 MHz tbd V internal, 1.8 V, 2.5 V, or 3.3 V I/O tbd V internal, 1.8 V, 2.5 V, or 3.3 V I/O
1
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06675-0-2/09(PrG)
Rev. PrG
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Page 80 of 80 |
February 2009

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