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Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DESCRIPTION
The NE/SE5562 is a single-output control circuit for switched-mode power supplies. This single monolithic IC contains all control and protection features needed for full-featured switched-mode power supplies. The 100mA source/sink output is designed to drive power FETs directly. The associated output logic is designed to prevent double pulsing or cross-conduction current spiking on the output. All of the control and protect features work cycle-by-cycle up to the maximum operating frequency of 600kHz. For ease of interface, all digital inputs are TTL or CMOS compatible. The NE5562 is supplied in 20-pin glass/ceramic (Cerdip), plastic DIP, and plastic SO packages. The NE grade part is characterized and guaranteed over the commercial ambient temperature range of 0C to +70C and junction temperature range of 0C to +85C. The SE5562 is supplied in the glass/ceramic (Cerdip) package. The SE grade part is characterized and guaranteed over the ambient temperature range of -55 to +125C and junction temperature range of -55 to +135C.
PIN CONFIGURATION
D, F, N Packages
FEED FORWARD 1 CT 2 RT 3 EXTERNAL MOD IN 4 DUTY CYCLE CONTROL 5 REMOTE ON/OFF 6 VI 7 20 GROUND 19 OUTPUT 18 DEMAG OVERVOLT IN 17 V S 16 C DELAY 15 OUT INVERT CONTROL 14 CURRENT SENSE 13 AUX COMP HYSTERESIS 12 AUX COMP INPUT 11 EXTERNAL SYNC IN TOP VIEW
FEEDBACK VOLTAGE 8 VZ 9
ERROR AMP OUT 10
SL00388
Figure 1. Pin Configuration
FEATURES
* Stabilized power supply * Temperature-compensated reference source * Sawtooth generator * Pulse width modulator * Remote on/off switching * Current limiting (2 levels)
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Small Outline (SO) Package 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Ceramic Dual In-Line Package (CERDIP)
* Auxiliary comparator, with adjustable hysteresis * Loop fault protection * Demagnetization/overvoltage protection * Duty cycle adjust and clamp * Feed-forward control * External synchronization * Total shutdown after adjustable number of overcurrent faults * Soft-start
TEMPERATURE RANGE 0 to +70C 0 to +70C -55C to +125C
ORDER CODE NE5562D NE5562N SE5562F
DWG # 1021B SOT146-1 SOT146-1
1994 Aug 31
1
853-0811 13721
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
BLOCK DIAGRAM
FEEDFORWARD + + 1 11 EXTERNAL SYNC IN
- + 3 2 OFF - +
S CLOCK OSC Q LATCH R DELAYED CLOCK OSCILLATOR OFF 1.5V ON - + ON/OFF COMP S OUTPUT Q LATCH R OC1 POWR OUTPUT NOR OUTPUT 19 OUTPUT INVERT CONTROL 15 0V DEMAG/OV IN 18 3.80V NORM DEMAG/OV COMP TIME DELAY
ON REMOTE ON/OFF 6 ERROR AMP OUT 10 3.80V FEEDBACK 8 VOLTAGE + - ERROR AMP - + LOOP FAULT COMP EXTERNAL MOD 4 IN DUTY CYCLE CONTROL 5 CLOCK 2k + - - -
PWM COMP
0.955V
NORM -+ 0.528V 0.645V OVERCURRENT 2 COMP -+ 0.955V - + SLOW OC1 START 0C2 COMP OC2 R NORM START/ STOP Q LATCH S LV STOP Q TRIP 3.80V NORM SHUT DOWN LATCH S R LOW BULK VI 7 3.80V 0.528V 0.645V POWER SUPPLY CKTS 0.955V GND 20 VS 17 VZ 9 OVERCURRENT 1 COMP CURRENT SENSE 14
OC CHARGE PUMPS 1:1 1:1
OC1-2 LATCHES
CDELAY 16 +V OC1 1A 11A +V OC2 80A
- +
OC ACCUM COMP
AUXILIARY COMP HYSTERESIS 13
NORM BULK SENSE 3.80V + - COMP -+ AUXILIARY COMP INPUT 12 3.80V
SL00389
Figure 2. Block Diagram
1994 Aug 31
2
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
ABSOLUTE MAXIMUM RATINGS
SYMBOL Supply VS ICC voltage-fed mode (Pin 17) current-fed mode (Pin 7) Output transistor output current Sync (Pin 11) Duty cycle control (Pin 5) Remote on/off (Pin 6) Output invert control (Pin 15) Feedback pin (Pin 8) CDELAY (Pin 16) External mod in (Pin 4) FF Feed-forward (Pin 1) Demag/overvoltage in (Pin 18) Current sense (Pin 14) 80Low supply sense and hysteresis (Pins 12, 13) TJ TSTG TSOLD Operating junction temperature Storage temperature range Lead soldering temperature (10sec) VS VZ VS VS VZ VZ VS VS VZ VS VS 135 -65 to +150 300 V V V V V V V V V V V C C C 16 30 100 V mA mA PARAMETER RATING UNIT
NOTES: 1. Ground Pin 20 must always be the most negative pin. 2. For power dissipation, see the application section which follows.
RECOMMENDED OPERATING CONDITIONS
SYMBOL Supply voltage-fed current-fed TA Ambient temperature range NE grade SE grade TJ Junction temperature range NE grade SE grade 0 to +85 -55 to +135 C C 0 to +70 -55 to +125 C C 10 to 16 15 V mA PARAMETER RATING UNIT
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = 12V, specifications apply over temperature, unless otherwise specified. SYMBOL PARAMETER TEST PINS TEST CONDITIONS SE5562 Min 3.76 3.72 Typ 3.80 3.8 30 0.5 Max 3.84 3.90 Min 3.76 3.725 NE5562 Typ 3.80 3.8 30 0.5 Max 3.84 3.870 UNIT
Internal reference
VREF VREF Reference voltage Reference voltage Temperature stability Long-term stability Internal Internal Internal Internal TA=25C Over temp. V V ppm/C V/1000 hrs
1994 Aug 31
3
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified. SYMBOL PARAMETER TEST PINS TEST CONDITIONS SE5562 Min Typ Max Min NE5562 Typ Max UNIT
Reference
VZ VZ VZ/ T Zener voltage Zener voltage Temperature stability Comparator threshold voltage Comparator threshold voltage Hysteresis 9 9 9 IL=7mA, TA=25C IL=7mA, Over temp. IL<1mA 7.35 7.25 50 7.60 7.75 7.80 7.35 7.20 50 7.6 7.75 7.78 V V ppm/C
Low supply shutdown
Internal Internal Internal 1, 2, 3, 11 1, 2, 3, 11 1, 2, 3, 11 1, 2, 3, 11, 17 1, 2, 3, 11 2, 3 2, 3 Sawtooth valley voltage Sync. in high level Sync. in low level Sync. in bias current Feed-forward ratio, maximum Feed-forward duty cycle reduction Feed-forward reference voltage Feed-forward bias current 2, 3 2, 3 11 11 11 1 1 1 9 1 VFF=2VZ, TA=25C Over temp. 11 6 (Sourced), V11<0.8V TA =25C1 5.00 4.80 1.25 1.0 2.0 0.0 0.50 2 13.5 13.5 VZ 2.5 19 22 VS 50.0 11 8 VZ 2.5 Over temp. TA=25C Over temp. RT=42.7k, CT=0.47F RT=2.87k, CT=380pF fO=52kHz, RT=16k and CT=0.0015F, TA=25C 10VOscillator
fMIN fMAX Frequency range, minimum Frequency range, maximum 60 80 600 60 80 Hz kHz
Initial accuracy
48.6
54
59.4
48.6
54
59.4
kHz
Voltage stability Temperature stability Sawtooth peak voltage
-215 300 5.25 5.25 1.70 1.7 500 5.40 5.60 2.00 2.1 VZ 0.8 10.0 5.00 4.80 1.25 1.25 2.0 0.0
-215 300 5.25 5.25 1.70 1.7 500 5.40 5.60 2.00 2.0 VZ 0.8 0.50 2 13.5 19 22 VS 50.0 10.0
ppm/V ppm/C V V V V V V A
% % V A
1994 Aug 31
4
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified. SYMBOL PARAMETER TEST PINS TEST CONDITIONS SE5562 Min Typ 1.0 RL>100k ISOURCE=1mA ISINK=1mA fO<300kHz -40 8 1 V8=V10=5V V8=3V, V10=1V AV=100, 0% duty cycle @VCOMP<, f=300kHz @VCOMP>, f=300kHz, V15=0V f=15kHz to 200kHz, VIN=0.472 VZ V15=0 (Sourced) (Sourced) .910 0 2 1 VZ 400 .593 .486 (Sourced) -18.2 -770 V12=VZ TA=25C 0.4 3.75 0.645 0.528 0.5 -13 -550 1.4 3.86 .697 .570 50 -6.5 -250 4.0 3.97 -18.2 -770 0.8 3.75 0.593 0.486 200 240 10 5 200 1 60 5 2.0 -40 8 240 10 5 86 Max 5.0 60 5 2.0 Min NE5562 Typ 1.0 86 Max 5.0 UNIT
Error amp
IBIAS AVOL VOH VOL Input bias current DC open-loop gain High output voltage Low output voltage PSRR from VZ and VS BW Small-signal gain bandwidth product Feedback resistor range ISINK ISOURCE Output sink current Output source current Sawtooth feedthrough 8 8, 10 10 10 Internal A dB V V dB MHz k mA mA mV
PWM comparator and modulator
Minimum duty cycle 19 0 0 %
Maximum duty cycle
19
95
98
95
98
%
ACC tPD IBIAS IBIAS
Duty cycle Propagation delay to output Bias current, external modulator input Bias current, duty cycle control Soft-start trip voltage
10, 19
41
49
55
41
49
55
%
2, 19 4 5 5 6 6 6 6 6, 19 14 14 14 16 16 16 16
400 0.20 0.20 0.955 20 20 0.990 0.80 VZ 10 VZ 0.922 0 2
400 0.20 0.20 0.955 20 20 0.988 0.80 VZ 1 400 0.645 0.528 0.5 -13 -550 1.4 3.86 0.697 0.570 50 -7.8 -330 2.0 3.97 10
ns A A V V V A V ns V V A A A A V
Remote on/off (shutdown)
Output enabled Output disabled IBIAS VIN Bias current Maximum input voltage Delay to output(s)
Current limit comparator(s)
Shutdown, OC2 Minimum duty cycle, OC1 IBIAS OC1 OC2 CDELAY CDELAY Bias current CDELAY charge current CDELAY charge current Discharge current Shut off trip level
1994 Aug 31
5
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 12V, specifications apply over temperature, unless otherwise specified. SYMBOL PARAMETER TEST PINS TEST CONDITIONS SE5562 Min Typ 1 3.69 VIN=3V 5 3.80 10 10 2 3.62 3.80 10 ISOURCE=100mA ISINK=2mA ISINK=100mA, TA=25C ISINK=100mA, over temp. 100 100 CL=2000pF CL=2000pF 10VAuxiliary comparator with shutdown
IBIAS CDELAY Bias current Threshold voltage Discharge current Hysteresis IBIAS Bias current Threshold voltage Hysteresis 12 12 12 12, 13 18 18 18 19 19 VOL Low output voltage 19 19 ISINK max ISOURCE max tR tF Rise time Fall time 19 19 19 19 (Sourced) A V mA mV A V mV V V V V mA mA ns ns
Demagnetization overvoltage comparator
Output stage
VOH High output voltage
Supply current/voltage
ICC Supply current 17 9 15 9 15 mA
VS
Input voltage
7, 17
15.3
16.7
14.2
15.3
16.7
V
Operating frequency range for all functions but feed-forward working cycle-by-cycle
fMIN fMAX Minimum frequency Maximum frequency All All 60 1000 80 600 60 1000 80 Hz kHz
103 TA = 25C FREQUENCY (kHz)
102
RT = 2.5k RT = 5k RT = 10k RT = 20k
101
RT = 40k
100 102
5 x 102
103 5 x 103 CT (pF)
104
SL00390
Figure 3. Frequency vs RT, CT NE/SE5562
1994 Aug 31
6
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
0 PHASE (DEG) TA = 25C PHASE -30 -60 -90 -120 40 GAIN (dB) 30 20 10 0 100 1k 10k 100k FREQUENCY 1M 10M -150 CLOSED-LOOP GAIN -180
SL00391
Figure 4. Error Amplifier Closed-Loop Response
100 90 80 DUTY CYCLE (%) 70 60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 9 10 PWM INPUT VOLTAGE (V) VCC = 12V TA = 25C
SL00392
Figure 5. Duty Cycle vs PWM Input Voltage
100 90 80 DUTY CYCLE (%) 70 60 50 40 30 20 10 0 5 6 7 8 9 10 11 12 13 14 15 FEED-FORWARD VOLTAGE (V) TA = 25C
SL00393
Figure 6. Duty Cycle vs Feed-forward Voltage
1994 Aug 31
7
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
22 SUPPLY CURRENT (PIN 17) (mA) 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE (PIN 17)(V) TA = 25C
SL00394
Figure 7. Current-Feed Characteristics
22 SUPPLY CURRENT (PIN 17) (mA) 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 SUPPLY VOLTAGE (PIN 17)(V) TA = 25C
SL00395
Figure 8. Voltage-Feed Characteristics
1994 Aug 31
8
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
THE NE/SE5562 THEORY OF OPERATION INTRODUCTION
Switched-mode power conversion relies on the principle of pulsed energy storage in an inductive or capacitive element. Capacitive switched converters are typically used with low power systems for which only tens of milliamperes are required. Medium and high power converters tend to use inductive storage elements as shown in Figures 9-11 with which a single switch may be moved around to create step-up (flyback) positive or negative polarity and step-down (forward or buck) conversion from a fixed-voltage source. The relationship between input and output voltage in each case is controlled by the switching on-to-off ratios, which is termed duty cycle. Duty cycle modulation is the common factor in this basic type of power control mechanism. By adding a high-gain operational amplifier, having one input tied to a stable DC reference voltage, configured in a negative feedback loop to maintain a constant output voltage as shown in Figure 12, the switched-mode controller becomes a dynamic voltage regulator. It is this single-switch topology that is most readily adapted to the NE/SE5562 SMPS Control IC. The ability to switch inductor currents at rates up to 600kHz with state-of-the-art power FETs makes the design of small, efficient switching power converters an attainable reality. Protective features such as programmable slow-start and cycle-by-cycle current limiting allow safe, maintenance-free power supplies to be mass-produced at reduced cost to the manufacturer. Integrated technology makes long-term reliability a predictably achievable goal.
SW + L + WHERE d +
t T
SW
ON
PERIOD
VIN COM
DB
CO
RL
V
OUT
+ dV IN
-
SL00398
Figure 11. Forward Converter (Single Inductor) Step Down
ISW +
L
REGULATED OUTPUT + IL C RL -
VIN UNREGULATED DC -
PWM
+ A - RF
VREF R2
SW
DO -
R1
VIN
L
CO
RL
V
OUT
+
* V IN 1*d
SL00399
Figure 12. The Forward (Buck) Converter (VOUT = VIN())
Di Dt SWITCH CURRENT
COM
+
SL00396
Figure 9. Negative Output Flyback Converter
+
E L
MAGNETIZATION CURRENT LOAD CURRENT
L +
DO + DIODE CURRENT AVERAGE INDUCTOR CURRENT
VIN
SW
CO
RL
V
OUT
+
V IN 1*d
COM
TOTAL INDUCTOR CURRENT -
SL00397
SL00400
Figure 10. Positive Output Flyback Converter
Figure 13. PWM Switching Waveforms
1994 Aug 31
9
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
FEEDFORWARD 1 +
EXT. SYNC 11 ACTIVE LOW 0.8V +
VZ +7.50V
IO (5.25V) R2 VH - S + TIME BASE SIGNAL FF CT (1.70V) R3 3k - R + CURRENT STEERING SAWTOOTH GENERATOR DISCH. +3.80V + - - - - 10 PWM COMPARATOR OUTPUT TO LATCH RESET TO DELAY CIRCUIT
3
28k 2 1
VOLTAGE FEEDBACK 8
ERROR AMP
SL00401
Figure 14.
THE NE/SE5562 THEORY OPERATION The Sawtooth Oscillator
The sawtooth oscillator consists of a gated charge-discharge capacitor circuit with threshold comparators setting the peak and valley voltages of the ramp. The resistor divider R1-3 is supplied with a source voltage derived from either VZ (7.50V) minus two diode drops, or, when feed-forward is in control, a voltage greater than VZ and proportional to the main supply voltage. The nominal upper threshold voltage is 5.25V and the lower threshold 1.70V. These then determine the sawtooth peak and valley voltages, respectively. Operation Beginning with the charge cycle, ramp voltage builds up on the timing capacitor due to a constant current supplied to the node at Pin 2. When capacitor voltage reaches the upper threshold, comparator A switches, setting the latching flip-flop. The output of the latch goes high, generating a clock pulse. The discharge transistor is simultaneously turned on, reducing charge on the timing capacitor to the point at which the lower threshold voltage, 1.70V, is reached. The lower comparator is then activated, resetting the latch and terminating the clock pulse. Note that the discharge transistor is referenced to the same return diodes as the threshold resistor divider and the discharge current is made to track with the charge current. This charge and discharge tracking results in a true sawtooth waveform even at extended frequencies. Figure 17 shows a family of curves which explains the relationship between RT, CT, and the frequency of the sawtooth generator. The data sheet shows the initial accuracy of the oscillator at 60Hz and 600kHz.
THE PULSE WIDTH MODULATOR AND ERROR AMPLIFIER
The PWM consists of a multi-input voltage comparator (Figure 15) having its positive input tied to the sawtooth ramp voltage and the various negative inputs referenced to ORed control signal nodes. The primary control signal is the error amplifier output voltage node which sets the active duty cycle termination point of the PWM output waveform. As the error amplifier input signal derived from the power supply load voltage varies, for instance in a negative direction, the amplifier output moves upward, raising the PWM comparator toward longer duty cycles at the output on Pin 19. The start-up sequence begins with zero voltage at the input to the error amplifier. Since this could signal an open feedback loop, the loop fault comparator on Pin 8 clamps the PWM duty cycle until the feedback voltage exceeds 0.955V. A second comparator monitors the duty cycle control, Pin 5, with the same threshold level, inhibiting the output via the start-stop latch (Figure 16). The charging of the slow-start capacitor provides a controlled ramp-up of the output duty cycle and a resultant gradual increase in energy fed to the output magnetics. The dynamic response of the PWM comparator is shown in the simulated waveform drawing of Figure 17. The error amplifier output voltage is depicted as sloping positive (increasing) with time as referenced to the sawtooth waveform. This causes the duty cycle to increase with time. This is an indication of an increasing load on the power supply as output voltage is decreasing. The Pin 5 (MAX) control voltage is also superimposed midway on the sawtooth, indicating the limits of duty cycle increase as the output waveform no longer increases in duty cycle after the MAX threshold is crossed. A hypothetical overcurrent pulse (Pin 14) is shown to illustrate cycle termination immediately at the output (Pin 19).
1994 Aug 31
10
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+VZ
35A
35A
35A
VH SAWTOOTH + (-) SAWTOOTH UPPER THRESHOLD (-)
10 (-)
4 (-)
5
DELTA MAX CONTROL
ERROR AMP OUT
MODULATOR IN
9k
2.5k
PWM SIGNAL TO OUTPUT NOR GATE
100A
SL00402
Figure 15. PWM Comparator
DELAYED CLOCK
VREF +3.80V S + + - 8 - - PWM NOR R OUTPUT LATCH TO OUTPUT STAGE
10
5 DUTY CYCLE CONTROL
SL00403
Figure 16. The Duty Cycle Control Circuit, Pulse Width Modulator, and Error Amplifier, Reference, and Output Latch
1994 Aug 31
11
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SAWTOOTH WAVEFORM PIN 5 MAX LEVEL
PWM COMPARATOR (INTERNAL)
FLYBACK PULSE (INTERNAL)
+0.528V PIN 14 CURRENT SENSE INPUT (OUTPUT) PIN 19
SL00404
Figure 17. Duty Cycle vs Feedback Error and Overcurrent Sense The error amplifier's non-inverting input is tied to a bandgap reference of 3.80V, accurate to 2% at 25C. The temperature stability of the voltage reference is 30ppm/C. The error amplifier is designed for an open-loop gain of 86dB having a small-signal unity gain bandwidth of 3MHz. Closed-loop gain is stable to 10dB, as shown in Figure 19. The DC output excursion of the amplifier is capable of controlling the full PWM range of 0 to 95%. The amplifier can sink 10mA and source 5mA. The nominal DC output for 50% duty cycle is 3.55V. Feedback control resistor value may range from 1k to 240k without overload or instability. However, low closed-loop gains must be compensated by lag lead network techniques for optimum stability. Loop compensation networks may intersect the open-loop gain curve with a slope 2 closure and must then be compensated to maintain overall phase and gain margin (Figure 18).
+VZ (7.50V) VZ 6k 2.5k
VZ ERROR AMP OUT 3.80 VREF 30 N BIAS 7pF FEEDBACK SENSE
10
8
6k
6k
SL00405
Figure 18. Error Amplifier
1994 Aug 31
12
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
80 70 (dB) 60 50 A OL 40 30 A CL 20 10 0 50 360 OFFSET ADJUST 5k
EST. -3dB FREQUENCY PHASE DELAY 160 143 130 98 +VREF 3.75V + (8) - 10M (10) SLOPE = (-)1 95
NE5562 ERROR AMPLIFIER PHASE/AMPLITUDE RESPONSE
92
83 80 70 32
fP1 1 10 100 1000 10000 100000 FREQUENCY (Hz)
SLOPE = (-)2
fP2
1000000
SL00406
Figure 19. Error Amp Response
FEED-FORWARD COMPENSATION (PIN 1)
To provide a means of automatically improving line-to-load voltage regulation, a technique called feed-forward regulation is made a part of the NE/SE5562 active mechanism. Referring back to the diagram for the sawtooth oscillator, note that Pin 1 is capable of changing the internal supply voltage to the charging circuit for the timing capacitor, Ct. With a nominal duty cycle of 30%, for instance, increasing Pin 1 voltage by 1V from 10.3 to 11.3 will reduce the output duty cycle by approximately 5%. Thus, a primary voltage change has caused a decrease in volt-seconds (duty cycle X primary volts) of 5/30 or 16% (Figure 6). The result is a small over-compensation in the output energy, but an overall safe margin in transformer flux. The mechanism which produces inverse duty cycle modulation is shown in Figure 20. Increasing Pin 1 voltage beyond the value of Vz
(7.50V) increases the charge rate on CT, causing the duty cycle to be terminated earlier for each cycle that input voltage is increased. The threshold voltages at the sawtooth limit comparator reference inputs are changed with Pin 1 also in order to offset any change in oscillator frequency. The secondary benefit of using feed-forward is the attenuation of any low-frequency AC riding on the DC supply before it reaches the regulated output. Note that a start delay circuit is added to the Pin 1 divider in order to prevent internal race conditions during initial power-up. Once the turn-on transient has decayed, normal operation of the feed-forward circuit is assured. Figure 21 shows an RC delay placed in a base clamping circuit to provide reliable starting.
2VZ
LINE VOLTAGE SENSE
VZ VTH VTH T T
+ PWM COMPARATOR
-
SL00407
Figure 20. Feed-Forward
1994 Aug 31
13
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
SYNCHRONIZATION
VFFWD 2N3906
0.2F
220k
1
The synchronization of the sawtooth oscillator to an external pulse of negative-going polarity is shown in Figure 22. When the sync input pulse crosses the 1.5V threshold, negative, the sawtooth oscillator is prevented from discharging the timing capacitor, causing the charge voltage on the capacitor to remain high (5.25V) until the sync pulse again goes above 1.5V, allowing reset. This action stretches the period of the oscillator and results in a lower frequency under-synchronization control than the free-running frequency. The following relationship holds-- f free*run u f sync f sync + t0 ) 1 t
NE/SE5562
SL00408
Figure 21. Feed-forward Turn-On Delay Circuit
A typical recommended starting point in calculating frequency for synchronous operation is to set the free-run frequency approximately 10% higher than the sync frequency. Then set the pulse width, , to 10% of t0, the free-run period, with the desired new frequency determined by the sum as above.
+VCC T
19 + 1.5V SYNC 11 NE/SE5562
2
d T
SL00409
Figure 22. Synchronization Signals
PIN 11 SYNC SIGNAL
+1.5V
SAWTOOTH WAVEFORM
TO
SL00410
Figure 23. Sync Signal Relationship to Controlled Sawtooth Waveform
DUTY CYCLE LIMIT (PIN 5)
The forward or buck converter, and even the flyback converters, may require an automatic duty cycle limit to prevent transformer saturation or unstable behavior. A special input provides access to the PWM comparator for this purpose. As discussed previously in regard to the error amplifier, increasing load demand may drive the system current beyond safe limits. A simple solution is the placement of a duty cycle limit within the system dynamic response before this can occur. Figure 15 shows the PWM comparator with its multiple input ports. All are inverting in polarity and provide a lowest 1994 Aug 31 14
priority level sensing circuit. The lowest level on Pin 4, 5, or 10 gains control of the duty cycle limit. During normal operation, the MAX circuit sends a continuous threshold signal to the PWM comparator, setting a fixed limit on how much the error amplifier is allowed to increase the duty cycle in response to load demand. Figure 24 shows the circuit within the NE/SE5562 which actually controls duty cycle as listed below: 1. Duty cycle ramp-up (slow-start) during power-up. Time constant controlled by external R, C ramp voltage at Pin 5.
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
2. Slow-start if remote ON/OFF is actuated, if OC2 threshold trips, demagnetization/overvoltage is sensed, or low supply voltage to the internal regulator is sensed (VS8.45V). 3. Note that Pin 8 is monitored by the loop fault comparator. When the regulated supply feedback drops below this threshold level (0.955V), the duty cycle is clamped by two diodes in series with a 2k load across Pin 5 to ground. This implies a minimum duty cycle condition as long as the low output level remains. Referring to the graph in Figure 25, the designer may choose a divider ratio which, when referenced to VZ, 7.5V, provides an easy duty cycle limit control. For example, a 50% limit results in a ratio of 0.48. Setting R2 at a nominal value between 10 and 20k and solving for R1, the proper limit is obtained.
R2 = 10k, find R1 R2 + 0.48 R1 ) R2 R2 = 0.48 (R1 + R2) 0.48R1 = R2 - 0.48R2 N R1 + + R 2(1 * 0.48) 0.48 (0.52) 0.48
10kW
= 10.8k
Example:
A duty cycle limit of 50% is required for a forward converter.
DELTA MAX TO PWM COMP
R1
SLOW START CAP
CSS
R2
5
VZ
0.9V VZ ERROR AMP IN
36A 8 0.9V 9k 0.955V SLOW START COMP 50 LOOP FAULT COMP SLOW START COMP OUT `A' FROM START/STOP LATCH + STOP N BIAS
1.5V
2k
SL00411
Figure 24. Duty Cycle Limit Control
1994 Aug 31
15
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
90 80 MAXIMUM DUTY CYCLE % 70 60 50 40 30 20 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
V Z + 7.50V
DUTY CYCLE CONTROL
R2 R1 ) R2
SL00412
Figure 25. Maximum Duty Cycle
TO OUTPUT NOR LOW SUPPLY SENSE
OC2 SENSE
DEMAG/OV SENSE REMOTE ON/OFF
TO OUTPUT NOR VZ R79 10k
R73 10k
Q262
Q264
R74 10k
R75 18k Q269
R76 15k
R77 10k
Q276
Q277
1.5V R78 10k Q279
Q282 Q284
Q260 OC ACCUM Q261 Q263 Q265
Q266 Q270 Q271 Q272 Q273 Q274 Q267 Q280 Q268 Q281 Q275 Q278
Q283
CSS DISCHARGE SLOW-START COMPARATOR + RESET Q283A
Q283B SHUTDOWN LATCH BULK SENSE + RESET 0V START STOP LATCH SIGNAL GND 20
SL00413
Figure 26. Start-Stop/Shutdown Latches
1994 Aug 31
16
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
THE START-STOP CONTROL SEQUENCE
The start-up circuit involves a sequential set of conditions which progresses as follows: power-up after OFF condition or remote ON after OFF. Initially, 0V exist on the supply output, causing zero feedback volts on Pin 8. The slow-start capacitor is discharged, forcing Pin 5 to 0V, having been clamped by the internal discharge transistor. Internal supply regulator input exceeds 8.45V, releasing low voltage shutdown condition with Pin 5 below 0.955V. The slow-start comparator output goes high, resetting the start/stop latch, sending a low output signal to the output stage power NOR gate. The PWM signal is then enabled to feed the output drive circuits, starting energy flow through the magnetics. However, instantaneously the power supply output is still below 0.955V and the loop fault comparator forces the PWM to remain at a minimum
duty cycle. The equivalent circuit at this instant in the start-up cycle which exists at Pin 5 is shown in Figure 28. The actual minimum duty cycle is determined by the parallel source resistance of R1 and R2 combined with the shunt loading internal to Pin 5. High values of divider resistance, 20-30k, will supply less shunt current to Pin 5 and create a lower modulator duty cycle, while lower values of R1 and R2 (5-10k) will generate a higher modulator voltage and a greater resultant minimum duty cycle. As the power conversion circuits become active and Pin 8 feedback voltage increases above 0.955V, the duty cycle network is unclamped; duty cycle increases, controlled by the RC time constant R1||R2.CSS, and as output voltage brings the feedback voltage up to equal the reference voltage, 3.80V, the error amplifier takes control and the supply is in regulation.
+7.50V DISCHARGE R1 5
DEMAG 0V
OC2
S CSS R2 - R 0.955V + SLOW-START COMPARATOR START/ STOP Q LATCH
SL00414
Figure 27. Slow-Start Comparator
7.50V
R1 VMOD 5 CSS
+ - PWM - COMP - ON 0.2V 5 1.4V LOOP FAULT COMPARATOR
MINIMUM DUTY CYCLE
R2
FEEDBACK VOLTAGE SENSE
2k
SL00415
Figure 28. Loop Fault Comparator and Minimum Duty Cycle Clamp The stop or shutdown sequence is initiated by any of the following conditions: a. Supply voltage (bulk) sense below 3.80V at Pin 12. b. Pin 17 below 8.45V or Pin 7 current below level (less than 9mA). c. Remote ON/OFF voltage at Pin 6 greater than 2V. d. Sustained OC2 causing CDLY to charge above 3.80V (current sense on Pin 14 continuously above 0.645V peak).
1994 Aug 31
17
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
DUAL-LEVEL OVERCURRENT COMPARATORS
The overcurrent sensing circuit (Figure 29) consists of a single PNP input buffer with emitter-follower tied to VZ, 7.50V, feeding into the base of an NPN split-emitter transistor. This forms the input node to a set of dual-level voltage comparators with references of 0.528 and 0.645V, respectively. Current sources for the comparator are fixed biased NPNs. The typical transition time delay for an overcurrent fault is 300ns. Bias current at the input averages 500nA.
If the overcurrent sense feature is not used, it is recommended that Pin 14 be tied to ground. When used for sensing current-derived voltage impulses from the primary driver, a high-speed, low-impedance transient filter network is advised. An example is shown in Figure 30. Keep CF close to the NE/SE5562.
VZ = 7.50V 135A 135A 135A
1.5V
3k OC2 REFERENCE 0.645V 100A CURRENT 14 SENSE INPUT
135A 1.5V 3k OC1 REFERENCE 0.528V 100A 0.528V 0.645V
SL00416
Figure 29. NE/SE5562 Overcurrent Comparator
THEORY--OC1 AND OC2 Overcurrent Logic and Delay Capacitor Operations
+VCC
NE/SE5562 500-1000 10% CARBON CF IMAG
RSH
SL00417
Figure 30. Transient Suppression
The circuit takes a voltage input from Pin 14 and compares the level to a dual reference comparator with trips at 0.53 and 0.65V. The lower trip point actuates cycle-by-cycle shutdown of the output stage with an intrinsic delay of 400ns. The second level actuates the slow-start function. In addition, there exists a separate housekeeping circuit whose function is to terminate operation of the output stage if its threshold is exceeded. This involves a time delay circuit based on two separate switchable current sources, OC1 and OC2. The time delay capacitor allows the user to program shutdown of the system after a predetermined number of overcurrent cycles have occurred within the period set by the ramp-up of the delay capacitor. Once shutdown has occurred in this manner, external reset is required to restart the system. Referring to the logic block Figure 31, which controls the gating of the two charge pumps into the delay capacitor at Pin 16, the complete signal flow may be traced. Logic signals from the overcurrent 1 and 2 comparators are gated by the clock and delayed clock signals generated by the
1994 Aug 31
18
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
sawtooth oscillator. The complete sequence for an overcurrent fault may be understood by referring to Figure 32 for OC2. Here it is shown that an OC2 signal exists indicating that the 0.65V threshold has been exceeded by a signal at Pin 14. Note that an overcurrent pulse within a particular clock frame turns on the respective OC2 charge ramp during the entire next clock
A B OC2 DELAYED A Q C B A A C C Q B OC1 A Q C B OC1 DLEAYED A C B A A C A B C A B C
frame. Consecutive overcurrent pulses of either OC1 or OC2 magnitude will activate the selected charge pump for the total duration that such overcurrent occurs. The charging cycle will continue until the delay capacitor reaches the 3.86V trip level.
Q
C
A B
C
A
C
A B OC2 LATCH
OC2 IN
OC2
C
A B B C CA A B OC1 LATCH DELAYED CLOCK OUT
B C A C A C A C A C CLOCK
A
C
A B OC1 IN
SL00418
Figure 31. Overcurrent Logic
SAWTOOTH
CLOCK CLOCK
DELAY CLOCK
LET OC2 GO UP AT ANY TIME BETWEEN DELAY CLOCK RISES AND CLOCK RISES
OC2 QA
QB
R
S
QPUMP
SL00419
Figure 32. Fault Cycle 1994 Aug 31 19
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
3.86V 0.1F 0.5F
1F
CDELAY 0.00V 100 200 300 OC1 DELAY TIME (MILLISECONDS)
3.66V
1F 5F
SL00421
Figure 34. OC1 Ramp and Shutdown Delay
10F
mode), on the first such pulse. OC2 delays are based on an interrupted charging cycle with total cycle time determined by the external slow-start delay capacitor duty cycle maximum divider--time constant. For a continuous OC1 overcurrent:
80
CDELAY 0.00V 10 20 30 40 50 60 70 OC2 DELAY TIME (MILLISECONDS) (neglecting recycle dfelay)
C DLY +
SL00420
(13X10 *6)(Delay time * sec) (1) 3.86V
For a continuous OC2 overcurrent: C DLY + (550X10 *6)(Delay cycles x 1 f SW) 3.86V (2)
Figure 33. Overcurrent Shutdown Function
CALCULATING THE DELAY CAPACITOR
Actual delay time for a given capacitor value at Pin 16 may be estimated using the graphs in Figure 33 for OC1 and OC2. By first determining the allowable overcurrent time product for a particular power converter, a capacitor delay value may be calculated. Note that the OC1 charge pump is typically 13A while OC2 pumps 550A into the capacitor. If the exact value is to be calculated for a particular delay requirement, use the following procedure: 1. Determine the level of overcurrent--OC1 or OC2. 2. Find the maximum delay time which the supply may safely sustain for this continuous overcurrent condition. Note that OC1 may be activated on every cycle if OC2 is not reached, causing continuous charging of C-Delay. However, OC2 overcurrent detection causes the supply to go into slow-start shutdown (hiccup
Some downward adjustment of the OC2 capacitor value may be necessary to compensate for the 1-2A of discharge current at Pin 16 during the delay cycles. Example: A maximum of 100 OC2 current fault cycles is allowed. fSW =400kHz, find CDLY (550X10 *6)(100 x 1 4 x 105) C DLY + 3.86V =0.036F Example: OC2/CDLY Find number of OC1 cycles before shutdown with 0.036F CDLY.
1994 Aug 31
20
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
Delay Time +
(3.6 X 10 *8)(3.86V) 13 x 10 *6A
=10.7ms Total cycles shutdown + 10.7 X 10 *3 2.5 x 10 *6 =4280
adjusted near midway, the line voltage will have to exceed VNOMINAL before the supply will restart. The hysteresis control may then be calibrated for the desired over-excursion before restart. This prevents unstable circuit chatter. The reset switch provides a means for resetting the shutdown latch after overcurrent faults have charged CDLY to its trip threshold. This also provides a discharge path for the delay capacitor. Figure 36 shows internal circuit.
+VS VBULK
Figure 35 shows an actual OC1 charging cycle for continuous fault current sensed at Pin 14 and a DLY = 1F.
BULK-SENSE AUXILIARY COMPARATOR WITH SHUTDOWN
This circuit is intended to act as an automatic low-line detection mechanism. As shown in Figure 35, a voltage divider is connected from the main unregulated DC supply to Pin 12. The lower divider resistor may be a potentiometer of 5-10k resistance with center-tap connected to Pin 13. The comparator which senses Pin 12 voltage is referenced to 3.80V and Pin 12 divider voltage must be greater than this voltage by a sufficient margin to operate within the prescribed low-line limits. For instance, if a line voltage drop of 25% is considered the shutdown threshold, then V12 should be calculated for a nominal operating voltage as shown in Figure 35. When the line voltage drops more than 25%, the output stage is disabled. With the hysteresis connected as shown and the pot
1.5V ++ VBULK 18k BULK SENSE OUT VZ 16 RESET CDELAY 25k 3.80V 36A N BIAS 12 BULK SENSE IN RA NE/SE5562 12
R1
13
R2 HYSTERESIS ADJUST
SL00422
Figure 35. Bulk-Sense Comparator Divider
BULK SENSE COMP 26k
26k
BULK 13 SENSE HYSTERESIS
RB POTENTIOMETER
SL00423
Figure 36. Bulk-Sense Comparator
THE OUTPUT DRIVE STAGE
The output stage contains the power NOR inhibit gate, invert logic function, and source-sink drivers. The driver stage is capable of sourcing and sinking 100mA at frequencies up to 600kHz. The output transistors are Schottky clamped to prevent saturation and the resultant switching delay due to stored charge. A 2.5 current sense resistor in the emitter of Q419 serves to drive active clamp Q427 when the output sources more than 200mA. This places a limit on the peak current available during instantaneous charging of a
power MOS FET gate. This feature protects the output stage from inadvertent catastrophic overload. When sinking current, the output is clamped to a maximum of 1.4V. Output swing for positive output is typically VS-1.9V at 100mA sourcing. Rise time for a 2000pF load at Pin 19 is typically 160ns with a fall time of 80ns. The power NOR gate provides a fast response inhibit function to shutdown the output in the event of a number of different fault
1994 Aug 31
21
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
conditions. All inputs are internal to the device and do not appear directly on the external pins as is shown on Figure 37. The additional flexibility of an invert control allows the polarity at the output during duty cycle to be reversed. This provides a simple
means of designing with P-channel power MOS FETs without adding external inverters. The invert logic is controlled by a simple logic signal at Pin 15. Grounding will cause the output to be a normal positive output and a high level gives inverted output.
17 R31 10k Q126 Q125 R33 5k Q127 R34 R30 R37 5k 15 10k Q128 R35 Q129 Q131 3k R38 1k Q132 Q155 Q130 PWM Q133 DEMAG 0.V SHUT DOWN LATCH OUTPUT LATCH 3.80V 1.5V R28 5k R29 5k R30 1.25k Q142 Q141 Q143 R41 5k PBIAS Q144 Q159 VZ Q160 Q161 Q165 R43 4k Q162 Q153 Q152 Q149 Q150 R42 1k Q163 Q164 Q165 R39 300 Q154 Q158 Q157 Q156
+V5
R32 3k
START/STOP LATCH
R40 2.5 19 OUTPUT
Q134
Q135
Q136
Q137 Q138 1.5V Q148 Q145 Q146 Q147
Q151
Q139
Q140
INVERT OUTPUT NCR NORM 15
SL00424
Figure 37. Output Driver Schematic
THE INTERNAL VOLTAGE REGULATOR
The internal regulator is configured to provide for external supply to the NE/SE5562 from either a voltage feed or a current feed.1 For the current-fed mode, a series-dropping resistor may be used to power the device from voltages greater than 18V with current supply of 15 to 25mA. Note that supply current stated in the data sheet is for the device only without load on the output or VZ. Drive currents also are pulse-related and thus reflect frequency components onto the current-feed circuit. These must be filtered out at Pin 7 with adequately large capacitors in order to prevent motor-boating (see Figure 38 and Figure 39). Input current to Pin 7 flows through Zeners Z1 and Z2, and shunt regulator transmitter QR. A differential amplifier with 3.80V reference provides feedback to regulate VS to 15V. In the voltage-fed mode using Pin 17, the Zeners prevent current flow through QR for input voltages less than 19V. Power dissipation of the device must stay within the allowable package limits. These limits are derived from the thermal characteristics of the particular package chosen. The NE5562N plastic package is capable of operating within the temperature range (ambient) of 0 to +70C. This rating applies to the surface-mount product NE5562D also. Obviously, the power dissipation of the "D" package is lower than the standard DIP. Thermal resistance for the various packages are: 20-Pin plastic--NE5562N/SE5562N: JA 61C/W
20-Pin glass/ceramic--NE5562F/ SE5562F: JA 90C/W 20-Pin SO: -55 to +85C/W (board-dependent)
NOTE: 1. See Figures 7 and 8 for internal Regulator Response Curves.
Design Example--An NE5562N is operated at 40C ambient in the voltage-fed mode with VS=15V; assume IS=22mA average:
++V 47-100F 35V +
7
19 NE/SE5562
20
SL00425
Figure 38. Current-Feed
1994 Aug 31
22
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
VOLTAGE SOURCE
VS
17
VI CURRENT SOURCE
7 790
VS
FROM BIASING NETWORK 30k
10k QR 20k
REGULATOR 3.80V
SL00426
Figure 39. Internal Voltage Regulator PD = (22x10-3) (15) =330mW Solving for the temperature rise from ambient to the IC functions: Temperature rise = 61C/Wx0.33W = 20.1C
+12-15V 10k 12 10k (0.472) VZ 4 5 NE5562 1F 3 2 14 VREF 100pF ERROR AMP 6 20 RSH 1k
Junction temperatures will be 20.1C above average ambient temperatures which is 40C TJ=40C 20.1C 60.1C The allowable maximum junction temperature is 150C 125C is more conservative. The conditions of this example are safe.
+25V LO VZ 17 CO 15 19 CL
IRF530
8 10k `A'
10 VARIABLE SUPPLY 0-5V 10k
NOTES: 1. Supply will become active as point `A' reaches the level of VREF, 3.80V. 2. Monitor Pin 19 and Pin 2 on dual-trace scope with voltmeter connected to supply output.
SL00427
Figure 40. Open-Loop Test Setup
1994 Aug 31
23
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
D3
LO + P2 n VIN Q1 P1 n - S1 D2 CO + CP VO
-
NOTE: The P1 clamp winding prevents collector voltage from exceeding 2X VIN during off time.
SL00428
Figure 41. Forward Converter
+
Flyback Converter Design
n
Flyback Converter
1
- m
Advantages: tion.
* Simple circuit. Only one inductive component even with line isola* Economic. Low component count, low cost. * Work over large input voltage variations. * Can accommodate multiple outputs. * Large output ripple current due to discontinuous energy transfer. * Large output capacitor; has to supply part of the load current. * Low leakage inductance required to prevent high voltage spikes at
the switching transistors. Disadvantages:
To Prevent Core Saturation Due to Flux Staircasing
d max t
m 1 * m ) nif m = n max < .5 Demagnetization of Core
V CEmax + V imax
m) n X m
(V)
* Relatively large core volume for the output power. Core driven in
one direction only. Design Parameters for Flyback Inductor
Maximum Voltage Across Transistor
SL00429
Figure 42. Forward Converter Design Formulas
* Minimum input voltage * Maximum input voltage * Output voltage or voltages * Output current or currents * Output load
Output
Input
D1 + CP CO VI - Q1 VO +
-
SL00430
Figure 43. Isolated Secondary
1994 Aug 31
24
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
Frequency of Operation Estimate of Overall Efficiency. ()
+16V AUXILIARY BOOTSTRAP SUPPLY (SEE FIGURE 43) 0.47F F. FWD SENSE 2N3906 220k 10k 0.22F 1 3 2 5.1k 570 pF 4 5 PWM L A T C H CLOCK DELAY 17 40k BYV26C 0.01F C3 RESET [O.C.] 12 n LOW SUPPLY DETECTOR 13 n T1 1 HYSTERESIS ADJUST 0.01F D1 D2 L0 3.9 D3 COM. BYV19-35 +VOUT +5V +VS = 12V 10 +V=48V 3.9 0.01F
(PIN 9) VZ 7.50V
13k 3.26V 10k
CSS
D R I V E R
BUZ41A 19 18 Q1 4.7
4.7nF BYV26C
6
START/ STOP 3.80V
10 INVERT LA645V 15 ICC SHUT DOWN PGM CL 1 IN914 14 100pF T2
OFF 0V ON
+5V REMOTE SHUT DOWN 1.3k +5 VOUT SENSE 8
+ ERROR AMP -
13A
550A CL 2 C@ T 100:1
OC1
OC2
Q1 10 20 16 PIN 14 0.00F 1.6k PIN 14 ALTERNATE CIRCUIT 0.53 R SH RSH 0.24
CDELAY 1k
I MAX +
SL00431
Figure 44. Forward Converter, 100W - 5V
1994 Aug 31
25
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V
+17V
100
15V
P3 D40K2 P2 n +VO +5V
33k 7 1 NE/SE5562 +3.80V 19 + 0.22F 8 - P1
n
n/2
220k 6.8k
n
RF
10
20
SL00432
Figure 45. Shunt-Regulated Output With Bootstrap Supply
1994 Aug 31
26
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+
S
-
VI
CURRENT PATH WITH SWITCH CLOSED
CURRENT PATH WITH SWITCH OPEN
VO
- + S
+
VI
CURRENT PATH WITH SWITCH CLOSED
CURRENT PATH WITH SWITCH OPEN
VO
Negative Output
- +
+ +
VI
VO
Positive Output
-
-
ID1 T1 L1 VI IC N1 VCE TR1 D1 CO
IO + VO
TR1 ON OFF a iL IL iL VCE
b iL IL c iL O T T
iL VCE
VCE O T T
NOTES: a. Unlimited choke current b. Interrupted choke current
Flyback Converter and Current and Voltage Waveforms Figure 46.
1994 Aug 31
27
EE EEE E EEE E EEE E
Development of Practical Flyback Converter Circuit
nVO VI nVO VI
VI
SL00433
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
48V +VS +5V T 33k 2N3906 220k 0.22F 6.8k 1 V0' SENSE +5V 570pF CT RT 5.1k 2 3 4 5 6 7 8 9 10 FEEDFORWARD NE5562 20 19 18 17 16 15 O.C. 14 13 HYST. 12 11 4.7 CDELAY 1k RSH 100pF BUZ41A 0.1F CERAMIC -12 +12V COM +12 COM
R1 3.8V RF
R2 CSS
3.5V
EXT SYNC +5 0V-
LOW SUPPLY SENSE RESET
+VS
NOTE: 400kHz operation with feed-forward line regulation and cycle-by-cycle current timing.
SL00434
Figure 47. NE5562 Flyback Converter
++V (17) -VOUT
(10) RF (8) - VZ (9) +7.50V ERROR AMP (20) (19) +
100 2N3906
100
+3.80V IS' RI
RS
IS
SL00435
Figure 48. Negative Output Regulator Using Current Mirror
1994 Aug 31
28
Philips Semiconductors
Product specification
Switched-mode power supply control circuit
NE/SE5562
+48V (+) +15V SLAVED OUTPUTS 17 +15V -15V NE/SE5562 + + 4 NE5018 D/A 1-5V PWM -
(-)
+5V
-12V
NE5034 A/D
15
5k
+ PROGRAMMED SUPPLY VOLTAGE P
SL00436
Figure 49. Microprocessor Controlled SMPS
REFERENCES
1. R.D. Middlebrook and Slobadan Cuk, Advances in Switched Mode Power Conversion, Volumes I and II, TESLA Co., Pasadena, CA, 1983. 2. Rudolf P. Stevens and Gordon E. Bloom, Modern DC to DC Switchmode Power Convertor Circuits, Van Nostrand Reinhold/ Computer Science and Engineering Series, 1985.
3. H. Dean Venable, Stability Analysis Made Simple, Venable Industries, Inc., 1981. 4. J. Jongsma and L.P.M. Bracke, High Frequency Ferrite Power Transformer and Choke Design, N. V. Philips ELCOMA Publications, Eindhoven, the Netherlands, September 1982. 5. Edwin S. Oxner, Power FETs and Their Applications, PrenticeHall, 1982.
1994 Aug 31
29

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