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10-Bit, 65/80/105 MSPS, 3 V A/D Converter AD9215
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V) SNR = 58 dBc (to Nyquist) SFDR = 77 dBc (to Nyquist) Low power ADC core: 96 mW at 65 MSPS, 104 mW @ 80 MSPS, 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On-chip reference and sample-and-hold amplifier DNL = 0.25 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD
VIN+ SHA VIN- REFT REFB
PIPELINE ADC CORE
AD9215
CORRECTION LOGIC 10 OUTPUT BUFFERS OR D9 (MSB)
VREF SENSE REF SELECT 0.5V CLOCK DUTY CYCLE STABLIZER MODE SELECT
D0
APPLICATIONS
Ultrasound equipment IF sampling in communications receivers Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes
AGND
CLK
PDWN
MODE DGND
Figure 1.
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit, 65/80/105 MSPS analog-to-digital converters (ADC). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9215 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9215 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which can be used with the MSB to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9215 is available in both a 28-lead surface-mount plastic package and a 32-lead chip scale package and is specified over the industrial temperature range of -40C to +85C.
PRODUCT HIGHLIGHTS
1. The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. Operating at 105 MSPS, the AD9215 core ADC consumes a low 120 mW; at 80 MSPS, the power dissipation is 104 mW; and at 65 MSPS, the power dissipation is 96 mW. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be configured for single-ended or differential operation. The AD9215 is part of several pin compatible 10-, 12-, and 14-bit low power ADCs. This allows a simplified upgrade from 10 bits to 12 bits for systems up to 80 MSPS. The clock duty cycle stabilizer maintains converter performance over a wide range of clock pulse widths. The out of range (OR) output bit indicates when the signal is beyond the selected input range.
2.
3.
4.
5. 6.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
02874-A-001
AD9215 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels ........................................................... 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Equivalent Circuits....................................................................... 8 Definitions of Specifications ....................................................... 8 Typical Performance Characteristics ........................................... 10 Applying the AD9215 Theory of Operation............................... 14 Clock Input and Considerations .............................................. 15 Evaluation Board ........................................................................ 18 Outline Dimensions ....................................................................... 33 Ordering Guide........................................................................... 34
REVISION HISTORY
2/04--Data Sheet Changed from a REV. 0 to a REV. A Renumbered Figures and Tables ..............................UNIVERSAL Changes to Product Title................................................................ 1 Changes to Features ........................................................................ 1 Changes to Product Description ................................................... 1 Changes to Product Highlights ..................................................... 1 Changes to Specifications............................................................... 2 Changes to Figure 2......................................................................... 4 Changes to Figures 9 to 11 ........................................................... 10 Added Figure 14 ............................................................................ 10 Added Figures 16 and 18 .............................................................. 11 Changes to Figures 21 to 24 and 25 to 26................................... 12 Deleted Figure 25........................................................................... 12 Changes to Figures 28 and 29 ...................................................... 13 Changes to Figure 31..................................................................... 14 Changes t0 Figure 35..................................................................... 16 Changes to Figures 50 through 58............................................... 26 Added Table 11 .............................................................................. 31 Updated Outline Dimensions...................................................... 32 Changes to Ordering Guide ......................................................... 33 5/03--Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9215 SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. DC Specifications
AD9215BRU-65/ AD9215BCP-65 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error1 Gain Error Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error1 Reference Voltage (1 V Mode) INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD IDRVDD PSRR POWER CONSUMPTION Sine Wave Input IAVDD IDRVDD Standby Power4
1 2 1 2 2 2 2 2
AD9215BRU-80/ AD9215BCP-80 Min 10 Typ Max
AD9215BRU-105/ AD9215BCP-105 Min 10 Typ Max Unit Bits
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full Full Full Full
Test Level VI VI VI VI VI VI V V V VI V V V V V IV IV V V
Min 10
Typ
Max
Guaranteed 0.3 2.0 0 +1.5 +4.0 -1.0 0.5 +1.0 0.5 1.2 +15 +30 230 2 0.2 1 0.2 0.8 0.4 1 2 2 7 35
Guaranteed 0.3 2.0 +1.5 +4.0 -1.0 0.5 +1.0 0.5 1.2 +15 +30 230 2 0.2 1 0.2 0.8 0.4 1 2 2 7 35
Guaranteed 0.3 2.0 +1.5 +4.0 -1.0 0.6 +1.2 0.65 1.2 +15 +30 230 2 0.2 1 0.2 0.8 0.4 1 2 2 7 35
% FSR % FSR LSB LSB ppm/C ppm/C ppm/C mV mV mV mV LSB rms LSB rms V p-p V p-p pF k
Full Full Full 25C Full
IV IV VI V V
2.7 2.25
3.0 2.5 32 7.0 0.1
3.3 3.6 35
2.7 2.25
3.0 2.5 34.5 8.6 0.1
3.3 3.6 39
2.7 2.25
3.0 2.5 40 11.3 0.1
3.3 3.6 44
V V mA mA % FSR
Full 25C 25C
VI V V
96 18 1.0
104 20 1.0
120 25 1.0
mW mW mW
1 2
With a 1.0 V internal reference. Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). Rev. A | Page 3 of 36
AD9215
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted. Table 2. AC Specifications
AD9215BRU-65/ AD9215BCP-65 Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = Nyquist1 fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = Nyquist1 fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = Nyquist1 fIN = 70 MHz fIN = 100 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = Nyquist1 fIN = 70 MHz fIN = 100 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = Nyquist1 fIN = 70 MHz fIN = 100 MHz TWO-TONE SFDR (AIN = -7 dBFS) fIN1 = 70.3 MHz, fIN2 = 71.3 MHz fIN1 = 100.3 MHz, fIN2 = 101.3 MHz ANALOG BANDWIDTH Temp Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C 25C 25C 25C Test Level VI I VI I V V VI I VI I V V VI I VI I V V VI I VI I V V VI I VI I V V V V V Min 56.0 57.0 56.0 56.5 Typ 58.5 59.0 58.0 58.5 Max AD9215BRU-80/ AD9215BCP-80 Min 56.0 57.0 56.0 56.5 Typ 58.5 59.0 58.0 58.5 58.0 57.5 58.5 58.5 58.0 58.5 56.0 55.5 9.5 9.5 9.4 9.5 9.1 9.0 -78 -80 -76 -78 -70 -70 -77 -77 -77 -77 -80 -80 75 74 300 -64 -65 -63 -65 Max AD9215BRU-105/ AD9215BCP-105 Min Typ 57.5 58.5 57.5 58.0 57.8 57.7 57.6 58.2 57.3 57.8 57.7 57.4 9.3 9.5 9.4 9.4 9.4 9.3 -78 -84 -74 -75 -75 -74 -73 -75 -71 -75 -75 -75 75 74 300 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz
56.6 56.4
55.8 56.5 55.8 56.3
58.5 59.0 58.0 58.5
55.7 56.8 55.5 56.3
56.5 56.1
9.1 9.2 9.1 9.1
9.5 9.6 9.4 9.5
9.0 9.3 9.0 9.0
9.2 9.1
-78 -80 -77 -78
-64 -65 -64 -65
-70 -61
-77 -78 -77 -78
-67 -68 -67 -68
-66 -68 -66 -68
-66 -63
300
1
Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105. Rev. A | Page 4 of 36
AD9215
Table 3. Digital Specifications
AD9215BRU-65/ AD9215BCP-65 Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 DRVDD = 2.5 V High Level Output Voltage Low Level Output Voltage Temp Full Full Full Full Full Test Level IV IV IV IV V Min 2.0 -650 -70 2 0.8 +10 +10 Typ Max AD9215BRU-80/ AD9215BCP-80 Min 2.0 -650 -70 2 0.8 +10 +10 Typ Max AD9215BRU-105/ AD9215BCP-105 Min 2.0 -650 -70 2 0.8 +10 +10 Typ Max Unit V V A A pF
Full Full
IV IV
2.45 0.05
2.45 0.05
2.45 0.05
V V
1
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/ AD9215BCP-65 Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLOCK Period DATA OUTPUT PARAMETERS Output Delay1 (tOD) Pipeline Delay (Latency) Aperture Delay Aperture Uncertainty (Jitter) Wake-Up Time2 OUT-OF-RANGE RECOVERY TIME Temp Full Full Full Full Full 25C 25C 25C 25C Test Level VI V V VI V V V V V
N N-1 ANALOG INPUT
AD9215BRU-80/ AD9215BCP-80 Min 80 Typ Max
AD9215BRU-105/ AD9215BCP-105 Unit Min 105 Typ Max MSPS MSPS ns ns Cycles ns ps rms ms Cycles
Min 65
Typ
Max
5 15.4 2.5 4.8 5 2.4 0.5 7 1 6.5 12.5 2.5 4.8 5 2.4 0.5 7 1
5 9.5 6.5 2.5 4.8 5 2.4 0.5 7 1
5
6.5
N+1 N+2 N+8 N+3 N+4 N+5 N+6 N+7
tA
CLK DATA OUT
tPD
Figure 2. Timing Diagram
1 2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB. Rev. A | Page 5 of 36
02874-A-002
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
N+2
AD9215 ABSOLUTE MAXIMUM RATINGS1
Table 5.
Mnemonic ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature With Respect to Min -0.3 -0.3 -0.3 -3.9 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150 Unit V V V V V V V V V V V C C C C
EXPLANATION OF TEST LEVELS
Test Level I II III IV V VI 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
-65
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances 28-lead TSSOP: JA = 67.7C/W, 32-lead LFCSP: JA = 32.7C/W; heat sink soldered down to ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 36
AD9215 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
31 AGND 28 AGND 32 AVDD 27 AVDD
OR 1 MODE 2 SENSE 3 VREF 4 REFB 5 REFT 6 28 D9 (MSB) 27 D8 26 D7 25 D6 24 DRVDD
DNC 1 CLK 2 DNC 3 PDWN 4 DNC 5 DNC 6 DNC 7 DNC 8
(LSB) D0 9 DRGND 15 DRVDD 16 D1 10 D2 11 D3 12 D4 13 D5 14
25 REFB
26 REFT
29 VIN+
30 VIN-
24 VREF 23 SENSE 22 MODE
AD9215
23 DRGND
TOP VIEW 22 D5 AVDD 7 (Not to Scale) 21 D4 AGND 8 VIN+ 9 VIN- 10 AGND 11 AVDD 12 CLK 13 PDWN 14 20 D3 19 D2 18 D1
AD9215
TOP VIEW (Not to Scale)
21 OR 20 D9 (MSB) 19 D8 18 D7 17 D6
16 DNC 15 DNC
02874-A-003
DNC = DO NOT CONNECT
DNC = DO NOT CONNECT
Figure 3. TSSOP (RU-28)
Figure 4. LFCSP (CP-32)
Table 6. Pin Function Descriptions
TSSOP Pin No. 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14 15 to 16 17 to 22, 25 to 28 23 24 LFCSP Pin No. 21 22 23 24 25 26 27, 32 28, 31 29 30 2 4 1, 3, 5 to 8 9 to 14, 17 to 20 15 16 Mnemonic OR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- CLK PDWN DNC D0 (LSB) to D9 (MSB) DRGND DRVDD Description Out-of-Range Indicator. Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. Reference Mode Selection. Voltage Reference Input/Output. Differential Reference (Negative). Differential Reference (Positive). Analog Power Supply. Analog Ground. Analog Input Pin (+). Analog Input Pin (-). Clock Input Pin. Power-Down Function Selection (Active High). Do not connect, recommend floating this pin. Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 F capacitor. Recommended decoupling is 0.1 F in parallel with 10 F.
Rev. A | Page 7 of 36
02874-A-004
17 D0 (LSB)
AD9215
EQUIVALENT CIRCUITS
AVDD
fications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
MODE
02874-A-005
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicate that all 1024 codes, respectively, must be present over all operating ranges.
Figure 5. Equivalent Analog Input Circuit
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective number of bits
AVDD
MODE 20k
02874-A-006
N = (SINAD - 1.76)/6.02 Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Figure 6. Equivalent MODE Input Circuit
DRVDD
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions.
D9-D0, OR
02874-A-007
Figure 7. Equivalent Digital Output Circuit
Integral Nonlinearity (INL)
AVDD
2.6k CLK 2.6k
02874-A-008
INL refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Figure 8. Equivalent Digital Input Circuit
Minimum Conversion Rate
DEFINITIONS OF SPECIFICATIONS
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Offset Error
The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Zero error is defined as the deviation of the actual transition from that point.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency-dependent noise on the input to the ADC.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these speci-
Output Propagation Delay
The delay between the clock logic threshold and the time when
Rev. A | Page 8 of 36
AD9215
all bits are within valid logic levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Power Supply Rejection
The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
Temperature Drift
The temperature drift for zero error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX.
Signal-to-Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
Rev. A | Page 9 of 36
AD9215 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, TA = 25C, 2 V differential input, AIN = -0.5 dBFS, VREF = 1.0 V, unless otherwise noted.
0 AIN = -0.5dBFS SNR = 58.0 ENOB = 9.4 BITS SFDR = 75.5dB
80 2V p-p SFDR (dBc) 75 AIN = -0.5dBFS
-20
AMPLITUDE (dBFS)
-40
70 1V p-p SFDR (dBc)
dB
-60
65
-80
60
2V p-p SNR (dB)
02874-A-062
1V p-p SNR (dB) 50 5 15 25 35 45 55 ENCODE (MSPS) 65 75 85
-120
0
6.56
13.13
19.69 26.25 32.81 FREQUENCY (MHz)
39.38
45.94
52.50
Figure 9. Single-Tone 32k FFT with fIN = 10.3 MHZ, fSAMPLE = 105 MSPS
0 AIN = -0.5dBFS SNR = 57.8 ENOB = 9.4 BITS SFDR = 75.0dB
Figure 12. AD9215-80 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
80 2V p-p SFDR (dBc) 75 AIN = -0.5dBFS
-20
AMPLITUDE (dBFS)
-40
dB
70
1V p-p SFDR (dBc)
-60
65
-80
60
2V p-p SNR (dB)
02874-A-063
1V p-p SNR (dB) 50 5 15 25 35 45 ENCODE (MSPS) 55 65
-120
0
6.56
13.13
19.69 26.25 32.81 FREQUENCY (MHz)
39.38
45.94
52.50
Figure 10. Single-Tone 32k FFT with fIN = 70.3 MHz, fSAMPLE = 105 MSPS
0 AIN = -0.5dBFS SNR = 57.7 ENOB = 9.3 BITS SFDR = 75dB
Figure 13. AD9215-65 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
85 2V p-p SFDR 80
-20
AMPLITUDE (dBFS)
-40
dB
75
-60
70
-80
65
02874-A-065
2V p-p SNR 55 0 20 40 60 80 100
-120
0
6.56
13.13
19.69 26.25 32.81 FREQUENCY (MHz)
39.38
45.94
52.50
fSAMPLE (MSPS)
Figure 11. Single-Tone 32k FFT with fIN = 100.3 MHz, fSAMPLE = 105 MSPS
Figure 14. AD9215-105 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Rev. A | Page 10 of 36
02874-A-066
-100
60
02874-A-013
-100
55
02874-A-012
-100
55
AD9215
80 70
80
75
60 50 80dB REFERENCE LINE 1V p-p SFDR (dBc)
SFDR 70
dB
40 30 20 10 0 -50 2V p-p SNR (dB)
dB
1V p-p SNR (dB) 2V p-p SFDR (dBc)
02874-A-014
65
60 SNR
02874-A-072
55
50
-45
-40
-35 -30 -25 -20 -15 ANALOG INPUT LEVEL
-10
-5
0
0
50
100 150 200 FREQUENCY (MHz)
250
300
Figure 15. AD9215-80 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 80 MSPS, fIN = 39.1 MHz
85
80 70 2 SFDR dBc 60 50
Figure 18. AD9215-105 SNR/SFDR vs. fIN, AIN = -0.5 dBFS, fSAMPLE = 105 MSPS
80
75 70
dB
dB
2V p-p SFDR (dBc) 65 60 2V p-p SNR (dB) 55
40 30 20 10 2V p-p SNR 0 -90 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT LEVEL (-dBFS) -10 0
02874-A-067
-70dBFS REFERENCE LINE 1V p-p SFDR (dBc) 1V p-p SNR
50 0 50 100 150 200 250 300
fIN (MHz)
Figure 16. AD9215-105 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 105 MSPS, fIN = 50.3 MHz
80 1V p-p SFDR (dBc) 70
75 80
Figure 19. AD9215-80 SNR/SFDR vs. fIN, AIN = -0.5 dBFS, fSAMPLE = 80 MSPS
60 80dB REFERENCE LINE 50
dB
2V p-p SFDR (dBc)
2V p-p SNR (dB)
dB
70
40 30 20 10 0 -50
65
1V p-p SNR (dB)
60
2V p-p SFDR (dBc)
02874-A-015
2V p-p SNR (dB)
02874-A-017
55
-45
-40
-35 -30 -25 -20 -15 ANALOG INPUT LEVEL
-10
-5
0
50 0 50 100 150 200 ANALOG INPUT (MHz) 250 300
Figure 17. AD9215-65 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 65 MSPS, fIN = 30.3 MHz
Figure 20. AD9215-65 SNR/SFDR vs. fIN, AIN = -0.5 dBFS, fSAMPLE = 65 MSPS
Rev. A | Page 11 of 36
02874-A-016
AD9215
0 AIN1, AIN2 = -7dBFS SFDR = 74dBc -20 60 SFDR -40 50 80 70
dB
dB
-60
40 80dBFS REFERENCE LINE 30
-80 20
02874-A-060
10 0 -60
-120 0 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
-55
-50
-45
-40
-35 -30 -25 AIN (dBFS)
-20
-15
-10
-5
Figure 21. Two-Tone 32k FFT with fIN1 = 70.1 MHz, and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
0 AIN1, AIN2 = -7dBFS SFDR = 74dBc -20
Figure 24. AD9215-80 Two-Tone SFDR vs. AIN, fIN1 = 100.3 MHz, and fIN2 = 101.3 MHz, fSAMPLE = 105 MSPS
80 75 70 65 60 SNR DCS ON SFDR DCS OFF SFDR DCS ON
-40
dB
dB
-60
55 50
-80
45 SNR DCS OFF
02874-A-061 02874-A-069
-100
40 35 30 20 30 40 50 60 CLOCK DUTY CYCLE HIGH (%) 70 80
-120 0 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
Figure 22. Two-Tone 32k FFT with fIN1 = 100.3 MHz, and fIN2 = 101.3 MHz, fSAMPLE = 105 MSPS
80 70 75 60 70 50 SFDR 80
Figure 25. SINAD, SFDR vs. Clock Duty Cycle, fSAMPLE = 105 MSPS, fIN = 50.3 MH
2V p-p SFDR (dBc)
40 30 20
02874-A-068
dBc
dB
65
1V p-p SFDR (dBc)
80dBFS REFERENCE LINE 60 2V p-p SINAD
10 0 -65
1V p-p SINAD 50 -40 -20 0 20 40 TEMPERATURE (C) 60 80
-55
-45 -35 -25 AIN1, AIN2 (dBFS)
-15
-5
Figure 23. AD9215-105 Two-Tone SFDR vs. AIN, fIN1 = 70.1 MHz, and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
Figure 26. SINAD, SFDR vs. Temperature, fSAMPLE = 105 MSPS, fIN = 50 MHz
Rev. A | Page 12 of 36
02874-A-070
55
02874-A-073
-100
AD9215
40 30 0.4 20 10 0 -10 -0.2 -20 -30 -40 -40
02874-A-025 02874-A-074
0.6
GAIN ERROR (ppm/C)
0.2
INL (LSB)
0
-0.4
-0.6
-20
0
20 40 TEMPERATURE (C)
60
80
0
128
256
384
512 CODE
640
768
896
1024
Figure 27. Gain vs. Temperature External 1 V Reference
0.5 0.4 0.3 0.2
Figure 29. AD9215-105 Typical INL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 CODE 640 768 896
02874-A-064
1024
Figure 28. AD9215-105 Typical DNL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
Rev. A | Page 13 of 36
AD9215 APPLYING THE AD9215 THEORY OF OPERATION
The AD9215 architecture consists of a front-end SHA followed by a pipelined switched capacitor ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. The input stage contains a differential SHA that can be configured as ac-coupled or dc-coupled in differential or single-ended modes. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. Redundancy is used in each one of the stages to facilitate digital correction of flash errors. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC's input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. The analog inputs of the AD9215 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. VCM = AVDD/2 is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 31).
85 80 2V p-p SFDR 75 70 65
dB
60 2V p-p SNR 55 50 45 40 0.25
02874-A-071
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 31. An input commonmode voltage of midsupply minimizes signal-dependent errors and provides optimum performance.
H
0.75 1.25 1.75 2.25 ANALOG INPUT COMMON-MODE VOLTAGE (V)
2.75
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as REFT = 1/2 (AVDD + VREF)
T VIN+ CPAR
0.5pF
T
T 0.5pF VIN-
02874-A-028
CPAR
T
REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum
H
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 30). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output
Rev. A | Page 14 of 36
AD9215
SNR performance is achieved with the AD9215 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VCMMIN = VREF/2 VCMMAX = (AVDD + VREF)/2 The minimum common-mode input level allows the AD9215 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN-. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN-. The AD9215 then accepts a signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.
R 2V p-p 49.9 R AVDD 1k 1k 0.1F C VIN- AGND C AVDD VIN+
AD9215
02874-A-031 02874-A-032
Figure 33. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are kept matched, there should be little effect on SNR performance. Figure 34 details a typical single-ended input configuration.
10F 1k 2V p-p 49.9 0.1F 1k R C AVDD VIN+
Differential Input Configurations
As previously detailed, optimum performance is achieved while driving the AD9215 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal.
1k 499 0.1F 1k 523 R C VCM 1V p-p 49.9 499 499 AVDD VIN+
AD9215
AVDD 1k 10F 1k 0.1F
R C
VIN- AGND
Figure 34. Single-Ended Input Configuration
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9215 contains a clock duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9215. As shown in Figure 25, noise and distortion performance are nearly flat over a 50% range of duty cycle. For best ac performance, enabling the duty cycle stabilizer is recommended for all applications. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate.
AD8138
R C
AD9215
02874-A-030
VIN- AGND
Figure 32. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9215. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependant on the input frequency and source impedance and should be reduced or removed. An example of this is shown in Figure 33.
Rev. A | Page 15 of 36
AD9215
Table 7. Reference Configuration Summary
Selected Mode Externally Supplied Reference Internal 0.5 V Reference Programmed Variable Reference Internally Programmed 1 V Reference External SENSE Connection AVDD VREF External Divider AGND to 0.2 V Internal Op Amp Configuration N/A Voltage Follower (G = 1) Noninverting (1 < G < 2) Internal Divider Resulting VREF (V) N/A 0.5 0.5 x (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF 2.0
Table 8. Digital Output Coding
Code 1023 512 511 0 VIN+ - VIN- Input Span = 2 V p-p (V) 1.000 0 -0.00195 -1.00 VIN+ - VIN- Input Span = 1 V p-p (V) 0.500 0 -0.000978 -0.5000 Digital Output Offset Binary (D9******D0) 11 1111 1111 10 0000 0000 01 1111 1111 00 0000 0000 Digital Output Twos Complement (D9******D0) 01 1111 1111 00 0000 0000 11 1111 1111 10 0000 0000
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tA) can be calculated with the following equation SNR Degradation = 20 x log10 [2 x x fINPUT x tA] In the equation, the rms aperture jitter, tA, represents the rootsum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9215. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
ber of output bits switching, which are determined by the encode rate and the characteristics of the analog input signal. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 35 was taken with a 5 pF load on each output driver.
40 AD9215-105 IAVDD 13 35 AD9215-65/80 IAVDD 11 9 7 25 5 3 20 IDRVDD 15 5 15 25 35 55 65 fSAMPLE (MSPS) 45 75 85 95 1 -1 105
02874-A-075
15
IAVDD (mA)
30
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as IDRVDD = VDRVDD x CLOAD x fCLOCK x N where N is the number of output bits, 10 in the case of the AD9215. This maximum current is for the condition of every output bit switching on every clock cycle, which can only occur for a full-scale square wave at the Nyquist frequency, fCLOCK/2. In practice, the DRVDD current is established by the average num-
Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. By asserting the PDWN pin high, the AD9215 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9215 into its normal operational mode.
Rev. A | Page 16 of 36
IDRVDD
AD9215
In standby mode, low power dissipation is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 10 F decoupling capacitors on REFT and REFB, it takes approximately one second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation.
R2 VREF = 0.5 x 1 + R1
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F 7k SELECT LOGIC SENSE 0.5V 0.1F 10F
Digital Outputs
The AD9215 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
7k
AD9215
Figure 36. Internal Reference Configuration
Timing
The AD9215 provides latched data outputs with a pipeline delay of five clock cycles. Data outputs are available one propagation delay (tOD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9215; these transients can detract from the converter's dynamic performance. The lowest typical conversion rate of the AD9215 is 5 MSPS. At clock rates below 5 MSPS, dynamic performance may degrade.
In all reference configurations, REFT and REFB drive the ADC conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F R2 0.5V SELECT LOGIC 0.1F 10F
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the AD9215. The input range can be adjusted by varying the reference voltage applied to the AD9215, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.
SENSE R1
02874-A-034
02874-A-035
AD9215
Internal Reference Connection
A comparator within the AD9215 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 1 If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 36), setting VREF to 1 V. Connecting the SENSE pin to the VREF pin switches the amplifier output to the SENSE pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 V reference output. If an external resistor divider is connected as shown in Figure 37, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
Figure 37. Programmable Reference Configuration
If the internal reference of the AD9215 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading.
Rev. A | Page 17 of 36
AD9215
0.05 0 VREF = 0.5V
negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.
VREF ERROR (%)
-0.05
Operational Mode Selection
VREF = 1.0V
-0.10
-0.15
-0.25 0 0.5 1.0 1.5 ILOAD (mA) 2.0 2.5 3.0
02874-A-036
-0.20
As discussed earlier, the AD9215 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (DCS). The MODE pin is a multilevel input that controls the data format and DCS state. For best ac performance, enabling the duty cycle stabilizer is recommended for all applications. The input threshold values and corresponding mode selections are outlined in Table 9. As detailed in Table 9, the data format can be selected for either offset binary or twos complement.
Table 9. Mode Selection
MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled
Figure 38. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 39 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
0.6
The MODE pin is internally pulled down to AGND by a 20 k resistor.
EVALUATION BOARD
VREF = 0.5V
0.5
VREF ERROR (%)
0.4
0.3 VREF = 1.0V 0.2
0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 39. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and
- 3.0V +
02874-A-037
0.1
The AD9215 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through an AD8351 driver, a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 40 shows the typical bench characterization setup used to evaluate the ac performance of the AD9215. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. Complete schematics and layout plots follow that demonstrate the proper routing and grounding techniques that should be applied at the system level.
2.5V - + - 2.5V + 5.0V - +
AVDD GND DRVDD GND VDL REFIN R AND S SMG, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER XFMR INPUT
VAMP DATA CAPTURE AND PROCESSING
AD9215
10MHz REFOUT R AND S SMG, 2V p-p SIGNAL SYNTHESIZER EVALUATION BOARD CLK
Figure 40. Evaluation Board Connections
Rev. A | Page 18 of 36
02874-A-038
P12
GND H1 MTHOLE6 H2 MTHOLE6
1 2 3 4 5 6 EXTREF 1V MAX E1 AVDD P6 1
R1 10k
AVDD GND P11 P9 P8
P2
C13 0.10F
C22 10F
2 MODE 2 P5
R5 1k
H3 MTHOLE6 H4 MTHOLE6
AVDD
3.0V
2.5V DRVDD
2.5V
R9 10k
C12 0.1F
P3
3 C8 0.1F GND
R6 1k
C9 0.10F 4 C29 10F GND C7 0.1F C11 0.1F GND P4
GND
GND
OVERRANGE BIT RP2 220 (MSB) 1 2 3 4 5 6 7 8 16 15 14 DRVDD GND 16 15 14 13 12 11 10 9 ORX D13X D12X D11X D10X D9X D8X D7X
C6 0.1F AVDD AMPIN R12 0 XOUT C21 SELECT GND AVDD GND GND C16 0.1F GND C5 0.1F OR L1 FOR FILTER GND C23 SELECT R3 0 AMPINB C18 0.10F
R SINGLE ENDED
R42 0 GND R36 1k R26 1k AVDD GND VIN+ VIN-
28 AGND 29 VIN+ 30 VIN- 31 AGND 32 AVDD 25 REFB 26 REFT 27 AVDD
VREF 24 SENSE 23 MODE 22 OR 21 D9 20
GND
1 DNC 2 CLK
3 DNC 4 PDWN 5 DNC 6 DNC 7 DNC 8 DNC
Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
AD9215
U4
D8 19 D7 18 D6 17
DRVDD DGND D5 D4
5.0V
P10
R7 1k
VAMP
GND GND
GND
GND VDL
P7 A B E P1
C
D
Rev. A | Page 19 of 36
R4 33 R10 36 E 45 C26 10pF R2 XX C19 10pF
6 2 CT 4
1 2 3 (LSB) 4 5 6 7 8 RP1 220 D1 10 D0 9
16 15 14 13 12 11 10 9
13 D3 12 D2 11
D6X D5X D4X D3X D2X D1X D0X
J1
L1 100
T1 ADT1-1WT
C15 AMP 0.1F
XFRIN1 1 5 NC 3 GND
GND GND XOUTB R11 36
PRI SEC
OPTIONAL XFR T2 FT C1-1-13 5 1 XOUT X FRIN 2 CT 3 4 GND XOUTB
CLK R15 33
R8 1k
P14
PRI SEC
R18 25
AVDD AVDD R13 1k R25 1k GND
P13
GND
SENSE PIN SOLDERABLE JUMPER: E TO A: EXTERNAL VOLTAGE DIVIDER E TO B: INTERNAL 1V REFERENCE (DEFAULT) E TO C: EXTERNAL REFERENCE E TO D: INTERNAL 0.5V REFERENCE
R3, R17, R18 ONLY ONE SHOULD BE ON BOARD AT A TIME
GND
AD9215
02874-A-039
MODE PIN SOLDERABLE JUMPER: 5 TO 1: TWOS COMPLEMENT/DCS OFF 5 TO 2: TWOS COMPLEMENT/DCS ON 5 TO 3: OFFSET BINARY/DCS ON 5 TO 4: OFFSET BINARY/DCS OFF
U1 74LVTH162374 25 26 GND GND MSB GND 8 10 8 10 12 14 16 18 20 22 24 26 28 30 32 34 DRY GND 36 38 40 28 30 32 34 36 38 40 DRVDD 12 14 16 18 20 22 24 GND 26 6 4 6 DR 4 2 1 27 28 29 2D6 2D5 VCC 2D4 2Q4 2Q3 GND 2Q2 2Q1 1Q8 13 12 11 10 9 8 DRVDD 7 6 5 4 3 2 1 GND GND 1Q7 GND 1Q6 1Q5 VCC 1Q4 1Q3 15 14 16 GND 2D3 GND 2D2 2D1 1D8 1D7 GND 1D6 1D5 VCC 1D4 1D3 18 17 2Q5 VCC 19 20 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE OUT R38 1k VAMP VAMP C24 10F GND POWER DOWN USE R40 OR R41 GND C44 0.1F VAMP GND GND C45 0.1F GND R39 1k IN GND 1D2 1D1 1CLK 1 GND 1Q2 1Q1 21 2D7 GND 2Q7 GND 2Q6 2DB 2QB 23 22 1 DRY 2 2CLK 2OE 24 GND P12 HEADER 40
AD9215
CLKAT/DAC
MSB
DRX D13X
GND D12X
D11X
DRVDD
D10X D9X
GND D8X
D7X D6X
D5X
GND
D4X D3X
DRVDD D2X D1X
LSB
GND D0X
3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 35 35 37 37 39 39 GND
Figure 42. LFCSP Evaluation Board, Digital Path
Rev. A | Page 20 of 36
R41 10k PWDN 1 C28 0.1F INHI 3 INLO 4 C35 0.10F R35 25 R33 25 RPG2 5 R34 1.2k RGP1 2 R40 10k
CLKLAT/DAC
U3 AD8351
10 VOCM 9 VPOS 8 OPHI 7 OPLO 6 COMM GND
R14 25 AMPINB R16 0 C27 0.1F
AMP IN
AMP
R19 50
GND GND
R17 0
C17 0.1F
AMPIN
02874-A-040
VDL AVDD DRVDD VDL C2 22F C49 0.001F GND DIGITAL BYPASSING LATCH BYPASSING GND ANALOG BYPASSING C30 0.001F C31 0.1F C34 0.1F C36 0.1F C38 0.001F C39 C1 0.001F 0.1F C47 0.1F C48 0.001F C20 10F C32 0.001F C33 C14 0.1F 0.001F C41 0.1F C25 10F
DRVDD AVDD
C10 22F GND
C4 10F
C3 10F
C37 0.1F
C40 0.001F
GND DUT BYPASSING
VAMP
C46 10F CLOCK TIMING ADJUSTMENTS FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 R28 0 ENCX ENC ENC E50 1Y 2Y
GND
GND
CLK
74VCX86 ENCX 3 6 7 GND 8 11 14 4Y U5
PWR
R27 0 R32 1k
2B
E51 1 1A 2 1B 4 2A 3Y
SCHEMATIC SHOWS TWO-GATE DELAY SETUP. FOR ONE DELAY REMOVE R22 AND R37 ATTACH Rx (Rx = 0) R23 0 CLKLAT/DAC
Figure 43. LFCSP Evaluation Board Schematic, Clock Input
R37 25 VDL
Rev. A | Page 21 of 36
VDL GND VDL E52 E53 5 9 10 12 13
3A 3B 4A 4B
Rx DNP DR
R22 0
ENCODE GND E31 R21 1k VDL E43 E44 GND E35
C43 0.1F
R31 1k
VDL R20 1k
J2 R29 50 GND GND R30 1k
GND
R24 1k VDL GND
02874-A-041
AD9215
AD9215
02874-A-042
Figure 44. LFCSP Evaluation Board Layout, Primary Side
Figure 45. LFCSP Evaluation Board Layout, Secondary Side
Rev. A | Page 22 of 36
02874-A-043
AD9215
02874-A-044
Figure 46. LFCSP Evaluation Board Layout, Ground Plane
Figure 47. LFCSP Evaluation Board Layout, Power Plane
Rev. A | Page 23 of 36
02874-A-045
AD9215
02874-A-046
Figure 48. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 49. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 24 of 36
02874-A-047
AD9215
Table 10. LFCSP Evaluation Board Bill of Materials (BOM)
Item 1 Qty 18 Omit1 Reference Designator C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 C6, C18, C27, C17, C28, C35, C45, C44 C2, C3, C4, C10, C20, C22, C25, C29 C46, C24, C14, C30, C32, C38, C39 C40, C48, C49 C19 C21, C23 C26 E31, E35, E43, E44, E50, E51, E52, E53 E1, E45 J1, J2 L1 P2 P12 R3, R12, R23, R18, RX R37, R22, R42, R16, R17, R27 R4, R15 R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 R19 RP1, RR2 T1 U1 U4 U5 PCB U3 T2 R9, R1, R2, R38, R39 R18, R14, R35 R40, R41 R34 R33 Device Chip Capacitor Package 0603 Value 0.1 F Recommended Vendor/ Part Number
8 2 8 2 3 4 5 6 8 1 2 1 9 2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2 1 1 1 5 6 2 14 2 1 1 2 1 1 1 1 1 1 1 5 3 2 1 1
Tantalum Capacitor
TAJD
10 F
Chip Capacitor Chip Capacitor Chip Capacitor Header
0603 0603 0603 EHOLE
0.001 F 10 pF 10 pF Jumper Blocks
SMA Connector/50 Inductor Terminal Block Header Dual 20-Pin RT Angle Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Resistor Pack ADT1-1WT 74LVTH162374 CMOS Register AD9215BCP ADC (DUT) 74VCX86M AD9XXBCP/PCB AD8351 Op Amp MACOM Transformer Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor
SMA 0603 TB6 HEADER40 0603 0603 0603 0603 0603 R_742 AWT1-T1 TSSOP-48 CSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 0603
10 nH
Coilcraft/0603CS10NXGBU Wieland/25.602.2653.0 z5-530-0625-0 Digi-Key S2131-20-ND
0 33 1 36 50 220 Digi-Key CTS/742C163220JTR Mini-Circuits
1-1 TX Select 25 10 k 1.2 k 110
Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. MACOM/ETC1-1-13
1
These items are included in the PCB design but are omitted at assembly.
Rev. A | Page 25 of 36
AD9215
MODE SELECT CONFIGURATION E:2C/DCS OFF F:2C/DCS ON G:OB/DCS ON H:OB/DCS OFF VREF MODE SELECT DRVDD
REFERENCE CONFIGURATION A: EXTERNAL VOLTAGE DIVIDER REFERENCE B: INTERNAL 1V REFERENCE C: EXTERNAL REFERENCE D: INTERNAL 0.5V REFERENCE 1V MAX
E24
E26 E28
AVDD + C52 10F 1 2 3 4 1
C30 0.1F
E6 E7 E
E27
R4 10k GND AVDD GND GND
R8 1k
GND
GND
AVDD
VCLK
GND
VDL
E16
E22
E18
E21
E1 E5 F
3.0V
2.5V DRVDD
3.0V
3.0V
E17
E19
E23
E20
R10 1k SENSE E3 E2 G GND R9 1k GND + OR1 C17 0.1F E4 E8 H OVERRANGE BIT (MSB) C15 0.1F
GND GND C16 0.1F C29 10F C13 0.1F GND
GND
RP2 220 1 2 3 4 5 6 7 8 DRVDD GND AVDD GND 16 15 14 13 12 11 10 9
SINGLE-ENDED INPUT OPERATION 1. PLACE R7( 50), R5( 0) AND R46 (25) 2. PLACE C23 (0.1F), C9 (0.1F) 3. REMOVE C33, C1, R34, R6, C32
C9 0.1F AVDD GND AMPIN R6 0 R19 33 C7 0.001F GND GND C6 0.1F R21 33 C5 10pF R16 XX C11 0.1F GND GND AIN C8 10pF AIN
R5 0
R44 1k
R45 1k
ORX D9X D8X D7X D6X D5X
02874-A-048
Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT
A B C D
Rev. A | Page 26 of 36
PRI SEC COM E45 R32 36 E12
1 5 3 6 2 4
DIFFERENTIAL INPUT
RP1 220
AMP R33 36
J1
C32 0.1F
L1 10nH
GND AVDD
R7 50 GND T1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
OR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- AGND AVDD CLK PWDN
D9 D8 D7 D6 DRVDD DRGND D5 D4 D3 D2 D1 D0 DNC DNC
28 27 26 25 24 23 22 21 20 19 18 17 16 15 (LSB) GND DEVICE = AD9215 U1 PARTS = 1
GND
OPTIONAL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
D4X D3X D2X D1X D0X NCX NC2X
GND R34 0 AVDD R24 1k C23 0.1F R25 25 AMPIN
AVDD
R29 1k
CLK
R1 10 OPTIONAL
R11 1k GND
E32 GND C14 0.1F C12 0.1F
ANALOG INPUT OPTIONS 1. R6, R34 FOR DIFFERENTIAL OPERATION 2. C1, C33 FOR OP AMP OPERATION 3. R7, R46, R5, C9, C23 FOR SINGLE-ENDED OPERATION E9 AVDD E11
R3 5k
COMMON MODE PLEASE JUMPER E45 TO E32 DC VOLTAGE ADJUST OR JUMPER E45 TO E12 CAPACITOR TO GROUND GND GND
GND
5.0V
C18 0.1F
R15 10k
VAMP
AVDD VDL VCLK
E25
E29
P2
OPTIONAL
2
3
4
GND RP3 220 VDL U2
U4 74LVT574 DEVICE = 74LVT574A
ORX MSB D9X D8X D7X D6X D5X D4X GND GND MSB GND DRX GND GND CLKLAT/DAC
1 2 3 4 5 6 7 8 9 10 OE X0 X1 X2 X3 X4 X5 X6 X7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CP 20 19 18 17 16 15 14 13 12 11
U3 74LVT574 DEVICE = 74LVT574A VDL GND GND RP4 220 GND
OUT OF RANGE BIT STRAP THIS AT ASSEMBLY E30 E13 E14 VAMP C47 10F C41 0.1F GND + GND
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 GND
GND GND GND D3X LSB D2X D1X D0X NCX NC2X GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDL R20 150 CLKLAT/DAC R23 100 C31 10pF GND R22 10k R47 10k GND VAMP VAMP R49 1k
02874-A-049
Figure 51. TSSOP Evaluation Board, Digital Path
Rev. A | Page 27 of 36
C44 0.1F AMP R50 25 1 2 3 4 5 R31 100 C45 0.1F R51 25 R36 25 PWUP RGP1 INHI INLO RGP2 GND
1 2 3 4 5 6 7 8 9 10 OE X0 X1 X2 X3 X4 X5 X6 X7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CP
20 19 18 17 16 15 14 13 12 11
C42 0.1F R48 1k GND C43 0.001F R28 0 R17 0 R27 0 U6 DEVICE = AD8351 R30 1.2k GND C1 0.1F AMPIN VOCM VPOS OPHI OPLO COMM 10 9 8 7 6 GND
C33 0.1F AMPIN
AD9215
AD9215
AVDD VDL DRVDD + C3 22F C50 10F C34 0.1F C35 0.001F C49 0.001F C51 0.1F C46 0.1F C21 0.1F C19 0.001F C48 0.1F + C2 + 22F C10 + 22F C4 + 10F DRVDD AVDD
VCLK
GND DUT BYPASSING VDL + C25 10F C24 0.1F GND U3/U4 BYPASSING U5 BYPASSING C26 0.1F C37 0.001F C38 0.001F C36 0.1F C39 0.001F C20 10F C27 + 10F + VCLK
GND
AVDD BYPASSING
GND
GND DUT DRVDD BYPASSING
GND
ENCODE FROM XOR FOR A BUFFERED ENCODE USE R37 FOR A DIRECT ENCODE USE R35 ENCX ENC R35 0
1A 1B 2A 2B 3A 3B 4A 4B 1Y
R37 0 ENCX
CLK
AVDD
ENC
U5 74VCX86
SCHEMATIC SHOWS 1-GATE DELAY SETUP FOR TWO-GATE DELAY REMOVE RESISTOR R52 ADD RESISTORS R38 AND R18
ENCODE
C40 0.1F
R42 1k
GND
R25 0
J3 R40 50 GND GND GND R41 1k
CLKLAT/DAC DRX VCLK R18 0
02874-A-050
Figure 52. TSSOP Evaluation Board Schematic, Clock Input
Rev. A | Page 28 of 36
1 2 4 5 9 10 12 13 3 6 2Y 7 8 GND 3Y 11 14 PWR 4Y R38 0 E35 E36 E43 E44 E52 E53 E50 E51 R39 1k VCLK GND VCLK GND VCLK R26 1k R2 1k GND VCLK R43 1k J4 GND
R52 0
DRX EXTERNAL DATA READY OPTIONAL
C28 R14 0.1F 50 GND GND
DRX
AD9215
Figure 53. TSSOP Evaluation Board Layout, Primary Side
02874-A-051
Figure 55. TSSOP Evaluation Board Layout, Ground Plane
Figure 54. TSSOP Evaluation Board Layout, Secondary Side
Figure 56. TSSOP Evaluation Board Layout, Power Plane
Rev. A | Page 29 of 36
02874-A-054
02874-A-052
02874-A-053
AD9215
02874-A-055
Figure 57. TSSOP Evaluation Board Layout, Primary Silkscreen
Figure 58. TSSOP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 30 of 36
02874-A-056
AD9215
Table 11. TSSOP Evaluation Board Bill of Materials (BOM)
Item 1 Qty. 11 Omit Reference Designator C2 to C4, C10, C20, C25, C27, C29, C47, C50, C52 C47 2 2 1 3 15 C5,C8 C31 C6, C9, C13, C15 to C18, C21, C24, C26, C30, C32, C34, C36, C40, C46, C48, C51 3 8 6 1 1 11 2 10 4 8 11 2 1 12 13 14 15 16 17 18 19 20 21 22 23 4 2 2 1 2 4 2 4 1 1 1 1 C12, C14, C23, C28 C7, C19, C35, C19, C37 to C39, C49 C1,C33, C41 to C42, C44 to C5 C43 C11 R2, R8 to R11, R24, R26, R29, R39, R41 to R45 R48, R49 R6, R25, R34, R37 R5, R35, R17 to R18, R27 to R28, R38, R52 R7, R40 R14 R19, R21 R32, R33 R16 R4, R15, R20, R22 to R23, R47 R48, R49 R36, R46, R50 to R51 R31 R30 R3 R1 RP1 to RP4 BRES603 RES0603 BRES603 BRES603 BRES603 BRES603 BRES603 BRES603 BRES603 BRES603 Potentiometer Resister Pack
Rev. A | Page 31 of 36
Device Tantalum Capacitor
Package TAJD
Value 10 F
Recommended Vendor/Part No.
Chip Capacitor
0603
10 pF
Chip Capacitor
0603
0.1 F
4 5 6 7 8 9
Chip Capacitor Chip Capacitor BCAP0402 BCAP0402 BCAP0603 BRES603
0603 0603 0402 0402 0603 0603A
Select 0.001 F 0.1 F 0.001 F Select 1 k
BRES603
0603A
0
BRES603
0603A
50
0603A 0603A 0603 0603 0603A 0603 0603 0603 0603 0603 RJ24FW 220*
33 36 Select 10 k Select 1 k 25 100 1.2 k 5 k 10 k 742C163221
AD9215
Item 24 25 26 27 28 29 30 31 2 1 32 2 Qty. 1 1 1 1 2 1 1 Omit Reference Designator L1 T1 U1 U2 U3, U4 U5 U6 J1, J3 J4 P1, P2 Power Connector PTMICRO4 Weiland Z5.531.3425.0 Posts 25.602.5453.0 Top TSW-120-07-G-S SMT-100-BK-G Device Chip Inductor 1:1 RF Transformer ADC Right Angle 40-Pin Header Octal D-Type Flip-Flop Quad XOR Gate High Speed Amplifier SMB Connecter SO14 SOMB10 SMBP Package 0603 CD542 28TSSOP Value 10 nH Recommended Vendor/Part No. Coilcraft/0603CS10NXGBU Mini-Circuits AWT1-1T Analog Devices, Inc. AD9215 Samtec TSW-120-08-T-D-RA Fairchild 74LVT57MSA Fairchild 74VCX86M Analog Devices, Inc. AD8351ARM
33
26
E1/E5, E2/E3, E4/E8, E9/E11, E6/E7, E16/E17, E19/E22, E18/E23, E21/20, E35/E51, E36/E50, E43/E53, E44/E52 12 E24/E27, E25/E26, E28/E29, E13/E14/E30, E12/E32/E45
Headers/Jumper Blocks
34
Wirehole
Rev. A | Page 32 of 36
AD9215 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30 6.40 BSC
1 14
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
17 16
9
0.25 MIN 3.50 REF
12 MAX
1.00 0.85 0.80 SEATING PLANE
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 NOTE: IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS AN INCREASED RELIABILITY OF THE SOLDER JOINTS, AND THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS ACHIEVED WITH THE EXPOSED PADDLE SOLDERED TO THE CUSTOMER BOARD.
Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters
Rev. A | Page 33 of 36
AD9215
ORDERING GUIDE
Model AD9215BRU-65 AD9215BRU-80 AD9215BRU-105 AD9215BRURL7-65 AD9215BRURL7-80 AD9215BRURL7-105 AD9215BRU-65EB AD9215BRU-80EB AD9215BRU-105EB AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 AD9215BCPZ-651 AD9215BCPZ-801 AD9215BCPZ-1051 AD9215BCP-65EB AD9215BCP-80EB AD9215BCP-105EB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) AD9215BRU-65 Evaluation Board (TSSOP) AD9215BRU-80 Evaluation Board (TSSOP) AD9215BRU-105 Evaluation Board (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) AD9215BCP-65 Evaluation Board (LFCSP) AD9215BCP-80 Evaluation Board (LFCSP) AD9215BCP-105 Evaluation Board (LFCSP) Package Option RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 CP-32 CP-32 CP-32 CP-32 CP-32 CP-32 CP-32 CP-32 CP-32
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
1
Z = Pb-free part.
Rev. A | Page 34 of 36
AD9215 NOTES
Rev. A | Page 35 of 36
AD9215 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02874-0-2/04(A)
Rev. A | Page 36 of 36

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