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| www..com S3C8275/F8275/C8278 /F8278/C8274/F8274 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.2 www..com Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S3C8275/F8275/C8278/F8278/C8274/F8274 8-Bit CMOS Microcontrollers User's Manual, Revision 1.2 Publication Number: 21.2-S3-C8275/F8275/C8278/F8278/C8274/F8274-082005 (c) 2005 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(031)-209-1934 FAX: (82)-(031)-209-1889 Home-Page URL: Http://www.samsungsemi.com Printed in the Republic of Korea www..com NOTIFICATION OF REVISIONS ORIGINATOR: PRODUCT NAME: DOCUMENT NAME: DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY: Samsung Electronics, LSI Development Group, Ki-Heung, South Korea S3C8275/F8275/C8278/F8278/C8274/F8274 8-bit CMOS Microcontroller S3C8275/F8275/C8278/F8278/C8274/F8274 User's Manual, Revision 1.2 21.2-S3- C8275/F8275/C8278/F8278/C8274/F8274 -082005 August, 2005 As a result of additional product testing and evaluation, some specifications published in the S3C8275/F8275/C8278/F8278/C8274/F8274 User's Manual, Revision 1, have been changed. These changes for S3C8275/F8275/C8278/ F8278/C8274/F8274 microcontroller, which are described in detail in the Revision Descriptions section below, are related to the followings: -- Chapter 16. Embedded flash memory interface -- Chapter 17. Electrical Data DIRECTIONS: Please note the changes in your copy (copies) of the S3C8275/F8275/C8278/ F8278/C8274/F8274 User's Manual, Revision 1. Or, simply attach the Revision Descriptions of the next page to S3C8275/F8275/C8278/F8278/C8274/F8274 User's Manual, Revision 1. REVISION HISTORY Revision 0 1 1.1 1.2 Date February, 2005 April, 2005 July, 2005 August, 2005 Remark Preliminary spec for internal release only. First edition. Reviewed by Finechips. Second edition. Reviewed by Finechips. Third edition. Reviewed by Finechips. www..com REVISION DESCRIPTIONS 1. ELECTRICAL DATA Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Programming time (1) Chip erasing time (2) Sector erasing time (3) Data access time Number of writing/erasing Symbol Ftp Ftp1 Ftp2 FtRS FNwe Conditions - - - - - Min 30 10 10 - - Typ - - - 25 - Max - - - - 10,000(4) Unit s ms ms ns Times NOTES: 1. The programming time is the time during which one byte (8-bit) is programmed. 2. The chip erasing time is the time during which all 16K byte block is erased. 3. The sector erasing time is the time during which all 128 byte block is erased. 4. Maximum number of writing/erasing is 10,000 times for full-flash(S3F8275) and 100 times for half-flash (S3F8278/F8274). 5. The chip erasing is available in Tool Program Mode o nly. 2. CONDITION OF OPERATING VOLTAGE Condition of operating voltage is modified "fx = 0 - 4.2MHz" to "fx = 0.4 - 4.2MHz" at 2.0V - 3.6V and "fx = 0-8MHz" to "fx = 0.4 - 8MHz" at 2.5V - 3.6V in the page 17-2. 3. CHAPTHER 16. EMBEDDED FLASH MEMORY INTERFACE This chapter is modified for only S3F8275. www..com Preface The S3C8275/F8275/C8278/F8278/C8274/F8274 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8275/F8275/C8278/F8278/C8274/F8274 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure Instruction Set Chapter 1, "Product Overview," is a high-level introduction to S3C8275/F8275/C8278/F8278/C8274/F8274 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C8275/F8275/C8278/F8278/C8274/F8274 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C8275/F8275/C8278/F8278/C8274/F8274 microcontroller. Also included in Part II are electrical, mechanical, Flash MCU, and development tools data. It has 14 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Clock Circuit RESET and Power-Down I/O Ports Basic Timer Timer 1 Watch Timer LCD Controller/Driver Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Serial I/O Interface Battery Level Detector Embedded Flash Memory Interface Electrical Data Mechanical Data S3F8275/F8278/F8274 Flash MCU Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C8275/F8275/C8278/F8278/C8274/F8274 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER iii www..com Table of Contents Part I -- Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ...............................................................................................................1-1 S3C8275/F8275/C8278/F8278/C8274/F8274 Microcontroller....................................................................1-1 Flash..................................................................................................................................................1-1 Features .............................................................................................................................................1-2 Block Diagram ....................................................................................................................................1-3 Pin Assignment...................................................................................................................................1-4 Pin Descriptions ..................................................................................................................................1-6 Pin Circuits .........................................................................................................................................1-8 Chapter 2 Address Spaces Overview .............................................................................................................................................2-1 Program Memory (ROM) ......................................................................................................................2-2 Smart Option ..............................................................................................................................2-3 Register Architecture ...........................................................................................................................2-5 Register Page Pointer (PP) ..........................................................................................................2-8 Register Set 1.............................................................................................................................2-10 Register Set 2.............................................................................................................................2-10 Prime Register Space..................................................................................................................2-11 Working Registers .......................................................................................................................2-12 Using the Register Points.............................................................................................................2-13 Register Addressing ............................................................................................................................2-15 Common Working Register Area (C0H-CFH) .................................................................................2-17 4-Bit Working Register Addressing................................................................................................2-18 8-Bit Working Register Addressing................................................................................................2-20 System and User Stack.......................................................................................................................2-22 Chapter 3 Addressing Modes Overview .............................................................................................................................................3-1 Register Addressing Mode (R) ..............................................................................................................3-2 Indirect Register Addressing Mode (IR)..................................................................................................3-3 Indexed Addressing Mode (X) ...............................................................................................................3-7 Direct Address Mode (DA)....................................................................................................................3-10 Indirect Address Mode (IA)...................................................................................................................3-12 Relative Address Mode (RA).................................................................................................................3-13 Immediate Mode (IM) ...........................................................................................................................3-14 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER v www..com Table of Contents Chapter 4 Control Registers (Continued) Overview .............................................................................................................................................4-1 Chapter 5 Interrupt Structure Overview .............................................................................................................................................5-1 Interrupt Types ............................................................................................................................5-2 S3C8275/C8278/C8274 Interrupt Structure.....................................................................................5-3 Interrupt Vector Addresses ...........................................................................................................5-4 Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-6 System-Level Interrupt Control Registers .......................................................................................5-6 Interrupt Processing Control Points ...............................................................................................5-7 Peripheral Interrupt Control Registers ............................................................................................5-8 System Mode Register (SYM) ......................................................................................................5-9 Interrupt Mask Register (IMR) .......................................................................................................5-10 Interrupt Priority Register (IPR) .....................................................................................................5-11 Interrupt Request Register (IRQ) ...................................................................................................5-13 Interrupt Pending Function Types ..................................................................................................5-14 Interrupt Source Polling Sequence ................................................................................................5-15 Interrupt Service Routines.............................................................................................................5-15 Generating Interrupt Vector Addresses ..........................................................................................5-16 Nesting of Vectored Interrupts.......................................................................................................5-16 Instruction Pointer (IP) .................................................................................................................5-16 Fast Interrupt Processing .............................................................................................................5-16 Chapter 6 Instruction Set Overview .............................................................................................................................................6-1 Data Types .................................................................................................................................6-1 Register Addressing ....................................................................................................................6-1 Addressing Modes.......................................................................................................................6-1 Flags Register (FLAGS)...............................................................................................................6-6 Flag Descriptions ........................................................................................................................6-7 Instruction Set Notation................................................................................................................6-8 Condition Codes ..........................................................................................................................6-12 Instruction Descriptions................................................................................................................6-13 vi S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER www..com Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview .............................................................................................................................................7-1 System Clock Circuit...................................................................................................................7-1 Main Oscillator Circuits................................................................................................................7-2 Sub Oscillator Circuits .................................................................................................................7-2 Clock Status During Power-Down Modes .......................................................................................7-3 System Clock Control Register (CLKCON).....................................................................................7-4 Clock Output Control Register (CLOCON)......................................................................................7-5 Oscillator Control Register (OSCCON)...........................................................................................7-6 Switching the CPU Clock .............................................................................................................7-7 Chapter 8 RESET and Power-Down System Reset .....................................................................................................................................8-1 Overview .....................................................................................................................................8-1 Normal Mode Reset Operation......................................................................................................8-1 Hardware Reset Values................................................................................................................8-2 Power-Down Modes .............................................................................................................................8-5 Stop Mode..................................................................................................................................8-5 Idle Mode....................................................................................................................................8-6 Chapter 9 I/O Ports Overview .............................................................................................................................................9-1 Port Data Registers .....................................................................................................................9-2 port 0 .........................................................................................................................................9-3 port 1 .........................................................................................................................................9-7 port 2 .........................................................................................................................................9-11 port 3 .........................................................................................................................................9-13 Port 4.........................................................................................................................................9-15 Port 5.........................................................................................................................................9-17 Port 6.........................................................................................................................................9-19 Chapter 10 Basic Timer Overview .............................................................................................................................................10-1 Basic Timer Control Register (BTCON) ..........................................................................................10-2 Basic Timer Function Description..................................................................................................10-3 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER vii www..com Table of Contents Chapter 11 Timer 1 (Continued) One 16-bit Timer Mode (Timer 1)...........................................................................................................11-1 Overview .....................................................................................................................................11-1 Function Description....................................................................................................................11-1 Two 8-bit Timers Mode (Timer A and B) .................................................................................................11-4 Overview .....................................................................................................................................11-4 Function Description....................................................................................................................11-4 Chapter 12 Watch Timer Overview .............................................................................................................................................12-1 Watch Timer Control Register (WTCON)........................................................................................12-2 Watch Timer Circuit Diagram........................................................................................................12-3 Chapter 13 LCD Controller/Driver Overview .............................................................................................................................................13-1 LCD Circuit Diagram ....................................................................................................................13-2 LCD RAM Address Area ..............................................................................................................13-3 LCD Control Register (LCON) .......................................................................................................13-4 LCD Voltage Dividing Resistor ......................................................................................................13-5 Common (COM) Signals ..............................................................................................................13-6 Segment (SEG) Signals...............................................................................................................13-6 Chapter 14 Serial I/O Interface Overview .............................................................................................................................................14-1 Programming Procedure...............................................................................................................14-1 SIO Control Registers (SIOCON)...................................................................................................14-2 SIO Pre-Scaler Register (SIOPS)..................................................................................................14-3 SIO Block Diagram..............................................................................................................................14-3 Serial I/O Timing Diagram (SIO) ....................................................................................................14-4 Chapter 15 Battery Level Detector Overview .............................................................................................................................................15-1 Battery Level Detector Control Register (BLDCON) .........................................................................15-2 viii S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER www..com Table of Contents Chapter 16 (Continued) Embedded Flash Memory Interface Overview .............................................................................................................................................16-1 User Program Mode.............................................................................................................................16-2 Flash Memory Control Registers (User Program Mode)...................................................................16-2 TM (On-Board Programming) Sector .................................................................................................16-5 ISP Sector Erase.......................................................................................................................................16-7 Programming ......................................................................................................................................16-9 Reading..............................................................................................................................................16-10 Hard Lock Protection ...........................................................................................................................16-11 Chapter 17 Electrical Data Overview .............................................................................................................................................17-1 Chapter 18 Mechanical Data Overview .............................................................................................................................................18-1 Chapter 19 S3F8275/F8278/F8274 Flash MCU Overview .............................................................................................................................................19-1 Operating Mode Characteristics....................................................................................................19-5 Chapter 20 Development Tools Overview .............................................................................................................................................20-1 SHINE ........................................................................................................................................20-1 SAMA Assembler........................................................................................................................20-1 SASM88.....................................................................................................................................20-1 HEX2ROM ..................................................................................................................................20-1 Target Boards .............................................................................................................................20-1 TB8275/8/4 Target Board..............................................................................................................20-3 SMDS2+ Selection (SAM8)..........................................................................................................20-6 Idle LED .....................................................................................................................................20-6 Stop LED....................................................................................................................................20-6 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER ix www..com List of Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 4-1 Title Page Number Block Diagram ....................................................................................................1-3 S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Assignments (64-QFP-1420F)........1-4 S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Assignments (64-LQFP-1010) ........1-5 Pin Circuit Type A ...............................................................................................1-8 Pin Circuit Type B (nRESET) ................................................................................1-8 Pin Circuit Type E-4 (P0, P1)................................................................................1-8 Pin Circuit Type H-4.............................................................................................1-9 Pin Circuit Type H-8 (P2.1-P2.7, P3) ....................................................................1-9 Pin Circuit Type H-9 (P4, P5, P6)..........................................................................1-10 Pin Circuit Type H-10 (P2.0) .................................................................................1-11 Program Memory Address Space .........................................................................2-2 Smart Option ......................................................................................................2-3 Internal Register File Organization (S3C8275) ........................................................2-6 Internal Register File Organization (S3C8278/C8274) ..............................................2-7 Register Page Pointer (PP) ..................................................................................2-8 Set 1, Set 2, Prime Area Register, and LCD Data Register Map ..............................2-11 8-Byte Working Register Areas (Slices).................................................................2-12 Contiguous 16-Byte Working Register Block..........................................................2-13 Non-Contiguous 16-Byte Working Register Block ...................................................2-14 16-Bit Register Pair .............................................................................................2-15 Register File Addressing ......................................................................................2-16 Common Working Register Area...........................................................................2-17 4-Bit Working Register Addressing........................................................................2-19 4-Bit Working Register Addressing Example..........................................................2-19 8-Bit Working Register Addressing........................................................................2-20 8-Bit Working Register Addressing Example..........................................................2-21 Stack Operations ................................................................................................2-22 Register Addressing ............................................................................................3-2 Working Register Addressing ...............................................................................3-2 Indirect Register Addressing to Register File..........................................................3-3 Indirect Register Addressing to Program Memory ...................................................3-4 Indirect Working Register Addressing to Register File.............................................3-5 Indirect Working Register Addressing to Program or Data Memory...........................3-6 Indexed Addressing to Register File ......................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset ...........................3-8 Indexed Addressing to Program or Data Memory ....................................................3-9 Direct Addressing for Load Instructions..................................................................3-10 Direct Addressing for Call and Jump Instructions ....................................................3-11 Indirect Addressing..............................................................................................3-12 Relative Addressing .............................................................................................3-13 Immediate Addressing .........................................................................................3-14 Register Description Format .................................................................................4-4 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xi www..com List of Figures Figure Number 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 Title Page Number S3C8-Series Interrupt Types .................................................................................5-2 S3C8275/C8278/C8274 Interrupt Structure.............................................................5-3 ROM Vector Address Area...................................................................................5-4 Interrupt Function Diagram ...................................................................................5-7 System Mode Register (SYM) ..............................................................................5-9 Interrupt Mask Register (IMR) ...............................................................................5-10 Interrupt Request Priority Groups ..........................................................................5-11 Interrupt Priority Register (IPR) .............................................................................5-12 Interrupt Request Register (IRQ) ...........................................................................5-13 System Flags Register (FLAGS)...........................................................................6-6 Crystal/Ceramic Oscillator (fx)..............................................................................7-2 External Oscillator (fx) .........................................................................................7-2 RC Oscillator (fx).................................................................................................7-2 Crystal Oscillator (fxt, Normal)..............................................................................7-2 Crystal Oscillator (fxt, for Low Current) ..................................................................7-2 External Oscillator (fxt) ........................................................................................7-2 System Clock Circuit Diagram..............................................................................7-3 System Clock Control Register (CLKCON).............................................................7-4 Clock Output Control Register (CLOCON)..............................................................7-5 Clock Output Block Diagram ................................................................................7-5 Oscillator Control Register (OSCCON)...................................................................7-6 STOP Control Register (STPCON) ........................................................................7-8 S3C8275/C8278/C8274 I/O Port Data Register Format............................................9-2 Port 0 High-Byte Control Register (P0CONH) .........................................................9-4 Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-4 Port 0 Pull-up Control Register (P0PUR)................................................................9-5 External Interrupt Control Register, Low Byte (EXTICONL).......................................9-5 External Interrupt Pending Register (EXTIPND).......................................................9-6 Port 1 High-Byte Control Register (P1CONH) .........................................................9-8 Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-8 Port 1 Pull-up Control Register (P1PUR)................................................................9-9 External Interrupt Control Register, High Byte (EXTICONH)......................................9-9 External Interrupt Control Register, Low Byte (EXTICONL).......................................9-10 External Interrupt Pending Register (EXTIPND).......................................................9-10 Port 2 High-byte Control Register (P2CONH)..........................................................9-11 Port 2 Low-byte Control Register (P2CONL)...........................................................9-12 Port 2 Pull-up Control Register (P2PUR)................................................................9-12 Port 3 High Byte Control Register (P3CONH) .........................................................9-13 Port 3 Low Byte Control Register (P3CONL) ..........................................................9-14 Port 3 Pull-up Control Register (P3PUR)................................................................9-14 xii S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER www..com List of Figures (Continued) Page Number 9-19 9-20 9-21 9-22 9-23 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 14-1 14-2 14-3 14-4 14-5 15-1 15-2 16-1 16-2 16-3 16-4 16-5 16-6 Title Page Number Port 4 High-Byte Control Register (P4CONH) .........................................................9-15 Port 4 Low-Byte Control Register (P4CONL) ..........................................................9-16 Port 5 High-Byte Control Register (P5CONH) .........................................................9-17 Port 5 Low-Byte Control Register (P5CONL) ..........................................................9-18 Port 6 Control Register (P6CON)...........................................................................9-19 Basic Timer Control Register (BTCON) ..................................................................10-2 Basic Timer Block Diagram ..................................................................................10-4 Timer 1/A Control Register (TACON) .....................................................................11-2 Timer 1 Block Diagram (One 16-bit Mode)..............................................................11-3 Timer 1/A Control Register (TACON) .....................................................................11-5 Timer B Control Register (TBCON) ........................................................................11-6 Timer A Block Diagram(Two 8-bit Timers Mode) .....................................................11-7 Timer B Block Diagram (Two 8-bit Timers Mode) ....................................................11-8 Watch Timer Control Register (WTCON)................................................................12-2 Watch Timer Circuit Diagram................................................................................12-3 LCD Function Diagram.........................................................................................13-1 LCD Circuit Diagram ............................................................................................13-2 LCD Display Data RAM Organization ....................................................................13-3 LCD Control Register (LCON) ...............................................................................13-4 Internal Voltage Dividing Resistor Connection.........................................................13-5 Select/No-Select Signals in Static Display Mode....................................................13-6 Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode....................................13-7 Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode....................................13-7 LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode.............13-8 Serial I/O Module Control Register (SIOCON).........................................................14-2 SIO Prescaler Register (SIOPS) ...........................................................................14-3 SIO Functional Block Diagram..............................................................................14-3 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0).................14-4 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................14-4 Block Diagram for Voltage Level Detect .................................................................15-1 Battery Level Detect Circuit and Control Register....................................................15-2 Flash Memory Control Register (FMCON)..............................................................16-2 Flash Memory User-Programming Enable Register (FMUSR) ..................................16-3 Flash Memory Sector Address Register, High Byte (FMSECH) ...............................16-4 Flash Memory Sector Address Register, Low Byte (FMSECL).................................16-4 Program Memory Address Space .........................................................................16-5 Sector Configurations in User Program Mode .........................................................16-7 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xiii www..com List of Figures (Concluded) Page Number 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 19-1 19-2 19-3 20-1 20-2 20-3 20-4 Title Page Number Stop Mode Release Timing When Initiated by an External Interrupt ..........................17-5 Stop Mode Release Timing When Initiated by a RESET..........................................17-6 Input Timing for External Interrupts ........................................................................17-7 Input Timing for RESET........................................................................................17-8 Serial Data Transfer Timing...................................................................................17-8 LVR (Low Voltage Reset) Timing...........................................................................17-9 Clock Timing Measurement at XIN .........................................................................17-11 Clock Timing Measurement at XTIN........................................................................17-12 Operating Voltage Range .....................................................................................17-13 64-Pin QFP Package Dimensions (64-QFP-1420F).................................................18-1 64-Pin LQFP Package Dimensions (64-LQFP-1010) ...............................................18-2 S3F8275/F8278/F8274 Pin Assignments (64-QFP-1420F).......................................19-2 S3F8275/F8278/F8274 Pin Assignments (64-LQFP-1010).......................................19-3 Operating Voltage Range .....................................................................................19-7 SMDS Product Configuration (SMDS2+)................................................................20-2 TB8275/8/4 Target Board Configuration..................................................................20-3 40-Pin Connectors (J101, J102) for TB8275/8/4 ......................................................20-7 S3E8270 Cables for 64-QFP Package...................................................................20-7 xiv S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER www..com List of Tables Table Number 1-1 2-1 2-2 4-1 4-2 4-3 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 8-3 9-1 9-2 13-1 15-1 16-1 16-2 Title Page Number S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Descriptions .................................1-6 S3C8275 Register Type Summary ........................................................................2-5 S3C8278/C8274 Register Type Summary ..............................................................2-5 Set 1 Registers ...................................................................................................4-1 Set 1, Bank 0 Registers .......................................................................................4-2 Set 1, Bank 1 Registers .......................................................................................4-3 Interrupt Vectors..................................................................................................5-5 Interrupt Control Register Overview ........................................................................5-6 Interrupt Source Control and Data Registers...........................................................5-8 Instruction Group Summary ..................................................................................6-2 Flag Notation Conventions ....................................................................................6-8 Instruction Set Symbols.......................................................................................6-8 Instruction Notation Conventions ...........................................................................6-9 Opcode Quick Reference .....................................................................................6-10 Condition Codes ..................................................................................................6-12 S3C8275/C8278/C8274 Set 1 Register and Values After RESET .............................8-2 S3C8275/C8278/C8274 Set 1, Bank 0 Register Values After RESET .......................8-3 S3C8275/C8278/C8274 Set 1, Bank 1 Register Values After RESET .......................8-4 S3C8275/C8278/C8274 Port Configuration Overview................................................9-1 Port Data Register Summary ................................................................................9-2 LCD Clock Signal Frame Frequency......................................................................13-3 BLDCON Value and Detection Level......................................................................15-2 ISP Sector Size ..................................................................................................16-6 Reset Vector Address..........................................................................................16-6 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xv www..com List of Tables Table Number 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 Title (Continued) Page Number Absolute Maximum Ratings..................................................................................17-2 D.C. Electrical Characteristics..............................................................................17-2 Data Retention Supply Voltage in Stop Mode.........................................................17-5 Input/Output Capacitance.....................................................................................17-6 A.C. Electrical Characteristics..............................................................................17-7 Battery Level Detector Electrical Characteristics ....................................................17-9 LVR (Low Voltage Reset) Electrical Characteristics................................................17-9 Main Oscillation Characteristics............................................................................17-10 Sub Oscillation Characteristics.............................................................................17-10 Main Oscillation Stabilization Time........................................................................17-11 Sub Oscillation Stabilization Time.........................................................................17-12 A.C. Electrical Characteristics for Internal Flash ROM ............................................17-13 Descriptions of Pins Used to Read/Write the Flash ROM ........................................19-4 Comparison of S3F8275/F8278/F8274 and S3C8275/C8278/C8274 Features ............19-4 Operating Mode Selection Criteria.........................................................................19-5 D.C. Electrical Characteristics..............................................................................19-6 Power Selection Settings for TB8275/8/4...............................................................20-4 Main-clock Selection Settings for TB8275/8/4 ........................................................20-4 Select Smart Option Source Setting for TB8275/8/4................................................20-5 Smart Option Switch Settings for TB8275/8/4.........................................................20-5 Device Selection Settings for TB8275/8/4...............................................................20-6 The SMDS2+ Tool Selection Setting .....................................................................20-6 xvi S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER www..com List of Programming Tips Description Chapter 2: Address Spaces Page Number Using the Page Pointer for RAM Clear (Page 0, Page 1) .....................................................................2-9 Setting the Register Pointers ............................................................................................................2-13 Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-14 Addressing the Common Working Register Area ................................................................................2-18 Standard Stack Operations Using PUSH and POP.............................................................................2-23 Chapter 7: Clock Circuit Switching the CPU Clock .................................................................................................................7-7 Chapter 16: Embedded Flash Memory Interface Sector Erase...................................................................................................................................16-8 Program .........................................................................................................................................16-9 Reading..........................................................................................................................................16-10 Hard Lock Protection .......................................................................................................................16-11 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xvii www..com List of Register Descriptions Register Identifier BLDCON BTCON CLKCON CLOCON EXTICONH EXTICONL EXITPND FLAGS FMCON FMSECH FMSECL FMUSR IMR IPH IPL IPR IRQ LCON OSCCON P0CONH P0CONL P0PUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P4CONH P4CONL P5CONH P5CONL P6CON PP RP0 RP1 SIOCON SPH SPL STPCON SYM TACON TBCON WTCON Full Register Name Page Number Battery Level Detector Control Register .................................................................4-5 Basic Timer Control Register ................................................................................4-6 System Clock Control Register.............................................................................4-7 Clock Output Control Register ..............................................................................4-8 External Interrupt Control Register (High Byte) .......................................................4-9 External Interrupt Control Register (Low Byte) ........................................................4-10 External Interrupt Pending Register .......................................................................4-11 System Flags Register ........................................................................................4-12 Flash Memory Control Register.............................................................................4-13 Flash Memory Sector Address Register (High Byte) ...............................................4-14 Flash Memory Sector Address Register (Low Byte)................................................4-14 Flash Memory User Programming Enable Register.................................................4-15 Interrupt Mask Register........................................................................................4-16 Instruction Pointer (High Byte) ..............................................................................4-17 Instruction Pointer (Low Byte)...............................................................................4-17 Interrupt Priority Register......................................................................................4-18 Interrupt Request Register....................................................................................4-19 LCD Control Register ...........................................................................................4-20 Oscillator Control Register....................................................................................4-21 Port 0 Control Register (High Byte) .......................................................................4-22 Port 0 Control Register (Low Byte) ........................................................................4-23 Port 0 Pull-Up Control Register .............................................................................4-24 Port 1 Control Register (High Byte) .......................................................................4-25 Port 1 Control Register (Low Byte) ........................................................................4-26 Port 1 Pull-up Control Register..............................................................................4-27 Port 2 Control Register (High Byte) .......................................................................4-28 Port 2 Control Register (Low Byte) ........................................................................4-29 Port 2 Pull-up Control Register..............................................................................4-30 Port 3 Control Register (High Byte) .......................................................................4-31 Port 3 Control Register (Low Byte) ........................................................................4-32 Port 3 Pull-up Control Register..............................................................................4-33 Port 4 Control Register (High Byte) .......................................................................4-34 Port 4 Control Register (Low Byte) ........................................................................4-35 Port 5 Control Register (High Byte) .......................................................................4-36 Port 5 Control Register (Low Byte) ........................................................................4-37 Port 6 Control Register.........................................................................................4-38 Register Page Pointer..........................................................................................4-39 Register Pointer 0................................................................................................4-40 Register Pointer 1................................................................................................4-40 SIO Control Register............................................................................................4-41 Stack Pointer (High Byte).....................................................................................4-42 Stack Pointer (Low Byte) .....................................................................................4-42 Stop Control Register...........................................................................................4-43 System Mode Register ........................................................................................4-44 Timer 1/A Control Register ...................................................................................4-45 Timer B Control Register ......................................................................................4-46 Watch Timer Control Register...............................................................................4-47 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xix www..com List of Instruction Descriptions Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB Full Register Name Page Number Add with Carry ....................................................................................................6-14 Add....................................................................................................................6-15 Logical AND........................................................................................................6-16 Bit AND..............................................................................................................6-17 Bit Compare........................................................................................................6-18 Bit Complement ..................................................................................................6-19 Bit Reset ............................................................................................................6-20 Bit Set................................................................................................................6-21 Bit OR................................................................................................................6-22 Bit Test, Jump Relative on False...........................................................................6-23 Bit Test, Jump Relative on True.............................................................................6-24 Bit XOR ..............................................................................................................6-25 Call Procedure ....................................................................................................6-26 Complement Carry Flag .......................................................................................6-27 Clear ..................................................................................................................6-28 Complement .......................................................................................................6-29 Compare.............................................................................................................6-30 Compare, Increment, and Jump on Equal...............................................................6-31 Compare, Increment, and Jump on Non-Equal........................................................6-32 Decimal Adjust....................................................................................................6-33 Decrement ..........................................................................................................6-35 Decrement Word .................................................................................................6-36 Disable Interrupts ................................................................................................6-37 Divide (Unsigned).................................................................................................6-38 Decrement and Jump if Non-Zero ..........................................................................6-39 Enable Interrupts .................................................................................................6-40 Enter..................................................................................................................6-41 Exit ....................................................................................................................6-42 Idle Operation......................................................................................................6-43 Increment ...........................................................................................................6-44 Increment Word...................................................................................................6-45 Interrupt Return ...................................................................................................6-46 Jump..................................................................................................................6-47 Jump Relative......................................................................................................6-48 Load...................................................................................................................6-49 Load Bit..............................................................................................................6-51 S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER xxi www..com List of Instruction Descriptions Instruction Mnemonic LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR Full Register Name (Continued) Page Number Load Memory ......................................................................................................6-52 Load Memory and Decrement ...............................................................................6-54 Load Memory and Increment ................................................................................6-55 Load Memory with Pre-Decrement ........................................................................6-56 Load Memory with Pre-Increment ..........................................................................6-57 Load Word..........................................................................................................6-58 Multiply (Unsigned)..............................................................................................6-59 Next...................................................................................................................6-60 No Operation.......................................................................................................6-61 Logical OR..........................................................................................................6-62 Pop from Stack ...................................................................................................6-63 Pop User Stack (Decrementing)............................................................................6-64 Pop User Stack (Incrementing) .............................................................................6-65 Push to Stack.....................................................................................................6-66 Push User Stack (Decrementing)..........................................................................6-67 Push User Stack (Incrementing) ...........................................................................6-68 Reset Carry Flag .................................................................................................6-69 Return ................................................................................................................6-70 Rotate Left ..........................................................................................................6-71 Rotate Left through Carry .....................................................................................6-72 Rotate Right........................................................................................................6-73 Rotate Right through Carry ...................................................................................6-74 Select Bank 0.....................................................................................................6-75 Select Bank 1.....................................................................................................6-76 Subtract with Carry ..............................................................................................6-77 Set Carry Flag.....................................................................................................6-78 Shift Right Arithmetic...........................................................................................6-79 Set Register Pointer ............................................................................................6-80 Stop Operation....................................................................................................6-81 Subtract .............................................................................................................6-82 Swap Nibbles ......................................................................................................6-83 Test Complement under Mask ..............................................................................6-84 Test under Mask .................................................................................................6-85 Wait for Interrupt..................................................................................................6-86 Logical Exclusive OR...........................................................................................6-87 xxii S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt or reset -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C8275/F8275/C8278/F8278/C8274/F8274 MICROCONTROLLER The S3C8275/F8275/C8278/F8278/C8274/F8274 single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based on Samsung's latest CPU architecture. The S3C8275/C8278/C8274 is a microcontroller with a 16/8/4K-byte mask-programmable ROM embedded. The S3F8275/F8278/F8274 is a microcontroller with a 16/8/4K-byte flash ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C8275/F8275/C8278/F8278/C8274/F8274 by integrating the following peripheral modules with the powerful SAM8 core: -- Seven programmable I/O ports, including six 8-bit ports and one 4-bit port, for a total of 52 pins. -- Eight bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). -- Two 8-bit timer/counter with selectable operating modes. -- Watch timer for real time FLASH The S3F8275/F8278/F8274 are FLASH version of the S3C8275/C8278/C8274 microcontroller. The S3F8275/F8278/F8274 microcontroller has an on-chip FLASH ROM instead of a masked ROM. The S3F8275/F8278/F8274 is comparable to the S3C8275/C8278/C8274, both in function and in pin configuration. The S3F8275 only is a full flash. The full flash means that data can be written into the program ROM by an instruction. 1-1 PRODUCT OVERVIEW S3C8275/F8275/C8278/F8278/C8274/F8274 www..com FEATURES CPU * SAM88RC CPU core Memory * Program Memory(ROM) - 16Kx8 bits program memory(S3C8275/F8275) - 8Kx8 bits program memory(S3C8278/F8278) - 4Kx8 bits program memory(S3C8274/F8274) - Internal flash memory(Program memory) v Sector size: 128 Bytes v 10 Years data retention v Fast programming time: + Chip erase: 10ms + Sector erase: 10ms + Byte program: 30us v User programmable by `LDC' instruction v Endurance: 10,000 erase/program cycles v Sector(128-bytes) erase available v Byte programmable v External serial programming support v Expandable OBPTM(On board program) sector * Data Memory (RAM) - Including LCD display data memory - 544 x 8 bits data memory(S3C8275/F8275) - 288 x 8 bits data memory(S3C8278/F8278) - 288 x 8 bits data memory(S3C8274/F8274) Instruction Set * * 78 instructions Idle and Stop instructions added for power-down modes 52 I/O Pins * I/O: 16 pins * I/O: 36 pins (Sharing with LCD signal outputs) Interrupts * 8 interrupt levels and 12 interrupt sources * Fast interrupt processing feature 8-Bit Basic Timer * Watchdog timer function * 4 kinds of clock source Two 8-Bit Timer/Counters * * * Programmable interval timer External event counter function Configurable as one 16-bit timer/counters Watch Timer * * * * * * * * * * * Interval time: 3.91mS, 0.25S, 0.5S, and 1S at 32.768 kHz 0.5/1/2/4 kHz Selectable buzzer output 32 segments and 4 common terminals Static, 1/2 duty, 1/3 duty, and 1/4 duty selectable Internal resistor circuit for LCD bias 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or External clock source 3-criteria voltage selectable (2.2V, 2.4V, 2.8V) En/Disable by software for current consumption source Criteria voltage: 2.2V En/Disable by smart option (ROM address: 3FH) Idle: only CPU clock stops Stop: selected system clock and CPU clock stop Crystal, ceramic, or RC for main clock Main clock frequency: 0.4 MHz - 8 MHz 32.768 kHz crystal for sub clock 500nS at 8 MHz fx(minimum) 2.0 V to 3.6 V at 0.4 - 4.2 MHz 2.5 V to 3.6 V at 0.4 - 8.0 MHz -25 C to +85 C 64-QFP-1420F, 64-LQFP-1010 Low Voltage Reset(LVR) level and enable/disable are at your hardwired option (ROM address 3FH) ISP related option selectable (ROM address 3EH) LCD Controller/Driver 8-bit Serial I/O Interface Battery Level Detector Low Voltage Reset (LVR) * * * * * * * * * * * * * * Two Power-Down Modes Oscillation Sources Instruction Execution Times Operating Voltage Range Operating Temperature Range Package Type Smart Option 1-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW BLOCK DIAGRAM TAOUT/P0.4 T1CLK/P0.3 TBOUT/P0.5 8-Bit Timer/ Counter A 8-Bit Timer/ Counter B 16-Bit Timer/ Counter 1 nRESET XIN XTIN XOUT XTOUT VREG Watchdog Timer Basic Timer Low Voltage Reset Clock Out Block Battery Level Detector Watch Timer CLKOUT/P0.6 VBLDREF/ P2.0/SEG31 BUZ/P0.7 COM0-COM3/P6.0-P6.3 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ P1.0/SCK P1.1/SO P1.2/SI P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 P2.0/SEG31/VBLDREF P2.1-P2.7/SEG30-SEG24 P3.0-P3.7/SEG23-SEG16 Port I/O and Interrupt Control I/O Port 0 SAM88RC CPU LCD Driver SEG0-SEG7/P5.7-P5.0 SEG8-SEG15/P4.7-P4.0 I/O Port 1 SEG16-SEG23/P3.7-P3.0 SEG24-SEG30/P2.7-P2.1 SEG31/P2.0/VBLDREF 544/288 Byte Register File I/O Port 2 16/8/4-Kbyte ROM SIO VLC0-VLC2 P1.0/SCK P1.1/SO P1.2/SI P6.0-P6.3/ COM0-COM3 P5.0-P5.7/ SEG7-SEG0 I/O Port 3 I/O Port 6 I/O Port 5 P4.0-P4.7/SEG15-SEG8 I/O Port 4 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PIN ASSIGNMENT SEG0/P5.7 COM0/P6.0 COM1/P6.1 COM2/P6.2 COM3/P6.3 VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT nRESET VREG P0.0/INT0 P0.1/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 S3C8275/F8275 S3C8278/F8278 S3C8274/F8274 (64-QFP-1420F) SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/VBLDREF P1.7/INT7 Figure 1-2. S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Assignments (64-QFP-1420F) 1-4 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ P1.0/SCK P1.1/SO P1.2/SI P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW SEG0/P5.7 COM0/P6.0 COM1/P6.1 COM2/P6.2 COM3/P6.3 VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT nRESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 S3C8275/F8275 S3C8278/F8278 S3C8274/F8274 (64-LQFP-1010) SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/VBLDREF P1.7/INT7 Figure 1-3. S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Assignments (64-LQFP-1010) VREG P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ P1.0/SCK P1.1/SO P1.2/SI P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1-5 PRODUCT OVERVIEW S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PIN DESCRIPTIONS Table 1-1. S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Descriptions Pin Names P0.0-P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3-P1.7 Pin Type I/O Pin Description I/O port with bit-programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups; P0.0-P0.2 are alternately used for external interrupt input(noise filters, interrupt enable and pending control). I/O port with bit-programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups; P1.3-P1.7 are alternately used for external interrupt input(noise filters, interrupt enable and pending control). I/O port with bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. I/O port with bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. I/O port with bit-programmable pins; Input or push-pull output and software assignable pull-ups. Circuit Type E-4 Pin No. 18-20 21 22 23 24 25 26 27 28 29-33 Shared Functions INT0-INT2 T1CLK TAOUT TBOUT CLKOUT BUZ SCK SO SI INT3-INT7 I/O E-4 P2.0 P2.1-P2.7 P3.0-P3.7 I/O H-10 H-8 H-8 34 35-41 42-49 SEG31/VBLDREF SEG30-SEG24 SEG23-SEG16 I/O P4.0-P4.7 P5.0-P5.7 P6.0-P6.3 I/O H-9 50-57 58-64, 1 2-5 SEG15-SEG8 SEG7-SEG0 COM0-COM3 1-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW Table 1-1. S3C8275/F8275/C8278/F8278/C8274/F8274 Pin Descriptions (Continued) Pin Names VLC0-VLC2 INT0-INT2 INT3-INT7 T1CLK TAOUT TBOUT CLKOUT BUZ SCK, SO, SI COM0-COM3 SEG0-SEG15 SEG16-SEG30 SEG31 VBLDREF VREG nRESET XTIN, XTOUT XIN, XOUT TEST VDD, VSS Pin Type - I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description LCD power supply pins. External interrupts input pins. Timer 1/A external clock input. Timer 1/A clock output. Timer B clock output. System clock output. Output pin for buzzer signal. Serial clock, data output, and data input. LCD common signal outputs. LCD segment signal outputs. Circuit Type - E-4 E-4 E-4 E-4 E-4 E-4 E-4 H-9 H-9 H-8 H-10 H-10 - B - - - - Pin No. 6-8 18-20 29-33 21 22 23 24 25 26,27,28 2-5 1,64- 50 49-35 34 34 17 16 14, 15 12, 11 13 9, 10 Shared Functions - P0.0-P0.2 P1.3-P1.7 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0, P1.1, P1.2 P6.0-P6.3 P5.7-P4.0 P3.7-P2.1 P2.0/VBLDREF P2.0/SEG31 - - - - - - I/O O I - - I - Battery level detector reference voltage Regulator voltage output for sub clock (needed 0.1uF) System reset pin Sub oscillator pins Main oscillator pins. Test input: it must be connected to VSS Power input pins 1-7 PRODUCT OVERVIEW S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PIN CIRCUITS VDD VDD Pull-Up Resistor In Schmitt Trigger P-Channel In N-Channel Figure 1-4. Pin Circuit Type A Figure 1-5. Pin Circuit Type B (nRESET) VDD Pull-up Resistor Resistor Enable P-CH I/O N-CH VDD Open Drain Data Output Disable Schmitt Trigger Figure 1-6. Pin Circuit Type E-4 (P0, P1) 1-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW VLC0 VLC1 COM/SEG Output Disable VLC2 Out VSS Figure 1-7. Pin Circuit Type H-4 VDD Pull-Up Resistor Resistor Enable P-CH Data Output Disable 1 N-CH I/O VDD Open Drain SEG Output Disable 2 Circuit Type H-4 Figure 1-8. Pin Circuit Type H-8 (P2.1-P2.7, P3) 1-9 PRODUCT OVERVIEW S3C8275/F8275/C8278/F8278/C8274/F8274 www..com VDD Pull-Up Resistor Resistor Enable P-CH Data Output Disable 1 N-CH I/O VDD COM/SEG Output Disable 2 Circuit Type H-4 Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6) 1-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PRODUCT OVERVIEW VDD Pull-Up Resistor Resistor Enable P-CH Data Output Disable 1 N-CH I/O VDD Open-Drain SEG Alternative Function Circuit Type H-4 BLDEN BLD Select To BLD Figure 1-10. Pin Circuit Type H-10 (P2.0) 1-11 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES 2 OVERVIEW ADDRESS SPACES The S3C8275/C8278/C8274 microcontroller has two types of address space: -- Internal program memory (ROM) -- Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C8275 has an internal 16-Kbyte mask-programmable ROM. The S3C8278 has an internal 8-Kbyte maskprogrammable ROM. The S3C8274 has an internal 4-Kbyte mask-programmable ROM. The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. A 16-byte LCD display register file is implemented. There are 605 mapped registers in the internal register file. Of these, 528 are for general-purpose. (This number includes a 16-byte working register common area used as a "scratch area" for data operations, two 192-byte prime register areas, and two 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the CPU and the system control, and 48 registers are mapped for peripheral controls and data registers. Nineteen register locations are not mapped. 2-1 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C8275 has 16K bytes internal maskprogrammable program memory, the S3C8278 has 8K bytes, the S3C8274 has 4K bytes. The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H in the S3C8275/C8278/C8274. The reset address of ROM can be changed by a smart option only in the S3F8275 (Full-Flash Device). Refer to the chapter 16. Embedded Flash Memory Interface for more detail contents. (Decimal) 16,383 (HEX) 3FFFH (Decimal) 8,191 16K-bytes Internal Program Memory Area 8K-bytes Internal Program Memory Area 8FFH 255 Available ISP Sector Area Interrupt Vector Area 3FH Smart Option Area 3CH 0 S3C8275/F8275 00H 0 S3C8278/F8278 Interrupt Vector Area FFH 255 (HEX) 1FFFH (Decimal) 4,095 4K-bytes Internal Program Memory Area FFH 255 Interrupt Vector Area (HEX) 0FFFH FFH 00H 0 S3C8274/F8274 00H Figure 2-1. Program Memory Address Space 2-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES SMART OPTION ROM Address: 003EH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB ISP reset vector change enable/disable bit: 0 = OBP reset vector address 1 = Normal vector (address 0100H) ISP reset vector address selection bit: 00 = 200H (ISP area size: 256 byte) 01 = 300H (ISP area size: 512 byte) 10 = 500H (ISP area size: 1024 byte) 11 = 900H (ISP area size: 2048 byte) Not used ISP protection size selection: (note) 00 = 256 bytes 01 = 512 bytes 10 = 1024 bytes 11 = 2048 bytes ISP protection enable/disable bit: 0 = Enable (not erasable by LDC) 1 = Disable (erasable by LDC) ROM Address: 003FH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used These bits should be always logic "110b". LVR enable/disable bit (criteria voltage: 2.2V): 0 = Disable LVR 1 = Enable LVR ROM Address: 003CH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used ROM Address: 003DH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used NOTES: 1. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP area size. 2. When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of the area may be changed but the Smart Option is not affected. The data for Smart Option should be written in the Smart Option area (003CH-003FH) by OTP/MTP tools (SPW2 plus single programmer, or GW-PRO2 gang programmer). Figure 2-2. Smart Option 2-3 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from 003CH to 003FH. The ISP of smart option (003EH) is available in the S3F8275 only. The default value of ROM address 003EH is FFH. And ROM address 003EH should be kept FFH when used the S3C8275/F8275/C8278/F8278/C8274/F8274. The LVR of smart option (003FH) is available in all the device, S3C8275/F8275/C8278/F8278/C8274/F8274. The default value of ROM address 003FH is FFH. 2-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES REGISTER ARCHITECTURE In the S3C8275/C8278/C8274 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3C8275 the total number of addressable 8-bit registers is 605. Of these 605 registers, 13 bytes are for CPU and system control registers, 16 bytes are for LCD data registers, 48 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 512 registers are for general-purpose use, page 0page 1 (in case of S3C8278/C8274, page 0). You can always address set 1 register locations, regardless of which of the two register pages is currently selected. Set 1 locations, however, can only be addressed using register addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. Table 2-1. S3C8275 Register Type Summary Register Type General-purpose registers (including the 16-byte common working register area, two 192-byte prime register area, and two 64-byte set 2 area) LCD data registers CPU and system control registers Mapped clock, peripheral, I/O control, and data registers Total Addressable Bytes Number of Bytes 528 16 13 48 605 Table 2-2. S3C8278/C8274 Register Type Summary Register Type General-purpose registers (including the 16-byte common working register area, one 192-byte prime register area, and one 64-byte set 2 area) LCD data registers CPU and system control registers Mapped clock, peripheral, I/O control, and data registers Total Addressable Bytes Number of Bytes 272 16 13 48 349 2-5 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Set1 FFH 32 Bytes Bank 1 Bank 0 and System Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode) System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) C0H C0H BFH Page 0 FFH FFH Page 1 Page 0 Set 2 E0H General-Purpose Data Registers (Indirect Register, Indexed Mode, and Stack Operations) 256 Bytes 64 Bytes E0H DFH D0H CFH Page 2 0FH 16 Bytes 00H Prime Data Registers 192 Bytes ~ ~ Prime Data Registers (All Addressing Modes) ~ ~ ~ ~ (All addressing modes) LCD Display Reigster ~ 00H Figure 2-3. Internal Register File Organization (S3C8275) 2-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES Set1 FFH 32 Bytes Bank 1 Bank 0 System and Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode) System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) C0H C0H BFH Page 0 FFH Page 0 Set 2 E0H General-Purpose Data Registers (Indirect Register, Indexed Mode, and Stack Operations) 256 Bytes 64 Bytes E0H DFH D0H CFH Page 2 0FH 16 Bytes 00H Prime Data Registers 192 Bytes ~ ~ Prime Data Registers (All Addressing Modes) ~ ~ (All addressing modes) LCD Display Reigster ~ 00H NOTE: In case of S3C8278/C8274, there are page 0 and page 2. Page 2 is for LCD display register, 16 bytes. Figure 2-4. Internal Register File Organization (S3C8278/C8274) 2-7 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C8275/C8278/C8274 microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. Register Page Pointer (PP) DFH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Source register page selection bits: 0000 0001 0010 others Destination register page selection bits: 0000 0001 0010 others Destination: Page 0 Destination: Page 1 (Not used for the S3C8278/C8274) Destination: Page 2 Not used for the S3C8275/C8278/C8274 Source: Page 0 Source: Page 1 (Not used for the S3C8278/C8274) Source: Page 2 Not used for the S3C8275/C8278/C8274 NOTES: 1. In the S3C8275 microcontroller, the internal register file is configured as three pages (Pages 0-2). The pages 0-1 are used for general purpose register file, and page 2 is used for LCD data register or general purpose register. 2. In the S3C8278/C8274 microcontroller, the internal register file is configured as two pages (Pages 0, 2). The page 0 is used for general purpose register file, and page 2 is used for LCD data register or general purpose register. 3. A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should be modified to address other pages. Figure 2-5. Register Page Pointer (PP) 2-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES F PROGRAMMING TIP -- Using the Page Pointer for RAM Clear (Page 0, Page 1) LD SRP LD CLR DJNZ CLR LD LD CLR DJNZ CLR PP,#00H #0C0H R0,#0FFH @R0 R0,RAMCL0 @R0 PP,#10H R0,#0FFH @R0 R0,RAMCL1 @R0 ; Page 0 RAM clear starts ; Destination 0, Source 0 RAMCL0 ; R0 = 00H ; Destination 1, Source 0 ; Page 1 RAM clear starts RAMCL1 ; R0 = 00H NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program. 2-9 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH. The upper 32-byte area of this 64-byte space (E0H-FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H-FFH) contains 48 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H-DFH) and a 16-byte common working register area (C0H-CFH). You can use the common working register area as a "scratch" area for data operations being performed in other areas of the register file. Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") REGISTER SET 2 The same 64-byte physical space that is used for set 1 locations C0H-FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C8275, the set 2 address range (C0H-FFH) is accessible on pages 0-1. S3C8278/C8274, the set 2 address range (C0H-FFH) is accessible on page 0. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area is commonly used for stack operations. 2-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes (00H-BFH) of the S3C8275/C8278/C8274's two or one 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, 1, or 2 you must set the register page pointer (PP) to the appropriate source and destination values. Set 1 Bank 0 FFH FCH E0H D0H C0H Bank 1 FFH FFH Page 1 Page 0 Set 2 Set 2 C0H BFH Page 0 CPU and system control General-purpose Peripheral and I/O LCD data register 00H Prime Space 0FH Page 2 LCD Data Register Area 00H NOTE: In case of S3C8278/C8274, there are page 0 and page 2. Page 2 is for LCD display register, 16 bytes. Figure 2-6. Set 1, Set 2, Prime Area Register, and LCD Data Register Map 2-11 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: -- One working register slice is 8 bytes (eight 8-bit working registers, R0-R7 or R8-R15) -- One working register block is 16 bytes (sixteen 8-bit working registers, R0-R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH). Slice 32 11111XXX RP1 (Registers R8-R15) Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. Slice 31 FFH F8H F7H F0H Set 1 Only CFH C0H ~ 00000XXX RP0 (Registers R0-R7) Slice 2 Slice 1 ~ 10H FH 8H 7H 0H Figure 2-7. 8-Byte Working Register Areas (Slices) 2-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H-C7H, and RP1 points to addresses C8H-CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-8 and 2-9). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H-FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-8). In some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. In Figure 2-9, RP0 points to the "upper" slice and RP1 to the "lower" slice. Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. F PROGRAMMING TIP -- Setting the Register Pointers SRP SRP1 SRP0 CLR LD #70H #48H #0A0H RP0 RP1,#0F8H ; ; ; ; ; RP0 RP0 RP0 RP0 RP0 70H, RP1 78H no change, RP1 48H, A0H, RP1 no change 00H, RP1 no change no change, RP1 0F8H Register File Contains 32 8-Byte Slices 00001XXX RP1 00000XXX RP0 8-Byte Slice 8-Byte Slice 8H 7H 0H (R0) FH (R15) 16-Byte Contiguous Working Register block Figure 2-8. Contiguous 16-Byte Working Register Block 2-13 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com F7H (R7) 8-Byte Slice F0H (R0) 11110 RP0 00000 RP1 XXX Register File Contains 32 8-Byte Slices 16-Byte Contiguous working Register block 7H (R15) 0H (R0) XXX 8-Byte Slice Figure 2-9. Non-Contiguous 16-Byte Working Register Block F PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15H respectively: SRP0 ADD ADC ADC ADC ADC #80H R0,R1 R0,R2 R0,R3 R0,R4 R0,R5 ; RP0 80H ; R0 R0 + R1 ; R0 R0 + R2 + C ; R0 R0 + R3 + C ; R0 R0 + R4 + C ; R0 R0 + R5 + C The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD ADC ADC ADC ADC 80H,81H 80H,82H 80H,83H 80H,84H 80H,85H ; 80H (80H) + (81H) ; 80H (80H) + (82H) + C ; 80H (80H) + (83H) + C ; 80H (80H) + (84H) + C ; 80H (80H) + (85H) + C Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles. 2-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space. MSB Rn LSB Rn+1 n = Even address Figure 2-10. 16-Bit Register Pair 2-15 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Special-Purpose Registers Bank 1 FFH Control Registers E0H D0H C0H BFH RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). NOTE: In the S3C8275/C8278/C8274 microcontroller, pages 0-2 are implemented. Pages 0-2 contain all of the addressable registers in the internal register file. System Registers CFH Bank 0 General-Purpose Register FFH Set 2 C0H Prime Registers LCD Data Registers 00H Page 0 Register Addressing Only All Addressing Modes Page 0 Indirect Register, All Indexed Addressing Addressing Modes Modes Can be Pointed to By register Pointer Can be Pointed by Register Pointer Figure 2-11. Register File Addressing 2-16 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H-CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H- CFH, as the active 16-byte working register block: RP0 C0H-C7H RP1 C8H-CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. FFH Set 1 FFH FCH E0H D0H C0H C0H BFH FFH Page 1 Page 0 Set 2 Set 2 Page 0 Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH. ~ Prime Space ~ ~ 0FH LCD Data Registers Page 2 RP0 = RP1 = 1100 1100 0000 1000 00H 00H NOTE: In case of S3C8278/C8274, there are page 0 and page 2. Page 2 is for LCD display register, 16 bytes. Figure 2-12. Common Working Register Area 2-17 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com F PROGRAMMING TIP -- Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: SRP LD 2. ADD #0C0H R2,40H 0C3H,#45H ; R2 (C2H) the value in location 40H ; Invalid addressing mode! Use working register addressing instead: SRP ADD #0C0H R3,#45H ; R3 (C3H) R3 + 45H 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: -- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). -- The five high-order bits in the register pointer select an 8-byte slice of the register space. -- The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-13, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-14 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B). 2-18 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES RP0 RP1 Selects RP0 or RP1 Address OPCODE Register pointer provides five high-order bits 4-bit address provides three low-order bits Together they create an 8-bit register address Figure 2-13. 4-Bit Working Register Addressing RP0 01110 000 Selects RP0 RP1 01111 000 01110 110 Register address (76H) R6 0110 OPCODE 1110 Instruction 'INC R6' Figure 2-14. 4-Bit Working Register Addressing Example 2-19 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing. As shown in Figure 2-15, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. Figure 2-16 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B). RP0 RP1 Selects RP0 or RP1 Address These address bits indicate 8-bit working register addressing 8-bit logical address 1 1 0 0 Register pointer provides five high-order bits Three low-order bits 8-bit physical address Figure 2-15. 8-Bit Working Register Addressing 2-20 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES RP0 01100 000 Selects RP1 RP1 10101 000 R11 1100 1 011 8-bit address form instruction 'LD R11, R2' 10101 011 Register address (0ABH) Specifies working register addressing Figure 2-16. 8-Bit Working Register Addressing Example 2-21 ADDRESS SPACES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C8275/C8278/C8274 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-17. High Address PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt Low Address Stack contents after a call instruction Figure 2-17. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. Stack Pointers (SPL, SPH) Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C8275/C8278/C8274, the SPL must be initialized to an 8-bit value in the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H". 2-22 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESS SPACES F Programming TIP -- Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) * * * PUSH PUSH PUSH PUSH * * * PP RP0 RP1 R3 ; Stack address 0FEH PP ; Stack address 0FDH RP0 ; Stack address 0FCH RP1 ; Stack address 0FBH R3 POP POP POP POP R3 RP1 RP0 PP ; R3 Stack address 0FBH ; RP1 Stack address 0FCH ; RP0 Stack address 0FDH ; PP Stack address 0FEH 2-23 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES 3 OVERVIEW -- Register (R) ADDRESSING MODES Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Indirect Address (IA) -- Relative Address (RA) -- Immediate (IM) 3-1 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2). Program Memory 8-bit Register File Address One-Operand Instruction (Example) Register File dst OPCODE Point to One Register in Register File Value used in Instruction Execution OPERAND Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address Figure 3-1. Register Addressing Register File MSB Point to RP0 ot RP1 RP0 or RP1 Selected RP points to start of working register block OPERAND Program Memory 4-bit Working Register 3 LSBs Point to the Working Register (1 of 8) dst src OPCODE Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ; Where R1 and R2 are registers in the currently selected working register area. Figure 3-2. Working Register Addressing 3-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H-FFH in set 1 using the Indirect Register addressing mode. Program Memory 8-bit Register File Address One-Operand Instruction (Example) Register File dst OPCODE ADDRESS Point to One Register in Register File Address of Operand used by Instruction Value used in Instruction Execution OPERAND Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address Figure 3-3. Indirect Register Addressing to Register File 3-3 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Register Pair 16-Bit Address Points to Program Memory dst OPCODE Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4. Indirect Register Addressing to Program Memory 3-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start fo working register block Program Memory 4-bit Working Register Address 3 LSBs Point to the Working Register (1 of 8) ~ ~ dst src OPCODE ADDRESS ~ Sample Instruction: OR R3, @R6 Value used in Instruction OPERAND ~ Figure 3-5. Indirect Working Register Addressing to Register File 3-5 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block Program Memory 4-bit Working Register Address dst src OPCODE Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Register Pair Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory 16-Bit address points to program memory or data memory Value used in Instruction OPERAND Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H-FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented. Register File RP0 or RP1 ~ Value used in Instruction OPERAND ~ Selected RP points to start of working register block + Program Memory Two-Operand Instruction Example Base Address dst/src x OPCODE 3 LSBs Point to One of the Woking Register (1 of 8) ~ INDEX ~ Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Figure 3-7. Indexed Addressing to Register File 3-7 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block ~ Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE NEXT 2 Bits Point to Working Register Pair (1 of 4) Register Pair ~ LSB Selects Program Memory or Data Memory 16-Bit address added to offset + 8-Bits 16-Bits Value used in Instruction OPERAND 16-Bits Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] ; The values in the program address (RR2 + 04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block Program Memory OFFSET 4-bit Working Register Address OFFSET dst/src src OPCODE NEXT 2 Bits Point to Working Register Pair ~ ~ Register Pair 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits Sample Instructions: LDC LDE R4, #1000H[RR2] R4,#1000H[RR2] OPERAND Value used in Instruction ; The values in the program address (RR2 + 1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-9. Indexed Addressing to Program or Data Memory 3-9 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Program or Data Memory Program Memory Memory Address Used Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Sample Instructions: LDC LDE R5,1234H R5,1234H ; The values in the program address (1234H) are loaded into register R5. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-10. Direct Addressing for Load Instructions 3-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; Where JOB1 is a 16-bit immediate address ; Where DISPLAY is a 16-bit immediate address Figure 3-11. Direct Addressing for Call and Jump Instructions 3-11 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. Program Memory Next Instruction LSB Must be Zero Current Instruction dst OPCODE Lower Address Byte Upper Address Byte Program Memory Locations 0-255 Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing 3-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR. Program Memory Next OPCODE Program Memory Address Used Current Instruction Displacement OPCODE Current PC Value + Signed Displacement Value Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128 Figure 3-13. Relative Addressing 3-13 ADDRESSING MODES S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14. Immediate Addressing 3-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER 4 OVERVIEW CONTROL REGISTERS In this chapter, detailed descriptions of the S3C8275/C8278/C8274 control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. Data and counter registers are not described in detail in this reference chapter. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C8275/C8278/C8274 register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down." Table 4-1. Set 1 Registers Register Name Mnemonic Address Decimal Locations D0H - D2H are not mapped. Basic timer control register System clock control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP 211 212 213 214 215 216 217 218 219 220 221 222 223 D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Hex R/W 4-1 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Address Decimal Oscillator control register SIO control register SIO data register SIO pre-scaler register Port 0 control register (high byte) Port 0 control register (low byte) Port 0 pull-up resistor enable register Port 1 control register (high byte) Port 1 control register (low byte) Port 1 pull-up resistor enable register Port 2 control register (high byte) Port 2 control register (low byte) Port 2 pull-up resistor enable register Port 3 control register (high byte) Port 3 control register (low byte) Port 3 Pull-up resistor enable register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register External interrupt pending register External interrupt control register (high byte) External interrupt control register (low byte) OSCCON SIOCON SIODATA SIOPS P0CONH P0CONL P0PUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P0 P1 P2 P3 P4 P5 P6 EXTIPND EXTICONH EXTICONL 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Locations FAH are not mapped. STOP control register STPCON 251 FBH R/W Locations FCH are not mapped. Basic timer counter BTCNT 253 FDH R Locations FEH are not mapped. Interrupt priority register IPR 255 FFH R/W 4-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Address Decimal LCD control Register Watch timer control register Timer A counter Timer B counter Timer A data register Timer B data register Timer 1/A control register Timer B control register Clock output control register Port 4 control register (high byte) Port 4 control register (low byte) Port 5 control register (high byte) Port 5 control register (low byte) Port 6 control register LCON WTCON TACNT TBCNT TADATA TBDATA TACON TBCON CLOCON P4CONH P4CONL P5CONH P5CONL P6CON Locations EEH - EFH are not mapped. Flash memory control register Flash memory user programming enable register Flash memory sector address register (high byte) Flash memory sector address register (low byte) Battery level detector control register FMCON FMUSR FMSECH FMSECL BLDCON Locations E5H - FFH are not mapped. NOTES: 1. An "x" means that the bit value is undefined following reset. 2. A dash("-") means that the bit is neither used nor mapped, but the bit is read as "0". R/W Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 224 225 226 227 228 229 230 231 232 233 234 235 236 237 240 241 242 243 244 F0H F1H F2H F3H F4H R/W R/W R/W R/W R/W 4-3 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Bit number(s) that is/are appended to the register name for bit addressing Register ID Name of individual bit or related bits Register address (hexadecimal) Full Register name Register location in the internal register file FLAGS - System Flags Register Bit Identifier Reset Value Read/Write Bit Addressing Mode .7 Carry Flag (C) 0 1 .6 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D5H .2 x R/W .1 x R/W Set 1 .0 0 R/W Register addressing mode only Operation does not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit 7 Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag (S) 0 1 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1") R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) Description of the effect of specific bit settings Bit number: MSB = Bit 7 LSB = Bit 0 nRESET value notation: '-' = Not used 'x' = Undetermined value '0' = Logic zero '1' = Logic one Figure 4-1. Register Description Format 4-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER BLDCON -- Battery Level Detector Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 - - .6 - - .5 0 R/W .4 0 R .3 0 R/W F4H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7-.6 Not used for the S3C8275/C8278/C8274 .5 VIN Source Bit 0 1 Internal source External source .4 Battery Level Detector Output Bit 0 1 VIN > VREF (when BLD is enabled) VIN < VREF (when BLD is enabled) .3 Battery Level Detector Enable/Disable Bit 0 1 Disable BLD Enable BLD .2-.0 Detection Voltage Selection Bits 0 1 0 0 0 1 0 1 1 VBLD = 2.2V VBLD = 2.4V VBLD = 2.8V Not available Other values 4-5 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BTCON -- Basic Timer Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W D3H .2 0 R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Disable watchdog timer function Enable watchdog timer function Other values .3-.2 Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/4096 (3) fxx/1024 fxx/128 fxx/16 .1 Basic Timer Counter Clear Bit (1) 0 1 No effect Clear the basic timer counter value .0 Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2) 0 1 No effect Clear both clock frequency dividers NOTES: 1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0". 2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0". 3. The fxx is selected clock for system (main OSC. or sub OSC.). 4-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER CLKCON -- System Clock Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 - - .5 - - .4 0 R/W .3 0 R/W D4H .2 - - .1 - - Set 1 .0 - - Register addressing mode only Oscillator IRQ Wake-up Function Bit 0 1 Enable IRQ for main wake-up in power down mode Disable IRQ for main wake-up in power down mode .6-.5 Not used for the S3C8275/C8278/C8274 (must keep always "0") CPU Clock (System Clock) Selection Bits (note) 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/2 fxx .4-.3 .2-.0 NOTE: Not used for the S3C8275/C8278/C8274 (must keep always "0") After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4. 4-7 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLOCON -- Clock Output Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 - - .6 - - .5 - - .4 - - .3 - - E8H .2 - - Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7-.2 Not used for the S3C8275/C8278/C8274 (must keep always "0") .1-.0 Clock Output Frequency Selection Bits 0 0 1 1 0 1 0 1 Select fxx/64 Select fxx/16 Select fxx/8 Select fxx/4 4-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER EXTICONH -- External Interrupt Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F8H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.7 External Interrupt (INT7) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .5-.4 P1.6 External Interrupt (INT6) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .3-.2 P1.5 External Interrupt (INT5) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .1-.0 P1.4 External Interrupt (INT4) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 4-9 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com EXTICONL -- External Interrupt Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F9H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.3 External Interrupt (INT3) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .5-.4 P0.2 External Interrupt (INT2) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .3-.2 P0.1 External Interrupt (INT1) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .1-.0 P0.0 External Interrupt (INT0) Configuration Bits 0 0 1 1 0 1 0 1 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 4-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER EXITPND -- External Interrupt Pending Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F7H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.7/INT7 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .6 P1.6/INT6 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .5 P1.5/INT5 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .4 P1.4/INT4 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .3 P1.3/INT3 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .2 P0.2/INT2 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .1 P0.1/INT1 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .0 P0.0/INT0 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending 4-11 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com FLAGS -- System Flags Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D5H .2 x R/W .1 0 R Set 1 .0 0 R/W Register addressing mode only Carry Flag (C) 0 1 Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7 .6 Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") .4 Overflow Flag (V) 0 1 Operation result is +127 or -128 Operation result is > +127 or < -128 .3 Decimal Adjust Flag (D) 0 1 Add operation completed Subtraction operation completed .2 Half-Carry Flag (H) 0 1 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 Fast Interrupt Status Flag (FIS) 0 1 Interrupt return (IRET) in progress (when read) Fast interrupt service routine in progress (when read) .0 Bank Address Selection Flag (BA) 0 1 Bank 0 is selected Bank 1 is selected 4-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER FMCON -- Flash Memory Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R F0H .2 - - Set 1, Bank 1 .1 - - .0 0 R/W Register addressing mode only Flash Memory Mode Selection Bits 0 1 0 1 0 1 0 1 1 1 0 0 Programming mode Sector erase mode Hard lock mode Not available Other values .3 Sector Erase Status Bit 0 1 Success sector erase Fail sector erase .2-.1 Not used for the S3F8275/F8278/F8274 .0 Flash Operation Start Bit 0 1 Operation stop Operation start (This bit will be cleared automatically just after the corresponding operator completed). 4-13 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com FMSECH -- Flash Memory Sector Address Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F2H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Flash Memory Sector Address Bits (High Byte) The 15th - 8th bits to select a sector of flash ROM NOTE: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address. FMSECL -- Flash Memory Sector Address Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F3H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Flash Memory Sector Address Bit (Low Byte) The 7th bit to select a sector of flash ROM .6-.0 Bits 6-0 Don't care NOTE: The low-byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address. 4-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER FMUSR -- Flash Memory User Programming Enable Register Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F1H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Flash Memory User Programming Enable Bits 1 0 1 0 0 1 0 1 Enable user programming mode Other values Disable user programming mode 4-15 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IMR -- Interrupt Mask Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W DDH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4-1.7 0 Disable (mask) 1 Enable (unmask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3 0 Disable (mask) 1 Enable (unmask) Interrupt Level 5 (IRQ5) Enable Bit; External Interrupt P0.2 0 Disable (mask) 1 Enable (unmask) Interrupt Level 4 (IRQ4) Enable Bit; External Interrupt P0.1 0 Disable (mask) 1 Enable (unmask) Interrupt Level 3 (IRQ3) Enable Bit; External Interrupt P0.0 0 Disable (mask) 1 Enable (unmask) Interrupt Level 2 (IRQ2) Enable Bit; Watch Timer Overflow 0 Disable (mask) 1 Enable (unmask) Interrupt Level 1 (IRQ1) Enable Bit; SIO Interrupt 0 Disable (mask) 1 Enable (unmask) Interrupt Level 0 (IRQ0) Enable Bit; Timer 1/A Match, Timer B Match 0 Disable (mask) 1 Enable (unmask) .6 .5 .4 .3 .2 .1 .0 NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU. 4-16 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER IPH -- Instruction Pointer (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W DAH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15-IP8). The lower byte of the IP address is located in the IPL register (DBH). IPL -- Instruction Pointer (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W DBH .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Instruction Pointer Address (Low Byte) The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7-IP0). The upper byte of the IP address is located in the IPH register (DAH). 4-17 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IPR -- Interrupt Priority Register Bit Identifier Reset Value Read/Write Addressing Mode .7, .4, and .1 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W FFH .2 x R/W Set 1, Bank 0 .1 x R/W .0 x R/W Register addressing mode only Priority Control Bits for Interrupt Groups A, B, and C (note) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Group priority undefined B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Group priority undefined .6 Interrupt Subgroup C Priority Control Bit 0 1 IRQ6 > IRQ7 IRQ7 > IRQ6 .5 Interrupt Group C Priority Control Bit 0 1 IRQ5 > (IRQ6, IRQ7) (IRQ6, IRQ7) > IRQ5 .3 Interrupt Subgroup B Priority Control Bit 0 1 IRQ3 > IRQ4 IRQ4 > IRQ3 .2 Interrupt Group B Priority Control Bit 0 1 IRQ2 > (IRQ3, IRQ4) (IRQ3, IRQ4) > IRQ2 .0 Interrupt Group A Priority Control Bit 0 1 IRQ0 > IRQ1 IRQ1 > IRQ0 NOTE: Interrupt Group A - IRQ0, IRQ1 Interrupt Group B - IRQ2, IRQ3, IRQ4 Interrupt Group C - IRQ5, IRQ6, IRQ7 4-18 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER IRQ -- Interrupt Request Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R .6 0 R .5 0 R .4 0 R .3 0 R DCH .2 0 R .1 0 R Set 1 .0 0 R Register addressing mode only Level 7 (IRQ7) Request Pending Bit; External Interrupt P1.4-1.7 0 1 Not pending Pending .6 Level 6 (IRQ6) Request Pending Bit; External Interrupt P1.3 0 1 Not pending Pending .5 Level 5 (IRQ5) Request Pending Bit; External Interrupt P0.2 0 1 Not pending Pending .4 Level 4 (IRQ4) Request Pending Bit; External Interrupt P0.1 0 1 Not pending Pending .3 Level 3 (IRQ3) Request Pending Bit; External Interrupt P0.0 0 1 Not pending Pending .2 Level 2 (IRQ2) Request Pending Bit; Watch Timer Overflow 0 1 Not pending Pending .1 Level 1 (IRQ1) Request Pending Bit; SIO Interrupt 0 1 Not pending Pending .0 Level 0 (IRQ0) Request Pending Bit; Timer 1/A Match, Timer B Match 0 1 Not pending Pending 4-19 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LCON -- LCD Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E0H .2 0 R/W Set 1, Bank 1 .1 - - .0 0 R/W Register addressing mode only Internal LCD Dividing Resistors Enable Bit 0 1 Enable internal LCD dividing resistors Disable internal LCD dividing resistors .6-.5 LCD Clock Selection Bits 0 0 1 1 0 1 0 1 fw/29 (64 Hz) fw/28 (128 Hz) fw/27 (256 Hz) fw/26 (512 Hz) .4-.2 LCD Duty and Bias Selection Bits 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x 1/4duty, 1/3bias 1/3duty, 1/3bias 1/3duty, 1/2bias 1/2duty, 1/2bias Static NOTES: 1. "x" means don't care. 2. When 1/2 bias is selected, the bias levels are set as VLC0, VLC1 (VLC2), and VSS. .1 Not used for the S3C8275/C8278/C8274 .0 LCD Display Control Bit 0 1 Turn display off (Turn off the P-Tr) Turn display on (Turn on the P-Tr) 4-20 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER OSCCON -- Oscillator Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 - - .5 - - .4 - - .3 0 R/W E0H .2 0 R/W Set 1, Bank 0 .1 - - .0 0 R/W Register addressing mode only Sub Oscillator Circuit Selection Bit 0 1 Select normal circuit for sub oscillator Select power saving circuit for sub oscillator (Automatically cleared to "0" when the sub oscillator is stopped by OSCCON.2 or the CPU is entered into stop mode in sub operating mode) .6-.4 Not used for the S3C8275/C8278/C8274 .3 Main Oscillator Control Bit 0 1 Main oscillator RUN Main oscillator STOP .2 Sub Oscillator Control Bit 0 1 Sub oscillator RUN Sub oscillator STOP .1 Not used for the S3C8275/C8278/C8274 .0 System Clock Selection Bit 0 1 Select main oscillator for system clock Select sub oscillator for system clock NOTE: A capacitor (0.1uF) should be connected between VREG and GND when the sub-oscillator is used to power saving mode (OSCCON.7="1") 4-21 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P0CONH -- Port 0 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E4H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P0.7/BUZ Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (BUZ) .5-.4 P0.6/CLKOUT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (CLKOUT) .3-.2 P0.5/TBOUT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (TBOUT) .1-.0 P0.4/TAOUT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (TAOUT) 4-22 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P0CONL -- Port 0 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E5H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P0.3/T1CLK Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode (T1CLK) N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .5-.4 P0.2/INT2 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .3-.2 P0.1/INT1 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .1-.0 P0.0/INT0 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 4-23 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P0PUR -- Port 0 Pull-Up Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E6H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P0.7's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .6 P0.6's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .5 P0.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P0.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P0.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P0.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P0.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P0.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: output A pull-up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push-pull or alternative function. 4-24 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P1CONH -- Port 1 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E7H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.7/INT7 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .5-.4 P1.6/INT6 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .3-.2 P1.5/INT5 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .1-.0 P1.4/INT4 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 4-25 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P1CONL -- Port 1 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressi ng Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E8H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.3/INT3 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .5-.4 P1.2/SI Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode (SI) N-channel open-drain output mode Push-pull output mode Not used for the S3C8275/C8278/C8274 .3-.2 P1.1/SO Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (SO) .1-.0 P1.0/SCK Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input mode (SCK) N-channel open-drain output mode Push-pull output mode Alternative function (SCK) 4-26 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P1PUR -- Port 1 Pull-up Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W F9H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P1.7's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .6 P1.6's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .5 P1.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P1.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P1.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P1.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P1.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P1.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: output A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull or alternative function. 4-27 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P2CONH -- Port 2 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EAH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P2.7/SEG24 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG24) .5-.4 P2.6/SEG25 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG25) .3-.2 P2.5/SEG26 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG26) .1-.0 P2.4/SEG27 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG27) 4-28 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P2CONL -- Port 2 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EBH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P2.3/SEG28 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG28) .5-.4 P2.2/SEG29 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG29) .3-.2 P2.1/SEG30 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG30) .1-.0 P2.0/SEG31/VBLDREF Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG31 or VBLDREF) 4-29 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P2PUR -- Port 2 Pull-up Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W ECH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P2.7's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .6 P2.6's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .5 P2.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P2.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P2.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P2.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P2.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P2.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: output A pull-up resistor of port 2 is automatically disabled only when the corresponding pin is selected as push-pull or alternative function. 4-30 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P3CONH -- Port 3 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EDH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P3.7/SEG16 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG16) .5-.4 P3.6/SEG17 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG17) .3-.2 P3.5/SEG18 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG18) .1-.0 P3.4/SEG19 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG19) 4-31 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P3CONL -- Port 3 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EEH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P3.3/SEG20 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG20) .5-.4 P3.2/SEG21 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG21) .3-.2 P3.1/SEG22 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG22) .1-.0 P3.0/SEG23 Configuration Bits 0 0 1 1 0 1 0 1 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG23) 4-32 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P3PUR -- Port 3 Pull-up Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EFH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only P3.7's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .6 P3.6's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .5 P3.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P3.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P3.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P3.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P3.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P3.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: output A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull or alternative function. 4-33 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P4CONH -- Port 4 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E9H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only P4.7/SEG8 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG8) .5-.4 P4.6/SEG9 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG9) .3-.2 P4.5/SEG10 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG10) .1-.0 P4.4/SEG11 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG11) 4-34 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P4CONL -- Port 4 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EAH .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only P4.3/SEG12 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG12) .5-.4 P4.2/SEG13 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG13) .3-.2 P4.1/SEG14 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG14) .1-.0 P4.0/SEG15 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG15) 4-35 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P5CONH -- Port 5 Control Register (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EBH .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only P5.7/SEG0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG0) .5-.4 P5.6/SEG1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG1) .3-.2 P5.5/SEG2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG2) .1-.0 P5.4/SEG3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG3) 4-36 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER P5CONL -- Port 5 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W ECH .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only P5.3/SEG4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG4) .5-.4 P5.2/SEG5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG5) .3-.2 P5.1/SEG6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG6) .1-.0 P5.0/SEG7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (SEG7) 4-37 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com P6CON -- Port 6 Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W EDH .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only P6.3/COM3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (COM3) .5-.4 P6.2/COM2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (COM2) .3-.2 P6.1/COM1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (COM1) .1-.0 P6.0/COM0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Input mode with pull-up resistor Push-pull output mode Alternative function (COM0) 4-38 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER PP -- Register Page Pointer Bit Identifier Reset Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W DFH .2 0 R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only Destination Register Page Selection Bits 0 0 0 0 0 0 0 0 1 0 1 0 Destination: page 0 Destination: page 1 (Not used for the S3C8278/C8274) Destination: page 2 Not used for the S3C8275/C8278/C8274 Others .3 - .0 Source Register Page Selection Bits 0 0 0 0 0 0 0 0 1 0 1 0 Source: page 0 Source: page 1 (Not used for the S3C8278/C8274) Source: page 2 Not used for the S3C8275/C8278/C8274 Others NOTES: 1. In the S3C8275 microcontroller, the internal register file is configured as three pages (Pages 0 -2). The pages 0 -1 are used for general purpose register file, and page 2 is used for LCD data register or general purpose registers. 2. In the S3C8278/C8274 microcontroller, the internal register file is configured as two pages (Pages 0, 2). The page 0 is used for general purpose register file, and page 2 is used for LCD data register or general purpose registers. 4-39 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RP0 -- Register Pointer 0 Bit Identifier Reset Value Read/Write Addressing Mode .7-.3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 0 R/W D6H .2 - - .1 - - Set 1 .0 - - Register addressing only Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H-C7H. .2-.0 Not used for the S3C8275/C8278/C8274 RP1 -- Register Pointer 1 Bit Identifier Reset Value Read/Write Addressing Mode .7 - .3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 1 R/W D7H .2 - - .1 - - Set 1 .0 - - Register addressing only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H-CFH. .2 - .0 Not used for the S3C8275/C8278/C8274 4-40 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER SIOCON -- SIO Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E1H .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only SIO Shift Clock Selection Bit 0 1 Internal clock (P.S clock) External clock (SCK) .6 Data Direction Control Bit 0 1 MSB-first mode LSB-first mode .5 SIO Mode Selection Bit 0 1 Receive-only mode Transmit/receive mode .4 Shift Clock Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges Tx at rising edges, Rx at falling edges .3 SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting .2 SIO Shift Operation Enable Bit 0 1 Disable shifter and clock counter Enable shifter and clock counter .1 SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt .0 SIO Interrupt Pending Bit 0 0 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) 4-41 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SPH -- Stack Pointer (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D8H .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15-SP8). The lower byte of the stack pointer value is located in register SPL (D9H). The SP value is undefined following a reset. SPL -- Stack Pointer (Low Byte) Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D9H .2 x R/W .1 x R/W Set 1 .0 x R/W Register addressing mode only Stack Pointer Address (Low Byte) The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7-SP0). The upper byte of the stack pointer value is located in register SPH (D8H). The SP value is undefined following a reset. 4-42 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER STPCON -- Stop Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W FBH .2 0 R/W Set 1, Bank 0 .1 0 R/W .0 0 R/W Register addressing mode only STOP Control Bits 10100101 Other values Enable stop instruction Disable stop instruction NOTE: Before execute the STOP instruction, set this STPCON register as "10100101b". Otherwise the STOP instruction will not execute as well as reset will be generated. 4-43 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SYM -- System Mode Register Bit Identifier Reset Value Read/Write Addressing Mode .7 0 R/W .6 - - .5 - - .4 x R/W .3 x R/W DEH .2 x R/W .1 0 R/W Set 1 .0 0 R/W Register addressing mode only .7 This bit must remain logic "0" .6-.5 Not used for the S3C8275/C8278/C8274 Fast Interrupt Level Selection Bits (1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 .4-.2 .1 Fast Interrupt Enable Bit (2) 0 1 Disable fast interrupt processing Enable fast interrupt processing .0 Global Interrupt Enable Bit (3) 0 1 Disable all interrupt processing Enable all interrupt processing NOTES: 1. You can select only one interrupt level at a time for fast interrupt processing. 2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4. 3. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.0). 4-44 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER TACON -- Timer 1/A Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E6H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Timer 1 Operating Mode Selection Bit 0 1 Two 8-bit timers mode (timer A/B) One 16-bit timer mode (timer 1) .6-.4 Timer 1/A Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock) T1CLK (external clock) Not available .3 Timer 1/A Counter Clear Bit 0 1 No effect Clear the timer 1/A counter (when write, automatically cleared to "0" after being cleared basic timer counter) .2 Timer 1/A Counter Operating Enable Bit 0 1 Disable counting operation Enable counting operation .1 Timer 1/A Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 Timer 1/A Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) 4-45 CONTROL REGISTERS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TBCON -- Timer B Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E7H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only .7 Not used for the S3C8275/C8278/C8274 .6-.4 Timer B Clock Selection Bits 0 0 0 0 1 0 0 1 1 0 Others 0 1 0 1 0 fxx/512 fxx/256 fxx/64 fxx/8 fxt (sub clock) Not available .3 Timer B Counter Clear Bit 0 1 No effect Clear the timer B counter (when write, automatically cleared to "0" after being cleared basic timer counter) .2 Timer B Counter Operating Enable Bit 0 1 Disable counting operation Enable counting operation .1 Timer B Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 Timer B Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) 4-46 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONTROL REGISTER WTCON -- Watch Timer Control Register Bit Identifier Reset Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W E1H .2 0 R/W Set 1, Bank 1 .1 0 R/W .0 0 R/W Register addressing mode only Watch Timer Clock Selection Bit 0 1 Main system clock divided by 27 (fx/128) Sub system clock (fxt) .6 Watch Timer Interrupt Enable Bit 0 1 Disable watch timer interrupt Enable watch timer interrupt .5-.4 Buzzer Signal Selection Bits 0 0 1 1 0 1 0 1 0.5 kHz 1 kHz 2 kHz 4 kHz .3-.2 Watch Timer Speed Selection Bits 0 0 1 1 0 1 0 1 Set watch timer interrupt to 1s Set watch timer interrupt to 0.5s Set watch timer interrupt to 0.25s Set watch timer interrupt to 3.91ms .1 Watch Timer Enable Bit 0 1 Disable watch timer; Clear frequency dividing circuits Enable watch timer .0 Watch Timer Interrupt Pending Bit 0 1 Interrupt is not pending, clear pending bit when write Interrupt is pending NOTE: Watch timer clock frequency (fw) is assumed to be 32.768 kHz. 4-47 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE 5 OVERVIEW Levels INTERRUPT STRUCTURE The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources. Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0-IRQ7, also called level 0-level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C8275/C8278/C8274 interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels. Vectors Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C8275/C8278/C8274 uses twelve vectors. Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3C8275/C8278/C8274 interrupt structure, there are twelve possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit. 5-1 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT TYPES The three components of the S3C8 interrupt structure described before -- levels, vectors, and sources -- are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: Type 2: Type 3: One level (IRQn) + one vector (V 1) + one source (S 1) One level (IRQn) + one vector (V 1) + multiple sources (S 1 - Sn) One level (IRQn) + multiple vectors (V 1 - Vn) + multiple sources (S 1 - Sn , Sn+1 - Sn+m) In the S3C8275/C8278/C8274 microcontroller, two interrupt types are implemented. Levels Type 1: IRQn Vectors V1 Sources S1 S1 Type 2: IRQn V1 S2 S3 Sn V1 Type 3: IRQn V2 V3 Vn S1 S2 S3 Sn Sn + 1 NOTES: 1. The number of Sn and Vn value is expandable. 2. In the S3C8275/C8278/C8274 implementation, interrupt types 1 and 3 are used. Sn + 2 Sn + m Figure 5-1. S3C8-Series Interrupt Types 5-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE S3C8275/C8278/C8274 INTERRUPT STRUCTURE The S3C8275/C8278/C8274 microcontroller supports twelve interrupt sources. All twelve of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware). When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. Levels RESET IRQ0 Vectors 100H F0H F2H Sources Basic timer overflow Timer 1/A match Timer B match SIO interrupt Watch timer overflow P0.0 external interrupt P0.1 external interrupt P0.2 external interrupt P1.3 external interrupt P1.4 external interrupt P1.5 external interrupt P1.6 external interrupt P1.7 external interrupt Reset/Clear H/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 F4H F6H E0H E2H E4H E6H E8H EAH IRQ7 ECH EEH NOTES: 1. Within a given interrupt level, the low vector address has high priority. For example, F0H has higher priority than F2H within the level IRQ.0 the priorities within each level are set at the factory. 2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. Figure 5-2. S3C8275/C8278/C8274 Interrupt Structure 5-3 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8275/C8278/C8274 interrupt structure are stored in the vector address area of the internal 16-Kbyte ROM, 0H-3FFFH, or 8, 4-Kbyte (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses). The program reset address in the ROM is 0100H. (Decimal) 16,383 16-Kbyte 8,191 8-Kbyte 4,095 4-Kbyte Internal Program Memory (ROM) Area (HEX) 3FFFH 1FFFH 0FFFH 255 Interrupt Vector Address Area 0 100H FFH Reset Address 00H Figure 5-3. ROM Vector Address Area 5-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Decimal Value 256 242 240 244 246 224 226 228 230 238 236 234 232 Hex Value 100H F2H F0H F4H F6H E0H E2H E4H E6H EEH ECH EAH E8H Basic timer overflow Timer B match Timer 1/A match SIO interrupt Watch timer overflow P0.0 external interrupt P0.1 external interrupt P0.2 external interrupt P1.3 external interrupt P1.7 external interrupt P1.6 external interrupt P1.5 external interrupt P1.4 external interrupt IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt Source Request Interrupt Level Reset IRQ0 Priority in Level - 1 0 - - - - - - 3 2 1 0 Reset/Clear H/W S/W NOTES: 1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware. 5-5 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure. During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: -- The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels. -- The interrupt priority register, IPR, controls the relative priorities of interrupt levels. -- The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). -- The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented). Table 5-2. Interrupt Control Register Overview Control Register Interrupt mask register Interrupt priority register ID IMR IPR R/W R/W R/W Function Description Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0-IRQ7. Controls the relative processing priorities of the interrupt levels. The seven levels of S3C8275/C8278/C8274 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7. This register contains a request pending bit for each interrupt level. This register enables/disables fast interrupt processing and dynamic global interrupt processing. Interrupt request register System mode register NOTE: IRQ SYM R R/W Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended. 5-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: -- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) -- Interrupt level enable/disable settings (IMR register) -- Interrupt level priority settings (IPR register) -- Interrupt source enable/disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. EI nRESET IRQ0-IRQ7, Interrupts S R Q Interrupt Request Register (Read-only) Polling Cycle Interrupt Priority Register Vector Interrupt Cycle Interrupt Mask Register Global Interrupt Control (EI, DI or SYM.0 manipulation) Figure 5-4. Interrupt Function Diagram 5-7 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers Interrupt Source Timer B match Timer 1/A match SIO interrupt Interrupt Level IRQ0 IRQ1 Register(s) TBCON, TBDATA, TBCNT TACON, TADATA, TACNT SIOCON SIODATA SIOPS WTCON P0CONL EXTICONL EXTIPND P0CONL EXTICONL EXTIPND P0CONL EXTICONL EXTIPND P1CONL EXTICONL EXTIPND P1CONH EXTICONH EXTIPND Location(s) in Set 1 E7H, E5H, E3H, bank 1 E6H, E4H, E2H, bank 1 E1H, bank 0 E2H, bank 0 E3H, bank 0 E1H, bank 1 E5H, bank 0 F9H, bank 0 F7H, bank 0 E5H, bank 0 F9H, bank 0 F7H, bank 0 E5H, bank 0 F9H, bank 0 F7H, bank 0 E8H, bank 0 F9H, bank 0 F7H, bank 0 E7H, bank 0 F8H, bank 0 F7H, bank 0 Watch timer overflow P0.0 external interrupt IRQ2 IRQ3 P0.1 external interrupt IRQ4 P0.2 external interrupt IRQ5 P1.3 external interrupt IRQ6 P1.7 P1.6 P1.5 P1.4 external external external external interrupt interrupt interrupt interrupt IRQ7 5-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4-SYM.2, is undetermined. The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose. System Mode Register (SYM) DEH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Always logic "0" Global interrupt enable bit: 0 = Disable all interrupts processing 1 = Enable all interrupts processing Fast interrupt enable bit: 0 = Disable fast interrupts processing 1 = Enable fast interrupts processing Not used for the S3C8275/C8278/C8274 Fast interrupt level selection bits: 0 0 0 = IRQ0 0 0 1 = IRQ1 0 1 0 = IRQ2 0 1 1 = IRQ3 1 0 0 = IRQ4 1 0 1 = IRQ5 1 1 0 = IRQ6 1 1 1 = IRQ7 Figure 5-5. System Mode Register (SYM) 5-9 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode. Interrupt Mask Register (IMR) DDH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Interrupt level enable bits: 0 = Disable (mask) interrupt level 1 = Enable (un-mask) interrupt level NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended. Figure 5-6. Interrupt Mask Register (IMR) 5-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware). To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A Group B Group C IRQ0, IRQ1 IRQ2, IRQ3, IRQ4 IRQ5, IRQ6, IRQ7 IPR Group A IPR Group B IPR Group C A1 A2 B1 B21 B2 B22 IRQ4 C1 C21 IRQ5 IRQ6 C2 C22 IRQ7 IRQ0 IRQ1 IRQ2 IRQ3 Figure 5-7. Interrupt Request Priority Groups As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: -- IPR.5 controls the relative priorities of group C interrupts. -- Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C. -- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. 5-11 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W MSB Group priority: D7 D4 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 = Undefined =B>C>A =A>B>C =B>A>C =C>A>B =C>B>A =A>C>B = Undefined .7 .6 .5 .4 .3 .2 .1 .0 LSB Group A: 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Group B: 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Subgroup B: 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C: 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C: 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Figure 5-8. Interrupt Priority Register (IPR) 5-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to "0". You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled. Interrupt Request Register (IRQ) DCH, Set 1, Read-only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Interrupt level request pending bits: 0 = Interrupt level is not pending 1 = Interrupt level is pending Figure 5-9. Interrupt Request Register (IRQ) 5-13 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source's mode or control register. 5-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. 2. 3. 4. 5. 6. 7. A source generates an interrupt request by setting the interrupt request bit to "1". The CPU polling procedure identifies a pending condition for that source. The CPU checks the source's interrupt level. The CPU generates an interrupt acknowledge signal. Interrupt logic determines the interrupt's vector address. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). The CPU continues polling for interrupt requests. INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced, the following conditions must be met: -- Interrupt processing must be globally enabled (EI, SYM.0 = "1") -- The interrupt level must be enabled (IMR register) -- The interrupt level must have the highest priority if more than one levels are currently requesting service -- The interrupt must be enabled at the interrupt's source (peripheral control register) When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. 2. 3. 4. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. Save the program counter (PC) and status flags to the system stack. Branch to the interrupt vector to fetch the address of the service routine. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request. 5-15 INTERRUPT STRUCTURE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H-FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. 2. 3. 4. 5. 6. Push the program counter's low-byte value to the stack. Push the program counter's high-byte value to the stack. Push the FLAG register values to the stack. Fetch the service routine's high-byte address from the vector location. Fetch the service routine's low-byte address from the vector location. Branch to the service routine specified by the concatenated 16-bit vector address. NOTE A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H-FFH. NESTING OF VECTORED INTERRUPTS It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps: 1. 2. 3. 4. 5. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). Load the IMR register with a new mask value that enables only the higher priority interrupt. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR). Execute an IRET. Depending on the application, you may be able to simplify the procedure above to some extent. INSTRUCTION POINTER (IP) The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP registers are IPH (high byte, IP15-IP8) and IPL (low byte, IP7-IP0). FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4-SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to "1". 5-16 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: -- The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and -- When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime"). NOTE For the S3C8275/C8278/C8274 microcontroller, the service routine for any one of the eight interrupt levels: IRQ0-IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1. 2. 3. Load the start address of the service routine into the instruction pointer (IP). Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4-SYM.2) Write a "1" to the fast interrupt enable bit in the SYM register. Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. 2. 3. 4. 5. 6. 7. The contents of the instruction pointer and the PC are swapped. The FLAG register values are written to the FLAGS' ("FLAGS prime") register. The fast interrupt status bit in the FLAGS register is set. The interrupt is serviced. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register. The fast interrupt status bit in FLAGS is cleared automatically. Relationship to Interrupt Pending Bit Types As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type of pending condition clear function -- by hardware or by software. Programming Guidelines Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends. 5-17 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET 6 OVERVIEW INSTRUCTION SET The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: -- A full complement of 8-bit arithmetic and logic operations, including multiply and divide -- No special I/O instructions (I/O control/data registers are mapped directly into the register file) -- Decimal adjustment included in binary-coded decimal (BCD) operations -- 16-bit (word) data can be incremented and decremented -- Flexible instructions for bit addressing, rotate, and shift operations DATA TYPES The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces." ADDRESSING MODES There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes." 6-1 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst dst,src dst,src src dst,src dst,src Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre-decrement Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing) 6-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC ADD CP DA DEC DECW DIV INC INCW MULT SBC SUB dst,src dst,src dst,src dst dst dst dst,src dst dst dst,src dst,src dst,src Add with carry Add Compare Decimal adjust Decrement Decrement word Divide Increment Increment word Multiply Subtract with carry Subtract Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR 6-3 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF BTJRT CALL CPIJE CPIJNE DJNZ ENTER EXIT IRET JP JP JR NEXT RET WFI Bit Manipulation Instructions BAND BCP BITC BITR BITS BOR BXOR TCM TM dst,src dst,src dst dst dst dst,src dst,src dst,src dst,src Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask cc,dst dst cc,dst dst,src dst,src dst dst,src dst,src r,dst Bit test and jump relative on false Bit test and jump relative on true Call procedure Compare, increment and jump on equal Compare, increment and jump on non-equal Decrement register and jump on non-zero Enter Exit Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt 6-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL RLC RR RRC SRA SWAP dst dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles CPU Control Instructions CCF DI EI IDLE NOP RCF SB0 SB1 SCF SRP SRP0 SRP1 STOP src src src Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6-5 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7-FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. System Flags Register (FLAGS) D5H, Set 1, R/W MSB Carry flag (C) .7 .6 .5 .4 .3 .2 .1 .0 LSB Bank address status flag (BA) Fast interrupt status flag (FIS) Half-carry flag (H) Zero flag (Z) Sign flag (S) Overflow flag (V) Decimal adjust flag (D) Figure 6-1. System Flags Register (FLAGS) 6-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. S V D Sign Flag (FLAGS.5) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Overflow Flag (FLAGS.4) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Decimal Adjust Flag (FLAGS.3) The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition. H Half-Carry Flag (FLAGS.2) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program. FIS Fast Interrupt Status Flag (FLAGS.1) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed. BA Bank Address Flag (FLAGS.0) The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction. 6-7 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V D H 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Description Table 6-3. Instruction Set Symbols Symbol dst src @ PC IP FLAGS RP # H D B opc Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register (D5H) Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description 6-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation cc r rb r0 rr R Rb RR IA Ir IR Irr IRR X XS xl da ra im iml Condition code Working register only Bit (b) of working register Bit 0 (LSB) of working register Working register pair Register or working register Bit 'b' of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate (long) addressing mode Description Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) Rn.b (n = 0-15, b = 0-7) Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg.b (reg = 0-255, b = 0-7) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) addr (addr = 0-254, even number only) @Rn (n = 0-15) @Rn or @reg (reg = 0-255, n = 0-15) @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg [Rn] (reg = 0-255, n = 0-15) #addr [RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-65535, where p = 0, 2, ..., 14) addr (addr = range 0-65535) addr (addr = number in the range +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255) #data (data = range 0-65535) 6-9 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F 0 DEC R1 RLC R1 INC R1 JP IRR1 DA R1 POP R1 COM R1 PUSH R2 DECW RR1 RL R1 INCW RR1 CLR R1 RRC R1 SRA R1 RR R1 SWAP R1 1 DEC IR1 RLC IR1 INC IR1 SRP/0/1 IM DA IR1 POP IR1 COM IR1 PUSH IR2 DECW IR1 RL IR1 INCW IR1 CLR IR1 RRC IR1 SRA IR1 RR IR1 SWAP IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 PUSHUD IR1,R2 POPUD IR2,R1 CP r1,r2 XOR r1,r2 CPIJE Ir,r2,RA CPIJNE Irr,r2,RA LDCD r1,Irr2 LDCPD r2,Irr1 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 PUSHUI IR1,R2 POPUI IR2,R1 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LDCPI r2,Irr1 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 MULT R2,RR1 DIV R2,RR1 CP R2,R1 XOR R2,R1 LDW RR2,RR1 CALL IA1 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 MULT IR2,RR1 DIV IR2,RR1 CP IR2,R1 XOR IR2,R1 LDW IR2,RR1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM MULT IM,RR1 DIV IM,RR1 CP R1,IM XOR R1,IM LDW RR1,IML LD IR1,IM LD R1,IM CALL DA1 7 BOR r0-Rb BCP r1.b, R2 BXOR r0-Rb BTJR r2.b, RA LDB r0-Rb BITC r1.b BAND r0-Rb BIT r1.b LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs 6-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 8 LD r1,R2 9 LD r2,R1 A DJNZ r1,RA B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F NEXT ENTER EXIT WFI SB0 SB1 IDLE STOP DI EI RET IRET RCF SCF CCF NOP 6-11 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (note) 1111 (note) 0110 (note) 1110 (note) 1101 0101 0100 1100 0110 (note) 1110 (note) 1001 0001 1010 0010 1111 (note) 0111 (note) 1011 0011 F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Mnemonic Description Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal - - C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S X OR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 Flags Set NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used. 6-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction 6-13 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ADC -- Add with carry ADC Operation: dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 12 13 Addr Mode dst src r r r lr C: Z: S: V: Format: opc src dst 3 6 6 14 15 R R R IR opc dst src 3 6 16 R IM Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 0 3H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1. 6-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET ADD ADD -- Add dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Operation: Flags: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 02 03 Addr Mode dst src r r r lr opc src dst 3 6 6 04 05 R R R IR opc dst src 3 6 06 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1. 6-15 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com AND AND -- Logical AND dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 52 53 Addr Mode dst src r r r lr opc src dst 3 6 6 54 55 R R R IR opc dst src 3 6 56 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1. 6-16 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET BAND BAND BAND Operation: -- Bit AND dst,src.b dst.b,src dst(0) dst(0) AND src(b) or dst(b) dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 6 Opcode (Hex) 67 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 6 67 Rb r0 In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H and register 01H = 05H: BAND R1,01H.1 BAND 01H.1,R1 R1 = 06H, register 01H = 05H Register 01H = 05H, R1 = 07H In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value 06H (00000110B) in register R1. 6-17 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BCP -- Bit Compare BCP Operation: dst,src.b dst(0) - src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Unaffected. Set if the two bits are the same; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc NOTE: dst | b | 0 Cycles 6 Opcode (Hex) 17 Addr Mode dst src r0 Rb src 3 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 R1 = 07H, register 01H = 01H If destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 6-18 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET BITC BITC -- Bit Complement dst.b dst(b) NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Operation: Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc NOTE: dst | b | 0 Cycles 4 Opcode (Hex) 57 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H BITC R1.1 R1 = 05H If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared. 6-19 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BITR -- Bit Reset BITR Operation: dst.b dst(b) 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: Format: Bytes opc NOTE: dst | b | 0 No flags are affected. Cycles 4 Opcode (Hex) 77 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITR R1.1 R1 = 05H If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B). 6-20 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET BITS -- Bit Set BITS Operation: dst.b dst(b) 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: Format: Bytes opc NOTE: dst | b | 1 No flags are affected. Cycles 4 Opcode (Hex) 77 Addr Mode dst rb 2 In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITS R1.3 R1 = 0FH If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B). 6-21 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BOR -- Bit OR BOR BOR Operation: dst,src.b dst.b,src dst(0) dst(0) OR src(b) or dst(b) dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 6 Opcode (Hex) 07 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 6 07 Rb r0 In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit. Examples: Given: R1 = 07H and register 01H = 03H: BOR BOR R1, 01H.1 01H.2, R1 R1 = 07H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working register R1. In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H. 6-22 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET BTJRF BTJRF Operation: -- Bit Test, Jump Relative on False dst,src.b If src(b) is a "0", then PC PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: Format: No flags are affected. Bytes (Note 1) Cycles 10 Opcode (Hex) 37 Addr Mode dst src RA rb opc NOTE: src | b | 0 dst 3 In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRF SKIP,R1.3 PC jumps to SKIP location If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-23 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BTJRT -- Bit Test, Jump Relative on True BTJRT Operation: dst,src.b If src(b) is a "1", then PC PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: Format: Bytes (Note 1) No flags are affected. Cycles 10 Opcode (Hex) 37 Addr Mode dst src RA rb opc NOTE: src | b | 1 dst 3 In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRT SKIP,R1.1 If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-24 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET BXOR -- Bit XOR BXOR BXOR Operation: dst,src.b dst.b,src dst(0) dst(0) XOR src(b) or dst(b) dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes opc dst | b | 0 Cycles 6 Opcode (Hex) 27 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 6 27 Rb r0 In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B): BXOR R1,01H.1 BXOR 01H.2,R1 R1 = 06H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected. 6-25 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CALL -- Call Procedure CALL Operation: dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc dst 3 Cycles 14 Opcode (Hex) F6 Addr Mode dst DA No flags are affected. opc dst 2 12 F4 IRR opc Examples: dst 2 14 D4 IA Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H: CALL 3521H SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction.) CALL CALL @RR0 #40H SP = 0000H (0000H = 1AH, 0001H = 49H) SP = 0000H (0000H = 1AH, 0001H = 49H) In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example. 6-26 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET CCF -- Complement Carry Flag CCF Operation: C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 6-27 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLR -- Clear CLR Operation: dst dst "0" The destination location is cleared to "0". Flags: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) B0 B1 Addr Mode dst R IR No flags are affected. Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H Register 00H = 00H Register 01H = 02H, register 02H = 00H @01H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6-28 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET COM -- Complement COM Operation: dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B). 6-29 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CP -- Compare CP Operation: dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) A2 A3 Addr Mode dst src r r r lr opc src dst 3 6 6 A4 A5 R R R IR opc Examples: 1. dst src 3 6 A6 R IM Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1 SKIP In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. 6-30 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET CPIJE -- Compare, Increment, and Jump on Equal CPIJE Operation: dst,src,RA If dst - src = "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed. Flags: Format: Bytes opc NOTE: No flags are affected. Cycles 12 Opcode (Hex) C2 Addr Mode dst src r Ir src dst RA 3 Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-31 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CPIJNE -- Compare, Increment, and Jump on Non-Equal CPIJNE Operation: dst,src,RA If dst - src "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: Format: Bytes opc NOTE: No flags are affected. Cycles 12 Opcode (Hex) D2 Addr Mode dst src r Ir src dst RA 3 Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location Working register R1 contains the value 02H, working register R2 (the source pointer) the value 03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to - 128.) 6-32 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET DA -- Decimal Adjust DA Operation: dst dst DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits): Instruction Carry Before DA 0 0 0 ADD ADC 0 0 0 1 1 1 0 SUB SBC 0 1 1 Bits 4-7 Value (Hex) 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H Flag Before DA 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 Value (Hex) 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F Number Added to Byte 00 06 06 60 66 66 60 66 66 00 = - 00 FA = - 06 A0 = - 60 9A = - 66 Carry After DA 0 0 0 1 1 1 1 1 1 0 0 1 1 Flags: C: Z: S: V: D: H: Set if there was a carry from the most significant bit; cleared otherwise (see table). Set if result is "0"; cleared otherwise. Set if result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 40 41 Addr Mode dst R IR 6-33 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DA -- Decimal Adjust DA Example: (Continued) Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD DA R1,R0 R1 ; ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = C, R1 3CH R1 3CH + 06 If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0001 + 0010 0011 0101 0111 1100 = 15 27 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained: 0011 + 0000 0100 1100 0110 0010 = 42 Assuming the same values given above, the statements SUB DA 27H,R0 ; @R1 ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = 1 @R1 31-0 leave the value 31 (BCD) in address 27H (@R1). 6-34 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET DEC -- Decrement DEC Operation: dst dst dst - 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR Examples: Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. 6-35 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DECW -- Decrement Word DECW Operation: dst dst dst - 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 80 81 Addr Mode dst RR IR Examples: Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW RR0 DECW @R2 R0 = 12H, R1 = 33H Register 30H = 0FH, register 31H = 20H In the first example, destination register R0 contains the value 12H and register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H. NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW RR0 LD OR JR R2,R1 R2,R0 NZ,LOOP 6-36 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET DI -- Disable Interrupts DI Operation: SYM (0) 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F No flags are affected. Example: Given: SYM = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing. Before changing IMR, interrupt pending and interrupt source control register, be sure DI state. 6-37 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DIV -- Divide (Unsigned) DIV Operation: dst,src dst / src dst (UPPER) REMAINDER dst (LOWER) QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if the V flag is set and quotient is between 28 and 29 -1; cleared otherwise. Set if divisor or quotient = "0"; cleared otherwise. Set if MSB of quotient = "1"; cleared otherwise. Set if quotient is 28 or if divisor = "0"; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc src dst 3 Cycles 26/10 26/10 26/10 NOTE: Opcode (Hex) 94 95 96 Addr Mode dst src RR RR RR R IR IM Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV DIV DIV RR0,R2 RR0,@R2 RR0,#20H R0 = 03H, R1 = 40H R0 = 03H, R1 = 20H R0 = 03H, R1 = 80H In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1). 6-38 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET DJNZ -- Decrement and Jump if Non-Zero DJNZ Operation: r,dst rr-1 If r 0, PC PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to -128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement. NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction. Flags: Format: No flags are affected. Bytes r | opc dst 2 Cycles 8 (jump taken) 8 (no jump) Opcode (Hex) rA r = 0 to F Addr Mode dst RA Example: Given: R1 = 02H and LOOP is the label of a relative address: SRP DJNZ #0C0H R1,LOOP DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label. 6-39 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com EI -- Enable Interrupts EI Operation: SYM (0) 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F No flags are affected. Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 6-40 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET ENTER -- Enter ENTER Operation: SP @SP IP PC IP SP - 2 IP PC @IP IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: Format: Bytes opc 1 Cycles 14 Opcode (Hex) 1F No flags are affected. Example: The diagram below shows one example of how to use an ENTER statement. Before Address IP 0050 Address PC 0040 40 41 42 43 Enter Address H Address L Address H Data 1F 01 10 PC 0110 Data Address IP 0043 After Data Address 40 41 42 43 Enter Address H Address L Address H Data 1F 01 10 SP 0022 SP 0020 22 Data Stack Memory 20 21 22 IPH IPL Data Stack 00 50 110 Routine Memory 6-41 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com EXIT -- Exit EXIT Operation: IP SP PC IP @SP SP + 2 @IP IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: Format: Bytes opc 1 Cycles 14 (internal stack) 16 (internal stack) Opcode (Hex) 2F No flags are affected. Example: The diagram below shows one example of how to use an EXIT statement. Before Address IP 0050 Address PC 0040 50 51 SP 0022 140 20 21 22 IPH IPL Data Stack 00 50 Memory 22 Data Stack Exit 2F PCL old PCH 60 00 SP 0022 Data PC 0060 Data Address IP 0052 After Data Address 60 Main Data Memory 6-42 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET IDLE -- Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - - No flags are affected. Example: The instruction IDLE NOP NOP NOP ; stops the CPU clock but not the system clock 6-43 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INC -- Increment INC Operation: dst dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F Addr Mode dst r opc dst 2 4 4 20 21 R IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 6-44 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET INCW -- Increment Word INCW Operation: dst dst dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) A0 A1 Addr Mode dst RR IR Examples: Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW INCW RR0 @R1 R0 = 1AH, R1 = 03H Register 02H = 10H, register 03H = 00H In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 00H and register 02H from 0FH to 10H. NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example: LOOP: INCW LD OR JR RR0 R2,R1 R2,R0 NZ,LOOP 6-45 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IRET -- Interrupt Return IRET Operation: IRET (Normal) FLAGS SP PC SP SYM(0) @SP SP + 1 @SP SP + 2 1 IRET (Fast) PC IP FLAGS FLAGS' FIS 0 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: Format: IRET (Normal) opc Bytes 1 Cycles 10 (internal stack) 12 (internal stack) IRET (Fast) opc Bytes 1 Cycles 6 Opcode (Hex) BF Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred). Example: In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H. 0H FFH 100H IRET Interrupt Service Routine JP to FFH FFFFH NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceded by a clearing of the interrupt status (as with a reset of the IPR register). 6-46 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET JP -- Jump JP JP Operation: cc,dst dst (Conditional) (Unconditional) If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: Format: (1) No flags are affected. Bytes (2) Cycles 8 Opcode (Hex) ccD cc = 0 to F Addr Mode dst DA cc | opc dst 3 opc dst 2 8 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2 -byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H. 6-47 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com JR -- Jump Relative JR Operation: cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes). The range of the relative address is +127, -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes (1) No flags are affected. Cycles 6 Opcode (Hex) ccB cc = 0 to F Addr Mode dst RA cc | opc dst 2 NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6-48 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET LD -- Load LD Operation: dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: Format: Bytes dst | opc src 2 Cycles 4 4 Opcode (Hex) rC r8 Addr Mode dst src r r IM R No flags are affected. src | opc dst 2 4 r9 r = 0 to F R r opc dst | src 2 4 4 C7 D7 r Ir lr r opc src dst 3 6 6 E4 E5 R R R IR opc dst src 3 6 6 E6 D6 R IR IM IM opc src dst 3 6 F5 IR R opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r 6-49 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LD -- Load LD Examples: (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH R0,#LOOP[R1] #LOOP[R0],R1 6-50 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET LDB -- Load Bit LDB LDB Operation: dst,src.b dst.b,src dst(0) src(b) or dst(b) src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: Format: Bytes opc dst | b | 0 No flags are affected. Cycles 6 Opcode (Hex) 47 Addr Mode dst src r0 Rb src 3 opc NOTE: src | b | 1 dst 3 6 47 Rb r0 In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R0 = 06H and general register 00H = 05H: LDB LDB R0,00H.2 00H.0,R0 R0 = 07H, register 00H = 05H R0 = 06H, register 00H = 04H In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H. 6-51 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LDC/LDE -- Load Memory LDC/LDE Operation: dst,src dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory. Flags: Format: Bytes 1. 2. 3. 4. 5. opc opc opc opc opc dst | src 2 No flags are affected. Cycles 10 Opcode (Hex) C3 Addr Mode dst src r Irr src | dst 2 10 D3 Irr r dst | src XS XS XLL XLL DA L DA L DA L DA L XLH XLH DA H DA H DA H DA H 3 12 E7 r XS [rr] src | dst 3 12 F7 XS [rr] r dst | src 4 14 A7 r XL [rr] 6. opc src | dst 4 14 B7 XL [rr] r 7. opc dst | 0000 4 14 A7 r DA 8. opc src | 0000 4 14 B7 DA r 9. opc dst | 0001 4 14 A7 r DA 10. opc src | 0001 4 14 B7 DA r NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0 -1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 6-52 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET LDC/LDE -- Load Memory LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; R0 contents of program memory location 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H) ; R0 contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 0 4H ; R0 contents of program memory location 1104H, R0=88H ; R0 contents of external data memory location 1104H, ; R0 = 98H ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) 11H ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) 11H LDE R0,@RR2 LDC (note) @RR2,R0 LDE @RR2,R0 LDC R0,#01H[RR2] LDE R0,#01H[RR2] LDC (note) #01H[RR2],R0 LDE #01H[RR2],R0 LDC R0,#1000H[RR2] LDE R0,#1000H[RR2] LDC LDE R0,1104H R0,1104H LDC (note) 1105H,R0 LDE 1105H,R0 NOTE: These instructions are not supported by masked ROM type devices. 6-53 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LDCD/LDED -- Load Memory and Decrement LDCD/LDED Operation: dst,src dst src rr rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected. Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 RR6 - 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H 6-54 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET LDCI/LDEI -- Load Memory and Increment LDCI/LDEI Operation: dst,src dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E3 Addr Mode dst src r Irr No flags are affected. Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H 6-55 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LDCPD/LDEPD -- Load Memory with Pre-Decrement LDCPD/ LDEPD Operation: dst,src rr rr - 1 dst src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory. Flags: Format: Bytes opc src | dst 2 Cycles 14 Opcode (Hex) F2 Addr Mode dst src Irr r No flags are affected. Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H: LDCPD @RR6,R0 ; ; ; ; ; ; ; ; (RR6 RR6 - 1) 77H (contents of R0) is loaded into program memory location 2FFFH (3000H - 1H) R0 = 77H, R6 = 2FH, R7 = 0FFH (RR6 RR6 - 1) 77H (contents of R0) is loaded into external data memory location 2FFFH (3000H - 1H) R0 = 77H, R6 = 2FH, R7 = 0FFH LDEPD @RR6,R0 6-56 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET LDCPI/LDEPI -- Load Memory with Pre-Increment LDCPI/ LDEPI Operation: dst,src rr rr + 1 dst src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc src | dst 2 Cycles 14 Opcode (Hex) F3 Addr Mode dst src Irr r No flags are affected. Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; ; ; ; ; ; ; ; (RR6 RR6 + 1) 7FH (contents of R0) is loaded into program memory location 2200H (21FFH + 1H) R0 = 7FH, R6 = 22H, R7 = 00H (RR6 RR6 + 1) 7FH (contents of R0) is loaded into external data memory location 2200H (21FFH + 1H) R0 = 7FH, R6 = 22H, R7 = 00H LDEPI @RR6,R0 6-57 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LDW -- Load Word LDW Operation: dst,src dst src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: Format: Bytes opc src dst 3 Cycles 8 8 Opcode (Hex) C4 C5 Addr Mode dst src RR RR RR IR No flags are affected. opc dst src 4 8 C6 RR IML Examples: Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH: LDW LDW RR6,RR4 00H,02H R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH R2 = 03H, R3 = 0FH, Register 04H = 03H, register 05H = 0FH R6 = 12H, R7 = 34H Register 02H = 0FH, register 03H = 0EDH LDW LDW LDW LDW RR2,@R7 04H,@01H RR6,#1234H 02H,#0FEDH In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H. The other examples show how to use the LDW instruction with various addressing modes and formats. 6-58 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET MULT -- Multiply (Unsigned) MULT Operation: dst,src dst dst x src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if result is > 255; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if MSB of the result is a "1"; cleared otherwise. Cleared. Unaffected. Unaffected. Format: Bytes opc src dst 3 Cycles 22 22 22 Opcode (Hex) 84 85 86 Addr Mode dst src RR RR RR R IR IM Examples: Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT MULT MULT 00H, 02H 00H, @01H 00H, #30H Register 00H = 01H, register 01H = 20H, register 02H = 09H Register 00H = 00H, register 01H = 0C0H Register 00H = 06H, register 01H = 00H In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit product, 0120H, is stored in the register pair 00H, 01H. 6-59 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com NEXT -- Next NEXT Operation: PC @ IP IP IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: Format: Bytes opc 1 Cycles 10 Opcode (Hex) 0F No flags are affected. Example: The following diagram shows one example of how to use the NEXT instruction. Before Address IP 0043 Address PC 0120 43 44 45 Address H Address L Address H Data 01 10 PC 0130 Data Address IP 0045 After Data Address 43 44 45 Address H Address L Address H Data 120 Next Memory 130 Routine Memory 6-60 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET NOP -- No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time. 6-61 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com OR -- Logical OR OR Operation: dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 42 43 Addr Mode dst src r r r lr opc src dst 3 6 6 44 45 R R R IR opc dst src 3 6 46 R IM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats. 6-62 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET POP -- Pop From Stack POP Operation: dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR No flags affected. Examples: Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 00FCH Register 00H = 01H, register 01H = 55H, SP = 00FCH In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH. 6-63 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com POPUD -- Pop User Stack (Decrementing) POPUD Operation: dst,src dst src IR IR - 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: Format: Bytes opc src dst 3 Cycles 8 Opcode (Hex) 92 Addr Mode dst src R IR No flags are affected. Example: Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H Register 00H = 41H, register 02H = 6FH, register 42H = 6FH If general register 00H contains the value 42H and register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H. 6-64 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET POPUI -- Pop User Stack (Incrementing) POPUI Operation: dst,src dst src IR IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: Format: Bytes opc src dst 3 Cycles 8 Opcode (Hex) 93 Addr Mode dst src R IR No flags are affected. Example: Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H If general register 00H contains the value 01H and register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H. 6-65 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PUSH -- Push To Stack PUSH Operation: src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: Bytes opc src 2 Cycles 8 (internal clock) 8 (external clock) 8 (internal clock) 8 (external clock) 71 IR Opcode (Hex) 70 Addr Mode dst R No flags are affected. Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH 40H Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH PUSH @40H In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack. 6-66 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET PUSHUD -- Push User Stack (Decrementing) PUSHUD Operation: dst,src IR IR - 1 dst src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: Format: Bytes opc dst src 3 Cycles 8 Opcode (Hex) 82 Addr Mode dst src IR R No flags are affected. Example: Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer. 6-67 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PUSHUI -- Push User Stack (Incrementing) PUSHUI Operation: dst,src IR IR + 1 dst src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: Format: Bytes opc dst src 3 Cycles 8 Opcode (Hex) 83 Addr Mode dst src IR R No flags are affected. Example: Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer. 6-68 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET RCF -- Reset Carry Flag RCF Operation: RCF C0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. 6-69 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RET -- Return RET Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: Format: Bytes opc 1 Cycles 8 (internal stack) 10 (internal stack) Opcode (Hex) AF No flags are affected. Example: Given: SP = 00FCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 00FEH The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH. 6-70 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET RL -- Rotate Left RL Operation: dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0 -6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags. 6-71 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RLC -- Rotate Left Through Carry RLC Operation: dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0 -6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 C 0 Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 6-72 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET RR -- Rotate Right RR Operation: dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0 -6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 C 0 Flags: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. C: Z: S: V: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR Examples: Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1". 6-73 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RRC -- Rotate Right Through Carry RRC Operation: dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0 -6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 C 0 Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0". 6-74 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET SB0 -- Select Bank 0 SB0 Operation: BANK 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 4F No flags are affected. Example: The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing. 6-75 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SB1 -- Select Bank 1 SB1 Operation: BANK 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.) Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 5F No flags are affected. Example: The statement SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented. 6-76 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET SBC -- Subtract with Carry SBC Operation: dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 32 33 Addr Mode dst src r r r lr opc src dst 3 6 6 34 35 R R R IR opc dst src 3 6 36 R IM Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC 0AH SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = Register 01H = 95H; C, S, and V = "1" In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1. 6-77 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SCF -- Set Carry Flag SCF Operation: C 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF Example: The statement SCF sets the carry flag to logic one. 6-78 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET SRA -- Shift Right Arithmetic SRA Operation: dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0 -6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 C 6 0 Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H. 6-79 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SRP/SRP0/SRP1 -- Set Register Pointer SRP SRP0 SRP1 Operation: src src src If src (1) = 1 and src (0) = 0 then: If src (1) = 0 and src (0) = 1 then: If src (1) = 0 and src (0) = 0 then: RP0 (3-7) RP1 (3-7) RP0 (4-7) RP0 (3) RP1 (4-7) RP1 (3) src (3-7) src (3-7) src (4-7), 0 src (4-7), 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3-7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one. Flags: Format: Bytes opc src 2 Cycles 4 Opcode (Hex) 31 Addr Mode src IM No flags are affected. Examples: The statement SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H to 48H. The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H. 6-80 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET STOP -- Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 7F Addr Mode dst src - - No flags are affected. Example: The statement STOP NOP NOP NOP ; halts all microcontroller operations 6-81 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SUB -- Subtract SUB Operation: dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 22 23 Addr Mode dst src r r r lr opc src dst 3 6 6 24 25 R R R IR opc dst src 3 6 26 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0" In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1. 6-82 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET SWAP -- Swap Nibbles SWAP Operation: dst dst (0 - 3) dst (4 - 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 43 0 Flags: C: Z: S: V: D: H: Undefined. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) F0 F1 Addr Mode dst R IR Examples: Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H: SWAP SWAP 00H @02H Register 00H = 0E3H Register 02H = 03H, register 03H = 4AH In the first example, if general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B). 6-83 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TCM -- Test Complement Under Mask TCM Operation: dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 62 63 Addr Mode dst src r r r lr opc src dst 3 6 6 64 65 R R R IR opc dst src 3 6 66 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2 BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation. 6-84 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET TM -- Test Under Mask TM Operation: dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 72 73 Addr Mode dst src r r r lr opc src dst 3 6 6 74 75 R R R IR opc dst src 3 6 76 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation. 6-85 INSTRUCTION SET S3C8275/F8275/C8278/F8278/C8274/F8274 www..com WFI -- Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt. Flags: Format: Bytes opc 1 Cycles 4n Opcode (Hex) 3F No flags are affected. ( n = 1, 2, 3, ... ) Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement: Main program . . . EI WFI (Next instruction) (Enable global interrupt) (Wait for interrupt) . . . Interrupt occurs Interrupt service routine . . . Clear interrupt flag IRET Service routine completed 6-86 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com INSTRUCTION SET XOR -- Logical Exclusive OR XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) B2 B3 Addr Mode dst src r r r lr opc src dst 3 6 6 B4 B5 R R R IR opc dst src 3 6 B6 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0. 6-87 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLOCK CIRCUIT 7 OVERVIEW CLOCK CIRCUIT The S3C8275/C8278/C8274 microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3C8275/C8278/C8274 is determined by CLKCON register settings. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- External crystal, ceramic resonator, RC oscillation source, or an external clock source -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- System clock control register, CLKCON -- Oscillator control register, OSCCON and STOP control register, STPCON -- Clock output control register, CLOCON CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock; fx: main clock fxt: sub clock fxx: selected system clock 7-1 CLOCK CIRCUIT S3C8275/F8275/C8278/F8278/C8274/F8274 www..com MAIN OSCILLATOR CIRCUITS SUB OSCILLATOR CIRCUITS 32.768 kHz XIN XTIN XOUT XTOUT Figure 7-1. Crystal/Ceramic Oscillator (fx) Figure 7-4. Crystal Oscillator (fxt, Normal) 32.768 kHz XTIN XIN XTOUT XOUT 104 VREG Figure 7-2. External Oscillator (fx) Figure 7-5. Crystal Oscillator (fxt, for Low Current) XIN R XOUT XTIN XTOUT Figure 7-3. RC Oscillator (fx) Figure 7-6. External Oscillator (fxt) 7-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLOCK CIRCUIT CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter). -- In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters. Idle mode is released by a reset or by an external or internal interrupt. Stop Release INT Main-System Oscillator Circuit fx fxt Sub-system Oscillator Circuit Watch Timer LCD Controller Selector 1 fXX Stop OSCCON.3 OSCCON.0 STOP OSC inst. STPCON 1/1-1/4096 Basic Timer Timer/Counters Frequency Dividing Circuit Watch Timer LCD Controller SIO BLD 1/1 1/2 1/8 1/16 System Clock CLKCON.4-.3 Selector 2 CPU Clock Stop OSCCON.2 IDLE Instruction Figure 7-7. System Clock Circuit Diagram 7-3 CLOCK CIRCUIT S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the set 1, at address D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake up function enable/disable -- Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a stop mode release (This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7. After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fxx/8, fxx/2, or fxx/1. System Clock Control Register (CLKCON) D4H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Oscillator IRQ wake-up function bit: 0 = Enable IRQ for main wake up in power down mode 1 = Disable IRQ for main wake up in power down mode Not used for S3C8275/C8278/C8274 (must keep always 0) Not used for S3C8275/C8278/C8274 (must keep always 0) Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fxx/2 11 = fxx/1 (non-divided) Figure 7-8. System Clock Control Register (CLKCON) 7-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLOCK CIRCUIT CLOCK OUTPUT CONTROL REGISTER (CLOCON) The clock output control register, CLOCON, is located in set 1 bank 1, at address E8H. It is read/write addressable and has the following functions: -- Clock output frequency selection After a reset, fxx/64 is select for clock output frequency because the reset value of CLOCON.1-.0 is "00b". Clock Output Control Register (CLOCON) E8H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used for S3C8275/C8278/C8274 (must keep always "0") Clock output frequency selection bits: 00 = Select fxx/64 01 = Select fxx/16 10 = Select fxx/8 11 = Select fxx/4 Figure 7-9. Clock Output Control Register (CLOCON) CLOCON.1-.0 fxx/64 fxx/16 fxx/8 fxx/4 MUX P0CONH.5-.4 CLKOUT/P0.6 Figure 7-10. Clock Output Block Diagram 7-5 CLOCK CIRCUIT S3C8275/F8275/C8278/F8278/C8274/F8274 www..com OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in set 1, bank 0, at address E0H. It is read/write addressable and has the following functions: -- System clock selection -- Main oscillator control -- Sub oscillator control -- Sub oscillator circuit selection OSCCON.0 register settings select Main clock or Sub clock as system clock. After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3. The sub oscillator can be stopped or run by setting OSCCON.2. Oscillator Control Register (OSCCON) E0H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used for S3C8275/ C8278/C8274 Sub oscillator circuit selection bit: 0 = Select normal circuit for sub oscillator 1 = Select power saving circuit for sub oscillator (Automatically cleared to "0" when the sub oscillator is stopped by OSCCON.2 or the CPU is entered into stop mode in sub operation mode) System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select Not used for S3C8275/C8278/C8274 Sub oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP Main oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP NOTE: A capacitor (0.1uF) should be connected between VREG and GND when the sub-oscillator is used to power saving mode (OSCCON.7="1") Figure 7-11. Oscillator Control Register (OSCCON) 7-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com CLOCK CIRCUIT SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON.3 start or stop main clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4-.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, 16. For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set CLKCON.4-.3 to "11", OSCCON.0 to "1", and OSCCON.3 to "1" simultaneously. This switches the clock from fx to fxt and stops main clock oscillation. The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to enable main clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock by setting OSCCON.0 to "0". F PROGRAMMING TIP -- Switching the CPU clock 1. This example shows how to change from the main clock to the sub clock: MA2SUB LD OSCCON,#01H ; Switches to the sub clock ; Stop the main clock oscillation RET 2. This example shows how to change from sub clock to main clock: SUB2MA AND CALL AND RET SRP LD NOP DJNZ RET OSCCON,#07H DLY16 OSCCON,#06H #0C0H R0,#20H R0,DEL ; Start the main clock oscillation ; Delay 16 ms ; Switch to the main clock DLY16 DEL 7-7 CLOCK CIRCUIT S3C8275/F8275/C8278/F8278/C8274/F8274 www..com STOP Control Register (STPCON) FBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB STOP control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction NOTE: Before execute the STOP instruction, set this STPCON register as "10100101B". Otherwise the STOP instuction will not execute as well as reset will be generated. Figure 7-12. STOP Control Register (STPCON) 7-8 S3C8275/F8275/C8278/F8278/C8274/F8274 RESET and POWER-DOWN www..com 8 OVERVIEW RESET and POWER-DOWN SYSTEM RESET During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3C8275/C8278/C8274 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required time of a reset operation for oscillation stabilization is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values In summary, the following sequence of events occurs during a reset operation: -- All interrupt is disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0-6 are set to input mode, and all pull-up resistors are disabled for the I/O port. -- Peripheral control and data register settings are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed at normal mode by smart option. -- The reset address at ROM can be changed by Smart Option only in the S3F8275 (full-flash device). Refer to "The chapter 16. Embedded Flash Memory Interface" for more detail contents. NORMAL MODE RESET OPERATION In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 16/8/4-Kbyte on-chip ROM (The external interface is not automatically configured). NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON. 8-1 RESET and POWER-DOWN S3C8275/F8275/C8278/F8278/C8274/F8274 www..com HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined after a reset. -- A dash ("-") means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1. S3C8275/C8278/C8274 Set 1 Register and Values After RESET Register Name Mnemonic Address Dec Hex 7 6 Bit Values After RESET 5 4 3 2 1 0 Locations D0H - D2H are not mapped. Basic timer control register System clock control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP 211 212 213 214 215 216 217 218 219 220 221 222 223 D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH 0 0 x 1 1 x x x x 0 x 0 0 0 - x 1 1 x x x x 0 x - 0 0 - x 0 0 x x x x 0 x - 0 0 0 x 0 0 x x x x 0 x x 0 0 0 x 0 1 x x x x 0 x x 0 0 - x - - x x x x 0 x x 0 0 - 0 - - x x x x 0 x 0 0 0 - 0 - - x x x x 0 x 0 0 8-2 S3C8275/F8275/C8278/F8278/C8274/F8274 RESET and POWER-DOWN www..com Table 8-2. S3C8275/C8278/C8274 Set 1, Bank 0 Register Values After RESET Register Name Mnemonic Address Dec Oscillator control register SIO control register SIO data register SIO pre-scaler register Port 0 control register (high byte) Port 0 control register (low byte) Port 0 pull-up resistor enable register Port 1 control register (high byte) Port 1 control register (low byte) Port 1 pull-up resistor enable register Port 2 control register (high byte) Port 2 control register (low byte) Port 2 pull-up resistor enable register Port 3 control register (high byte) Port 3 control register (low byte) Port 3 pull-up resistor enable register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register External interrupt pending register External interrupt control register (high byte) External interrupt control register (low byte) OSCCON SIOCON SIODATA SIOPS P0CONH P0CONL P0PUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P0 P1 P2 P3 P4 P5 P6 EXTIPND EXTICONH EXTICONL 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 Bit Values After RESET 6 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 5 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 4 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Location FAH is not mapped. STOP control register STPCON 251 FBH 0 0 0 0 0 0 0 0 Location FCH is not mapped. Basic timer counter BTCNT 253 FDH 0 0 0 0 0 0 0 0 Location FEH is not mapped. Interrupt priority register IPR 255 FFH x x x x x x x x 8-3 RESET and POWER-DOWN S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 8-3. S3C8275/C8278/C8274 Set 1, Bank 1 Register Values After RESET Register Name Mnemonic Address Dec LCD control register Watch timer control register Timer A counter Timer B counter Timer A data register Timer B data register Timer 1/A control register Timer B control register Clock output control register Port 4 control register (high byte) Port 4 control register (low byte) Port 5 control register (high byte) Port 5 control register (low byte) Port 6 control register LCON WTCON TACNT TBCNT TADATA TBDATA TACON TBCON CLOCON P4CONH P4CONL P5CONH P5CONL P6CON 224 225 226 227 228 229 230 231 232 233 234 235 236 237 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH 7 0 0 0 0 1 1 0 - - 0 0 0 0 0 Bit Values After RESET 6 0 0 0 0 1 1 0 0 - 0 0 0 0 0 5 0 0 0 0 1 1 0 0 - 0 0 0 0 0 4 0 0 0 0 1 1 0 0 - 0 0 0 0 0 3 0 0 0 0 1 1 0 0 - 0 0 0 0 0 2 0 0 0 0 1 1 0 0 - 0 0 0 0 0 1 - 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Locations EEH - EFH are not mapped. Flash memory control register Flash memory user programming enable register Flash memory sector address register (high byte) Flash memory sector address register (low byte) Battery level detector control register FMCON FMUSR FMSECH FMSECL BLDCON 240 241 242 243 244 F0H F1H F2H F3H F4H 0 0 0 0 - 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 - 0 0 0 0 0 0 0 0 0 Locations F5H - FFH are not mapped. 8-4 S3C8275/F8275/C8278/F8278/C8274/F8274 RESET and POWER-DOWN www..com POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 A. All system functions stop when the clock "freezes", but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-7. NOTE Do not use stop mode if you are using an external clock source because XIN or XTIN input must be restricted internally to VSS to reduce current leakage. Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to `00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H) Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. The external interrupts in the S3C8275/C8278/C8274 interrupt structure that can be used to release Stop mode are: -- External interrupts P0.0-P0.2 (INT0-INT2) and P1.3-P1.7 (INT3-INT7) Please note the following conditions for Stop mode release: -- If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except STPCON register. -- If you use an internal or external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. -- When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. -- The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. How to Enter into Stop Mode Handling STPCON register then writing Stop instruction (keep the order). LD STOP NOP NOP NOP STPCON, #10100101B 8-5 RESET and POWER-DOWN S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to `00B'. If interrupts are masked, a reset is the only way to release idle mode. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed. 2. 8-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS 9 OVERVIEW I/O PORTS The S3C8275/C8278/C8274 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0-port 5 are 8-bit ports, port 6 is 4-bit. This gives a total of 52 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C8275/C8278/C8274 can be configured to input or output mode. P2-P6 are shared with LCD signals. Table 9-1 gives you a general overview of S3C8275/C8278/C8274 I/O port functions. Table 9-1. S3C8275/C8278/C8274 Port Configuration Overview Port 0 Configuration Options 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P0.0-P0.2 can be used as input for external interrupts INT and P0.3-P0.7 can be used as T1CLK, TAOUT, TBOUT, CLKOUT, and BUZ. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P1.3-P1.7 can be used as input for external interrupts INT and P1.0-P1.2 can be used as SCK, SO, and SI. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P2 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P3 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull output and software assignable pull-ups. Alternatively P4 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull output and software assignable pull-ups. Alternatively P5 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull output and software assignable pull-ups. Alternately P6.0-P6.3 can be used as outputs for LCD common signals. 1 2 3 4 5 6 9-1 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C8275/C8278/C8274 I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Mnemonic P0 P1 P2 P3 P4 P5 P6 Decimal 240 241 242 243 244 245 246 Hex F0H F1H F2H F3H F4H F5H F6H Location Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 R/W R/W R/W R/W R/W R/W R/W R/W S3C8275/C8278/C8274 I/O Port Data Register Format (n = 0-6) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0 Figure 9-1. S3C8275/C8278/C8274 I/O Port Data Register Format 9-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in set 1, bank 0. P0.0-P0.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P0.0-P0.3): INT0-INT2, T1CLK -- High-nibble pins (P0.4-P0.7): TAOUT, TBOUT, CLKOUT, BUZ Port 0 Control Registers (P0CONH, P0CONL) Port 0 has two 8-bit control registers: P0CONH for P0.4-P0.7 and P0CONL for P0.0-P0.3. A reset clears the P0CONH and P0CONL registers to "00H", configuring P0.0-P0.2 pins to input mode with interrupt and P0.3-P0.7 pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 0 control registers must also be enabled in the associated peripheral module. Port 0 Pull-up Resistor Control Register (P0PUR) Using the port 0 pull-up resistor control register, P0PUR (E6H, set 1, bank 0) you can configure pull-up resistors to individual port 0 pins. Port 0 Interrupt Control Registers (EXTICONL.5-.0, EXTIPND.2-.0) To process external interrupts at the port 0 pins, two additional control registers are provided: the external interrupt control register EXTICONL.5-.0 (F9H, set 1, bank 0) and the external interrupt pending register EXTIPND.2-.0 (F7H, set 1, bank 0) The external interrupt pending register EXTIPND.2-.0 lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the EXTIPND.2-.0 register at regular intervals. When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding pending bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding EXTIPND bit. 9-3 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 0 Control Register, High Byte (P0CONH) E4H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P0.7/BUZ P0.6/CLKOUT P0.5/TBOUT P0.4/TAOUT P0CONH bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Alternative function (BUZ, CLKOUT, TBOUT, TAOUT) Figure 9-2. Port 0 High-Byte Control Register (P0CONH) Port 0 Control Register, Low Byte (P0CONL) E5H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P0.3/T1CLK P0.2/INT2 P0.1/INT1 P0.0/INT0 P0CONL bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (T1CLK) N-channel open-drain output mode Push-pull output mode Not available Figure 9-3. Port 0 Low-Byte Control Register (P0CONL) 9-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS Port 0 Pull-up Control Register (P0PUR) E6H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P0PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 0 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-4. Port 0 Pull-up Control Register (P0PUR) External Interrupt Control Register, Low Byte (EXTICONL) E9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 EXTICONL bit configuration settings: 00 01 10 11 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL) 9-5 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com External Interrupt Pending Register (EXTIPND) F7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7 P1.6 P1.5 P1.4 P1.3 P0.2 P0.1 P0.0 (INT7) (INT6) (INT5) (INT4) (INT3) (INT2) (INT1) (INT0) EXTIPND bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-6. External Interrupt Pending Register (EXTIPND) 9-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 0. P1.0-P1.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P1.0-P1.3): SCK, SO, SI, INT3 -- High-nibble pins (P1.4-P1.7): INT4-INT7 Port 1 Control Registers (P1CONH, P1CONL) Port 1 has two 8-bit control registers: P1CONH for P1.4-P1.7 and P1CONL for P1.0-P1.3. A reset clears the P1CONH and P1CONL registers to "00H", configuring P1.3-P1.7 pins to input mode with interrupt and P1.0-P1.2 pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 1 control registers must also be enabled in the associated peripheral module. Port 1 Pull-up Resistor Control Register (P1PUR) Using the port 1 pull-up resistor control register, P1PUR (E9H, set 1, bank 0), you can configure pull-up resistors to individual port 1 pins. Port 1 Interrupt Control Registers (EXTICONH, EXTICONL.7-.6, EXTIPND.7-.3) To process external interrupts at the port 1 pins, three additional control registers are provided: the external interrupt control registers EXTICONH/EXTICONL.7-.6 (F8H/F9H, set 1, bank 0) and the external interrupt pending register EXTIPND.7-.3 (F7H, set 1, bank 0). The external interrupt pending register EXTIPND.7-.3 lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the EXTIPND.7-.3 register at regular intervals. When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding pending bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding EXTIPND bit. 9-7 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 1 Control Register, High Byte (P1CONH) E7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7/INT7 P1.6/INT6 P1.5/INT5 P1.4/INT4 P1CONH bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode N-channel open-drain output mode Push-pull output mode Not available Figure 9-7. Port 1 High-Byte Control Register (P1CONH) Port 1 Control Register, Low Byte (P1CONL) E8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3/INT3 P1.2/SI P1.1/SO P1.0/SCK P1CONL bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (SI, SCK) N-channel open-drain output mode Push-pull output mode Alternative function (SCK, SO) Figure 9-8. Port 1 Low-Byte Control Register (P1CONL) 9-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS Port 1 Pull-up Control Register (P1PUR) E9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P1PUR bit configuration settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor A pull-up resistor of port 1 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-9. Port 1 Pull-up Control Register (P1PUR) External Interrupt Control Register, High Byte (EXTICONH) F8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7/INT7 P1.6/INT6 P1.5/INT5 P1.4/INT4 EXTICONH bit configuration settings: 00 01 10 11 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9-10. External Interrupt Control Register, High Byte (EXTICONH) 9-9 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com External Interrupt Control Register, Low Byte (EXTICONL) F9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 EXTICONL bit configuration settings: 00 01 10 11 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL) External Interrupt Pending Register (EXTIPND) F7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7 P1.6 P1.5 P1.4 P1.3 P0.2 P0.1 P0.0 (INT7) (INT6) (INT5) (INT4) (INT3) (INT2) (INT1) (INT0) EXTIPND bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-12. External Interrupt Pending Register (EXTIPND) 9-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, Bank 0. P2.0-P2.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P2.0-P2.3): SEG31-SEG28, VBLDREF -- High-nibble pins (P2.4-P2.7): SEG27-SEG24 Port 2 Control Registers (P2CONH, P2CONL) Port 2 has two 8-bit control registers: P2CONH for P2.4-P2.7 and P2CONL for P2.0-P2.3. A reset clears the P2CONH and P2CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 2 control registers must also be enabled in the associated peripheral module. Port 2 Pull-up Resistor Control Register (P2PUR) Using the port 2 pull-up resistor control register, P2PUR (ECH, set 1, bank 0), you can configure pull-up resistors to individual port 2 pins. Port 2 Control Register, High Byte (P2CONH) EAH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.7/SEG24 P2.6/SEG25 P2.5/SEG26 P2.4/SEG27 P2CONH bit-pair pin configuration settings: 00 01 10 11 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG24-SEG27) Figure 9-13. Port 2 High-byte Control Register (P2CONH) 9-11 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 2 Control Register, Low Byte (P2CONL) EBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.3/SEG28 P2.2/SEG29 P2.1/SEG30 P2CONL bit-pair pin configuration settings: 00 01 10 11 Input mode N-channel open-drain output mode Push-pull output mode P2.0/SEG31/VBLDREF Alternative function (SEG28-SEG31/VBLDREF) Figure 9-14. Port 2 Low-byte Control Register (P2CONL) Port 2 Pull-up Control Register (P2PUR) ECH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P2PUR bit configuration settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-15. Port 2 Pull-up Control Register (P2PUR) 9-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 0. P3.0-P3.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P3.0-P3.3): SEG23-SEG20 -- High-nibble pins (P3.4-P3.7): SEG19-SEG16 Port 3 Control Registers (P3CONH, P3CONL) Port 3 has two 8-bit control registers: P3CONH for P3.4-P3.7 and P3CONL for P3.0-P3.3. A reset clears the P3CONH and P3CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 3 control registers must also be enabled in the associated peripheral module. Port 3 Pull-up Resistor Control Register (P3PUR) Using the port 3 pull-up resistor control register, P3PUR (EFH, set 1, bank 0), you can configure pull-up resistors to individually port 3 pins. Port 3 Control Register, High Byte (P3CONH) EDH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.7/SEG16 P3.6/SEG17 P3.5/SEG18 P3.4/SEG19 P3CONH bit-pair pin configuration settings: 00 01 10 11 Input mode N-channel open-drain output mode Push-pull output mode Alternative fumction (SEG16-SEG19) Figure 9-16. Port 3 High Byte Control Register (P3CONH) 9-13 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 3 Control Register, Low Byte (P3CONL) EEH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.3/SEG20 P3.2/SEG21 P3.1/SEG22 P3.0/SEG23 P3CONL bit-pair pin configuration settings: 00 01 10 11 Input mode N-channel open-drain output mode Push-pull output mode Alternative function (SEG20-SEG23) Figure 9-17. Port 3 Low Byte Control Register (P3CONL) Port 3 Pull-up Control Register (P3PUR) EFH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P3PUR bit configuration settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor A pull-up resistor of port 3 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-18. Port 3 Pull-up Control Register (P3PUR) 9-14 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location F4H in set 1, bank 0. P4.0-P4.7 can serve as inputs (with or without pull-up), as push-pull output or you can be configured the following functions. -- Low-nibble pins (P4.0-P4.3): SEG15-SEG12 -- High-nibble pins (P4.4-P4.7): SEG11-SEG8 Port 4 Control Registers (P4CONH, P4CONL) Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input (with or without pull-up) or push-pull output mode and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 4 control registers must also be enabled in the associated peripheral module. Port 4 Control Register, High Byte (P4CONH) E9H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P4.7/SEG8 P4.6/SEG9 P4.5/SEG10 P4.4/SEG11 P4CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG8-SEG11) Figure 9-19. Port 4 High-Byte Control Register (P4CONH) 9-15 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 4 Control Register, Low Byte (P4CONL) EAH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P4.3/SEG12 P4.2/SEG13 P4.1/SEG14 P4.0/SEG15 P4CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG12-SEG15) Figure 9-20. Port 4 Low-Byte Control Register (P4CONL) 9-16 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location F5H in set 1, bank 0. P5.0-P5.7 can serve as inputs (with or without pull-up), as push-pull output or you can be configured the following functions. -- Low-nibble pins (P5.0-P5.3): SEG7-SEG4 -- High-nibble pins (P5.4-P5.7): SEG3-SEG0 Port 5 Control Registers (P5CONH, P5CONL) Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P5CONL for P5.0-P5.3. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input (with or without pull-up) or push-pull output mode and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 5 control registers must also be enabled in the associated peripheral module. Port 5 Control Register, High Byte (P5CONH) EBH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.7/SEG0 P5.6/SEG1 P5.5/SEG2 P5.4/SEG3 P5CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG0-SEG3) Figure 9-21. Port 5 High-Byte Control Register (P5CONH) 9-17 I/O PORTS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Port 5 Control Register, Low Byte (P5CONL) ECH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.3/SEG4 P5.2/SEG5 P5.1/SEG6 P5.0/SEG7 P5CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Input with pull-up resistor Push-pull output mode Alternative function (SEG4-SEG7) Figure 9-22. Port 5 Low-Byte Control Register (P5CONL) 9-18 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com I/O PORTS PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location F6H in set 1, bank 0. P6.0-P6.3 can serve as inputs (with or without pull-up), as push-pull output or you can be configured the following functions. -- Low-nibble pins (P6.0-P6.3): COM0-COM3 Port 6 Control Register (P6CON) Port 6 has an 8-bit control register: P6CON for P6.0-P6.3. A reset clears the P6CON register to "00H", configuring all pins to input mode. You use control register setting to select input (with or without pull-up) or push-pull output mode and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 6 control register must also be enabled in the associated peripheral module. Port 6 Control Register (P6CON) EDH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P6.3/COM3 P6.2/COM2 P6.1/COM1 P6.0/COM0 P6CON bit-pair pin configuration settings: 00 01 10 11 Input mode Input with pull-up resistor Push-pull output mode Alternative function (COM3-COM0) Figure 9-23. Port 6 Control Register (P6CON) 9-19 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BASIC TIMER 10 OVERVIEW BASIC TIMER Basic timer (BT) can be used in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer -- 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only) -- Basic timer control register, BTCON (set 1, D3H, read/write) 10-1 BASIC TIMER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for all timers input clock, you write a "1" to BTCON.0. Basic Timer Control Register (BTCON) D3H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Watchdog function enable bits: 1010B = Disable watchdog timer Other values = Enable watchdog timer Divider clear bit for all timers: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT Basic timer input clock selection bits: 00 = fXX/4096 01 = fXX/1024 10 = fXX/128 11 = fXX/16 Figure 10-1. Basic Timer Control Register (BTCON) 10-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. 2. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. When a BTCNT.3 overflow occurs, normal CPU operation resumes. 3. 4. 10-3 BASIC TIMER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RESET or STOP Bit 1 Bits 3, 2 Data Bus fXX/4096 fXX/1024 fXX DIV fXX/128 fXX/16 u Start the CPU (note) MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF RESET Clear Basic Timer Control Register (Write '1010xxxxB' to Disable) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2. Basic Timer Block Diagram 10-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TIMER 1 11 OVERVIEW TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. -- One 16-bit timer mode (Timer 1) -- Two 8-bit timers mode (Timer A and B) The 16-bit timer 1 is a 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting. Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer -- 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA) -- Timer 1 match interrupt (IRQ 0, vector F0H) generation -- Timer 1 control register, TACON (set 1, bank 1, E6H, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to the interrupt level IRQ 0, and is assigned a separate vector address, F0H. The T1INT pending condition should be cleared by software after IRQ 0 is serviced. The T1INT pending bit must be cleared by the application sub-routine by writing a "0" to the TACON.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and clears the counter. If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes. 11-1 TIMER 1 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to -- Enable the timer 1 operating (interval timer) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, TACNT and TBCNT -- Enable the timer 1 interrupt -- Clear timer 1 interrupt pending conditions TACON is located in set 1, bank 1, at address E6H, and is read/write addressable using Register addressing mode. A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal operation by writing a "1" to TACON.3. To enable the timer 1 interrupt (IRQ 0, vector F0H), you must write TACON.7, TACON.2, and TACON.1 to "1". To generate the exact time interval, you should write TACON.3 and TACON.0 to "10B", which cleared counter and interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, TACON.0. Timer 1/A Control Register (TACON) E6H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 1 operating mode selection bit: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer 1 interrupt pending bit: 0 = No interrupt pending (when read) Clear pending bit (when write) 1 = Interrupt is pending (when read) No effect (when write) Timer 1 interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 1 counter operating enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer 1 counter clear bit: 0 = No affect 1 = Clear the timer 1 counter (when write) Timer 1 clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available Figure 11-1. Timer 1/A Control Register (TACON) 11-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TIMER 1 BTCON.0 TACON.6-.4 R 1/512 1/256 TACON.2 Data Bus M U X 16-Bit Comparator LSB MSB TBDATA TADATA Buffer Buffer LSB TBCNT TACON.3 MSB TACNT R Match TACON.0 TAOUT T1INT Clear TACON.1 fxx (XIN or XTIN) DIV 1/64 1/8 1/1 fxt T1CLK Match Signal T1CLR TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode) 11-3 TIMER 1 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: -- Clock frequency divider with multiplexer - fxx divided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A - fxx divided by 512, 256, 64 or 8 and fxt for timer B -- 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA) -- Timer A have I/O pin for match output (TAOUT) -- Timer A match interrupt (IRQ 0, vector F0H) generation -- Timer A control register, TACON (set 1, bank 1, E6H, read/write) -- Timer B have I/O pin for match output (TBOUT) -- Timer B match interrupt (IRQ 0, vector F2H) generation -- Timer B control register, TBCON (set 1, bank 1, E7H, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). TAINT belongs to the interrupt level IRQ 0, and is assigned a separate vector address, F0H. TBINT belongs to the interrupt level IRQ 0 and is assigned a separate vector address, F2H. The TAINT and TBINT pending condition should be cleared by software after they are serviced. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the TA or TB reference data registers, TADATA and TBDATA. The match signal generates corresponding match interrupt (TAINT, vector F0H; TBINT, vector F2H) and clears the counter. If, for example, you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and counting resumes. Timer A and B Control Register (TACON, TBCON) You use the timer A and B control register, TACON and TBCON, to -- Enable the timer A (interval timer mode) and B operating (interval timer mode) -- Select the timer A and B input clock frequency -- Clear the timer A and B counter, TACNT and TBCNT -- Enable the timer A and B interrupts -- Clear timer A and B interrupt pending conditions 11-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TIMER 1 TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write addressable using Register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer B interrupt. You can clear the timer B counter at any time during normal operation by writing a "1" to TBCON.3. To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2 (TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3 (TBCON.3) and TACON.0 (TBCON.0), which cleared counter and interrupt pending bit. When the TAINT and TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A and B interrupt pending bits, TACON.0 or TBCON.0. Timer 1/A Control Register (TACON) E6H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer A operating mode selection bit: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer A interrupt pending bit: 0 = No interrupt pending (when read) Clear pending bit (when write) 1 = Interrupt is pending (when read) No effect (when write) Timer A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer A counter operating enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer A counter clear bit: 0 = No affect 1 = Clear the timer A counter (when write) Timer A clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available Figure 11-3. Timer 1/A Control Register (TACON) 11-5 TIMER 1 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Timer B Control Register (TBCON) E7H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used for S3C8275/C8278/C8274 Timer B interrupt pending bit: 0 = No interrupt pending (when read) Clear pending bit (when write) 1 = Interrupt is pending (when read) No effect (when write) Timer B interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer B counter operating enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer B counter clear bit: 0 = No affect 1 = Clear the timer B counter (when write) Timer B clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxt (sub clock) Others = Not available Figure 11-4. Timer B Control Register (TBCON) 11-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com TIMER 1 BTCON.0 TACON.6-.4 R 1/512 1/256 TACON.2 Data Bus M U X 8-Bit Comparator LSB MSB LSB TACON.3 MSB Clear TACON.1 Match TACON.0 TAOUT TAINT fxx (XIN or XTIN) DIV 1/64 1/8 1/1 TACNT (8-Bit Up-Counter) R fxt T1CLK TADATA Buffer Match Signal TACLR TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5. Timer A Block Diagram (Two 8-bit Timers Mode) 11-7 TIMER 1 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BTCON.0 TBCON.6-.4 R 1/512 1/256 Data Bus M U X TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R Clear TBCON.1 Match 8-Bit Comparator LSB MSB TBCON.0 TBOUT TBINT TBCON.3 fxx (XIN or XTIN) DIV 1/64 1/8 fxt TBDATA Buffer Match Signal TBCLR TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode) 11-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com WATCH TIMER 12 OVERVIEW WATCH TIMER Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt (IRQ 2, vector F6H), then set the WTCON.6 to "1". The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 - .2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. Also, you can select watch timer clock source by setting the WTCON.7 appropriately value. The watch timer supplies the clock frequency for the LCD controller (fLCD ). Therefore, if the watch timer is disabled, the LCD controller does not operate. Watch timer has the following functional components: -- Real Time and Watch-Time Measurement -- Using a Main or Sub Clock Source (Main clock divided by 27(fx/128) or Sub clock(fxt)) -- Clock Source Generation for LCD Controller (fLCD ) -- I/O pin for Buzzer Output Frequency Generator (P0.7, BUZ) -- Timing Tests in High-Speed Mode -- Watch timer overflow interrupt (IRQ 2, vector F6H) generation -- Watch timer control register, WTCON (set 1, bank 1, E1H, read/write) 12-1 WATCH TIMER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in set 1, bank 1 at address E1H, and is read/write addressable using Register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock. So, if you want to use the watch timer, you must write appropriate value to WTCON. Watch Timer Control Register (WTCON) E1H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Watch timer clock selection bit: 0 = Select main clock divided by 27 (fx/128) 1 = Select sub clock (fxt) Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT Buzzer signal selection bits: 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz Watch timer interrupt pending bit: 0 = Interrupt request is not pending (Clear pending bit when write"0") 1 = Interrupt request is pending Watch timer Enable/Disable bit: 0 = Disable watch timer; clear frequency dividing circuits 1 = Enable watch timer Watch timer speed selection bits: 00 = Set watch timer interrupt to 1 s 01 = Set watch timer interrupt to 0.5 s 10 = Set watch timer interrupt to 0.25 s 11 = Set watch timer interrupt to 3.91 ms Figure 12-1. Watch Timer Control Register (WTCON) 12-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com WATCH TIMER WATCH TIMER CIRCUIT DIASGRAM WTCON.7 WTCON.6 WTCON.5 8 WTCON.4 WTCON.3 WTCON.2 WTCON.1 (Pending Bit) WT INT Enable WTCON.6 MUX fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit BUZ (P0.7) WTINT WTCON.0 WTCON.0 Clock Selector fW 32.768 kHz Frequency Dividing Circuit fW/2 7 fW/2 13 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz fxt fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32.768 kHz) fW = Watch timer frequency Figure 12-2. Watch Timer Circuit Diagram 12-3 S3C8275/F8275/C8278/F8278/C8274/F8274 LCD CONTROLLER/DRIVER www..com 13 OVERVIEW -- LCD controller/driver LCD CONTROLLER/DRIVER The S3C8275/C8278/C8274 microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its LCD block has the following components: -- Display RAM (00H-0FH of page 2) for storing display data -- 32 segment output pins (SEG0-SEG31) -- 4 common output pins (COM0-COM3) -- Three LCD operating power supply pins (V LC0-VLC2) -- LCD bias by Internal/External register The LCD control register, LCON, is used to turn the LCD display on or off, to select LCD clock frequency, to select bias and duty, and switch the current to the dividing resistor for the LCD display. Data written to the LCD display RAM can be automatically transferred to the segment signal pins without program control. When a sub clock is selected as the LCD clock source, the LCD display is enabled even in main clock stop or idle mode. VLC0-VLC2 Data BUS 3 LCD Controller/ Driver COM0-COM3 4 SEG0-SEG31 32 8 Figure 13-1. LCD Function Diagram 13-1 LCD CONTROLLER/DRIVER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LCD CIRCUIT DIAGRAM Port Latch SEG31/P2.0 SEG/Port Driver SEG16/P3.7 SEG15/P4.0 SEG0/P5.7 Data BUS LCD Display RAM (200H-20FH) fLCD COM/Port Driver COM3/P6.3 COM2/P6.2 COM0/P6.0 Timing Controller LCON LCD Voltage Controller VLC0 VLC1 VLC2 Figure 13-2. LCD Circuit Diagram 13-2 S3C8275/F8275/C8278/F8278/C8274/F8274 LCD CONTROLLER/DRIVER www..com LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG31 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use. COM0 b0 b4 COM1 b1 b5 COM2 b2 b6 COM3 b3 b7 200H b0 b4 b1 b5 b2 b6 b3 b7 201H b0 b4 b1 b5 b2 b6 b3 b7 202H b0 b4 b1 b5 b2 b6 b3 b7 203H b0 b4 b1 b5 b2 b6 b3 b7 204H b0 b4 b1 b5 b2 b6 b3 b7 20DH Figure 13-3. LCD Display Data RAM Organization Table 13-1. LCD Clock Signal Frame Frequency LCDCK Frequency (fLCD) 64 Hz 128 Hz 256Hz 512 Hz Static 64 128 256 512 1/2 Duty 32 64 128 256 1/3 Duty 21 43 85 171 1/4 Duty 16 32 64 128 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 b0 b4 b0 b4 b1 b5 b1 b5 b2 b6 b2 b6 b3 b7 b3 b7 20EH 20FH SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 13-3 LCD CONTROLLER/DRIVER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com LCD CONTROL REGISTER (LCON) A LCON is located in set 1, bank 1, at address E0H, and is read/write addressable using Register addressing mode. It has the following control functions. -- LCD duty and bias selection -- LCD clock selection -- LCD display control -- Internal/External LCD dividing resistors selection The LCON register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock and control the flow of the current to the dividing in the LCD circuit. Following a RESET, all LCON values are cleared to "0". This turns off the LCD display, select 1/4 duty and 1/3 bias, select 64Hz for LCD clock, and Enable internal LCD dividing resistors. The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer should be enabled when the LCD display is turned on. LCD Control Register (LCON) E0H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Internal LCD dividing register enable bit: 0 = Enable internal LCD dividing resistors 1 = Disable internal LCD dividing resistors LCD clock selection bits: 00 = fw/2 9 (64 Hz) 01 = fw/2 8 (128 Hz) 10 = fw/2 7 (256 Hz) 11 = fw/2 6 (512 Hz) LCD display control bit: 0 = Turn display off (Turn off the P-Tr) 1 = Turn display on (Turn on the P-Tr) Not used for S3C8275/C8278/C8274 LCD duty and bias selection bits: 000 = 1/4 duty, 1/3 bias 001 = 1/3 duty, 1/3 bias 010 = 1/3 duty, 1/2 bias 011 = 1/2 duty, 1/2 bias 1xx = Static NOTES: 1. "x" means don't care. 2. When 1/2 bias is selected, the bias levels are set as VLC0, VLC1(VLC2), and VSS. Figure 13-4. LCD Control Register (LCON) 13-4 S3C8275/F8275/C8278/F8278/C8274/F8274 LCD CONTROLLER/DRIVER www..com LCD VOLTAGE DIVIDING RESISTOR Static and 1/3 Bias 1/2 Bias S3C8275/8/4 VDD LCON.0 VDD S3C8275/8/4 LCON.0 VLC0 VLC1 VLC2 R R R VSS LCON.7 = 0: Enable internal resistors VLC0 VLC1 R R R VSS LCON.7 = 0: Enable internal resistors VLCD VLC2 VLCD Voltage Dividing Resistor Adjustment S3C8275/8/4 VDD LCON.0 VLC0 R' R' R' VSS VLC1 VLC2 LCON.7 = 1: Disable internal resistors VLCD NOTES: 1. R = Internal LCD dividing resistors. The resistors can be disconnected by LCON.7. 2. R' = External LCD dividing resistors. Figure 13-5. Internal Voltage Dividing Resistor Connection 13-5 LCD CONTROLLER/DRIVER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/4 duty mode, COM0-COM3 pins are selected -- In 1/3 duty mode, COM0-COM2 pins are selected -- In 1/2 duty mode, COM0-COM1 pins are selected SEGMENT (SEG) SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at page 2. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal to the corresponding segment pin. Select FR 1 Frame COM SEG Non-Select VLC0 VSS VLC0 VSS VLC0 VSS -VLC0 COM-SEG Figure 13-6. Select/No-Select Signals in Static Display Mode 13-6 S3C8275/F8275/C8278/F8278/C8274/F8274 LCD CONTROLLER/DRIVER www..com Select FR 1 Frame Non-Select COM VLC 0 VLC1, 2 Vss VLC 0 VLC1, 2 Vss VLC 0 VLC1, 2 Vss -VLC1, 2 -VLC 0 SEG COM-SEG Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode Select FR 1 Frame COM Non-Select VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 SEG COM-SEG Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode 13-7 LCD CONTROLLER/DRIVER S3C8275/F8275/C8278/F8278/C8274/F8274 www..com 0 FR 1 2 3 0 1 2 3 SEG1.4 x C0 SEG0.0 x C0 SEG1.5 x C1 VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 COM2 COM3 1 Frame COM0 COM1 SEG0.1 x C1 SEG0.2 x C2 SEG1.6 C2 SEG2.0 x C0 COM2 COM3 SEG2.1 x C1 SEG0.3 C3 SEG1.7 x C3 SEG0 SEG1 SEG0 SEG1 SEG2 SEG3 SEG4 1100 .0 .1 .2 .3 COM0 COM1 COM0 -SEG0 0111 1100 0101 1110 .0 .1 .2 .3 .4 .5 .6 .7 .0 .1 .2 .3 .4 .5 .6 .7 Data Register page 4, address B0H LD B0H, #3Eh Data Register page 4, address B1H LD B1H, #7Ah COM1 -SEG0 COM1 -SEG1 Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode 13-8 Data Register page 4, address B2H LD B2H, #63h COM0 -SEG1 .4 .5 .6 .7 0110 SEG5 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SERIAL I/O INTERFACE 14 OVERVIEW -- Clock selector logic SERIAL I/O INTERFACE Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: -- 8-bit control register (SIOCON) -- 8-bit data buffer (SIODATA) -- 8-bit prescaler (SIOPS) -- 3-bit serial clock counter -- Serial data I/O pins (SI, SO) -- Serial clock input/output pin (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. 2. 3. 4. 5. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P1CONL register if necessary. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1". When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) are set to "1" and SIO interrupt request is generated. 14-1 SERIAL I/O INTERFACE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in set 1, bank 0. It has the control setting for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation -- Shift operation (transmit) enable -- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first. Serial I/O Module Control Register (SIOCON) E1H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK) Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode Shift clock edge selection bit: 0 = TX at falling edges, Rx at rising edges 1 = TX at rising edges, Rx at falling edges SIO interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting Figure 14-1. Serial I/O Module Control Register (SIOCON) 14-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, is located at E3H in set 1, bank 0. The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock. SIO Pre-scaler Register (SIOPS) E3H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Baud rate = (fXX/4)/(SIOPS + 1) Figure 14-2. SIO Prescaler Register (SIOPS) SIO BLOCK DIAGRAM CLK 3-Bit Counter Clear SIO INT SIOCON.0 Pending SIOCON.3 SIOCON.7 SIOCON.4 (Edge Select) SCK SIOPS (E3H, set 1, bank 0) fxx/2 8-bit P.S. 1/2 M U X CLK 8-Bit SIO Shift Buffer (SIODATA, E2H, set 1, bank 0) SIOCON.2 (Shift Enable) SIOCON.1 (Interrupt Enable) SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select) 8 SI Data Bus Figure 14-3. SIO Functional Block Diagram 14-3 SERIAL I/O INTERFACE S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SERIAL I/O TIMING DIAGRAM (SIO) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO INT Set SIOCON.3 Transmit Complete Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO INT Set SIOCON.3 Transmit Complete Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) 14-4 S3C8275/F8275/C8278/F8278/C8274/F8274 BATTERY LEVEL DETECTOR www..com 15 OVERVIEW BATTERY LEVEL DETECTOR The S3C8275/C8278/C8274 micro-controller has a built-in BLD (Battery Level Detector) circuit which allows detection of power voltage drop or external input level through software. Turning the BLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during BLD operation. It is recommended that the BLD operation should be kept OFF unless it is necessary. Also the BLD criteria voltage can be set by the software. The criteria voltage can be set by matching to one of the 3 kinds of voltage below that can be used. 2.2 V, 2.4 V or 2.8 V (V DD reference voltage), or external input level (External reference voltage) The BLD block works only when BLDCON.3 is set. If VDD level is lower than the reference voltage selected with BLDCON.2-.0, BLDCON.4 will be set. If VDD level is higher, BLDCON.4 will be cleared. When users need to minimize current consumption, do not operate the BLD block. VDD Pin fBLD Battery Level Detector BLDCON.4 BLD Out BLDCON.5 MUX BLDCON.3 VBLDREF/P2.0 Battery Level Setting BLD Run P2CONL.1-.0 ExtRef Input Enable BLDCON.2-0 Set the Level Figure 15-1. Block Diagram for Voltage Level Detect 15-1 BATTERY LEVEL DETECTOR S3C8275/F8275/C8278/F8278/C8274/F8274 www..com BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 3 of BLDCON controls to run or disable the operation of Battery Level Detector. Basically this VBLD is set as 2.2V by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detector Control Register (BLDCON). When you write 3-bit data value to BLDCON, an established resistor string is selected and the VBLD is fixed in accordance with this resistor. Table 15-1 shows specific VBLD of 3 levels. Resistor String Battery Level Detector Control Register F4H, Set 1, Bank 1, R/W, Reset : 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used RBLD Mux VIN + Comparator BLD OUT VREF VBAT VBLDREF BANDGAP fBLD BLD Enable/Disable P2CONL.1-.0 Bias NOTES: 1. The reset value of BLDCON is #00H. 2. VREF is about 1 volt. Figure 15-2. Battery Level Detect Circuit and Control Register Table 15-1. BLDCON Value and Detection Level BLDCON .2-.0 0 1 0 0 0 1 0 1 1 VBLD 2.2 V 2.4 V 2.8 V Not available Other values 15-2 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com 16 OVERVIEW EMBEDDED FLASH MEMORY INTERFACE This chapter is only for the S3F8275. The S3F8275 has an on-chip full-flash memory internally instead of masked ROM. The flash memory is accessed by "LDC" instruction and the type of sector erase and a byte programmable flash, a user can program the data in the flash memory area any time you want. The S3F8275's embedded 16Kbyte memory has two operating features: -- User program mode: S3F8275 only -- Tool program mode: Refer to the chapter 19. S3F8275/F8278/F8274 FLASH MCU. 16-1 EMBEDDED FLASH MEMORY INTERFACE www..com S3F8275 USER PROGRAM MODE This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection). The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection, you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool. The S3F8275 has the pumping circuit internally. Therefore, 12.5V into VPP (test) pin is not needed. To program a flash memory in this mode several control registers will be used. There are four kind functions- programming, reading, sector erase, hard lock protection. FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) Flash Memory Control Register FMCON register is available only in user program mode to select the Flash Memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection. Flash Memory Control Register (FMCON) F0H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Flash memory mode selection bits: 0101 = Programming mode 1010 = Sector erase mode 0110 = Hard lock mode others = Not available Sector erase status bit: 0 = Success sector erase 1 = Fail sector erase Flash operation start bit: 0 = Operation stop 1 = Operation start (This bit will be cleared automatically just after the corresponding operation completed). Not used for S3F8275 Figure 16-1. Flash Memory Control Register (FMCON) The bit 0 of FMCON register (FMCON.0) is a start bit for Erase and Hard Lock operation mode. Therefore, operation of Erase and Hard Lock mode is activated when you set FMCON.0 to "1". Also you should wait a time of Erase (Sector erase) or Hard lock to complete it's operation before a byte programming or a byte read of same sector area by using "LDC" instruction. When you read or program a byte data from or into flash memory, this bit is not needed to manipulate. The sector erase status bit is read only. If an interrupt is requested during the operation of "Sector erase", the operation of "Sector Erase" is discontinued, and the interrupt is served by CPU. Therefore, the sector erase status bit should be checked after executing "Sector Erase". The "Sector Erase" operation is success if the bit is logic "0", and is failure if the bit is logic "1". NOTE: When the ID code, "A5H", is written to the FMUSR register. A mode of sector erase, user program, and hard lock may be executed unfortunately. So, It should be careful of the above situation. 16-2 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory. This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B" by reset operation. If necessary to operate the flash memory, you can use the user programming mode by setting the value of FMUSR to "10100101B". The other value of "10100101b", user program mode is disabled. Flash Memory User Programming Enable Register (FMUSR) F1H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Flash memory user programming enable bits: 10100101: Enable user programming mode Other values: Disable user programming mode Figure 16-2. Flash Memory User Programming Enable Register (FMUSR) 16-3 EMBEDDED FLASH MEMORY INTERFACE www..com S3F8275 Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Sector Address Register High Byte) indicates the high byte of sector address. The FMSECH is needed for S3F8275 because it has 128 sectors, respectively. One sector consist of 128-bytes. Each sector's address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H. So FMSECL register 6-0 don't mean whether the value is `1' or '0'. We recommend that the simplest way is to load sector base address into FMSECH and FMSECL register. When programming the flash memory, you should write data after loading sector base address located in the target address to write data into FMSECH and FMSECL register. If the next operation is also to write data, you should check whether next address is located in the same sector or not. It case of other sectors, you must load sector address to FMSECH and FMSECL register according to the sector. Flash Memory Sector Address Register, High Byte (FMSECH) F2H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Flash Memory Setor Address (High Byte) NOTE: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address. Figure 16-3. Flash Memory Sector Address Register, High Byte (FMSECH) Flash Memory Sector Address Register, Low Byte (FMSECL) F3H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Don't care Flash Memory Sector Address (Low Byte) NOTE: The low-byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address. Figure 16-4. Flash Memory Sector Address Register, Low Byte (FMSECL) 16-4 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can store on board program software (boot program code for upgrading application code by interfacing with I/O pin). The ISPTM sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software. The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart Option. If you don't like to use ISP sector, this area can be used as a normal program memory (can be erased or programmed by LDC instruction) by setting ISP disable bit ("1") at the Smart Option. Even if ISP sector is selected, ISP sector can be erased or programmed in the Tool Program mode, by Serial programming tools. The size of ISP sector can be varied by settings of Smart Option. You can choose appropriate ISP sector size according to the size of On Board Program software. (Decimal) 16,383 (HEX) 3FFFH 16K-bytes Internal Program Memory Area 8FFH 255 Available ISP Sector Area Interrupt Vector Area 3FH Smart Option Area 3CH 0 00H FFH S3F8275 Figure 16-5. Program Memory Address Space 16-5 EMBEDDED FLASH MEMORY INTERFACE www..com S3F8275 Table 16-1. ISP Sector Size Smart Option(003EH) ISP Size Selection Bit Bit 2 1 0 0 0 0 NOTE: Area of ISP Sector - 100H - 1FFH (256 byte) 100H - 2FFH (512 byte) 100H - 4FFH (1024 byte) 100H - 8FFH (2048 byte) ISP Sector Size 0 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes Bit 1 x 0 0 1 1 Bit 0 x 0 1 0 1 The area of the ISP sector selected by Smart Option bit (003EH.2 - 003EH.0) can not be erased and programmed by LDC instruction in user program mode. ISP Reset Vector and ISP Sector Size If you use ISP sectors by setting the ISP enable/disable bit to "0" and the Reset Vector Selection bit to "0" at the Smart Option, you can choose the reset vector address of CPU as shown in Table 16-3 by setting the ISP Reset Vector Address Selection bits. Table 16-2. Reset Vector Address Smart Option (003EH) ISP Reset Vector Address Selection Bit Bit 7 1 0 0 0 0 NOTE: Reset Vector Address After POR 0100H 0200H 0300H 0500H 0900H Usable Area for ISP Sector - 100H - 1FFH 100H - 2FFH 100H - 4FFH 100H - 8FFH ISP Sector Size Bit 6 x 0 0 1 1 Bit 5 x 0 1 0 1 - 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes The selection of the ISP reset vector address by smart option (003EH.7 - 003EH.5) is not dependent of the selection of ISP sector size by smart option (003EH.2 - 003EH.0). 16-6 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and programmed in User Program Mode is called sector. The program memory of S3F8275 is divided into 128 sectors for unit of erase and programming. Every sector has all 128-byte sizes of program memory areas. So each sector should be erased first to program a new data (byte) into a sector. Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit (FMCON.0). Sector Erase is not supported in Tool Program Modes (MDS mode tool or Programming tool). 3FFFH Sector 127 (128 Byte) Sector 126 (128 Byte) 3F7FH 3EFFH 1FFFH Sector 63 (128 Byte) 1F7FH 05FFH Sector 11 (128 Byte) 057FH Sector 10 (128 Byte) Sector 0-9 (128 byte x 10) 0500H 04FFH 0000H S3F8275 Figure 16-6. Sector Configurations in User Program Mode 16-7 EMBEDDED FLASH MEMORY INTERFACE www..com S3F8275 The Sector Erase Procedure in User Program Mode 1. 2. 3. 4. 5. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B". Set Flash Memory Sector Address Register (FMSECH/FMSECL). Set Flash Memory Control Register (FMCON) to "10100001B". Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B" Check the "sector erase status bit" whether "sector erase" is success or not. F PROGRAMMING TIP -- Sector Erase * * reErase: SB1 LD LD LD LD NOP NOP LD TM JR FMUSR,#0A5H FMSECH,#10H FMSECL,#00H FMCON,#10100001B ; User program mode enable ; ; ; ; ; ; ; Set sector address (1000H - 107FH) Start sector erase Dummy instruction, this instruction must be needed Dummy instruction, this instruction must be needed User program mode disable Check "sector erase status bit" Jump to reErase if fail FMUSR,#0 FMCON,#00001000B NZ,reErase 16-8 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set FMSECH and FMSECL to flash memory sector value. The write operation of programming starts by 'LDC' instruction. You can write until 128byte, because this flash sector's limit is 128byte. So if you written 128byte, must reset FMSECH and FMSECL. The Program Procedure in User Program Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. Must erase sector before programming. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B". Set Flash Memory Control Register (FMCON) to "01010000B". Set Flash Memory Sector Register (FMSECH, FMSECL) to sector value of write address. Load a transmission data into a working register. Load a flash memory upper address into upper register of pair working register. Load a flash memory lower address into lower register of pair working register. Load transmission data to flash memory location area on 'LDC' instruction by indirectly addressing mode. Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B". F PROGRAMMING TIP -- Program * * SB1 LD LD LD LD LD LD LD LDC NOP LD FMSECH,#17H FMSECL,#80H R2,#17H R3,#84H R4,#78H FMUSR,#0A5H FMCON,#01010000B @RR2,R4 FMUSR,#0 ; Set sector address (1780H-17FFH) ; Set a ROM address in the same sector 1780H-17FFH ; ; ; ; ; ; Temporary data User program mode enable Start program Write the data to a address of same sector (1784H) Dummy instruction, this instruction must be needed User program mode disable 16-9 EMBEDDED FLASH MEMORY INTERFACE www..com S3F8275 READING The read operation of programming starts by 'LDC' instruction. The Program Procedure in User Program Mode 1. 2. 3. Load a flash memory upper address into upper register of pair working register. Load a flash memory lower address into lower register of pair working register. Load receive data from flash memory location area on 'LDC' instruction by indirectly addressing mode. F PROGRAMMING TIP -- Reading * * LD LD LOOP: LDC INC CP JP * * * * R2,#3H R3,#0 R0,@RR2 R3 R3,#0H NZ,LOOP ; Load flash memory upper address ; To upper of pair working register ; Load flash memory lower address ; To lower pair working register ; Read data from flash memory location ; (Between 300H and 3FFH) 16-10 S3F8275 EMBEDDED FLASH MEMORY INTERFACE www..com HARD LOCK PROTECTION User can set Hard Lock Protection by write '0110' in FMCON.7-.4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool program mode). In terms of user program mode, the procedure of setting Hard Lock Protection is following that. Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the manufacturer. The Program Procedure in User Program Mode 1. 2. 3. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B". Set Flash Memory Control Register (FMCON) to "01100001B". Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B". F PROGRAMMING TIP -- Hard Lock Protection * * SB1 LD LD NOP LD * * FMUSR,#0A5H FMCON,#01100001B FMUSR,#0 ; User program mode enable ; Hard Lock mode set & start ; Dummy instruction, this instruction must be needed ; User program mode disable 16-11 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA 17 OVERVIEW ELECTRICAL DATA In this chapter, S3C8275/C8278/C8274 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a RESET -- I/O capacitance -- A.C. electrical characteristics -- Input timing for external interrupts -- Input timing for RESET -- Serial data transfer timing -- BLD electrical characteristics -- LVR electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range -- A.C. electrical characteristics for Internal flash ROM 17-1 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 17-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VI VO IOH IOL TA TSTG One I/O pin active All I/O pins active Output current Low One I/O pin active Total pin current for ports Operating temperature Storage temperature - - Ports 0-6 - Conditions - Rating - 0.3 to + 4.6 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 60 + 30 (Peak value) + 100 (Peak value) - 25 to + 85 - 65 to + 150 C C Unit V V V mA mA Table 17-2. D.C. Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Operating voltage Symbol VDD VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage Output low voltage VOH VOL1 Conditions fx = 0.4 - 4.2MHz, fxt = 32.8kHz fx = 0.4 - 8.0MHz Input high voltage All input pins except for VIH2, VIH3 Ports 0-1, nRESET XIN, XOUT and XTIN, XTOUT All input pins except for VIL2, VIL3 Ports 0-1, nRESET XIN, XOUT, XTIN, XTOUT VDD = 2.7 to 3.6 V; All output ports; IOH = -1 mA VDD = 2.7 to 3.6 V IOL = 15mA Ports 0-1 VOL2 VDD = 2.7 to 3.6 V IOL = 10mA All output ports except for VOL1 Input high leakage current ILIH1 ILIH2 VI = VDD All input pins except for ILIH2 VI = VDD XIN, XOUT, XTIN, XTOUT - - 3 A - - 1.0 V - - 1.0 V Min 2.0 2.5 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 - - - - Typ - - - Max 3.6 3.6 VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V V Unit V 20 17-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 85C, VDD = 2.0 V to 3.6 V) Parameter Input low leakage current Symbol ILIL1 Conditions VI = 0 V; All input pins except nRESET, ILIL2 VI = 0 V; XIN, XOUT, XTIN, XTOUT VO = VDD All output pins VO = 0 V All output pins RL1 RL2 Oscillator feed back resistors ROSC1 ROSC2 LCD voltage dividing resistor VLCD-COMi voltage drop (i = 0-3) VLCD-SEGx voltage drop (x = 0-31) Middle output voltage (1) RLCD VDC VI = 0 V; VDD = 3V, TA = 25C Ports 0-6 VI = 0 V; VDD = 3V, TA = 25C nRESET VDD = 3 V, TA = 25 C XIN = VDD, XOUT = 0V VDD = 3 V, TA = 25 C XTIN = VDD, XTOUT = 0 V TA = 25 C - 15 A per common pin 60 - 110 - 160 120 k mV 2000 4000 8000 40 70 100 k - - - - Min - Typ - Max -3 Unit A ILIL2 Output high leakage current Output low leakage current Pull-up resistors ILOH ILOL -20 3 -3 220 360 500 600 1700 3000 k VDS - 15 A per common pin - - 120 VLC1 VLC2 VDD = 2.7 V to 3.6 V, 1/3 bias LCD clock = 0Hz, VLC0 = VDD 2/3VDD-0.2 1/3VDD-0.2 2/3VDD 1/3VDD 2/3VDD+ 0.2 1/3VDD+ 0.2 V NOTE: It is middle output voltage when the VLC0 pin is opened. 17-3 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 17-2. D.C. Electrical Characteristics (Concluded) (TA = - 25C to + 85C, VDD = 2.0 V to 3.6 V) Parameter Supply current (1) Symbol IDD1(2) Conditions Run mode: VDD = 3.3 V 0.3 V Crystal oscillator C1 = C2 = 22pF IDD2(2) Idle mode: VDD = 3.3 V 0.3 V Crystal oscillator C1 = C2 = 22pF IDD3(3) 8.0 MHz 4.0 MHz 8.0 MHz 4.0 MHz Min - Typ 3.0 1.5 0.5 0.4 12.0 Max 6.0 3.0 1.6 1.2 25.0 A Unit mA Run mode: VDD = 3.3 V 0.3 V, 32 kHz crystal oscillator TA = 25 C, OSCCON.7=1 Idle mode: VDD = 3.3 V 0.3 V, 32 kHz crystal oscillator TA = 25 C, OSCCON.7=1 Stop mode; VDD = 3.3 V 0.3 V TA = 25 C TA = -25 C ~ +85 C IDD4(3) 2.0 4.0 IDD5(4) 0.2 - 2.0 10 NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the LVR block, and external output current loads. 2. IDD1 and IDD2 include power consumption for sub clock oscillation. 3. 4. 5. IDD3 and IDD4 are current when main clock oscillation stops and the sub clock is used (OSCCON.7=1). IDD5 is current when main clock and sub clock oscillation stops. Every values in this table is measured when bits 4 -3 of the system clock control register (CLKCON.4-.3) is set to 11B. 17-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - Stop mode, TA = 25 C VDDDR = 2.0 V Disable LVR block Min 2.0 - Typ - - Max 3.6 1 Unit V A Idle Mode (Basic Timer Active) ~ ~ ~ ~ Stop Mode Data Retention Mode Normal Operating Mode VDD VDDDR Execution of STOP Instruction 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock. Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt 17-5 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com RESET Occurs Oscillation Stabilization TIme Normal Operating Mode ~ ~ ~ ~ Stop Mode Data Retention Mode VDD VDDDR Execution of STOP Instrction nRESET 0.2 VDD 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock. Figure 17-2. Stop Mode Release Timing When Initiated by a RESET Table 17-4. Input/Output Capacitance (TA = -25 C ~ + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF 17-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Table 17-5. A.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 3.6 V) Parameter SCK cycle time Symbol tKCY tKH, tKL Conditions External SCK source Internal SCK source SCK high, low width External SCK source Internal SCK source SI setup time to SCK high tSIK tKSI External SCK source Internal SCK source SI hold time to SCK high External SCK source Internal SCK source Output delay for SCK to SO tKSO tINTH, tINTL nRESET input Low width tRSL External SCK source Internal SCK source Interrupt input, High, Low width All interrupt VDD = 3 V Input VDD = 3 V 500 700 Min 1,000 1,000 500 tKCY /2-50 250 250 400 400 - - 300 250 - ns s ns Typ - Max - Unit ns 10 - - tINTL tINTH External Interrupt 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 17-3. Input Timing for External Interrupts 17-7 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com tRSL nRESET 0.2 VDD Figure 17-4. Input Timing for RESET tKCY tKL SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO tKH SO Output Data Figure 17-5. Serial Data Transfer Timing 17-8 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Table 17-6. Battery Level Detector Electrical Characteristics (TA = 25C, VDD = 2.0 V to 3.6 V) Parameter Operating voltage of BLD Voltage of BLD Symbol VDDBLD VBLD Conditions - BLDCON.2-.0 = 000b BLDCON.2-.0 = 101b BLDCON.2-.0 = 011b Current consumption IBLD VDD = 3.3 V VDD = 2.2 V Hysteresis voltage of BLD BLD circuit response time V TB BLDCON.2-0 = 000b, 101b, 011b Fw = 32.768 kHz Min 2.0 2.0 2.15 2.5 - - - - Typ - 2.2 2.4 2.8 70 50 10 - Max 3.6 2.4 2.65 3.1 120 100 100 1 mV ms A Unit V Table 17-7. LVR (Low Voltage Reset) Electrical Characteristics (TA = 25C) Parameter Voltage of LVR VDD voltage rising time VDD voltage off time Hysteresis voltage of LVR Current consumption Symbol VLVR tR tOFF V IDDPR VDD = 3.3 V Conditions TA = 25 C - - - Min 2.0 10 0.5 - - Typ 2.2 - - 10 70 Max 2.4 - - 100 120 Unit V s s mV A NOTES: 1. The current of LVR circuit is consumed when LVR is enabled by "Smart Option" 2. Current consumed when low voltage reset circuit is provided internally. tOFF tR VDD 0.9 VDD 0.1 VDD Figure 17-6. LVR (Low Voltage Reset) Timing 17-9 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 17-8. Main Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration C1 XIN Parameter Main oscillation frequency Test Condition 2.5 V - 3.6 V Min 0.4 Typ - Max 8 Units MHz XOUT 2.0 V - 3.6 V Ceramic oscillator C1 XIN 0.4 0.4 - - 4.2 8 Main oscillation frequency 2.5 V - 3.6 V XOUT 2.0 V - 3.6 V External clock XIN input frequency XIN 0.4 0.4 - - 4.2 8 2.5 V - 3.6 V XOUT 2.0 V - 3.6 V RC oscillator R XOUT 0.4 0.4 - - 4.2 1 MHz Frequency XIN 3.3 V Table 17-9. Sub Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration C1 XTIN Parameter Sub oscillation frequency Test Condition 2.0 V - 3.6 V Min 32 Typ 32.768 Max 35 Units kHz XTOUT External clock XTIN input XTIN 2.0 V - 3.6 V 32 - 100 frequency XTOUT 17-10 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Table 17-10. Main Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Oscillator Crystal Ceramic fx > 1 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. External clock XIN input high and low width (t XH, tXL) 62.5 - 1250 ns Test Condition Min - - Typ - - Max 40 10 Unit ms ms 1/fx tXL tX XIN 0.1 V VDD-0.1 V Figure 17-7. Clock Timing Measurement at XIN 17-11 ELECTRICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 17-11. Sub Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Oscillator Crystal External clock Test Condition - XTIN input high and low width (t XH, tXL) Min - 5 Typ - - Max 10 15 Unit s s 1/fxt tXTL tXTH XTIN VDD-0.1 V 0.1 V Figure 17-8. Clock Timing Measurement at XTIN 17-12 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com ELECTRICAL DATA Instruction Clock 2 MHz 1.05 MHz fx (Main/Sub oscillation frequency) 8 MHz 4.2 MHz 6.25 kHz(main)/8.2 kHz(sub) 1 2 2.5 3 3.6 4 400 kHz (main)/32.8 kHz(sub) Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 17-9. Operating Voltage Range Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Programming time (1) Chip erasing time (2) Sector erasing time (3) Data access time Number of writing/erasing Symbol Ftp Ftp1 Ftp2 FtRS FNwe Conditions - - - - - Min 30 10 10 - - Typ - - - 25 - Max - - - - 10,000(4) Unit s ms ms ns Times NOTES: 1. The programming time is the time during which one byte (8-bit) is programmed. 2. The chip erasing time is the time during which all 16K byte block is erased. 3. The sector erasing time is the time during which all 128 byte block is erased. 4. Maximum number of writing/erasing is 10,000 times for full-flash(S3F8275) and 100 times for half-flash (S3F8278/F8274). 5. The chip erasing is available in Tool Program Mode only. 17-13 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com MECHANICAL DATA 18 OVERVIEW MECHANICAL DATA The S3C8275/C8278/C8274 microcontroller is currently available in a 64-pin QFP and LQFP package. 23.90 0.30 20.00 0.20 0-8 + 0.10 0.15 - 0.05 0.30 0.20 17.90 14.00 64-QFP-1420F 0.80 0.20 #1 1.00 0.40 + 0.10 - 0.05 0.10 MAX #64 0.15 MAX 0.05 MIN (1.00) 2.65 0.10 3.00 MAX 0.80 + 0.20 NOTE: Dimensions are in millimeters. Figure 18-1. 64-Pin QFP Package Dimensions (64-QFP-1420F) 18-1 MECHANICAL DATA S3C8275/F8275/C8278/F8278/C8274/F8274 www..com 12.00 BSC 10.00 BSC 0-7 0.09~0.20 12.00 BSC 10.00 BSC 64-LQFP-1010 0.45~0.75 #1 0.50 BSC 0.20 + 0.07 - 0.03 0.08 MAX #64 0.10 0.05 1.40 0.05 1.60 MAX NOTE: Dimensions are in millimeters. Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010) 18-2 S3C8275/F8275/C8278/F8278/C8274/F8274 S3F8275/F8278/F8274 FLASH MCU www..com 19 OVERVIEW NOTE: S3F8275/F8278/F8274 FLASH MCU The S3F8275/F8278/F8274 single-chip CMOS microcontroller is the Flash MCU version of the S3C8275/C8278/C8274 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F8275/F8278/F8274 is fully compatible with the S3C8275/C8278/C8274, both in function and in pin configuration. Because of its simple programming requirements, the S3F8275/F8278/F8274 is ideal for use as an evaluation chip for the S3C8275/C8278/C8274. This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program Mode, refer to the chapter 16. Embedded Flash Memory Interface. 19-1 S3F8275/F8278/F8274 FLASH MCU S3C8275/F8275/C8278/F8278/C8274/F8274 www..com SEG0/P5.7 COM0/P6.0 COM1/P6.1 COM2/P6.2 COM3/P6.3 VLC0 SDAT/VLC1 SCLK/VLC2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT nRESET/nRESET VREG P0.0/INT0 P0.1/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 S3F8275 S3F8278 S3F8274 (64-QFP-1420F) SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/VBLDREF P1.7/INT7 Figure 19-1. S3F8275/F8278/F8274 Pin Assignments (64-QFP-1420F) 19-2 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ P1.0/SCK P1.1/SO P1.2/SI P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8275/F8275/C8278/F8278/C8274/F8274 S3F8275/F8278/F8274 FLASH MCU www..com SEG0/P5.7 COM0/P6.0 COM1/P6.1 COM2/P6.2 COM3/P6.3 VLC0 SDAT/VLC1 SCLK/VLC2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT nRESET/nRESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 S3F8275 S3F8278 S3F8274 (64-LQFP-1010) SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.0 SEG24/P2.7 SEG25/P2.6 SEG26/P2.5 SEG27/P2.4 SEG28/P2.3 SEG29/P2.2 SEG30/P2.1 SEG31/P2.0/VBLDREF P1.7/INT7 Figure 19-2. S3F8275/F8278/F8274 Pin Assignments (64-LQFP-1010) VREG P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ P1.0/SCK P1.1/SO P1.2/SI P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 19-3 S3F8275/F8278/F8274 FLASH MCU S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name VLC1 Pin Name SDAT Pin No. 7 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as an Input or push-pull output port. Serial clock pin. Input only pin. Power supply pin for Flash ROM cell writing (indicates that FLASH MCU enters into the writing mode). When 12.5V is applied, FLASH MCU is in writing mode and when 3.3V is applied, Flash MCU is in reading mode. Chip initialization Power supply pin for logic circuit. VDD should be tied to +3.3 V during programming. VLC2 TEST SCLK VPP 8 13 I/O I nRESET VDD/VSS nRESET VDD/VSS 16 9 / 10 I I Table 19-2. Comparison of S3F8275/F8278/F8274 and S3C8275/C8278/C8274 Features Characteristic Program memory Operating voltage (V DD) Flash ROM programming mode Pin configuration Flash ROM programmability NOTE: S3F8275/F8278/F8274 16/8/4-Kbyte Flash ROM 2.0 V to 3.6 V VDD = 3.3 V, VPP(TEST)=12.5V 64-QFP, 64-LQFP User Program multi time S3C8275/C8278/C8274 16/8/4-Kbyte mask ROM 2.0 V to 3.6 V - 64-QFP, 64-LQFP Programmed at the factory The VPP (Test) pin had better connect to VDD (S3F8275 only). 19-4 S3C8275/F8275/C8278/F8278/C8274/F8274 S3F8275/F8278/F8274 FLASH MCU www..com OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3F8275/F8278/F8274, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 19-3 below. Table 19-3. Operating Mode Selection Criteria VDD 3.3 V VPP (TEST) 3.3 V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Mode Flash ROM read Flash ROM program Flash ROM verify Flash ROM read protection NOTES: 1. The VPP (Test) pin had better connect to VDD (S3F8275 only). 2. "0" means Low level; "1" means High level. 19-5 S3F8275/F8278/F8274 FLASH MCU S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 19-4. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 3.6 V) Parameter Supply current (1) Symbol IDD1 (2) Conditions Run mode: VDD = 3.3 V 0.3 V Crystal oscillator C1 = C2 = 22pF IDD2 (2) Idle mode: VDD = 3.3 V 0.3 V Crystal oscillator C1 = C2 = 22pF IDD3 (3) 8.0 MHz 4.0 MHz 8.0 MHz 4.0 MHz Min - Typ 3.0 1.5 0.5 0.4 Max 6.0 3.0 1.6 1.2 A Unit mA Run mode: VDD = 3.3 V 0.3 V, 32 kHz crystal oscillator TA = 25 C, OSCCON.7=1 Idle mode: VDD = 3.3 V 0.3 V 32 kHz crystal oscillator TA = 25 C, OSCCON.7=1 12.0 25.0 IDD4 (3) 2.0 4.0 IDD5 (4) Stop mode; VDD = 3.3V 0.3 V TA = 25 C TA = -25 C ~ +85 C 0.2 - 2.0 10 NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the LVR block and external output current loads. 2. IDD1 and IDD2 include power consumption for sub clock oscillation. 3. 4. 5. IDD3 and IDD4 are current when main clock oscillation stops and the sub clock is used (OSCCON.7=1). IDD5 is current when main clock and sub clock oscillation stops. Every values in this table is measured when bits 4 -3 of the system clock control register (CLKCON.4-.3) is set to 11B. 19-6 S3C8275/F8275/C8278/F8278/C8274/F8274 S3F8275/F8278/F8274 FLASH MCU www..com Instruction Clock 2 MHz 1.05 MHz fx (Main/Sub oscillation frequency) 8 MHz 4.2 MHz 6.25 kHz (main)/8.2 kHz(sub) 1 2 3 4 400 kHz(main)/32.8 kHz(sub) 2.5 3.6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 19-3. Operating Voltage Range 19-7 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DEVELOPMENT TOOLS 20 OVERVIEW SHINE DEVELOPMENT TOOLS Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS, Windows 95, and 98 as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, and OPENice for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM88 The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. 20-1 DEVELOPMENT TOOLS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com IBM-PC AT or Compatible RS-232C SMDS2+ PROM/OTP Writer Unit Target Application System RAM Break/Display Unit Probe Adapter BUS Trace/Timer Unit SAM8 Base Unit POD TB8275/8/4 Target Board EVA Chip Power Supply Unit Figure 20-1. SMDS Product Configuration (SMDS2+) 20-2 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DEVELOPMENT TOOLS TB8275/8/4 TARGET BOARD The TB8275/8/4 target board is used for the S3C8275/C8278/C8274 microcontroller. It is supported with the SMDS2+. TB8275/8/4 To User_VCC OFF ON IDLE + STOP + RESET VCC J101 1 2 41 GND J102 42 79 40-pin connector 40 80 40-pin connector 39 7411 X-TAL XTAL VDD VLC0 VLC1 VLC2 External LCD Bias Y1(sub-clock) JP6 40 41 160 100-pin connector 1 25 160 QFP S3E8270 EVA Chip 80 81 120 121 1 Device Selection Low: S3F8278/4 High: S3F8275 Select Smart Option Source Low: Internal High: External Smart Option SW1 SMDS2 SMDS2+ Figure 20-2. TB8275/8/4 Target Board Configuration MDS 20-3 DEVELOPMENT TOOLS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 20-1. Power Selection Settings for TB8275/8/4 "To User_Vcc" Settings To User_VCC Off On Operating Mode Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. TB8275 TB8278 TB8274 VSS VCC Target System VCC SMDS2/SMDS2+ To User_VCC Off On TB8275 TB8278 TB8274 External VCC VSS Target System The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply. VCC SMDS2/SMDS2+ NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration: Table 20-2. Main-clock Selection Settings for TB8275/8/4 Main Clock Settings XIN XTAL MDS Operating Mode EVA Chip S3E8270 XOUT No Connection 100 Pin Connector SMDS2/SMDS2+ Comments Set the XI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+. XIN XIN XTAL MDS EVA Chip S3E8270 XOUT XTAL Target Board Set the XI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+. XIN 20-4 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DEVELOPMENT TOOLS Table 20-3. Select Smart Option Source Setting for TB8275/8/4 "Smart Option Source" Settings Select Smart Option Source Internal External Operating Mode Comments The Smart Option is selected by external smart option switch (SW1) TB8275/8/4 Target System Select Smart Option Source Internal External TB8275/8/4 Target System The Smart Option is selected by internal smart option area (003EH-003FH of ROM). But this selection is not available. Table 20-4. Smart Option Switch Settings for TB8275/8/4 "Smart Option" Settings Smart Option SW1 Low : "0" High: "1" B0 B1 B2 B3 B4 B5 B6 B7 B8 Comments The Smart Option is selected by this switch when the Smart Option source is selected by external. The B2-B0 are comparable to the 003EH.2-.0. The B7-B5 are comparable to the 003EH.7-.5. The B8 is comparable to the 003FH.0. The B4-B3 is not connected. 20-5 DEVELOPMENT TOOLS S3C8275/F8275/C8278/F8278/C8274/F8274 www..com Table 20-5. Device Selection Settings for TB8275/8/4 "Device Selection" Settings Device Selection S3F8278/4 S3F8275 Operating Mode Comments Operate with TB8275 TB8275 Target System Device Selection S3F8278/4 S3F8275 Operate with TB8278/4 TB8278/4 Target System SMDS2+ SELECTION (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 20-6. The SMDS2+ Tool Selection Setting "JP2" Setting JP2 SMDS2 SMDS2+ Operating Mode R/W SMDS2+ R/W Target System IDLE LED The Yellow LED is ON when the evaluation chip (S3E8270) is in idle mode. STOP LED The Red LED is ON when the evaluation chip (S3E8270) is in stop mode. 20-6 S3C8275/F8275/C8278/F8278/C8274/F8274 www..com DEVELOPMENT TOOLS J101 SEG0/P5.7 COM1/P6.1 COM3/P6.3 VLC1 VDD N.C TEST N.C VREG INT1/P0.1 T1CLK/P0.3 TBOUT/P0.5 BUZ/P0.7 SO/P1.1 INT3/P1.3 INT5/P1.5 N.C N.C N.C N.C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 P6.0/COM0 P6.2/COM2 VLC0 VLC2 VSS N.C N.C nRESET P0.0/INT0 P0.2/INT2 P0.4/TAOUT P0.6/CLKOUT P1.0/SCK P1.2/SI P1.4/INT4 P1.6/INT6 N.C N.C N.C N.C INT7/P1.7 SEG30/P2.1 SEG28/P2.3 SEG26/P2.5 SEG24/P2.7 SEG22/P3.1 SEG20/P3.3 SEG18/P3.5 SEG16/P3.7 SEG14/P4.1 SEG12/P4.3 SEG10/P4.5 SEG8/P4.7 SEG6/P5.1 SEG4/P5.3 SEG2/P5.5 N.C N.C N.C N.C 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 J102 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 SEG31/P2.0/VBLDREF SEG29/P2.2 SEG27/P2.4 SEG25/P2.6 SEG23/P3.0 SEG21/P3.2 SEG19/P3.4 SEG17/P3.6 SEG15/P4.0 SEG13/P4.2 SEG11/P4.4 SEG9/P4.6 SEG7/P5.0 SEG5/P5.2 SEG3/P5.4 SEG1/P5.6 N.C N.C N.C N.C Target Board J101 1 40-Pin Connector J102 2 33 34 Target Cable for 40-pin Connector Part Name: AS40D-A Order Code: SM6306 31 32 63 64 63 64 31 32 Figure 20-4. S3E8270 Cables for 64-QFP Package 40-Pin Connector 40-Pin DIP Connector Figure 20-3. 40-Pin Connectors (J101, J102) for TB8275/8/4 J102 33 34 1 40-Pin DIP Connector Target Board J101 2 20-7 www..com S3C8 SERIES MASK ROM ORDER FORM Product description: Device Number: S3C8__________- ___________(write down the ROM code number) Package Pellet Wafer Package Type: __________ Product Order Form: Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line) SEC @ YWW Device Name @ YWW Device Name @ YWW @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form F For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other If you are replacing an existing product, please indicate the former product name ( ) F What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation Mask Charge (US$ / Won): Customer Information: Company Name: Signatures: ____________________________ ___________________ ________________________ (Person placing the order) Telephone number _________________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) www..com S3C8 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3C8________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: ____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________ ________________________________________________________________ ________________________________________________________________ Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS Signatures: _______________________________ (Person Placing the Risk Order) ______________________________________ (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) www..com S3C8275/C8278/C8274 MASK OPTION SELECTION FORM Device Number: S3C8_______-________(write down the ROM code number) Attachment (Check one): Diskette PROM Customer Checksum: ________________________________________________________________ Company Name: ________________________________________________________________ Signature (Engineer): ________________________________________________________________ Please answer the following questions: F Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation Please describe in detail its application (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3F8 SERIES FLASH MCU FACTORY WRITING ORDER FORM(1/2) Product Description: Device Number: S3F8________-________(write down the ROM code number) Package Package Type: Pellet _____________________ Wafer www..com Product Order Form: If the product order form is package: Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line) SEC @ YWW Device Name @ YWW Device Name @ YWW @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity Please answer the following questions: F What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other If you are replacing an existing microcontroller, please indicate the former microcontroller name ( ) F What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _____________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) www..com S3F8275/F8278/F8274 FLASH MCU FACTORY WRITING ORDER FORM (2/2) Device Number: S3F8________-__________ (write down the ROM code number) Customer Checksums: _______________________________________________________________ Company Name: ________________________________________________________________ Signature (Engineer): ________________________________________________________________ Read Protection (1): Yes No Please answer the following questions: F Are you going to continue ordering this device? Yes If so, how much will you be ordering? No _________________pcs F Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation Please describe in detail its application __________________________________________________________________________ NOTES: 1. Once you choose a read protection, you cannot read again the programming code from the EPROM. 2. OTP Writing will be executed in our manufacturing site. 3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program. (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) |
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