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D a t a S h e e t , Rev. 1.13, M a i 2 00 4
HYB18T512[400/800/160]AC-[3.7/5] HYB18T512[400/800/160]AF-[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
The information in this document is subject to change without notice. Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 1.13, M a i 2 00 4
HYB18T512[400/800/160]AC-[3.7/5] HYB18T512[400/800/160]AF-[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYB18T512[400/800/160]A[C/F]-[3.7/5] Revision History: Page all Rev. 1.13 2004-05
Subjects (major changes since last revision) initial release
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Template: mp_a4_v2.3_2004-01-14.fm
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.1 2.2 2.2.1 2.2.2 2.2.2.1 2.2.3 2.2.4 2.2.5 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.7 2.7.1 2.7.2 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.10 2.11 2.11.1 2.11.2 2.12 2.13 3 4 5 5.1 5.2 5.3 5.4 5.4.1 5.5 5.6 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 512Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 SDRAM Extended Mode Register Set (EMRS(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMRS(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMRS(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Operation Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous CKE Low Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 22 22 23 23 25 27 27 28 31 35 36 37 38 39 42 45 46 48 48 51 52 52 55 56 57 57 57 58 59 63 63 63 63 64
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 68 68 69 71 72 74 75 76
Data Sheet
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Table of Contents 6 6.1 6.2 7 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 8.3.3 8.4 9 10 Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IDD Specifications and Conditions
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Electrical Characteristics & AC Timing - Absolute Specification . . . . . . . . . . . . . . . . . . . . . . . . 80 Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating . . . . . . . . . . . . . . . . Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slewrate Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Slewrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Slewrate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Slewrate - Single ended signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Definition for Input Setup (tIS) and Hold Time (tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Definition for Data Setup (tDS) and Hold Time (tDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 83 83 83 84 84 84 85 91
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DDR2 Component Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Data Sheet
6
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.1
* * *
Features
* Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS Data masks (DM) for write data Posted CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. Auto-Precharge operation for read and write bursts Auto-Refresh, Self-Refresh and power saving Power-Down modes Average Refresh Period 7.8 s at a TCASE lower than 85 C, 3.9 s between 85 C and 95 C Normal and Weak Strength Data-Output Drivers
1K page size for x4 & x8, 2K page size for x16
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: 1.8 V 0.1 V Power Supply 1.8 V 0.1 V (SSTL_18) compatible I/O DRAM organisations with 4, 8 and 16 data in/outputs Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation CAS Latency: 3, 4 and 5 Burst Length: 4 and 8 Differential clock inputs (CK and CK) Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. DLL aligns DQ and DQS transitions with clock DQS can be disabled for single-ended data strobe operation
* * * * * * *
*
* * * *
* *
*
Packages: P-TFBGA-60-6 for x4 & x8 components P-TFBGA-84-1 for x16 components
Table 1
High Performance -3.7 DDR2-533 4-4-4 @CL5 @CL4 @CL3 -5 DDR2-400 3-3-3 200 200 200 15 15 40 55 Units -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1.2
Description
1. 2. 3. 4. 5. posted CAS with additive latency, write latency = read latency - 1, normal and weak strength data-output driver, Off-Chip Driver (OCD) impedance adjustment and an On-Die Termination (ODT) function.
The 512-Mb DDR2 DRAM is a high-speed DoubleData-Rate-2 CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit x 4 I/O x 4 bank, 16 Mbit x 8 I/O x 4 bank or 8 Mbit x 16 I/O x 4 bank chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures. The device is designed to comply with all DDR2 DRAM key features:
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.
Data Sheet
7
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview A 16-bit address bus for x4 and x8 organised components and a 15-bit address bus for x16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style. The DDR2 device operates with a 1.8 V 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package.
1.3
Table 2
Ordering Information
Ordering information Org. Speed x4 x8 x16 x4 x8 x16 P-TFBGA-84-1 DDR2-533 4-4-4 266 3-3-3 200 P-TFBGA-84-1 P-TFBGA-60-6 CAS-RCD-RP Clock (MHz) Latencies 200 CAS-RCD-RP Clock (MHz) Latencies -- -- Package P-TFBGA-60-6
Part Number HYB18T512400AC-5 HYB18T512800AC-5 HYB18T512160AC-5 HYB18T512400AC-3.7 HYB18T512800AC-3.7 HYB18T512160AC-3.7
DDR2-400 3-3-3
HYB18T512400AF-5 HYB18T512800AF-5 HYB18T512160AF-5 HYB18T512400AF-3.7 HYB18T512800AF-3.7 HYB18T512160AF-3.7
x4 x8 x16 x4 x8 x16
DDR2-400 3-3-3
200
--
--
P-TFBGA-60-6 P-TFBGA-84-1
DDR2-533 4-4-4
266
3-3-3
200
P-TFBGA-60-6 P-TFBGA-84-1
Note: For product nomenclature see Chapter 10 of this data sheet
Data Sheet
8
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1.4
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer Type columns are explained in Table 4 and Table 5 respectively. The pin numbering for the FBGA package is depicted in Figure 1 for x4, Figure 2 for x8 and Figure 3 for x16. Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Name Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 13 9 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P Address Signal 12:0 Function
Clock Signals x4/x8 organizations E8 F8 F2 J8 K8 K2 F7 G7 F3 G8 K7 L7 K3 L8 G2 G3 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 Data Sheet CK CK CKE CK CK CKE RAS CAS WE CS RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 Clock Signal Complementary Clock Signal Clock Enable Rank Clock Signal Complementary Clock Signal Clock Enable Rank Row Address Strobe Column Address Strobe Write Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Chip Select Bank Address Bus 1:0
Clock Signals x16 organization
Control Signals x4/x8 organizations
Control Signals x16 organization
Address Signals x4/x8 organizations
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Name Pin Type I I - I I I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Signal 0 Data Signal 1 Data Signal 2 Data Signal 3 Data Signal 4 Data Signal 5 Data Signal 6 Data Signal 7 Data Signal 0 Data Signal 1 Data Signal 2 Data Signal 3 Data Signal 4 Data Signal 5 Data Signal 6 Data Signal 7 Data Signal 8 Data Signal 9 Data Signal 10 Address Signal 12:0 Function
Address Signals x16 organization L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 C8 C2 D7 D3 D1 D9 B1 B9 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 BA0 BA1 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 Bank Address Bus 1:0
Data Signals x4/x8 organizations
Data Signals x8 organization
Data Signals x16 organization
Data Sheet
10
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview Table 3 Ball#/Pin# D3 D1 D9 B1 B9 B7 A8 B3 A2 B7 A8 F7 E8 B3 B3 F3 A9,C1,C3,C7, C9 A1 A7,B2,B8,D2, D8 A3,E3 E2 E1 E9,H9,L1 E7 J1,K9 J2 E9, G1, G3, G7, G9 J1 Pin Configuration of DDR SDRAM Name DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS RDQS RDQS UDQS UDQS LDQS LDQS DM UDM LDM Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I PWR PWR PWR PWR AI PWR PWR PWR PWR AI PWR PWR Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - - - - - - - - - - - - Function Data Signal 11 Data Signal 12 Data Signal 13 Data Signal 14 Data Signal 15 Data Strobe Data Strobe Mode Register Select Data Strobe Data Strobe Upper Byte Data Strobe Upper Byte Data Strobe Lower Byte Data Strobe Lower Byte Data Mask Data Mask Upper Byte Data Mask Lower Byte I/O Driver Power Supply Power Supply Power Supply Power Supply I/O Reference Voltage Power Supply Power Supply Power Supply Power Supply I/O Reference Voltage I/O Driver Power Supply Power Supply
Data Strobe x4/x8 organisations
Data Strobe x8 organisations
Data Strobe x16 organization
Data Mask x4/x8 organizations Data Mask x16 organization
Power Supplies x4/x8/x16 organizations
VDDQ VDD VSSQ VSS VREF VDDL VDD VSSDL VSS VREF VDDQ VDDL
Power Supplies x4/x8 organizations
Power Supplies x16 organization
Data Sheet
11
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Name Pin Type PWR PWR PWR PWR NC NC Buffer Type - - - - - - Function Power Supply Power Supply Power Supply Power Supply Not Connected Not Connected
E1, J9, M9, R1 VDD E7, F2, F8, H2, VSSQ H8 J7 J3,N1,P9 L3,L7, G1 A2, B1, B9, D1, D9
VSSDL VSS
NC NC
Not Connected x4/x8 organizations Not Connected x4 organization
Not Connected x16 organization A2, E2, L1, R3, NC R7, R8 F9 K9
Table 4 Abbreviation I O I/O AI PWR GND NC
NC
-
Not Connected
Other Pins x4/x8 organizations ODT ODT - - - - On-Die Termination Control On-Die Termination Control Other Pins x16 organization
Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Table 5 Abbreviation SSTL LV-CMOS
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
2
3
4
5
6
7
8
9
VDD
NC
NC
VSS
DM
A B C
VSSQ
DQS
DQS
VDDQ
NC
VSSQ
DQ1
VSSQ
DQ0
VDDQ
NC
VDDQ
DQ3
V DDQ
DQ2
VDDQ
NC
VSSQ V REF
CKE
D E
VSSQ
CK CK
V DDL
VSS
WE
V SSDL
RAS
V DD
ODT
F G
NC/BA2
BA0 A10/AP
BA1 A1
CAS A2
CS A0
H J
V DD
V SS
A3 A7
A5 A9
A6 A11
A4 A8
K L
VSS
VDD
A12
NC
NC
NC/A13
MPPT0010
Figure 1 Notes
Pin Configuration P-TFBGA-60 (x4) Top View, see the balls throught the package
1. VDDL and VSSDL are power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS and VSSQ.
2. Ball position G1 is Not Connected and will be used for BA2 on 1-Gbit memory densities and higher 3. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit
Data Sheet
13
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
2 NU/ RDQS
3
4
5
6
7
8
9
VDD
DQ6
VSS
DM/ RDQS
A B C
VSSQ
DQS
DQS
VDDQ
DQ7
VSSQ
DQ1
VSSQ
DQ0
VDDQ
DQ4
VDDQ
DQ3
V DDQ
DQ2
VDDQ
DQ5
VSSQ V REF
CKE
D E
VSSQ
CK CK
V DDL
VSS
WE
V SSDL
RAS
V DD
ODT
F G
NC/BA2
BA0 A10/AP
BA1 A1
CAS A2
CS A0
H J
V DD
V SS
A3 A7
A5 A9
A6 A11
A4 A8
K L
VSS
VDD
A12
NC
NC
NC/A13
MPPT0080
Figure 2 Notes
Pin Configuration P-TFBGA-60 (x8) Top View, see the balls throught the package
1. RDQS / RDQS are enabled by EMRS(1) command. 2. If RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. They are isolated on thedevice from VDD, VDDQ, VSS and VSSQ. 5. Ball position G1 is Not Connected and will be used for BA2 on 1-Gbit memory densities and higher 6. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit
Data Sheet
14
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
2
3
4
5
6
7
8
9
VDD
DQ14
NC
VSS
UDM
A B
VSSQ
UDQS
UDQS
VDDQ
DQ15
VSSQ
DQ9
VSSQ
DQ8
VDDQ
DQ12
VDDQ
DQ11
C D
V DDQ
UDQ2
VDDQ
DQ13
VSSQ
NC
VSSQ
LDQS
VDD
DQ6
VSS
LDM
E F G
VSSQ
LDQS
VDDQ
DQ7
VSSQ
DQ1
VSSQ
DQ0
VDDQ
DQ4
VDDQ
DQ3
V DDQ
DQ2
VDDQ
DQ5
VSSQ V REF
CKE
H J
VSSQ
CK CK
V DDL
VSS
WE
V SSDL
RAS
V DD
ODT
K L
NC/BA2
BA0 A10/AP
BA1 A1
CAS A2
CS A0
M N
V DD
V SS
A3 A7
A5 A9
A6 A11
A4 A8
P R
VSS
VDD
A12
NC
NC
NC/A13
MPPT0110
Figure 3 Notes
Pin Configuration P-TFBGA-84 (x16) Top View, see the balls throught the package
1. UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower byte 2. UDM is the data mask signal for the upper byte UDQ[7:0], LDM is the data mask signal for the lower byte LDQ[7:0]
3. Ball position L1 will be used for BA2 on 1-Gbit memory densities and higher
Data Sheet
15
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1.5
Table 6
512Mbit DDR2 Addressing
512 Mbit DDR2 Addressing 128 Mb x 4 4 BA[1:0] A10 / AP A[13:0] A11, A[9:0] 4 1024 (1K) 64 Mb x 8 4 BA[1:0] A10 / AP A[13:0] A[9:0] 10 8 1024 (1K) 32 Mb x 16 4 BA[1:0] A10 / AP A[12:0] A[9:0] 10 16 2048 (2K)
1) 2) 3)
Configuration Number of Banks Bank Address Auto-Precharge Row Address Column Address Number of I/Os Page Size [Bytes]
1) Refered to as 'colbits' 2) Refered to as 'org' 3) org PageSize = 2 colbits x ------8
Note
Number of Column Address Bits 11
[ Bytes ]
1.6
Table 7 Symbol CK, CK
Input/Output Functional Description
Input/Output Functional Description Type Input Function Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both directions of crossing). Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Chip Select: All commands are masked when CS is registered high. CS provides for external rank selection on systems with multiple ranks. CS is considered part of the command code. On Die Termination: ODT (registered high) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM signal for x4 and DQ, DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE
Input
Data Sheet
16
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview Table 7 Symbol Input/Output Functional Description Type Function Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for x16 components and control the lower or upper bytes. For x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1) command. Bank Address Inputs: BA[1:0] define to which bank an Activate, Read, Write or Precharge command is being applied. BA[1:0] also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS(1) cycle. Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA[1:0]. The address inputs also provide the op-code during Mode Register Set commands. Row address A13 is used on x4 and x8 components only. Data Inputs/Output: Bi-directional data bus. DQ[0:3] for x4 components, DQ[0:7] for x8 components, DQ[0:15] for x16 components. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the x16, LDQS corresponds to the data on LDQ[7:0]; UDQS corresponds to the data on UDQ[7:0]. The data strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. Read Data Strobe: For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1) for read timing. RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on x8 components. No Connect: no internal electrical connection is present
DM, LDM, UDM Input
BA[1:0]
Input
A[13:0]
Input
DQx DQS, (DQS) LDQS, (LDQS), UDQS,(UDQS)
Input/ Output Input/ Output
RDQS, (RDQS) Input/ Output
NC
--
VDDQ VSSQ VDDL VSSDL VDD VSS VREF
(BA2), A[15:14]
Supply DQ Power Supply: 1.8 V 0.1 V Supply DQ Ground Supply DLL Power Supply: 1.8 V 0.1 V Supply DLL Ground Supply Power Supply: 1.8 V 0.1 V Supply Ground Supply Reference Voltage -- BA2, A[15:14] are additional address pins for future generation DRAMs and are not connected on this component.
Data Sheet
17
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
1.7
Block Diagrams
DQS, DQS
Receivers
CK, CK
DLL
DQS
Drivers
2
DQ0DQ3, DM
1
Data
D QS Generator
Input Register 1 1
1
1
1
4
4
4 4 4
4
COL0,1
Mask
Data
MUX
rite W FIFO & D rivers
4
4
4
4
16
4
Read Latch
16
Bank3
16
Bank 0 Memo ry Array (16384x 51 16) 2x
Sense Am plifier
I/OGating DM M askLogic
Bank1
8192
512 (x16) olumn C lumn Co C Decoder olu mn Decoder Colum Decon der er Decod
Bank2
16
Bank0 Row-Address Latch & Decoder
Bank Control Logic
9
Row-Address MUX
Refresh Counter
Control Logic
Command D ecode
Mode R egisters
16
Address Register
A0 -A13, BA0, BA1
CKE CK CK
CS WE CAS RAS
16
11 Column-Address Counter/Latch
16
2
16
14
2
2
COL 0, 1
16384
MPBT0040
Figure 4 Notes
Block Diagram 32 Mbit x 4 I/O x 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
1. 64Mbit x 4 Organisation with 14 Row, 2 Bank and 11 Column External Addresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the
Data Sheet
18
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
CK, CK
COL0,1
1
1
1
4
4
4
4
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
CK, CK
DLL
DQS
Drivers
DQ0DQ7, DM
1
1
DQS, DQS
Receivers
Data
DQS Generator
Input Register 1 1
1
1
1
8
8
8 8 8
8
COL0,1
Mask
Data
MUX
Write FIFO & Drivers
8
8
8
8
32
4
Read Latch
32
Bank3
32
Bank0 Memory Array (16384x 256 x 32)
Sense Amplifier
I/O Gating DM Mask Logic
Bank1
8192
256 (x32) Column Column Decoder Column Decoder Column Decoder Decoder
Bank2
32
Bank0 Row-Address Latch & Decoder
16384
Bank Control Logic
8
Row-Address MUX
Refresh Counter
Control Logic
Command Decode
Mode Registers
16
Address Register
16
A0 - A13, BA0, BA1
CKE CK CK
CS WE CAS RAS
10 Column-Address Counter/Latch
16
14
2
16
2
2
COL0,1
MPBT0050
Figure 5 Notes
Block Diagram 16 Mbit x 8 I/O x 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
1. 64Mb x 8 Organisation with 14 Row, 2 Bank and 10 Column External Addresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the
Data Sheet
19
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
CK, CK
COL0,1
1
1
1
8
8
8
8
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Overview
LDQ0LDQ7, LDM
CK, CK
DLL
1 DQS Generator
DQS
Drivers
UDQ0UDQ7, UDQM
Receivers
Data
16
16
16
2
16
LDQS, LDQS 16 2
Input Register 2 2
2
16
2
COL0,1
Mask
Data
MUX
Write FIFO & Drivers
16
16
16
16
64
8
Read Latch
64
Bank3
64
Bank0 ory Mem Array ) (16384x256 x64
Sense Amplifier
I/O Gating DMMask Logic
Bank1
16384
x64) 256 ( Column Column r Decode Column Decoder Column Decoder Decoder
Bank2
64
Bank0 Row-Address Latch & Decoder
Bank Control Logic
8
Row-Address MUX
Refresh Counter
Control Logic
Command Decode
ode M Registers
15
Address Register
A0 - A12, BA0, BA1
CKE CK CK
CS WE CAS RAS
15
10 Column-Address Counter/Latch
15
13
2
15
2
2
COL 0, 1
8192
MPBT0060
Figure 6 Notes
Block Diagram 8 Mbit x 16 I/O x 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals.
1. 32 Mb x 16 Organisation with 13 Row, 2 Bank and 10 Column External Adresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the
Data Sheet
20
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
CK, CK
COL0,1
16
16
16
16
2
2
2
UDQS, UDQS
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2
2.1
Functional Description
Simplified State Diagram
Initialization Sequence
Auto Refreshing tRFC
REFA
REF
SX
CKEL Self Refresh
RE
FS
CKEL Precharge PD
PD_entry CKEH
AC T
Idle
MRS tMRD
Setting MRS or EMRS
Activating tRCD WL + BL/2 + WR Writing_AP tRP Precharging
PRE
RL + BL/2 + tRTP Reading_AP
PRE
Writing
Wr
Re
Write
ad
_A
Read_AP
Write_AP
P
Wr it e _A P
Read Reading
CKEL PD_entry CKEH
i te
Re
ad
Active PD
Bank Active
Automatic Sequence Command Sequence
MPFT0010
Figure 7
Simplified State Diagram bank, enabling / disabling on-die termination, Power-Down entry / exit - among other things are not captured in full detail.
Note: This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and thecommands to control them. In particular situations involving more than one
Data Sheet
21
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.2
Basic Functionality
select the row for x4 and x8 components, A[12:0] select the row for x16 components. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accessed. BA[1:0] select the bank, A[13:0]
2.2.1
Power On and Initialization
DDR2 SDRAM's must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 x VDDQ and ODT at a low state (all other inputs may be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Maximum power up interval for VDD / VDDQ is specified as 10.0 ms. The power interval is defined as the amount of time it takes for VDD / VDDQ to power-up from 0 V to 1.8 V 100 mV. At least one of these two sets of conditions must be met: - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND - Vref tracks VDDQ/2 or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 s.. Apply NOP or Deselect commands and take CKE high. Wait minimum of 400 ns, then issue a Precharge-all command. Issue EMRS(2) command. To issue EMRS(2) command, provide "low" to BA0 and "high" to BA1. 6. Issue EMRS(3) command. To issue EMRS(3) command, provide "high" to BA[1:0]. 7. Issue EMRS(1) to enable DLL. To issue "DLL Enable" command, provide "low" to A0 and "high" to BA0 and "low" to BA1 and A13. 8. Issue a MRS command for "DLL reset". To issue DLL reset command, provide "high" to A8 and "low" to BA[1:0] and A13. 9. Issue Precharge-all command. 10. Issue 2 or more Auto-refresh commands. 11. Issue a MRS command with low on A8 to initialize device operation (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute Off Chip Driver impedance adjustment ( OCD Calibration). If OCD calibration is not used, EMRS OCD Default command (A9 = A8 = A7 = 1) followed by EMRS OCD Calibration Mode Exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS(1). 13. The DDR2 SDRAM is now ready for normal operation.
2. 3. 4. 5.
Data Sheet
22
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
CK, CK
CKE ODT "low"
400 ns
NOP PRE ALL
tRP
EMRS(2)
tMRS
tMRS
tMRS
tMRS
MRS PRE ALL
tRP
tRFC
1st Auto refresh 2nd Auto refresh
tRFC
MRS
tMRS
Follow OCD flowchart
tMRS
EMRS(1) OCD Any Command
EMRS(3)
EMRS(1)
EMRS(1) OCD
min. 200 cycles to lock the DLL
Extended Mode Register(1) Set with DLL enable Mode Register Set with DLL reset Mode Register Set w/o DLL reset
OCD Drive(1) or OCD default
OCD calibration mode exit
Figure 8
Initialization Sequence after Power Up
2.2.2
Programming the Mode Register and Extended Mode Registers
must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Either MRS or EMRS Commands are activated by the low signals of CS, RAS, CAS and WE at the positive edge of the clock. When both bank addresses BA[1:0] are low, the DDR2 SDRAM enables the MRS command. When the bank addresses BA0 is high and BA1 is low, the DDR2 SDRAM enables the EMRS(1) command. The address input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and DLL Reset do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents.
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive CAS latency, driver impedance, On Die Termination (ODT), single-ended strobe and Off Chip Driver impedance adjustment (OCD) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MRS) or Extended Mode Registers (EMRS(#)) can be altered by reexecuting the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. Also any programming of EMRS(2) or EMRS(3) must be followed by programming of MRS and EMRS(1). After initial power up, all MRS and EMRS Commands
2.2.2.1
DDR2 SDRAM Mode Register Set (MRS)
and clock cycle requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields depending on functionality. Burst length is defined by A[2:0] with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A[6:4]. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A[11:9] are used for write recovery time (tWR) definition for Auto-Precharge mode. With address bit A12 two Power-Down modes can be selected, a "standard mode" and a "low-power" Power-Down mode, where the DLL is disabled. Address bit A13 and all "higher" address bits have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities.
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA[1:0], while controlling the state of address pins A[13:0]. The DDR2 SDRAM should be in all bank precharged (idle) mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command Data Sheet 23
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
MR Mode Register Definition
BA1 0 BA0 0 A13 01) A12 PD w A11 A10 WR w A9
(BA[1:0] = 00B)
A8 DLL
w
A7 TM
w
A6
A5 CL w
A4
A3 BT w
A2
A1 BL w
A0
reg. addr
1) A13 is only available for x4 and x8 configuration.
Field Bits BL [2:0]
Type1) Description w Burst Length Number of sequential bits per DQ related to one read/write command. 010 4 011 8 Burst Type See Table 12 for internal address sequence of low order address bits; see Chapter 2.6.2. 0 Sequential 1 Interleaved CAS Latency Number of clock cycles from read command to first data valid window; see Chapter 2.6.1. Note: All other bit combinations are RESERVED. 010 011 100 101 2 2) 3 4 5
BT
3
w
CL
[6:4]
w
TM
7
w
Test Mode 0 Normal mode 1 Vendor specific test mode DLL Reset Reset of DLL is required after application of a stable clock; see . 0 No 1 Yes Write Recovery Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR[cycles] tWR(ns) / tCK(ns) The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing. WRmin is determined by tCK,max and WRmax is determined by tCK,min. Note: All other bit combinations are RESERVED. 001 010 011 100 101 2 3 4 5 6
DLL
8
w
WR
[11:9] w
PD
12
w
Active Power-Down Mode Select 0 Fast exit (use tXARD) 1 Slow exit (use tXARDs)
1) w = write only register bits 2) CAS Latency 2 is optional for Jedec compliant devices. This option is implemented in this device but is neither tested nor guaranteed.
Data Sheet
24
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.2.3
DDR2 SDRAM Extended Mode Register Set (EMRS(1))
BAO, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.
The Extended Mode Register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE, BA1 and high on EMR(1) Extended Mode Register Definition
BA1 0 BA0 1 A13 01) A12 Q OFF A11 A10 A9
(BA[1:0] = 01B)
A8 A7 A6 Rtt w A5 A4 AL w A3 A2 Rtt w A1 DIC w A0 DLL w
RDQS DQS w w
OCD Program w
reg. addr
1) A13 is only available for x4 and x8 configuration.
Field DLL
Bits 0
Type1) Description w DLL Enable The DLL must be enabled for normal operation. See . 0 Enable 1 Disable Off-chip Driver Impedance Control 0 Normal (Driver Size = 100%) 1 Weak (Driver Size = 60%) Nominal Termination Resistance of ODT Note: All other bit combinations are RESERVED. 00 10 01 (ODT disabled) 75 Ohm 150 Ohm
DIC
1
w
RTT
2,6
w
AL
[5:3]
w
Additive Latency The additive latency must be programmed into the device to delay all read and write commands; see Chapter 2.5. Note: All other bit combinations are RESERVED. 000 001 010 011 100 0 1 2 3 4
Data Sheet
25
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description Field Bits Type1) Description (cont'd) w Off-Chip Driver Calibration Program Every calibration mode command should be followed by "OCD calibration mode exit" before any other command will be issued; see Chapter 2.3. 000 OCD calibration mode exit, maintain setting 001 Drive 1 010 Drive 0 100 Adjust mode
Note: When Adjust Mode is issued, AL from previously set value must be applied.
OCD [9:7] Program
111 OCD calibration default
Note: After setting to default, OCD mode needs to be exited by setting A[9:7] to 000.
DQS
10
w
Complement Query Strobe (DQS, RDQS Output) If enabled the complement query strobe (DQS output) is driven high one clock cycle before valid query data (DQ) is driven onto the data bus; see Chapter 2.6.3. 0 Enable 1 Disable Read Data Strobe Output (RDQS, RDQS) 0 Disable 1 Enable Output Disable Disabling the DRAM outputs (DQ, DQS, DQS, RDQS, RDQS) allows users to measure IDD during Read operations without including the output buffer current. 0 Output buffers enabled 1 Output buffers disabled
RDQS
11
w
Qoff
12
w
1) w = write only register bits
A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables ODT (On-Die termination) and sets the Rtt value. A[5:3] are used for additive latency settings and A[9:7] enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals, A11 disables or enables RDQS. Address bit A12 have to be set to "low" for normal Single-ended and Differential Data Strobe Signals Table 8 lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A[11:10] address bits in EMRS. RDQS and RDQS are available in x8 components only. Table 8 EMRS(1)
operation. With A12 set to "high" the SDRAM outputs are disabled and in Hi-Z. "High" on BA0 and "low" for BA1 have to be set to access the EMRS(1). A13 and all "higher" address bits have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities. Refer to Mode Register Definition (BA[1:0] = 00B).
If RDQS is enabled in x8 components, the DM function is disabled. RDQS is active for reads and don't care for writes.
Single-ended and Differential Data Strobe Signals Strobe Function Matrix RDQS Hi-Z Hi-Z RDQS Hi-Z DQS DQS DQS DQS DQS DQS DQS Hi-Z DQS Hi-Z differential DQS signals single-ended DQS signals differential DQS signals single-ended DQS signals Signaling
A11 A10 RDQS/DM (RDQS Enable) (DQS Enable) 0 (Disable) 0 (Disable) 1 (Enable) 1 (Enable) 0 (Enable) 1 (Disable) 0 (Enable) 1 (Disable) DM DM RDQS RDQS
DLL Enable/Disable
Data Sheet
26
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically reenabled upon exit of Self-Refresh operation. Any time Output Disable (Qoff) Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current. the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
2.2.4
EMRS(2)
BA1,while controlling the states of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.
The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and must be programmed when setting the mode register during initialization. The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be written after Power-up for proper operation. The extended mode register EMRS(2) is written by asserting low on CS, RAS, CAS, WE, BA0 and high on EMRS(2) Programming Extended Mode Register Definition
BA1 1 BA0 0 A13 A12 A11 A10 A9
(BA[1:0] = 01B)
A8 A7 01)2) reg.addr A6 A5 A4 A3 A2 A1 A0
1) A13 is only available for x4 and x8 configuration. 2) Must be programmed to "0"
2.2.5
EMRS(3)
programmed to 0 when setting the mode register during initialization.
The Extended Mode Register EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be EMRS(3) Programming Extended Mode Register Definition
BA1 1 BA0 1 A13 A12 A11 A10 A9
(BA[1:0] = 01B)
A8 A7 01)2) reg. addr A6 A5 A4 A3 A2 A1 A0
1) A13 is only available for x4 and x8 configuration. 2) Must be programmed to "0"
Data Sheet
27
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.3
Off-Chip Driver (OCD) Impedance Adjustment
command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefully controlled depending on system environment.
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other
Start EMRS: OCD calibration mode exit
EMRS: Drive (1) DQ & DQS High; DQS Low
EMRS: Drive (0) DQ & DQS Low; DQS High
Test
ALL OK
ALL OK
Test Need Calibration
Need Calibration EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: Enter Adjust Mode
EMRS: Enter Adjust Mode
BL = 4 code input to all DQs Inc, Dec or NOP
BL = 4 code input to all DQs Inc, Dec or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
MPFT0020
Figure 9 Note
OCD Impedance Adjustment Flow Chart
1. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment
Data Sheet
28
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and
Table 9
voltage conditions. Output driver characteristics for OCD calibration default are specified in Table 10. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A[9:7] as '000' in order to maintain the default or calibrated value.
Output driver characteristics for OCD calibration
A9 0 0 0 1 1
A8 0 0 1 0 1
A7 0 1 0 0 1
Operation OCD calibration mode exit Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high Adjust mode OCD calibration default
OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to DDR2 SDRAM as in Table 10. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 in Table 10 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and
Table 10 Off- Chip-Driver Adjust Program
after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied.
4 bit burst code inputs to all DQs DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 DT2 0 0 1 0 0 0 1 0 1 DT3 0 1 0 0 0 1 0 1 0
Operation Pull-up driver strength NOP (no operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Pull-down driver strength NOP (no operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Reserved
Other Combinations
Data Sheet
29
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS / tDH should be met as Figure 10. Input data pattern for adjustment, DT[0:3] is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment.
CK, CK
CMD
EMRS(1)
NOP
NOP
NOP
NOP
NOP
NOP
EMRS(1)
NOP
WL
DQS DQS_in
tWR
tDS tDH
DQ_in DT0 DT1 DT2 DT3
DM
OCD adjust mode
OCD calibration mode exit
OCD1
Figure 10 Drive Mode
Timing Diagram Adjust Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "enter drive
mode" command and all output drivers are turned-off
tOIT after "OCD calibration mode exit" command. See
Figure 11.
CK, CK
CMD
EMRS(1) tOIT
NOP
NOP
NOP
NOP
EMRS(1) tOIT
NOP
NOP
NOP
DQS_in
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1)
DQ_in
DQS high for Drive(0)
Enter Drive Mode
OCD calibration mode exit
OCD2
Figure 11
Timing Diagram Drive Mode
Data Sheet
30
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.4
On-Die Termination (ODT)
the ODT control pin. UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.
On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, DQS, DQS, DM for x4 and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the same pin), RDQS for x8 configuration via the ODT control pin. DQS is terminated only when enabled in the EMRS(1) by address bit A10 = 0. For x8 configuration RDQS is only terminated, when enabled in the EMRS(1) by address bits A10 = 0 and A11 = 1. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
VDDQ
VDDQ
sw1
sw2
Rval1 DRAM Input Buffer Rval1
Rval2 Input Pin Rval2
sw1
sw2
VSSQ
VSSQ
Figure 12
Functional Representation of ODT Target Rtt = 0.5 x Rval1 or 0.5 x Rval2. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS(1) address bits A6 & A2.
Data Sheet
31
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 11 Input Pin x4 components DQ[3:0] DQS DQS DM x8 components DQ[7:0] DQS DQS RDQS RDQS DM x16 components DQ[15:0] LDQS LDQS UDQS UDQS LDM UDM X X 0 X 0 X X X X X X X X X X X 0 X 0 X X X X 1 1 0 X X 0 X X X X X ODT Truth Table EMRS(1) Address Bit A10 EMRS(1) Address Bit A11 organisations (x4, x8 and x16). To activate termination of any of these pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2.
Note: X = don't care; 0 = bit set to low; 1 = bit set to high ODT timing modes Depending on the operating mode synchronous or asynchronous ODT timings apply. Synchronous timings (tAOND, tAOFD, tAON and tAOF) apply for all modes, when the on-die DLL is enabled. These modes are: * * * Active Mode Standby Mode Fast Exit Active Power Down Mode (with MRS bit A12 is set to "0") Asynchronous ODT timings (tAOFPD, tAONPD) apply when the on-die DLL is disabled. These modes are: * * Slow Exit Active Power Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode
Data Sheet
32
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
CK, CK
CKE
see note 1 t t
IS
ODT
IS
tAOND (2 tck)
tAOFD (2.5 tCK)
Rtt
DQ
tAON(min)
tAOF(min) tAON(max) tAOF(max)
ODT01
Figure 13 Note:
ODT Timing for Active and Standby (Idle) Modes
1. Synchronous ODT timings apply for Active Mode and Standby Mode with CKE "high" and for the "Fast Exit" Active Power Down Mode (MRS bit A12 set to "0"). In all these modes the on-die DLL is enabled. 2. ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins
T 0
CK, CK
to turn on. ODT turn on time max. (tAON max) is when the ODT resistance is fully on. Both are measured from tAOND. 3. ODT turn off time min. (tAOF min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF max) is when the bus is in high impedance. Both are measured from tAOFD.
T 4 T 5 T 6 T 7 T 8
T 1
T 2
T 3
CKE
"low"
tIS
ODT
tIS
tAOFPD,min tAOFPD,max
DQ
Rtt
tAONPD,min tAONPD,max
ODT02
Figure 14
ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit)
(Asynchronous ODT timings)
Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and "Slow Exit" Active Power Down Mode (MRS bit A12 set to "1"), where the on-die DLL is disabled in this mode of operation.
Data Sheet
33
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description Mode entry: As long as the timing parameter tANPD, min is satisfied when ODT is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. If tANPD, min is not satisfied, asynchronous timing parameters apply.
T5 CK, CK
T4
T3
T2
T1
T 0
T 1
T 2
tANPD (3 tCK)
CKE t
IS
ODT turn-off, tANPD >= 3 tCK :
t ODT
IS
RTT
ODT turn-off, tANPD <3 tCK :
ODT
Synchronou timings apply
tAOFD
RTT
tAOFPDmax ODT turn-on, tANPD >= 3 tCK :
t
IS
Asynchronou timings apply
ODT
tAOND
RTT
t
IS
Synchronou timings apply
ODT turn-on, tANPD < 3 tCK : tAONPDmax
ODT
RTT
ODT0 3
Asynchronou timings apply
Figure 15
ODT Mode entry Timing Diagram
Data Sheet
34
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description Mode exit: As long as the timing parameter tAXPD, min is satisfied when ODT is turned on or off after exiting these powerdown modes, synchronous timing parameters can be
T 0 T 1 T 5 T 6
applied. If tAXPD, min is not satisfied, asynchronous timing parameters apply.
T 7
T 8
T 9
T10
CK, CK
t IS
CKE
tAXPD
ODT turn-off, tAXPD >= tAXPDmin: Synchronous timings apply
ODT
t IS
Rtt
ODT turn-off, tAXPD < tAXPDmin: Asynchronous timings apply
ODT
tAOFD t IS
Rtt
ODT turn-on, tAXPD >= tAXPDmin: Synchronou s timings apply
ODT
tAOFPDmax t IS
Rtt
t IS ODT turn-on, tAXPD < tAXPDmin: Asynchronous timings apply tAONPDmax
ODT04
tAOND
ODT
Rtt
Figure 16
ODT Mode exit Timing Diagram
2.5
Bank Activate Command
(with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD, min specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCD, min is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, 35 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA[1:0] are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank for x4 and x8 organised components. For x16 components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
Data Sheet
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). In order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supplying capability, certain restrictions on operation of the 8 banks must be observed. There are two rules. One for restricting the number of sequential Active commands that can be issued and another for allowing more time for RAS precharge for a Precharge-All command. The rules are as follows: 1. Sequential Bank Activation Restriction (JEDEC ballot item 1293.15): No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by deviding tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clocks N + 1 through N + 9. 2. Precharge All Allowance: tRP for a Precharge-All command will equal to tRP + 1 tCK, where tRP is the value for a single bank precharge.
T 0 CK, CK
T 1
T 2
T 3
T 4
T n
Tn+1
Tn+2
Tn+3
Internal RAS-CAS delay tRCDmin. Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. Bank B Addr. Bank A Row Addr.
Address
NOP
Bank A to Bank B delay tRRD. additive latency AL=2 Read A Begins Posted CAS Read B Bank A Precharge
NOP
Command
Bank A Activate
Posted CAS Read A
Bank B Activate
Bank B Precharge
Bank A Activate
tRAS Row Active Time (Bank A) tCCD
tRP Row Precharge Time (Bank A) tRC Row Cycle Time (Bank A)
ACT
Figure 17
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2
2.6
Read and Write Commands and Access Modes
In case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely addressable segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments (defined by CA[8:0] beginning with the column address supplied to the device during the Read or Write Command (CA[9:0] & A11). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. In case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely addressable double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 double segments (defined by CA[7:0]) 36 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667 Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA[9:0] & CA11).
Data Sheet
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description beginning with the column address supplied to the device during the Read or Write Command (CA[9:0] & CA11). A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation (BL = 8) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see Chapter 2.6.6.
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T12
CK, CK
CMD
READ A
NOP tCCD
READ B
NOP tCCD
READ C
NOP
NOP
NOP
NOP
NOP
DQS, DQS
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
Dout C0
Dout C1
Dout C2
Dout C3
RB
Figure 18
Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
2.6.1
Posted CAS
the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCD, min, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCD, min period, the Read Latency is also defined as RL = AL + CL.
5 6 7 8 9 10 11
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and
0
CK, CK
1
2
3
4
WL = RL -1 = 4 CMD DQS, DQS
Activate Bank A Read Bank A Write Bank A
AL = 2 tRCD RL = AL + CL = 5 DQ
CL = 3
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS1
Figure 19
Activate to Read Timing Example : Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Data Sheet
37
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
WL = RL -1 = 4 CMD DQS, DQS
Activate Bank A Read Bank A Write Bank A
AL = 2
CL = 3
tRCD RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7 Din0 Din1 Din2 Din3
DQ
PostCAS3
Figure 20
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
0 1 2 3 4 5 6 7 8 9 10 11
CK, CK AL = 0 CMD DQS, DQS
Activate Bank A Read Bank A Write Bank A
CL = 3
WL = RL -1 = 2
tRCD RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
DQ
PostCAS2
Figure 21
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay = tRCDmin: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13
CK, CK WL = 3 CMD DQS, DQS RL = 4 DQ
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
Activate Bank A
Read Bank A
Write Bank A
tRCD > tRCDmin.
PostCAS5
Figure 22
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay > tRCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
2.6.2
Burst Mode Operation
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A[2:0] of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the 38 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst Data Sheet
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or Table 12 Burst Length and Sequence Starting Address (A2 A1 A0) 000 001 010 011 8 000 001 010 011 100 101 110 111 Note: 1. Page length is a function of I/O organization: 128Mb X 4 organization (CA[9:0], CA11); Page Length = 1 kByte; 64Mb X 8 organization (CA[9:0]); Page Length = 1 kByte; 32Mb X 16 organization (CA[9:0]); Page Length = 2 kByte 2. Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 write burst when burst length = 8 is used, see the Chapter 2.6.6. A Burst Stop command is not supported on DDR2 SDRAM devices.
Burst Length 4
2.6.3
Read Command
data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS(1)).
The Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the
Data Sheet
39
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
t CH
CLK CLK, CLK CLK
t CL
t CK
t DQSCK
DQS DQS, DQS DQS
t AC
t RPRE
DQ
t LZ
Dout Dout Dout
t RPST
Dout
t HZ
t DQSQmax t QH
Figure 23 Basic Read Timing Diagram
t DQSQmax
t QH
DO-Read
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
CK, CK
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
NOP <= tDQSCK
NOP
NOP
NOP
DQS, DQS
AL = 2 RL = 5
DQ
CL = 3
Dout A0 Dout A1 Dout A2 Dout A3
BRead523
Figure 24
Burst Operation Example 1: RL = 5 (AL = 2, CL = 3, BL = 4)
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
Data Sheet
40
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
CK, CK
CM D
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
<= tDQSCK DQS, DQS CL = 3
DQ' s
RL = 3
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
BRead303
Figure 25
Read Operation Example 2: RL = 3 (AL = 0, CL = 3, BL = 8)
T 0
T 1
T 3
T 4
T 5
T 6
T 7
T 8
T 9
CK, CK
CMD
Posted CAS READ A
NOP
NOP
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
BL/2 + 2
DQS, DQS
WL = RL - 1 = 4 RL = 5
DQ
Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3
BRBW514
Figure 26
Read followed by Write Example: RL = 5, WL = (RL-1) = 4, BL = 4
The minimum time from the read command to the write command is defined by a read-to-write turn-around time, which is BL/2 + 2 clocks.
Data Sheet
41
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
CK, CK
CMD
Post CAS READ A
NOP
Post CAS READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
AL = 2
DQ
CL = 3 RL = 5
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3
SBR523
Figure 27
Seamless Read Operation Example: RL = 5, AL = 2, CL = 3, BL = 4
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
T 9
T10
CK, CK
CMD
Post CAS READ A
NOP
NOP
NOP
Post CAS READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
CL = 3
DQ
RL = 3
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7
SBR_BL8
Figure 28
Seamless Read Operation Example: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
2.6.4
Write Command
successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing parameter (see AC & DC Operating Conditions) and is not the programmed value for WR in the MRS.
The Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL 1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on Data Sheet 42
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
t DQSH
DQS DQS, DQS DQS
tDQSL
t WPRE
Din Din Din Din
t WPST
t DS
Figure 29 Basic Write Timing
T0
CK, CK
t DH
T1
T2
T3
T4
T5
T6
T7
T9
CMD
P o st C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re c h a rg e
<= tDQSS
DQS, DQS
C o m p le tio n o f th e B u rs t W rite
WL = RL-1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW543
Figure 30
Example Timing Diagram : Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T0 T1 T2 T3 T4 T5 T6 T7 T9
CK, CK
CMD
P ost C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
P recha rge
B ank A A ctiva te
<= tDQSS
DQS, DQS
C om pletion of the B urst W rite
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
tR P
BW322
Figure 31
Write Operation Example: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
Data Sheet
43
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
W rite to R ea d = (C L - 1)+ B L/2 + tW T R (2) = 6
CMD
NOP NOP NOP NOP P o st C A S READ A NOP NOP NOP NOP
DQS, DQS
W L = RL - 1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
A L= 2 tW T R R L= 5
C L= 3
BWBR
Figure 32
Write followed by Burst Read Example: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + tWTR, where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S W R IT E A
NOP
P o st C A S W R IT E B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
W L = RL - 1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR
Figure 33
Seamless Write Operation Example 1: RL = 5, WL = 4, BL = 4
The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
Data Sheet
44
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
W R IT E A
NOP
NOP
NOP
W R IT E B
NOP
NOP
NOP
NOP
DQS, DQS
W L = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 SBW_BL8
Figure 34
Seamless Write Operation Example 2: RL = 3, WL = 2, BL = 8, non interrupting
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
2.6.5
Write Data Mask
insure matched system timing. Data mask is not used during read cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1).
One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16 components are supported on DDR2 SDRAM's, consistent with the implementation on DDR SDRAM's. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to
t DQSH
DQS DQS, DQS DQS
tDQSL
t WPRE
DQ D D D D
t WPST
t DS
DM
Mask Mask
t DH
Mask Mask
don't care
Figure 35
Write Data Mask Timing
Data Sheet
45
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T9
CMD
W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e
B ank A A ctiva te
<= tDQSS
DQS, DQS
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
tR P
DM
DM
Figure 36
Write Operation with Data Mask Example: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
2.6.6
Burst Interruption
6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end.
Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
Data Sheet
46
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
DQ
Dout A0 Dout A1
Dout A2 Dout A3 Dout B0 Dout B1
Dout B2 Dout B3 Dout B4 Dout B5
Dout B6 Dout B7
RBI
Figure 37
Read Interrupt Timing Example 1: (CL = 3, AL = 0, RL = 3, BL = 8)
T0 T1 T2 T3 T4 T5 T6 T7 T8
C K, C K
CMD
NOP
W R IT E A
NOP
W R IT E B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
DQ
Din A0
Din A1
Din A2
Din A3
Din B0
Din B1
Din B2
Din B3
Dout B4 Din B5
Din B6
Din B7
WBI
Figure 38
Write Interrupt Timing Example 2: (CL = 3, AL = 0, WL = 2, BL = 8)
Data Sheet
47
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.7
Precharge Command
charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued.
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The PreTable 13 A10 LOW LOW LOW LOW HIGH
Bank Selection for Precharge by Address Bits BA0 LOW LOW HIGH HIGH Don't Care BA1 LOW HIGH LOW HIGH Don't Care Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only all banks
Note: The bank address assignment is the same for activating and precharging a specific bank.
2.7.1
Read Operation Followed by a Precharge
A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins. 2. The RAS cycle time (tRC, min) from the previous bank activation has been satisfied. For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks.
T4 T5 T6 T7 T8
The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and 533 speed sorts): Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the Precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum tRAS timing is satisfied.
T0
CK, CK
T1
T2
T3
CMD
P ost C A S READ A
NOP A L + B L /2 clks
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
NOP
NOP
DQS, DQS
AL = 1 CL = 3 RL = 4
DQ
> = tR A S > = tR C > = tR T P
Dout A0
Dout A1
Dout A2
Dout A3
CL = 3
BR-P413
Figure 39
Read Operation Followed by Precharge Example 1: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP 2 clocks 48 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
Data Sheet
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S READ A
NOP A L + B L /2 clks
NOP
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
DQS, DQS
AL = 1 CL = 3 RL = 4
DQ
> = tR A S > = tR C
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
CL = 3 > = tR T P
BR-P413(8)
first 4-bit prefetch
second 4-bit prefetch
Figure 40
Read Operation Followed by Precharge Example 2: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP 2 clocks
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK, CK
CMD
P o st C A S READ A
NOP A L + B L /2 clks
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
NOP
DQS, DQS
AL = 2 RL = 5 CL = 3
DQ
> = tR A S > = tR C > = tR T P CL = 3
Dout A0
Dout A1
Dout A2
Dout A3
BR-P523
Figure 41
Read Operation Followed by Precharge Example 3: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks
Data Sheet
49
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S READ A
NOP A L + B L /2 clo cks
NOP
NOP
P re ch a rg e A
NOP tR P
NOP
NOP
B ank A A ctiva te
DQS, DQS
AL = 2 CL = 4 RL = 6
DQ
> = tR A S > = tR C > = tR T P CL = 4
Dout A0
Dout A1
Dout A2
Dout A3
BR-P624
Figure 42
Read Operation Followed by Precharge Example 4: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
READ A
NOP
NOP
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
A L + B L /2 clks + 1
DQS, DQS
CL = 4 RL = 4
DQ
> = tR A S
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
> = tR T P
BR-P404(8)
first 4-bit prefetch
second 4-bit prefetch
Figure 43
Read Operation Followed by Precharge Example 5: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks
Data Sheet
50
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.7.2
Write followed by Precharge
to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see Chapter 7) and is not the programmed value for tWR in the MRS.
T5 T6 T7 T8
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write
T0
CK, CK
T1
T2
T3
T4
CMD
P ost C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e A
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = 3
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW-P3
Figure 44
T0
CK, CK
Write followed by Precharge Example 1: WL = (RL - 1) = 3, BL = 4, tWR = 3
T1 T2 T3 T4 T5 T6 T7 T9
CMD
P o st C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e A
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW-P4
Figure 45
Write followed by Precharge Example 2: WL = (RL - 1) = 4, BL = 4, tWR = 3
Data Sheet
51
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.8
Auto-Precharge Operation
Auto-Precharge is also implemented for Write Commands.The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command.
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst.
2.8.1
Read with Auto-Precharge
becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTPmin is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTPmin is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command
Data Sheet
52
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o ste d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
A10 ="high" AL + BL/2
DQS, DQS A u to -P re ch a rg e B e g in s
AL = 2
DQ
CL = 3 RL = 5
tRP
Dout A0 Dout A1 Dout A2 Dout A3
tRAS tRCmin.
BR-AP5231
Figure 46
Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o ste d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
NOP
A10 ="high"
tRAS(min) DQS, DQS A u to -P re ch a rg e B e g in s
AL = 2
DQ tRC
CL = 3 RL = 5
Dout A0
tRP
Dout A1 Dout A2 Dout A3
BR-AP5232
Figure 47
Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks
Data Sheet
53
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o ste d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
A10 ="high"
DQS, DQS
AL + BL/2
A u to -P re ch a rg e B e g in s
tRP
AL = 1
DQ
CL = 3 RL = 4
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>= tRTP
BR-AP413(8)2
first 4-bit prefetch
second 4-bit prefetch
Figure 48
Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP 2 clocks
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK, CK
CMD
P o ste d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
NOP
A10 ="high"
DQS, DQS
AL + tRTP + tRP
A u to -P re ch a rg e B e g in s
AL = 1
DQ
CL = 3 RL = 4
Dout A0 Dout A1 Dout A2 Dout A3
tRTP
tRP
BR-AP4133
first 4-bit prefetch
Figure 49
Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP > 2 clocks
Data Sheet
54
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.8.2
Write with Auto-Precharge
1. The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. In DDR2 SDRAM's the write recovery time delay (tWR) has to be programmed into the MRS mode register. As long as the analog tWR timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.
T4 T5 T6 T7
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (tWR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.
T0
CK, CK
T1
T2
T3
CMD
W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A A ctiva te
A10 ="high"
Completion of the Burst Write
A u to -P re ch a rg e B e g in s
DQS, DQS
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR tDAL tRCmin. >=tRASmin.
tRP
BW-AP223
Figure 50
Write with Auto-Precharge Example 1 (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0 T3 T4 T5 T6 T7 T8 T9 T12
CK, CK
CMD
P o s te d C A S W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A A ctiva te
A10 ="high"
DQS, DQS
Completion of the Burst Write
A u to -P re ch a rg e B e g in s
WL = RL-1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR tDAL >=tRC >=tRAS
tRP
BW-AP423
Figure 51
Write with Auto-Precharge Example 2 (WR + tRP Limit): WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4
Data Sheet
55
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.8.3
Read or Write to Precharge Command Spacing Summary
Write w/AP to the Precharge commands to the same banks and Precharge-All commands.
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Table 14 Minimum Command Delays To Command PRECHARGE (to same banks as READ) PRECHARGE-ALL READ w/AP PRECHARGE (to same banks as READ w/AP) PRECHARGE-ALL WRITE PRECHARGE (to same banks as WRITE) PRECHARGE-ALL WRITE w/AP PRECHARGE (to same banks as WRITE w/AP) PRECHARGE-ALL PRECHARGE PRECHARGE (to same banks as PRECHARGE) PRECHARGE-ALL PRECHARGE-ALL PRECHARGE PRECHARGE-ALL
From Command READ
Minimum Delay between "From Command" to "To Command" AL + BL/2 + max(tRTP, 2) - 2 AL + BL/2 + max(tRTP, 2) - 2 AL + BL/2 + max(tRTP, 2) - 2 AL + BL/2 + max(tRTP, 2) - 2 WL + BL/2 + tWR WL + BL/2 + tWR WL + BL/2 + WR WL + BL/2 + WR 1 1 1 1
Units Notes
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
1)2)
1)2) 1)2)
1)2) 2)3)
2)3) 2)
2) 2)
2) 2) 2)
1) RU{tRTP(ns) / tCK(ns)} must be used, where RU stands for "Round Up" 2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or prechargeall, issued to that bank. The precharge period is satisfied after tRP or tRP, all depending on the latest precharge command issued to that bank
3) RU{tWR(ns) / tCK(ns)} must be used, where RU stands for "Round Up"
Data Sheet
56
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.8.4
Concurrent Auto-Precharge
The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different bank, is summarized in Table 15. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized.
DDR2 devices support the "Concurrent AutoPrecharge" feature. A Read with Auto-Precharge enabled, or a Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided externally and on the internal data bus. Table 15 Command Delay Table
From Command To Command (different bank, non-interrupting command) WRITE w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Read w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate
Minimum Delay with Concurrent Auto- Units Precharge Support (CL -1) + (BL/2) + tWTR BL/2 1 BL/2 BL/2 + 2 1
Note
1)
tCK tCK tCK tCK tCK tCK
2)
2)
1) RU{tWTR(ns)/tCK(ns)} must be used where RU stands for "Round Up" 2) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is illegal
2.9
Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.
2.9.1
Auto-Refresh Command
external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the AutoRefresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 x tREFI.
Auto-Refresh is used during normal operation of the DDR2 SDRAM's. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "don't care" during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic interval of tREF(maximum). When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the
Data Sheet
57
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0 CK, CK
"high" CKE
T1
T2
T3
> = tRP
CMD
P re ch a rg e NOP NOP
> = t RFC
AUTO REFRESH NOP AUTO REFRESH NOP
> = t RFC
NOP ANY
AR
Figure 52
Auto Refresh Timing
2.9.2
Self-Refresh Command
clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self-Refresh Exit command is registered, a delay of at least tXSNR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain high for the entire Self-Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after tXSNR expires. NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXSNR. ODT should be turned off during tXSNR. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh Mode.
The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate SelfRefresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered SelfRefresh mode all of the external control signals, except CKE, are "don't care". The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external
Data Sheet
58
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0 CK/CK
T1
T2
T3
T4
T5
Tm
Tn
Tr
tRP tis
CKE
tis tCKE
>=tXSRD
tis
ODT
tAOFD
>= tXSNR
CMD
Self Refresh Entry
NOP
Non-Read Command
Read Command
CK/CK may be halted
CK/CK must be stable
Figure 53 Note:
Self Refresh Timing
1. Device must be in the "All banks idle" state before entering Self Refresh mode. 2. tXSRD ( 200 tCK) has to be satisfied for a Read or a Read
with Auto-Precharge command.
3. tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command 4. Since CKE is an SSTL input, VREF must be maintained during Self Refresh.
2.10
Power-Down
referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In powerdown mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in Table 40.
Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. DRAM design guarantees it's DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is
Data Sheet
59
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description Power-Down Entry Active Power-down mode can be entered after an Activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command. It is also allowed to enter powermode after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied.
T0
CK, CK
Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active powerdown mode entry is allowed when WL + BL/2 + tWTR is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with AutoPrecharge command. In this case the DDR2 SDRAM enters the Precharge Power-down mode.
T1
T2
Tn
Tn+1
Tn+2
CM D
A ctivate
NOP
NOP
NOP
NOP
NOP
V alid C om m and
CKE
tIS tIS tXARD or tXARDS *)
Act.PD 0
Active Power-Down Entry
Active Power-Down Exit
Figure 54
Active Power-Down Mode Entry and Exit after an Activate Command
Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn+1
Tn+2
CMD
READ R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid C om m a nd
CKE DQ S, DQS
tIS
RL + BL/2
tIS tXARD or tXARDS *)
Dout A0 Dout A1 Dout A2 Dout A3
AL = 1
DQ
CL = 3 RL = 4
Active Power-Down Entry
Active Power-Down Exit
Act.PD 1
Figure 55
Active Power-Down Mode Entry and Exit Example after a Read Command: RL = 4 (AL = 1, CL =3), BL = 4
Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Data Sheet 60 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
Tn
Tn+1
Tn+2
CMD
W R IT E
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V alid C o m m and
CKE DQS, DQS
WL + BL/2 + tWTR
tIS tIS
WL = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tWTR
tXARD or tXARDS *)
Active Power-Down Entry
Active Power-Down Exit
Act.PD 2
Figure 56
Active Power-Down Mode Entry and Exit Example after a Write Command: WL = 2, tWTR = 2, BL = 4
Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
Tn
Tn+1
Tn+2
CM D
W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid Com m and
CKE DQS, DQS
WL + BL/2 + WR
tIS
tIS
WL = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR
tXARD or tXARDS *)
Active Power-Down Entry
Active Power-Down Exit
Act.PD 3
Figure 57
Active Power-Down Mode Entry and Exit Example after a Write Command with AP: WL = 2, WR = 3, BL = 4
Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. WR is the programmed value in the MRS mode register.
Data Sheet
61
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
CK, CK
T1
T2
T3
Tn
Tn+1
Tn+2
CMD
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
Valid Command
NOP
tIS
CKE
tIS tRP tXP
Precharge Power-Down Entry
Precharge Power-Down Exit
Figure 58
Precharge Power Down Mode Entry and Exit
Note: "Precharge" may be an external command or an internal precharge following Write with AP.
T0
CK, CK
T1
T2
T3
T4
Tn
CMD
Auto Refresh
tRFC tXP
Valid Command
CKE
tis
CKE can go low one clock after an Auto-Refresh command When tRFC expires the DRAM is in Precharge Power-Down Mode
ARPD
Figure 59
T0
CK, CK
Auto-Refresh command to Power-Down entry
T1 T2 T3 T4 T5 T6 T7
CMD
MRS or EMRS
t MRD
CKE Enters Precharge Power-Down Mode
MRS_PD
Figure 60
MRS, EMRS command to Power-Down entry
Data Sheet
62
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.11 2.11.1
Other Commands No Operation Command
registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
The No Operation Command (NOP) should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is
2.11.2
Deselect Command
when CS is brought high, the RAS, CAS, and WE signals become don't care.
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs
2.12
Input Clock Frequency Change
satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL relock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency.
During operation the DRAM input clock frequency can be changed under the following conditions: * * During Self-Refresh operation DRAM is in Precharge Power-down mode and ODT is completely turned off.
The DDR2-SDRAM has to be in Precharged Powerdown mode and idle. ODT must be already turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been
T0
CK, CK
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Tz
CMD
NOP
NOP
NO P
NOP
NOP
NOP
NOP
NOP
NO P
D LL RESET
NO P
V alid C o m m a nd
CKE
tRP tAOFD
Minimum 2 clocks required before changing the frequency Frequency Change occurs here Stable new clock before power-down exit
tXP
200 clocks ODT is off during DLL RESET
Frequ.Ch.
Figure 61
Input Frequency Change Example during Precharge Power-Down mode
Data Sheet
63
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.13
Asynchronous CKE Low Reset Event
contents of the memory array. If this event occurs, the memory controller must satisfy a time delay (tdelay) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See Chapter 7.
In a given system, Asynchronous Reset event can occur at any time without prior knowledge. In this situation, memory controller is forced to drop CKE asynchronously low, immediately interrupting any valid operation. DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation, the DRAM is not guaranteed to preserve the
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an asynchronous reset event
Clocks can be turned off after this point
Figure 62
Asynchronous Low Reset Event
Data Sheet
64
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Truth Tables
3
Table 16 Function
Truth Tables
Command Truth Table CKE CS RAS CAS WE BA0 A[13:11] A10 A[9:0] BA1 Previous Current Cycle Cycle H H L H H H H H H H H X X L H L L L H L L L L L L L L H H L H L L L L X L L L H H H H H X X H X H L L L X H H H L L L L H X X H X H L H H X L L H L L H H H X X H X H X X X X
4)8)
Notes
1)2)3)4)
(Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge No Operation Device Deselect Power Down Entry Power Down Exit
H H H L H H H H H H H H H L
BA X X X BA X BA BA BA BA BA X X X
OP Code X X X X X Column Column Column Column X X X X X X L H L H L H X X X X X X X X
5)
6) 6) 5)
Single Bank Precharge H
Row Address Column Column Column Column X X X
5) 5)7) 5)7)
5)7) 5)7)
8)
1) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 3) "X" means "H or L (but a defined logic level)". 4) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode Register. 6)
VREF must be maintained during Self refresh Operation
7) Burst reads or writes at BL = 4 cannot be terminated. 8) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in Chapter 2.9.
Data Sheet
65
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Truth Tables
Table 17
Clock Enable (CKE) Truth Table for Synchronous Transitions Command (N)2) 3) Action (N)2) Notes4)5) Previous Cycle6) Current Cycle6) RAS, CAS, WE, CS (N-1) (N)
Current State1) CKE
Power-Down Self Refresh Bank(s) Active All Banks Idle
L L L L H H H
L H L H L L L H
X X
Maintain Power-Down Maintain Self Refresh
7)8)11) 9)10)11)7) 11)8)12) 9)13)14)12) 9)10)15)11)7)
DESELECT or NOP Power-Down Exit DESELECT or NOP Self Refresh Exit DESELECT or NOP Active Power-Down Entry DESELECT or NOP Precharge Power-Down Entry AUTOREFRESH Self Refresh Entry Refer to the Command Truth Table
9)10)15)11)
16)14)11)7) 17)
Any State other H than listed above
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) 3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 4) CKE must be maintained high while the device is in OCD calibration mode. 5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements 8) "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). 9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 11) Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. 12) VREF must be maintained during Self Refreh Operation 13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 14) Valid commands for Self Refresh Exit are NOP and DESELCT only. 15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See Chapter 2.10 and Chapter 2.9.2 for a detailed list of restrictions. 16) Self Refresh mode can only be entered from the All Banks Idle state. 17) Must be a legal command as defined in the Command Truth Table.
Table 18
Data Mask (DM) Truth Table DM L H DQs Valid X Notes
1) 1)
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
Data Sheet
66
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Operating Conditions
4
Operating Conditions
Table 19 Symbol
Absolute Maximum Ratings Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating -1.0 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -55 to +100 Units V V V V C Notes
1) 1) 1) 1) 1)
VDD VDDQ VDDL VIN, VOUT TSTG
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 20 Symbol TOPER
DRAM Component Operating Temperature Range Parameter Operating Temperature Rating 0 to 95 Units
o
Notes
1)2)3)4)
C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 oC under all other specification parameters. 3) Above 85 oC case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
Data Sheet
67
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
5
5.1
Table 21 Symbol
AC & DC Operating Conditions
DC Operating Conditions
Recommended DC Operating Conditions (SSTL_18) Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ V V V V V
1) 1) 1) 2)3) 4)
Units
Notes
VDD VDDDL VDDQ VREF VTT
1)
1.7 1.7 1.7 0.49 x VDDQ
VREF - 0.04
VREF
VREF + 0.04
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3) Peak to peak ac noise on VREF may not exceed 2% VREF (dc) 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
Table 22 ODT DC Electrical Characteristics Symbol Rtt1(eff) Rtt2(eff) delta VM Min. 60 120 -6.00 Nom. 75 150 -- Max. 90 180 + 6.00 Units % Notes
1)
Parameter / Condition Termination resistor impedance value for EMRS(1)(A6,A2)= 0,1 Termination resistor impedance value for EMRS(1)(A6,A2)=1,0 Deviation of VM with respect to VDDQ / 2
1)
1)
2)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /(I(VIHac) - I(VILac)).
2) Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =((2 x VM / VDDQ) - 1) x 100%
Table 23 Symbol IIL IOL
Input and Output Leakage Currents Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Units A A Notes
1) 2)
1) all other pins not under test = 0 V 2) DQ's, DQS, DQS and ODT are disabled
Data Sheet
68
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
5.2
DC & AC Logic Input Levels
relative to the rising or falling edges of DQS crossing at
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured Table 24 Symbol Single-ended DC & AC Logic Input Levels Parameter DC input logic high DC input low AC input logic high AC input low Single-ended AC Input Test Conditions Condition Input reference voltage
VREF. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care.
Min.
Max.
Units V V V V
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
Table 25 Symbol
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
VREF + 0.250
--
VREF - 0.250
Value 0.5 x VDDQ 1.0 1.0
Units V V V / ns
Notes
1)2) 1)2) 3)4)
VREF VSWING(max)
SLEW
1.
Input signal maximum peak to peak swing Input signal minimum slew rate
1) This timing and slew rate definition is valid for all single-ended signals except tIS, tIH, tDS, tDH. 2) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 3) The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in Figure 63 4) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac on the negative transitions.
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
VIH(ac) min - VIL(dc) max delta TR
VSWING(MAX)
delta TF Falling Slew = VIH (dc) min - V IL(ac) max delta TF
delta TR Rising Slew =
Figure 63
Single-ended AC Input Test Conditions Diagram
Data Sheet
69
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
Table 26 Symbol
Differential DC and AC Input and Output Logic Levels Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Min. -0.3 0.25 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 Max. Units Notes
1) 2)
VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
1) 2) 3) 4) 5)
VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.175
0.5 x VDDQ + 0.125
V V V
3) 4)
5)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR- VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VDDQ VTR VID VIX or VOX VSSQ
SSTL18_3
Crossing Point
VCP
Figure 64
Differential DC and AC Input and Output Logic Levels Diagram
Data Sheet
70
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
5.3
Table 27 Symbol
Output Buffer
SSTL_18 Output AC Test Conditions Parameter Minimum Required Output Pull-up Maximum Required Output Pull-down Output Timing Measurement Reference Level SSTL_18 Class II Units V V V Notes
1) 1) 2)
VOH VOL VOTR
VTT + 0.603 VTT - 0.603 0.5 x VDDQ
1) SSTL_18 test load for VOH and VOL is different from the referenced load described in Chapter 8.1. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA x 45 Ohm = 603 mV). 2) The VDDQ of the device under test is referenced.
Table 28 Symbol
SSTL_18 Output DC Current Drive Parameter Output Minimum Source DC Currentl Output Minimum Sink DC Current SSTL_18 Class II -13.4 13.4 Units mA mA Notes
1)2)3) 2)3)4)
IOH IOL
1) 280 mV.
VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ -
2) The dc value of VREF applied to the receiving device is set to VTT 3) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 4). They are used to test drive current capability to ensure VIHmin. plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 4)
VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
OCD Default Characteristics Description Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Output Slew Rate Min. 12.6 0 0 1.5 Nominal 18 -- -- -- Max. 23.4 4 1.5 5.0 Units Ohms Ohms Ohms V / ns Notes
1)2) 1)2)3) 4)
Table 29 Symbol -- -- --
SOUT
1) 2)
1)5)6)7)8)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT-VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 0.75 Ohms under nominal conditions. Slew rates measured from VIL(ac) to VIH(ac) with the load specified in Chapter 8.2. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is verified by design and characterisation but not subject to production test.
3)
4)
5)
6)
Data Sheet
71
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions 7) Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ's is included in tDQSQ and tQHS specification. 8) DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins.
5.4
Default Output V-I Characteristics
show the driver characteristics graphically and the tables show the same data suitable for input into simulation tools.
DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A[9:7] ='111'. Figure 65 and Figure 66 Table 30 Voltage (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Full Strength Default Pull-up Driver Characteristics Pull-up Driver Current [mA] Min. -8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6 -- -- Nominal Default low -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6 -- Nominal Default high -11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8 -- Max. -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1
Note: The driver characteristics evaluation conditions are: 1. Nominal Default 25oC (Tcase), VDDQ = 1.8 V, typical process 2. Minimum 95 oC (Tcase), VDDQ = 1.7V, slow-slow process 3. Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process
Data Sheet
72
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
0 -20
Pullup current (mA)
-40 -60 -80 -100 -120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VDDQ to VOUT (V)
Minimum Nominal Default Low Nominal Default High Maximum
Figure 65 Table 31 Voltage (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Full Strength Default Pull-up Driver Diagram Full Strength Default Pull-down Driver Characteristics Pull-down Driver Current [mA] Minimum 8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6 -- -- Nominal Default low 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9 -- Nominal Default high 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.4 52.6 54.2 55.9 57.1 58.4 59.6 60.9 -- Maximum 15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1
Note: The driver characteristics evaluation conditions are: 1. Nominal Default 25 oC (Tcase), VDDQ = 1.8 V, typical process, 2. Minimum 95 oC (Tcase), VDDQ = 1.7V, slow-slow process, 3. Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process
Data Sheet
73
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
120 Pulldown current (mA) 100 80 60 40 20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOUT to VSSQ (V)
Minimum Nominal Default Low Nominal Default High Maximum
Figure 66
Full Strength Default Pull-down Driver Diagram
5.4.1
Calibrated Output Driver V-I Characteristics
looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, recalibration policy and uncertainty with DQ to DQ variation, it is recommended that only the default values to be used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa.
DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The Table 32 and Table 33 show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves are represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while
Data Sheet
74
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
Table 32 Voltage (V)
Full Strength Calibrated Pull-down Driver Characteristics Calibrated Pull-down Driver Current [mA] Nominal Minimum (21 Ohms) Normal Low (18.75 Ohms) 10.7 16.0 21.0 Nominal (18 ohms) 11.5 16.6 21.6 Normal High (17.25 Ohms) 11.8 17.4 23.0 Nominal Maximum (15 Ohms) 13.3 20.0 27.0
0.2 0.3 0.4
9.5 14.3 18.7
Note: The driver characteristics evaluation conditions are: 1. 2. 3. 4. Nominal 25 oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0 oC (Tcase), VDDQ = 1.9 V, any process Full Strength Calibrated Pull-up Driver Characteristics Calibrated Pull-up Driver Current [mA] Nominal Minimum (21 Ohms) 0.2 0.3 0.4 -9.5 -14.3 -18.3 Normal Low (18.75 Ohms) -10.7 -16.0 -21.0 Nominal (18 ohms) -11.4 -16.5 -21.2 Normal High (17.25 Ohms) -11.8 -17.4 -23.0 Nominal Maximum (15 Ohms) -13.3 -20.0 -27.0
Table 33 Voltage (V)
Note: The driver characteristics evaluation conditions are: 1. 2. 3. 4. Nominal 25 oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0 oC (Tcase), VDDQ = 1.9 V, any process
5.5
Table 34 Symbol CCK CDCK CI CDI CIO CDIO
Input / Output Capacitance
Input / Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS min. 1.0 -- 1.0 -- 3.0 -- max. 2.0 0.25 2.0 0.25 4.0 0.5 Units pF pF pF pF pF pF
Data Sheet
75
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
5.6
Power & Ground Clamp V-I Characteristics
pins. The V-I characteristics for pins with clamps is shown in Table 35.
Power and Ground clamps are provided on address (A[13:0], BA[1:0]), RAS, CAS, CS, WE, CKE and ODT Table 35
Power & Ground Clamp V-I Characteristics Minimum Power Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 Minimum Ground Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
Voltage across clamp (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Data Sheet
76
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
IDD Specifications and Conditions
6
Table 36 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions
Symbol Notes
1)2)3)4)5)6)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCKmin;Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N
IDD2Q
Active Power-Down Current IDD3P(0) All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current IDD3N Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
IDD5D
Data Sheet
77
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
IDD Specifications and Conditions Table 36 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
IDD Measurement Conditions
Symbol Notes
1)2)3)4)5)6)
IDD6
IDD7
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. 5) Definitions for IDD: LOW is defined as VIN VIL(ac)max; HIGH is defined as VIN VIH(ac)min; STABLE is defined as inputs are stable at a HIGH or LOW level; FLOATING is defined as inputs are VREF = VDDQ / 2; SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per clock) for DQ signals not including mask or strobes. 6) Timing parameter minimum and maximum values for IDD current measurements are defined in Table 38.
Table 37
IDD Specification
-5 DDR2 - 400 Max. 55 70 60 75 4 32 25 13 5 35 70 85 75 90 120 6 4 2 130 210 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 x16 x4/x8 x16 x16/x4/x8 x16/x4/x8 x16/x4/x8 x16/x4/x8 MRS(12)=0 x16/x4/x8 MRS(12)=1 x16/x4/x8 x4/x8 x16 x4/x8 x16 x16/x4/x8 x16/x4/x8
1)
1)
Product Type Speed Code -3.7 Speed Grade Symbol DDR2 - 533 Max. 65 80 75 90 4 40 30 16 5 40 90 100 95 110 130 6 4 2 140 220
1)
Unit
Notes
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 IDD6: 0 TCASE 85 oC
, standard products
, low power products
x4/x8 x16
Data Sheet
78
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
IDD Specifications and Conditions
6.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used: Table 38 Parameter IDD Measurement Test Condition Symbol -3.7 -5 Units Notes
DDR2-533 4-4-4 DDR2-400 3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period
1) x4 & x8 (1 kB page size) 2) x16 (2 kB page size)
CLmin
4 3.75 15 60 7.5 10 45 15 105
3 5 15 55 7.5 10 40 15 105
tCK
ns ns ns ns ns ns ns ns
1) 2)
tCKmin tRCDmin tRCmin tRRDmin tRASmin tRPmin tRFCmin
6.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The
.
Table 39
ODT current per terminated input pin: EMRS(1) State min. A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0 5 2.5 10 5 typ. 6 3 12 6 max. 7.5 3.75 15 7.5 Unit mA/DQ mA/DQ mA/DQ mA/DQ
ODT Current Enabled ODT current per DQ IODTO added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ IODTT added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
79
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
7
Table 40
Electrical Characteristics & AC Timing - Absolute Specification
Timing Parameter by Speed Grade - DDR2-400 & DDR2-5331)2)3)4)5)6) -5 DDR2-400 3-3-3 Min. Max. + 600 + 500 0.55 0.55 8000 8000 -- -- -- -- -- -- -600 -500 0.45 0.45 5000 5000 350 475 150 275 0.6 -3.7 DDR2-533 4-4-4 Min. -500 -450 0.45 0.45 5000 3750 250 375 100 225 0.6 0.35 -- 2xtACmin Max. +500 +450 0.55 0.55 8000 8000 -- -- -- -- -- -- ps ps Unit Notes
Symbol Parameter
tAC tDQSCK tCH tCL tHP tCK tIS tIH tDS tDH tIPW tDIPW tHZ tLZ(DQ) tLZ(DQS) tDQSQ tQHS tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRE tWPST tRPRE tRPST tRAS tRC
DQ output access time from CK / CK DQS output access time from CK / CK CK, CK high-level width CK, CK low-level width Clock half period Clock cycle time Address and control input setup time Address and control input hold time DQ and DM input setup time DQ and DM input hold time Address and control input pulse width (each input) Data-out high-impedance time from CK / CK DQ low-impedance time from CK / CK DQS low-impedance from CK / CK
tCK tCK
7)
min. (tCL, tCH)
min. (tCL, tCH) ps ps ps ps ps ps
8)9) 8)10) 11) 11) 12) 12)
tCK tCK
ps ps ps ps ps
13)
DQ and DM input pulse width (each input) 0.35 -- 2xtACmin
tACmax tACmax tACmax
350 450 -- WL +0.25 -- -- -- -- -- 0.60 1.1 0.60 70000 --
tACmax tACmax tACmax
300 400 -- WL +0.25 -- -- -- -- -- 0.60 1.1 0.60 70000 --
13) 13) 14)
tACmin
tACmin
-- --
DQS-DQ skew (for DQS & associated DQ -- signals) Data hold skew factor Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) --
tHP-tQHS
WL -0.25 0.35 0.2
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60
tCK tCK tCK tCK tCK tCK tCK tCK tCK
ns ns
DQS falling edge hold time from CK (write 0.2 cycle) Mode register set command cycle time Write preamble Write postamble Read preamble Read postamble Active to Precharge command Active to Active/Auto-Refresh command period 2 0.25 0.40 0.9 0.40 40 55
15) 13) 13) 16)
Data Sheet
80
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification Table 40 Timing Parameter by Speed Grade - DDR2-400 & DDR2-5331)2)3)4)5)6) -5 DDR2-400 3-3-3 Min. Max. -- -- -- -- -- -- 105 15 15 7.5 10 2 15 WR + tRP -- 10 7.5 2 6 - AL 2 200 -- -- -- -- -- -- -- -- 7.8 3.9 12 -3.7 DDR2-533 4-4-4 Min. 105 15 15 7.5 10 2 15 -- WR + tRP -- 7.5 7.5 2 6 - AL 2 200 -- -- -- -- -- -- -- 7.8 3.9 12 Max. -- -- -- -- -- ns ns ns ns ns
19) 20) 17)
Symbol Parameter
Unit Notes
tRFC tRCD tRP tRRD tCCD tWR tDAL tWTR tRTP tXARD tXARDS tXP tXSRD tXSNR tCKE tREFI tOIT tDELAY
Auto-Refresh to Active/Auto-Refresh command period Active to Read or Write delay (with and without Auto-Precharge) Precharge command period Active bank A to Active bank B command period CAS A to CAS B command period Write recovery time Auto-Precharge write recovery + precharge time Internal Write to Read command delay Internal Read to Precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command Exit Self-Refresh to non-Read command CKE minimum high and low pulse width Average periodic refresh Interval OCD drive mode output delay
18)
tCK
ns
tCK
ns ns
21)
22)
tCK tCK tCK tCK
ns
23)
23)
tRFC+10
3 -- -- 0
tRFC+10
3 -- -- 0
tCK s s
ns ns
24)25) 26)
Minimum time clocks remain ON after CKE tIS+tCK+tIH -- asynchronously drops LOW
tIS+tCK+tIH --
27)
1) VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) See notes 3)4)5)6) 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew rates see Chapter 8 of this datasheet. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH, tDS, tDH is VREF. For tIS, tiH, tDS, tDH input reference levels see Chapter 8.3 of this datasheet. 5) Inputs are not recognized as valid until recognized as LOW.
VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements. 7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 8) For input frequency change during DRAM operation, see Chapter 2.12 of this datasheet.
Data Sheet
81
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
9) CL = 3
10) CL = 4 & 5
11) For timing definition, slew rate and slew rate derating see Chapter 8.3 12) For timing definition, slew rate and slew rate derating see Chapter 8.3 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterisation, but not subject to production test. 14) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between DQS / DQS and associated DQ in any given cycle. 15) The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 16) tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 x tREFI. 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore. 19) x4 & x8 (1k page size) 20) x16 (2k page size) 21) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 22) tWTR is at least two clocks independent of operation frequency. 23) User can choose two different active power-down modes for additional power saving via MRS address bit A12. 24) The Auto-Refresh command interval has be reduced to 3.9 between 85oC and 95oC. 25) 0 oC - 85 oC 26) 85 oC - 95 oC 27) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
s when operating the DDR2 DRAM in a temperature range
Table 41 Symbol
ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency Min. 2 Max. 2 Units Notes
1)
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
tAC(min) tAC(min) + 2 ns
2.5
tAC(max) + 1 ns 2 tCK + tAC(max) + 1 ns
2.5
tCK
ns ns
2)
tAC(min) tAC(min) + 2 ns
3
tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns
-- --
tCK tCK
ODT Power Down Exit Latency 8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
82
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
8
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Reference Load for Timing Measurements
transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterisation. The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
8.1
The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial
VDDQ DQ DQS DQS RDQS RDQS
CK, CK DUT
25 Ohm
VTT = VDDQ / 2
Timing Reference Points
Figure 67
Reference Load for Timing Measurements
8.2 8.2.1
Slewrate Measurements Output Slewrate
For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = 500 mV and DQS - DQS = + 500 mV. Output slew rate is verified by design and characterisiation, but not subject to production test.
With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.
8.2.2
Input Slewrate - Differential signals
and from CK - CK = +250 mV to CK - CK = -500mV for falling edges.
Input slewrate for differential signals (CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from f.e. CK - CK = -250 mV to CK - CK = +500 mV
8.2.3
Input Slewrate - Single ended signals
from VREF + 125 mV to VREF - 250 mV for falling edges. For slew rate definition of the input and data setup and hold parameters see Chapter 8.3 of this datasheet.
Input slew rate for single ended signals (other than tIS, tIH, tDS and tDH) are measured from dc-level to ac-level: VREF -125 mV to VREF + 250 mV for rising edges and
Data Sheet
83
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
8.3 8.3.1
Input and Data Setup and Hold Time Timing Definition for Input Setup (tIS) and Hold Time (tIH)
(tIH) is referenced from the input signal crossing at the
Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time
.
VIL(dc) level for a rising signal and VIH(dc) for a falling
signal applied to the device under test.
CK CK t IS t IH t IS t IH
V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS
Figure 68
Input, setup and Hold Time Diagram
8.3.2
Timing Definition for Data Setup (tDS) and Hold Time (tDH)
2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the singleended data strobe crossing VREF for a rising signal and VIH(dc) to the single-ended data strobe crossing VREF for a falling signal applied to the device under test.
1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing VREF for a rising signal, and from the input signal crossing at the VIL(ac) level to the singleended data strobe crossing VREF for a falling signal applied to the device under test.
Data Sheet
84
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
DQS DQS DQS
Differential Input Waveform Single-ended Input Waveform
V REF
t
DS
t
DH
t
t DS DH
V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS
Figure 69
Data, Setup and Hold Time Diagram
8.3.3
Slew Rate Definition for Input and Data Setup and Hold Times
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc level to VREF(dc) region', use nominal slew rate for derating value. (Figure 72) If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value.(Figure 73)
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value.(Figure 70) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. (Figure 71)
Data Sheet
85
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK,DQS
CK,DQS
t IS ,t DS t IH ,t DH t IS ,t DS t ,t IH DH
V DDQ V IH (ac) V
IH (dc) min min Nominal slew rate
V REF(dc)
Nominal slew rate
V V
IL (dc)
max
V REF to ac
region
IL (ac)
max
V SS
Delta TF
Delta TR
Setup Slew Rate = Falling Signal Setup Slew Rate = Rising Signal
Vref(dc) - VIL(ac)max Delta TF VIH(ac)min - VREF(dc) Delta TR
Figure 70
Slew Rate Definition Nominal Diagram for tIS(tDS)
Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min.
Data Sheet
86
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK,DQS
CK,DQS
V DDQ V IH (ac) V IH (dc) min min
t IS ,t DS
t
IH ,t DH
t
,t t ,t IS DS IH DH
VREF to ac region
Nominal line
V REF Tangent line V IL (dc) max
Tangent line
V IL (ac)
max Nominal line
VREF to ac region
Delta TR
V SS Delta TF
Setup Slew Rate = Falling Signal Setup Slew Rate = Rising Signal
tangent line [VREF(dc) - VIL(ac)max] Delta TF tangent line [VIH(ac)min - VREF(dc)] Delta TR
Figure 71
Slew Rate Definition Tangent Diagram for tIS(tDS)
Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min.
Data Sheet
87
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK ,DQS
CK ,DQS
V
t IS ,t DS
t
IH ,t DH
t
IS
,t
t ,t DS IH DH
DDQ min min
V IH (ac) V IH (dc)
Dc to VREF region
V REF(dc) Dc to VREF region V IL (dc) V IL (ac) max Nominal slew rate Nominal slew rate
max
V SS Delta TR Delta TF
Hold Slew Rate Falling Signal
VIH(dc)min - VREF(dc) = Delta TF VREF(dc) - VIL(dc)max Delta TR
Hold Slew Rate = Rising Signal
Figure 72
Slew Rate Definition Nominal Diagram for tIH(tDH)
Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min.
Data Sheet
88
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK,DQS
CK,DQS
V
DDQ min min
t IS ,t DS
t
IH ,t DH
t
,t t ,t IS DS IH DH
Nominal V IH (ac) V IH (dc) slew rate Dc to VREF region
Tangent line
V REF(dc) Dc to VREF region V IL (dc) V IL (ac) max Tangent line Nominal slew rate
max
V SS Delta TR Delta TF
Hold Slew Rate Falling Signal
Tangent line [VIH(dc)min - VREF(dc)] = Delta TF Tangent line [VREF(dc) - VIL(dc)max] Delta TR
Hold Slew Rate = Rising Signal
Figure 73
Slew Rate Definition Tangent Diagram for tIH(tDH)
Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min.
Data Sheet
89
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Table 42
Input Setup (tIS) and Hold (tIH) Time Derating Table Units CK, CK Differential Slew Rate 2.0 V/ns tIS tIH 94 89 83 75 45 21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 1.5 V/ns tIS 217 209 197 180 155 113 30 19 5 -13 -37 -80 -145 -255 -320 -495 -770 -1420 tIH 124 119 113 105 75 51 30 16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 1.0 V/ns tIS 247 239 227 210 185 143 60 49 35 17 -7 -50 -115 -225 -290 -465 -740 -1390 tIH 154 149 143 135 105 81 60 46 29 6 -23 -65 -128 -232 -315 -440 -648 -1065 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes
1)
Command / Address Slew rate (V/ns)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1
187 179 167 150 125 83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450
1) For all input signals the total tIS (input setup time) and value to the derating value listed in this table.
tIH (input hold time) required is calculated by adding the individual
Data Sheet
90
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Table 43 DQ Slewrate (V/ns)
Data Setup (tDS) and Hold Time (tDH) Derating Table1)2)
DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
tDS
tDH tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
125 45 125 45 83 0 -- -- -- -- -- -- 21 83 0 -- -- -- -- -- -- 0 -- -- -- -- -- 21 0 -- -- -- -- --
125 45 83 0 21 0
-- 95 12
-- 33 12 -2
-- -- 24 13
-- -- 24 10 -7
-- -- -- 25 11
-- -- -- 22 5
-- -- -- -- 23
-- -- -- -- 17 -6 -35 -77
-- -- -- -- -- 17 -7 -50
-- -- -- -- -- 6 -23 -65
-- -- -- -- -- -- 5 -38
-- -- -- -- -- -- -11 -53
-11 -14 -11 -14 1 -- -- -- -- -- -- -- --
-25 -31 -13 -19 -1 -- -- -- -- -- --
-31 -42 -19 -30 -7 -- -- -- --
-18 5
-43 -49 -31 -47 -19 -74 -89 -62 -- --
-127 -140 -115 -128 -103 -116
1) All units in ps. 2) For all input signals the total tDS (setup time) and value to the derating value listed in this table.
tDH (hold time) required is calculated by adding the individual datasheet
8.4
Table 44 Parameter
Overshoot and Undershoot Specification
AC Overshoot / Undershoot Specification for Address and Control Pins DDR2-400 0.9 0.9 0.75 0.75 DDR2-533 0.9 0.9 0.56 0.56 Units V V V.ns V.ns
Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS
Maximum Amplitude Volts (V)
Overshoot Area
VDD
VSS Undershoot Area
Maximum Amplitude Time (ns)
Figure 74
AC Overshoot / Undershoot Diagram for Address and Control Pins
Data Sheet
91
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Table 45 Parameter
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins DDR2-400 0.9 0.9 0.38 0.38 DDR2-533 0.9 0.9 0.28 0.28 Units V V V.ns V.ns
Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ
Maximum Amplitude Volts (V)
Overshoot Area
VDDQ
VSSQ Undershoot Area
Maximum Amplitude Time (ns)
Figure 75
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
Data Sheet
92
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Package Dimensions
9
Package Dimensions
10.5 11 x 0.8 = 8.8 0.8 0.2 0.18 MAX.
8 x 0.8 = 6.4
2.2 MAX.
0.8
B
2)
1)
5)
A
2)
4) 3)
0.1 C 0.1 C
1.2 MAX. 0.31 MIN.
o0.46 0.05
60x AB o0.15 M C o0.08 M
C SEATING PLANE
1) Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial
Figure 76
Package Pinout P-TFBGA-60-6 (top view)
Data Sheet
93
10
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
Package Dimensions
12.5 14 x 0.8 = 11.2 0.8 0.2 0.18 MAX.
8 x 0.8 = 6.4
2.2 MAX.
0.8
B
2)
1)
5)
A
2)
4)
3)
0.1 C 0.1 C
1.2 MAX.
0.31 MIN.
o0.46 0.05
84x o0.15 M AB C o0.08 M
C SEATING PLANE
1) Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial
Figure 77
Package Pinout P-TFBGA-84-1 (top view)
Data Sheet
94
10
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
HYB18T512[400/800/160]A[C/F]-[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM
DDR2 Component Nomenclature
10
Table 46
DDR2 Component Nomenclature
Nomenclature Fields and Examples Field Number 1 2 18 3 T 4 512 5 16 6 7 0 8 A 9 C 10 -5 11 HYB
Example for DDR2 DRAM Table 47 Field 1 2 3 4
DDR2 DRAM Nomenclature Description INFINEON Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G Coding Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533 DDR2-400
5+6
Number of I/Os
40 80 16
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F
10 11
-3.7 -5
Data Sheet
95
Rev. 1.13, 2004-05 09112003-SDM9-IQ3P
www.infineon.com
Published by Infineon Technologies AG

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