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| Freescale Semiconductor Data Sheet: Advance Information Document Number: MCF51QM128 Rev. 2, 05/2011 Supports the MCF51QM128VLH, MCF51QM128VHX, MCF51QM128VHS, MCF51QM64VLF, MCF51QM64VHS, MCF51QM32VHS, MCF51QM32VFM Features * Operating characteristics - Voltage range: 1.71 V to 3.6 V - Flash write voltage range: 1.71 V to 3.6 V - Temperature range (ambient): -40C to 105C * Core - Up to 50 MHz V1 ColdFire CPU - Dhrystone 2.1 performance: 1.10 DMIPS per MHz when executing from internal RAM, 0.99 DMIPS per MHz when executing from flash memory * System - DMA controller with four programmable channels - Integrated ColdFire DEBUG_Rev_B+ interface with single-wire BDM connection * Power management - 10 low power modes to provide power optimization based on application requirements - Low-leakage wakeup unit (LLWU) - Voltage regulator (VREG) * Clocks - Crystal oscillators (two, each with range options): 1 kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8 MHz to 32 MHz (high) - Multipurpose clock generator (MCG) * Memories and memory interfaces - Flash memory, FlexNVM, FlexRAM, and RAM - Serial programming interface (EzPort) - Mini-FlexBus external bus interface * Security and integrity - Hardware CRC module to support fast cyclic redundancy checks - Hardware random number generator (RNGB) - Hardware cryptographic acceleration unit (CAU) - 128-bit unique identification (ID) number per chip * Analog - 16-bit SAR ADC - 12-bit DAC - Analog comparator (CMP) containing a 6-bit DAC and programmable reference input - Voltage reference (VREF) * Timers - Programmable delay block (PDB) - Motor control/general purpose/PWM timers (FTM) - 16-bit low-power timers (LPTMRs) - 16-bit modulo timer (MTIM) - Carrier modulator transmitter (CMT) * Communication interfaces - UARTs with Smart Card support and FIFO - SPI modules, one with FIFO - Inter-Integrated Circuit (I2C) modules * Human-machine interface - Up to 48 EGPIO pins - Up to 16 rapid general purpose I/O (RGPIO) pins - Low-power hardware touch sensor interface (TSI) - Interrupt request pin (IRQ) MCF51QM128 Advance Information MCF51QM128 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) 2010-2011 Freescale Semiconductor, Inc. Preliminary Table of Contents 1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................5 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............6 3.8 Definition: Typical value.....................................................7 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................8 4.3 ESD handling ratings.........................................................9 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 Typical Value Conditions...................................................9 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and Current Operating Requirements......10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............12 Power mode transition operating behaviors..........12 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......16 Designing with radiated emissions in mind...........16 Capacitance attributes..........................................16 5.3.1 General Switching Specifications..........................17 5.4 Thermal specifications.......................................................19 5.4.1 5.4.2 Thermal operating requirements...........................19 Thermal attributes.................................................19 6 Peripheral operating requirements and behaviors....................20 6.1 Core modules....................................................................20 6.1.1 Debug specifications.............................................20 6.2 System modules................................................................21 6.2.1 VREG electrical specifications..............................21 6.3 Clock modules...................................................................21 6.3.1 6.3.2 MCG specifications...............................................21 Oscillator electrical specifications.........................24 6.4 Memories and memory interfaces.....................................26 6.4.1 6.4.2 6.4.3 Flash (FTFL) electrical specifications....................26 EzPort Switching Specifications............................31 Mini-Flexbus Switching Specifications..................32 6.5 Security and integrity modules..........................................34 6.6 Analog...............................................................................35 6.6.1 6.6.2 6.6.3 6.6.4 ADC electrical specifications.................................35 CMP and 6-bit DAC electrical specifications.........39 12-bit DAC electrical characteristics.....................41 Voltage reference electrical specifications............44 6.7 Timers................................................................................45 6.8 Communication interfaces.................................................46 6.8.1 SPI switching specifications..................................46 6.9 Human-machine interfaces (HMI)......................................49 6.9.1 TSI electrical specifications...................................49 7 Dimensions...............................................................................50 7.1 Obtaining package dimensions.........................................50 8 Pinout........................................................................................51 8.1 Signal Multiplexing and Pin Assignments..........................51 8.2 Pinout diagrams.................................................................53 8.3 Module-by-module signals.................................................57 9 Revision History........................................................................67 5.3 Switching electrical specifications.....................................17 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 2 Preliminary Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device: 1. Go to http://www.freescale.com. 2. Perform a part number search for the following partial device numbers: PCF51QM and MCF51QM. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q CCCC DD MMM T PP 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q Description Qualification status Values * M = Fully qualified, general market flow * P = Prequalification CF51 = ColdFire V1 JF, JU, QF, QH, QM, QU CCCC DD Core code Device number Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 3 Terminology and guidelines Field MMM Description Memory size (program flash memory)1 Values * 32 = 32 KB * 64 = 64 KB * 128 = 128 KB V = -40 to 105 * FM = 32 QFN (5 mm x 5 mm) * HS = 44 Laminate QFN (5 mm x 5 mm) * LF = 48 LQFP (7 mm x 7 mm) * HX = 64 Laminate QFN (9 mm x 9 mm) * LH = 64 LQFP (10 mm x 10 mm) T PP Temperature range, ambient (C) Package identifier 1. All parts also have FlexNVM, FlexRAM, and RAM. 2.4 Example This is an example part number: MCF51QM128VLH 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 4 Preliminary Freescale Semiconductor, Inc. Terminology and guidelines 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. A Unit 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins -- Min. 7 Max. pF Unit 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 5 Terminology and guidelines 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage -0.3 Min. 1.2 Max. V Unit 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 20 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements go r n ha dli ng ra g tin (m in. ) em en t( n. mi ) ir qu em en t( x ma .) r n ha dli ng ra g tin .) ax (m gr e ir qu gr e go O ra pe tin O ra pe tin O ra pe tin O ra pe tin Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Normal operating range - No permanent failure - Correct operation Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Handling range - No permanent failure - 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 6 Preliminary Freescale Semiconductor, Inc. Terminology and guidelines * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. A Unit 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 7 Ratings 5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 C 105 C 25 C -40 C 4 Ratings 4.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. -55 -- -- Max. 150 260 245 Unit C C Notes 1 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. -- Max. 3 Unit -- Notes 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 8 Preliminary Freescale Semiconductor, Inc. General 4.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD IDD VDIO VAIO ID VDDA IDDA VREGIN Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Analog, RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage Analog supply current Regulator input Min. -0.3 -- -0.3 -0.3 -25 VDD - 0.3 -- -0.3 Max. 3.8 120 VDD + 0.3 VDD + 0.3 25 VDD + 0.3 TBD 6.0 Unit V mA V V mA V mA V 5 General 5.1 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Ambient temperature 3.3 V supply voltage 25 3.3 Value C V Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 9 Nonswitching electrical specifications 5.2 Nonswitching electrical specifications 5.2.1 Voltage and Current Operating Requirements Table 1. Voltage and current operating requirements Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 -0.1 -0.1 Max. 3.6 3.6 0.1 0.1 Unit V V V V 1 0.7 x VDD 0.75 x VDD -- -- V V 2 -- -- 0.35 x VDD 0.3 x VDD V V 3 0 0 2 -0.2 mA mA 3 0 0 1.2 25 -5 -- mA mA V Notes VDD - VDDA VDD-to-VDDA differential voltage VSS - VSSA VSS-to-VSSA differential voltage VIH Input high voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V VIL Input low voltage * 2.7 V VDD 3.6 V * 1.7 V VDD 2.7 V IIC DC injection current -- single pin * VIN > VDD * VIN < VSS DC injection current -- total MCU limit, includes sum of all stressed pins * VIN > VDD * VIN < VSS VRAM VDD voltage required to retain RAM 1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to VIH (max.), regardless of whether input hysteresis is turned on. 2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to VIL (min.), regardless of whether input hysteresis is turned on. 3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 10 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications 5.2.2 LVD and POR operating requirements Table 2. LVD and POR operating requirements Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold -- high range (LVDV=01) Low-voltage warning thresholds -- high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL * Level 1 falling (LVWV=00) * Level 2 falling (LVWV=01) * Level 3 falling (LVWV=10) * Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis -- high range Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO * Level 1 falling (LVWV=00) * Level 2 falling (LVWV=01) * Level 3 falling (LVWV=10) * Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis -- low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1. Rising thresholds are falling threshold + hysteresis voltage TBD TBD TBD TBD TBD TBD 1.80 1.90 2.00 2.10 40 1.00 1000 TBD TBD TBD TBD TBD TBD TBD V V V V mV V s TBD TBD TBD TBD TBD 2.70 2.80 2.90 3.00 60 1.60 TBD TBD TBD TBD TBD TBD V V V V mV V 1 Min. TBD TBD Typ. 1.1 2.56 Max. TBD TBD Unit V V 1 Notes MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 11 Nonswitching electrical specifications 5.2.3 Voltage and current operating behaviors Table 3. Voltage and current operating behaviors Symbol VOH Description Output high voltage -- high drive strength * 2.7 V VDD 3.6 V, IOH = -10 mA * 1.71 V VDD 2.7 V, IOH = -3 mA Output high voltage -- low drive strength * 2.7 V VDD 3.6 V, IOH = -2 mA * 1.71 V VDD 2.7 V, IOH = -0.6 mA IOHT VOL Output high current total for all ports Output low voltage -- high drive strength * 2.7 V VDD 3.6 V, IOL = 10 mA * 1.71 V VDD 2.7 V, IOL = 3 mA Output low voltage -- low drive strength * 2.7 V VDD 3.6 V, IOL = 2 mA * 1.71 V VDD 2.7 V, IOL = 0.6 mA IOLT IIN Output low current total for all ports Input leakage current (per pin) * @ full temperature range * @ 25 C IOZ RPU RPD Hi-Z (off-state) leakage current (per pin) Internal pullup resistors Internal pulldown resistors -- -- -- 20 20 TBD TBD TBD 50 50 A A A k k 1 2 -- -- -- 0.5 0.5 100 V V mA -- -- 0.5 0.5 V V VDD - 0.5 VDD - 0.5 -- -- -- 100 V V mA VDD - 0.5 VDD - 0.5 -- -- V V Min. Max. Unit Notes 1. Measured at Vinput = VSS 2. Measured at Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx-RUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 50 MHz * Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 12 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. RUN VLLS1 RUN * RUN VLLS1 * VLLS1 RUN RUN VLLS2 RUN * RUN VLLS2 * VLLS2 RUN RUN VLLS3 RUN * RUN VLLS3 * VLLS3 RUN RUN LLS RUN * RUN LLS * LLS RUN RUN VLPS RUN * RUN VLPS * VLPS RUN RUN STOP RUN * RUN STOP * STOP RUN 1. Normal boot (FTFL_FOPT[LPBOOT] is 1) -- -- 4.4 4.6 s s -- -- 4.4 4.6 s s -- -- 4.4 6.5 s s -- -- 4.4 TBD s s -- -- 4.6 TBD s s 1 -- -- 4.4 TBD s s 1 Min. -- Max. 300 Unit s Notes 1 1 5.2.5 Power consumption operating behaviors Table 5. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Run mode current -- all peripheral clocks disabled, code executing from RAM * @ 1.8 V * @ 3.0 V -- -- Table continues on the next page... 13.5 14 TBD TBD mA mA Min. -- Typ. -- Max. TBD Unit mA Notes 1 2 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 13 Nonswitching electrical specifications Table 5. Power consumption operating behaviors (continued) Symbol IDD_RUN Description Run mode current -- all peripheral clocks disabled, code executing from flash memory with page buffering disabled * @ 1.8 V * @ 3.0 V IDD_RUN Run mode current -- all peripheral clocks enabled, code executing from RAM, exercising flash memory * @ 1.8 V * @ 3.0 V IDD_RUN_MAX Run mode current -- all peripheral clocks enabled and peripherals active, code executing from flash memory * @ 1.8 V * @ 3.0 V IDD_WAIT IDD_WAIT IDD_STOP IDD_VLPR IDD_VLPR IDD_VLPW IDD_VLPS IDD_LLS Wait mode current at 3.0 V -- all peripheral clocks disabled Wait mode current at 3.0 V -- all peripheral clocks disabled Stop mode current at 3.0 V Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled Very-low-power wait mode current at 3.0 V Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V * @ -40 to 25 C * @ 70 C * @ 105 C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V * @ -40 to 25 C * @ 70 C * @ 105 C IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V * @ -40 to 25 C * @ 70 C * @ 105 C -- -- -- Table continues on the next page... 1.5 TBD TBD TBD TBD TBD A A A -- -- -- 2.0 TBD TBD TBD TBD TBD A A A 10,11 -- -- -- 3.0 TBD TBD TBD TBD TBD A A A 10,11,12 -- -- 20 20 TBD TBD mA mA 4 -- -- -- -- -- -- -- -- -- TBD TBD 6.6 TBD 0.34 0.63 0.78 0.15 12 TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA A 7 8 9 10 10,11,12 5 6 -- -- 16.6 17 TBD TBD mA mA 3 Min. Typ. Max. Unit Notes 2 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 14 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 5. Power consumption operating behaviors (continued) Symbol IDD_VLLS1 Description Very low-leakage stop mode 1 current at 3.0 V * @ -40 to 25 C * @ 70 C * @ 105 C IDD_OSC Average current for OSC enabled with 32 kHz crystal at 3.0 V * @ -40 to 25 C * @ 70 C * @ 105 C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled. 3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode. 6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. 7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash memory. 8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled, but peripherals are not in active operation. Code executing from flash memory. 9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 10. OSC clocks disabled. 11. All pads disabled. 12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For devices with 8 KB of RAM, power consumption is reduced by 750 nA. -- -- -- 1.3 TBD TBD TBD TBD TBD A A A Min. Typ. Max. Unit Notes 10,11 -- -- -- 0.7 TBD TBD -- -- -- A A A 5.2.5.1 * * * * * Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks disabled except FTFL LVD disabled, voltage regulator disabled No GPIOs toggled Code execution from flash memory DIAGRAM TBD Figure 1. Run mode supply current vs. core frequency -- all peripheral clocks disabled The following data was measured under these conditions: * MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) * All peripheral clocks enabled, but peripherals are not in active operation MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 15 Nonswitching electrical specifications * LVD disabled, voltage regulator disabled * No GPIOs toggled * Code execution from flash memory DIAGRAM TBD Figure 2. Run mode supply current vs. core frequency -- all peripheral clocks enabled 5.2.6 EMC radiated emissions operating behaviors Table 6. EMC radiated emissions operating behaviors Symbol VRE1 VRE2 VRE3 VRE4 Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 Frequency band (MHz) 0.15-50 50-150 150-500 500-1000 0.15-1000 Typ. TBD TBD TBD TBD TBD -- 2, 3 Unit dBV Notes 1, 2 VRE_IEC_SAE IEC and SAE level 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/ Wideband TEM (GTEM) Cell Method. 2. VDD = 3 V, TA = 25 C, fOSC = 16 MHz (crystal), fBUS = 25 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits--TEM/Wideband TEM (GTEM) Cell Method. 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for "EMC design." 5.2.8 Capacitance attributes Table 7. Capacitance attributes Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. -- -- Max. 7 7 Unit pF pF MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 16 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications 5.3 Switching electrical specifications Table 8. Device clock specifications Symbol Description Normal run mode fSYS fBUS FB_CLK fLPTMR System and core clock Bus clock Mini-FlexBus clock LPTMR clock VLPR mode fSYS fBUS FB_CLK fLPTMR System and core clock Bus clock Mini-FlexBus clock LPTMR clock -- -- -- -- 2 1 1 25 MHz MHz MHz MHz -- -- -- -- 50 25 25 25 MHz MHz MHz MHz Min. Max. Unit Notes 5.3.1 General Switching Specifications These general purpose specifications apply to all signals configured for EGPIO, MTIM, CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V, and full temperature range. The GPIO are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. Table 9. EGPIO General Control Timing Symbol G1 G2 G3 G4 Description Bus clock from CLK_OUT pin high to GPIO output valid Bus clock from CLK_OUT pin high to GPIO output invalid (output hold) GPIO input valid to bus clock high Bus clock from CLK_OUT pin high to GPIO input invalid GPIO pin interrupt pulse width (digital glitch filter disabled) Synchronous path1 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) Asynchronous path2 Table continues on the next page... 100 -- -- 1 28 -- 1.5 Min. 32 -- -- 4 -- Max. ns ns ns ns Bus clock cycles ns Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 17 Nonswitching electrical specifications Table 9. EGPIO General Control Timing (continued) Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) Asynchronous path2 External reset pulse width (digital glitch filter disabled) Mode select (MS) hold time after reset deassertion 100 2 -- -- ns Bus clock cycles 50 Min. -- Max. ns Unit 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. Bus clock G1 G2 Data outputs G3 G4 Data inputs Figure 3. EGPIO timing diagram The following general purpose specifications apply to all signals configured for RGPIO, FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full temperature range. The GPIO are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. Table 10. RGPIO General Control Timing Symbol R1 R2 R3 R4 Description CPUCLK from CLK_OUT pin high to GPIO output valid CPUCLK from CLK_OUT pin high to GPIO output invalid (output hold) GPIO input valid to bus clock high CPUCLK from CLK_OUT pin high to GPIO input invalid -- 1 17 -- Min. 16 -- -- 2 Max. ns ns ns ns Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 18 Preliminary Freescale Semiconductor, Inc. Thermal specifications Bus clock R1 R2 Data outputs R3 R4 Data inputs Figure 4. RGPIO timing diagram 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. -40 -40 Max. 125 105 Unit C C 5.4.2 Thermal attributes Board type Symbol Description 64 LQFP 64 Laminate QFN 108 48 LQFP 44 Laminate QFN 108 32 QFN Unit Notes Single-layer RJA (1s) Four-layer (2s2p) RJA Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to ambient (200 ft./min. air speed) 73 79 98 C/W 1 54 69 55 69 33 C/W 1 Single-layer RJMA (1s) Four-layer (2s2p) RJMA 61 91 66 91 81 C/W 1 48 63 48 63 28 C/W 1 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 19 Peripheral operating requirements and behaviors Board type Symbol Description 64 LQFP 64 Laminate QFN 44 31 6.0 48 LQFP 44 Laminate QFN 44 31 6.0 32 QFN Unit Notes -- -- -- RJB RJC JT Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection) 37 20 5.0 34 20 4.0 13 2.2 6.0 C/W C/W C/W 2 3 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions --Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions --Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions --Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug specifications Table 12. Background debug mode (BDM) timing Number 1 2 Symbol tMSSU tMSH Description BKGD/MS setup time after issuing background debug force reset to enter user mode or BDM BKGD/MS hold time after issuing background debug force reset to enter user mode or BDM1 Min. 500 100 -- -- Max. ns s Unit 1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 20 Preliminary Freescale Semiconductor, Inc. System modules 6.2 System modules 6.2.1 VREG electrical specifications Table 13. VREG electrical specifications Symbol VREGIN IDDon IDDstby IDDoff Description Input supply voltage Quiescent current -- Run mode, load current equal zero, input supply (VREGIN) > 3.6 V Quiescent current -- Standby mode, load current equal zero Quiescent current -- Shutdown mode * VREGIN = 5.0 V and temperature=25C * Across operating voltage and temperature ILOADrun ILOADstby VReg33out Maximum load current -- Run mode Maximum load current -- Standby mode Regulator output voltage -- Input supply (VREGIN) > 3.6 V * Run mode * Standby mode VReg33out COUT ESR ILIM Regulator output voltage -- Input supply (VREGIN) < 3.6 V, pass-through mode External output capacitor External output capacitor equivalent series resistance Short circuit current 3 TBD TBD 1.76 1 TBD 3.3 2.8 -- 2.2 -- 290 3.6 3.6 3.6 8.16 100 TBD V V V F m mA 1 -- -- -- -- 500 -- -- -- -- TBD 120 1 nA A mA mA Min. 2.7 -- -- Typ. -- 120 1.1 Max. 5.5 TBD TBD Unit V A A Notes 1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 6.3 Clock modules 6.3.1 MCG specifications Table 14. MCG specifications Symbol fints_ft Description Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25C Min. -- Typ. 32.768 Max. -- Unit kHz Notes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 21 Clock modules Table 14. MCG specifications (continued) Symbol fints_t Iints tirefsts fdco_res_t Description Internal reference frequency (slow clock) -- user trimmed Internal reference (slow clock) current Internal reference (slow clock) startup time Resolution of trimmed DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM Resolution of trimmed DCO output frequency at fixed voltage and temperature -- using SCTRIM only Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C Internal reference frequency (fast clock) -- user trimmed Internal reference (fast clock) current Internal reference startup time (fast clock) Loss of external clock minimum frequency -- RANGE = 00 Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref Table continues on the next page... 80 83.89 100 MHz 60 62.91 75 MHz 40 41.94 50 MHz 31.25 20 -- 20.97 39.0625 25 kHz MHz 2, 3 Min. 31.25 -- -- -- Typ. -- TBD TBD 0.1 Max. 39.0625 -- 4 0.3 Unit kHz A s %fdco 1 Notes fdco_res_t -- 0.2 0.5 %fdco 1 fdco_t fdco_t -- + 0.5 - 1.0 3.5 %fdco %fdco 1 -- 0.5 TBD 1 fintf_ft fintf_t Iintf tirefstf floc_low floc_high 3.4 3 -- -- (3/5) x fints_t (16/5) x fints_t -- -- TBD TBD -- -- 4 5 -- TBD -- -- MHz MHz A s kHz kHz MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 22 Preliminary Freescale Semiconductor, Inc. Clock modules Table 14. MCG specifications (continued) Symbol Description Low range (DRS=00) 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll Jacc_fll tfll_acquire FLL period jitter FLL accumulated jitter of DCO output over a 1s time window FLL target frequency acquisition time PLL fvco Ipll VCO operating frequency PLL operating current * PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) PLL operating current * PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) PLL reference frequency range PLL period jitter * fvco = 48 MHz * fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1s window * fvco = 48 MHz * fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time -- -- 1.49 4.47 -- 1350 600 -- -- -- -- -- 2.98 5.97 0.15 + 1075(1/ fpll_ref) ps ps % % ms 11 -- -- 120 50 -- -- ps ps 9, 10 48.0 -- -- 1060 100 -- MHz A 8 -- -- -- TBD TBD -- TBD TBD 1 ps ps ms 6 6 7 -- 95.98 -- MHz -- 71.99 -- MHz -- 47.97 -- MHz Min. -- Typ. 23.99 Max. -- Unit MHz Notes 4, 5 fdco_t_DMX3 DCO output frequency 2 Ipll -- 600 -- A 8 fpll_ref Jcyc_pll 2.0 -- 4.0 MHz 9, 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 23 Clock modules 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. PLL period jitter is measured in RMS. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Symbol VDD IDDOSC Oscillator DC electrical specifications Description Supply voltage Supply current -- low-power mode (HGO=0) * 32 kHz * 1 MHz * 4 MHz * 8 MHz (only RANGE=01) * 16 MHz * 24 MHz * 32 MHz -- -- -- -- -- -- -- Min. 1.71 Table 15. Oscillator DC electrical specifications Typ. -- Max. 3.6 Unit V 1 500 100 200 300 950 1.2 1.5 -- -- -- -- -- -- -- nA A A A A mA mA 1 -- -- -- -- -- -- -- -- -- Table continues on the next page... 25 200 400 500 2.5 3 4 -- -- -- -- -- -- -- -- -- -- -- A A A A mA mA mA 2, 3 2, 3 Notes IDDOSC Supply current -- high gain mode (HGO=1) * 32 kHz * 1 MHz * 4 MHz * 8 MHz (only RANGE=01) * 16 MHz * 24 MHz * 32 MHz Cx Cy EXTAL load capacitance XTAL load capacitance MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 24 Preliminary Freescale Semiconductor, Inc. Clock modules Table 15. Oscillator DC electrical specifications (continued) Symbol RF Description Feedback resistor -- low-frequency, low-power mode (HGO=0) Feedback resistor -- low-frequency, high-gain mode (HGO=1) Feedback resistor -- high-frequency, low-power mode (HGO=0) Feedback resistor -- high-frequency, high-gain mode (HGO=1) RS Series resistor -- low-frequency, low-power mode (HGO=0) Series resistor -- low-frequency, high-gain mode (HGO=1) Series resistor -- high-frequency, low-power mode (HGO=0) Series resistor -- high-frequency, high-gain mode (HGO=1) * 1 MHz resonator * 2 MHz resonator * 4 MHz resonator * 8 MHz resonator * 16 MHz resonator * 20 MHz resonator * 32 MHz resonator Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) 1. 2. 3. 4. 5. -- -- -- -- -- -- -- -- 6.6 3.3 0 0 0 0 0 0.6 -- -- -- -- -- -- -- -- k k k k k k k V Min. -- -- -- -- -- -- -- Typ. -- 10 -- 1 -- 200 -- Max. -- -- -- -- -- -- -- Unit M M M M k k k Notes 2, 4 -- VDD -- V -- 0.6 -- V -- VDD -- V VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 25 Memories and memory interfaces 6.3.2.2 Symbol fosc_lo fosc_hi_1 Oscillator frequency specifications Description Oscillator crystal or resonator frequency -- low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency -- high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 1 Table 16. Oscillator frequency specifications Typ. -- -- Max. 40 8 Unit kHz MHz Notes fosc_hi_2 8 -- 32 MHz fec_extal tdc_extal tcst -- 40 -- -- -- -- 50 750 250 0.6 50 60 -- -- -- MHz % ms ms ms 1 2, 3 -- 1 -- ms 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFL) electrical specifications This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 17. NVM program/erase timing specifications Symbol thvpgm4 Description Longword Program high-voltage time Min. -- Typ. 20 Max. TBD Unit s Notes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 26 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Table 17. NVM program/erase timing specifications (continued) Symbol thversscr thversblk32k Description Sector Erase high-voltage time Erase Block high-voltage time for 32 KB Min. -- -- -- Typ. 20 20 80 Max. 100 100 400 Unit ms ms ms Notes 1 1 1 thversblk128k Erase Block high-voltage time for 128 KB 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications -- commands Description Read 1s Block execution time Min. Table 18. Flash command timing specifications Typ. Max. Unit Notes trd1blk32k trd1blk128k trd1sec1k tpgmchk trdrsrc tpgm4 * 32 KB data flash * 128 KB data flash Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Block execution time -- -- -- -- -- -- -- -- -- -- -- 50 0.4 1.4 40 35 35 TBD ms ms s s s s 2 1 1 1 tersblk32k tersblk128k tersscr * 32 KB data flash * 128 KB data flash Erase Flash Sector execution time Program Section execution time -- -- -- 20 80 20 100 400 100 ms ms ms 2 tpgmsec512 tpgmsec1k trd1all trdonce tpgmonce tersall tvfykey * 512 B flash * 1 KB flash Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Program Partition for EEPROM execution time -- -- -- -- -- -- -- TBD TBD -- -- 50 100 -- TBD TBD 1.8 35 TBD 500 35 ms ms ms s s ms s 2 1 1 tpgmpart32k * 32 KB FlexNVM Set FlexRAM Function execution time: -- 25 TBD ms tsetram8k tsetram32k * 8 KB EEPROM backup * 32 KB EEPROM backup -- -- TBD TBD TBD TBD ms ms Byte-write to FlexRAM for EEPROM operation Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 27 Memories and memory interfaces Table 18. Flash command timing specifications (continued) Symbol teewr8bers Description Byte-write to erased FlexRAM location execution time Byte-write to FlexRAM execution time: teewr8b8k teewr8b16k teewr8b32k * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup -- -- -- TBD TBD TBD TBD TBD 1.5 ms ms ms Min. -- Typ. 100 Max. TBD Unit s Notes 3 Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time Word-write to FlexRAM execution time: teewr16b8k teewr16b16k teewr16b32k * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup -- -- -- TBD TBD TBD TBD TBD 1.5 ms ms ms -- 100 TBD s Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time Longword-write to FlexRAM execution time: teewr32b8k teewr32b16k teewr32b32k * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup -- -- -- TBD TBD TBD TBD TBD 2.7 ms ms ms -- 200 TBD s 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash (FTFL) current and power specfications Description Worst case programming current in program flash Table 19. Flash (FTFL) current and power specfications Typ. 10 Unit mA Symbol IDD_PGM 6.4.1.4 Symbol Reliability specifications Description Table 20. NVM reliability specifications Min. Program Flash Typ.1 Max. Unit Notes tnvmretp10k tnvmretp1k Data retention after up to 10 K cycles Data retention after up to 1 K cycles 5 10 TBD TBD -- -- years years 2 2 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 28 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Table 20. NVM reliability specifications (continued) Symbol tnvmretp100 nnvmcycp Description Data retention after up to 100 cycles Cycling endurance Min. 15 10 K Data Flash tnvmretd10k tnvmretd1k tnvmretd100 nnvmcycd Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance 5 10 15 10 K FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance tnvmretee10 tnvmretee1 Data retention up to 10% of write endurance Data retention up to 1% of write endurance Write endurance nnvmwree16 nnvmwree128 nnvmwree512 nnvmwree4k nnvmwree8k * EEPROM backup to FlexRAM ratio = 16 * EEPROM backup to FlexRAM ratio = 128 * EEPROM backup to FlexRAM ratio = 512 * EEPROM backup to FlexRAM ratio = 4096 * EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M TBD TBD TBD TBD TBD -- -- -- -- -- writes writes writes writes writes 5 10 15 TBD TBD TBD -- -- -- years years years 2 2 2 4 TBD TBD TBD TBD -- -- -- -- years years years cycles 2 2 2 3 Typ.1 TBD TBD Max. -- -- Unit years cycles Notes 2 3 1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 4. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum value assumes all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 29 Memories and memory interfaces While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_FlexRAM = EEPROM - 2 x EEESIZE EEESIZE x Write_efficiency x nnvmcycd where * Writes_FlexRAM -- minimum number of writes to each FlexRAM location * EEPROM -- allocated FlexNVM based on DEPART; entered with Program Partition command * EEESIZE -- allocated FlexRAM based on DEPART; entered with Program Partition command * Write_efficiency -- * 0.25 for 8-bit writes to FlexRAM * 0.50 for 16-bit or 32-bit writes to FlexRAM * nnvmcycd -- data flash cycling endurance MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 30 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Figure 5. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 21. EzPort switching specifications Num Description Operating voltage EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid (setup) EZP_CK low to EZP_Q output invalid (hold) Table continues on the next page... Min. 2.7 -- -- 2 x tEZP_CK 15 0.0 15 0.0 -- 0.0 Max. 3.6 fSYS/2 fSYS/8 -- -- -- -- -- 25 -- Unit V MHz MHz ns ns ns ns ns ns ns MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 31 Memories and memory interfaces Table 21. EzPort switching specifications (continued) Num EP9 Description EZP_CS negation to EZP_Q tri-state Min. -- Max. 12 Unit ns EZP_CK EP3 EP4 EP2 EZP_CS EP7 EP8 EP9 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 6. EzPort Timing Diagram 6.4.3 Mini-Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 22. Flexbus switching specifications Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 2.7 -- 20 TBD 1 20 10 Max. 3.6 25 -- 20 -- -- -- Unit V MHz ns ns ns ns ns 1 1 2 2 Notes MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 32 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces 1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS. 2. Specification is valid for all FB_AD[31:0]. Note The following diagrams refer to signal names that may not be included on your particular device. Ignore these extraneous signals. Also, ignore the AA=0 portions of the diagrams because this setting is not supported in the Mini-FlexBus. FB1 FB_CLK FB3 FB5 FB_A[Y] FB2 Address FB4 Data FB_D[X] FB_RW FB_TS FB_ALE Address AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 7. Mini-FlexBus read timing diagram MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 33 Memories and memory interfaces FB1 FB_CLK FB2 FB3 Address FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE Address Data AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 8. Mini-FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 34 Preliminary Freescale Semiconductor, Inc. Analog 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 Symbol VDDA VDDA VSSA VREFH VREFL VADIN CADIN 16-bit ADC operating conditions Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Reference voltage low Input voltage Input capacitance * 16 bit modes * 8/10/12 bit modes Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 VSSA VREFL -- -- Table 23. 16-bit ADC operating conditions Typ.1 -- 0 0 VDDA VSSA -- 8 4 Max. 3.6 +100 +100 VDDA VSSA VREFH 10 5 Unit V mV mV V V V pF 2 2 Notes RADIN RAS Input resistance Analog source resistance 13/12 bit modes fADCK < 4MHz 13 bit modes -- 2 5 k 3 -- -- 5 k fADCK fADCK ADC conversion clock frequency ADC conversion clock frequency 4 1.0 -- 18.0 MHz 5 2.0 -- 12.0 MHz 16 bit modes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 35 Analog Table 23. 16-bit ADC operating conditions (continued) Symbol Crate Description ADC conversion rate Conditions 13 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has <8 analog source resistance. The RAS/ CAS time constant should be kept to <1ns. 4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear. 5. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear. 6. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Min. Typ.1 Max. Unit Notes 6 20.000 -- 818.330 Ksps 7 37.037 -- 461.467 Ksps Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Z AS R AS V ADIN V AS C AS Pad leakage due to input protection R ADIN ADC SAR ENGINE R ADIN INPUT PIN R ADIN INPUT PIN R ADIN C ADIN INPUT PIN Figure 9. ADC input impedance equivalency diagram MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 36 Preliminary Freescale Semiconductor, Inc. Analog 6.6.1.2 Symbol IDDA_ADC Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Description Supply current ADC asynchronous clock source * ADLPC=1, ADHSC=0 * ADLPC=1, ADHSC=1 * ADLPC=0, ADHSC=0 * ADLPC=0, ADHSC=1 Sample Time Conditions1 Min. 0.215 1.2 3.0 2.4 4.4 Typ.2 -- 2.4 4.0 5.2 6.2 Max. 1.7 3.9 7.3 6.1 9.5 Unit mA MHz MHz MHz MHz Notes 3 tADACK = 1/ fADACK 16-bit ADC electrical characteristics fADACK See Reference Manual chapter for sample times Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/ converters/ADC_CALCULATOR_CNV.zip?fpsp=1 TUE Total unadjusted error * 13 bit modes * <12 bit modes 0.8 0.5 TBD 1 LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Max averaging VADIN = VDDA DNL Differential nonlinearity * 13 bit modes * <12 bit modes 0.7 0.2 TBD 0.5 LSB4 INL Integral nonlinearity Full-scale error * 13 bit modes * <12 bit modes * 13 bit modes * <12 bit modes -- -- -- -- -- -- 1.0 0.5 0.4 1.0 -1 to 0 -- TBD TBD TBD TBD -- 0.5 LSB4 EFS EQ LSB4 Quantization error * 16 bit modes * 13 bit modes LSB4 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 37 Analog Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol ENOB Description Conditions1 Min. Typ.2 Max. -- TBD TBD 13.6 13.2 -- -- TBD TBD TBD TBD 6.02 x ENOB + 1.76 bits bits dB 5 -- -- -94 TBD TBD TBD dB dB 5 TBD TBD 95 TBD IIn x RAS -- -- dB dB mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage * -40C to 25C * 25C to 105C 25C -- -- -- TBD TBD TBD -- -- -- mV/C mV/C mV -- bits bits Unit Notes 5 Effective number 16 bit differential mode of bits * Avg=32 * Avg=1 16 bit single-ended mode * Avg=32 * Avg=1 SINAD THD Signal-to-noise plus distortion Total harmonic distortion See ENOB 16 bit differential mode * Avg=32 16 bit single-ended mode * Avg=32 SFDR Spurious free dynamic range 16 bit differential mode * Avg=32 16 bit single-ended mode * Avg=32 EIL Input leakage error 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. Input data is 1 kHz sine wave. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 38 Preliminary Freescale Semiconductor, Inc. Analog Figure TBD Figure 10. Typical TUE vs. ADC conversion rate 12-bit single-ended mode Figure TBD Figure 11. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended modes 6.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol VDD IDDHS IDDLS VAIN VAIO VH Description Supply voltage Supply current, High-speed mode (EN=1, PMODE=1) Supply current, low-speed mode (EN=1, PMODE=0) Analog input voltage Analog input offset voltage Analog comparator hysteresis1 * CR0[HYSTCTR] = 00 * CR0[HYSTCTR] = 01 * CR0[HYSTCTR] = 10 * CR0[HYSTCTR] = 11 VCMPOh VCMPOl tDHS tDLS Output high Output low Propagation delay, high-speed mode (EN=1, PMODE=1) Propagation delay, low-speed mode (EN=1, PMODE=0) Analog comparator initialization delay2 IDAC6b INL DNL 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity 6-bit DAC differential non-linearity -- -- -- -- VDD - 0.5 -- 20 120 -- -- -0.5 -0.3 5 10 20 30 -- -- 50 250 -- 7 -- -- -- -- -- -- -- 0.5 200 600 40 -- 0.5 0.3 mV mV mV mV V V ns ns s A LSB3 LSB Min. 1.71 -- -- VSS - 0.3 -- Typ. -- -- -- -- -- Max. 3.6 200 20 VDD 20 Unit V A A V mV 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 39 Analog 0.08 0.07 0.06 0.05 CM P Hystereris (V) HYSTCTR Setting 00 01 10 0.04 0.03 0.02 0.01 0 11 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 12. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 40 Preliminary Freescale Semiconductor, Inc. 12-bit DAC electrical characteristics 0.18 0.16 0.14 0.12 CMP Hystereris (V) P HYSTCTR Setting 00 01 10 11 0.1 0 08 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 Vin level (V) 1.6 1.9 2.2 2.5 2.8 3.1 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol VDDA VDACR TA CL IL 12-bit DAC operating requirements Desciption Supply voltage Reference voltage Temperature Output load capacitance Output load current Table 26. 12-bit DAC operating requirements Min. 1.71 1.13 -40 -- -- Max. 3.6 3.6 105 100 1 Unit V V C pF mA 2 1 Notes 1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 41 12-bit DAC electrical characteristics 6.6.3.2 Symbol 12-bit DAC operating behaviors Description Table 27. 12-bit DAC operating behaviors Min. -- -- -- -- -- -- VDACR -100 -- -- -- 0.4 0.1 60 -- -- -- -- 3.7 TBD -- -- Typ. -- -- 100 15 0.7 -- -- -- -- -- -- -- Max. 150 700 200 30 1 100 VDACR 8 1 1 0.8 0.6 90 -- -- TBD 250 Unit A A s s s mV mV LSB LSB LSB %FSR %FSR dB V/C ppm of FSR/C V/yr V/s 1.2 0.05 -- 1.7 0.12 -- -- -- -80 dB kHz 550 40 -- -- -- -- 6 2 3 4 5 5 1 1 1 Notes IDDA_DACLP Supply current -- low-power mode IDDA_DACH Supply current -- high-speed mode P tDACLP tDACHP tCCDACLP Vdacoutl Vdacouth INL DNL DNL VOFFSET EG PSRR TCO TGE AC Rop SR Full-scale settling time (0x080 to 0xF7F) -- lowpower mode Full-scale settling time (0x080 to 0xF7F) -- highpower mode Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode DAC output voltage range low -- high-speed mode, no load, DAC set to 0x000 DAC output voltage range high -- high-speed mode, no load, DAC set to 0xFFF Integral non-linearity error -- high speed mode Differential non-linearity error -- VDACR > 2 V Differential non-linearity error -- VDACR = VREFO (1.15 V) Offset error Gain error Power supply rejection ratio, VDDA > = 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Offset aging coefficient Output resistance load = 3 k Slew rate -80h F7Fh 80h * High power (SPHP) * Low power (SPLP) CT BW Channel to channel cross talk 3dB bandwidth * High power (SPHP) * Low power (SPLP) 1. 2. 3. 4. 5. Settling within 1 LSB The INL is measured for 0+100mV to VDACR-100 mV The DNL is measured for 0+100 mV to VDACR-100 mV The DNL is measured for 0+100mV to VDACR-100 mV with VDDA > 2.4V Calculated by a best fit curve from VSS+100 mV to VREF-100 mV MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 42 Preliminary Freescale Semiconductor, Inc. 12-bit DAC electrical characteristics 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C Figure 14. Typical INL error vs. digital code MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 43 12-bit DAC electrical characteristics Figure 15. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 28. VREF full-range operating requirements Symbol VDDA TA CL Description Supply voltage Temperature Output load capacitance Min. 1.71 -40 -- Max. 3.6 105 100 Unit V C nF Notes Table 29. VREF full-range operating behaviors Symbol Vout Vout Description Voltage reference output with factory trim at nominal VDDA and temperature=25C Voltage reference output with-- factory trim Min. TBD TBD Typ. 1.2 -- Max. TBD TBD Unit V V Notes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 44 Preliminary Freescale Semiconductor, Inc. 12-bit DAC electrical characteristics Table 29. VREF full-range operating behaviors (continued) Symbol Vout Vstep Vdrift Ac Ibg Itr VLOAD Description Voltage reference output -- user trim Voltage reference trim step Temperature drift (Vmax -Vmin across the full temperature range) Aging coefficient Bandgap only (MODE_LV = 00) current Tight-regulation buffer (MODE_LV =10) current Load regulation (MODE_LV = 10) * current = + 1.0 mA * current = - 1.0 mA Tstup DC Buffer startup time Line regulation (power supply rejection) -- -- -- -- -60 -- -- -- -- -- TBD TBD 100 TBD TBD s mV dB Min. 1.198 -- -- -- -- -- Typ. -- 0.5 -- -- -- -- Max. 1.202 -- 40 TBD TBD 1.1 Unit V mV mV ppm/year A mA mV 1 See Figure 16 Notes 1. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 30. VREF limited-range operating requirements Symbol TA Description Temperature Min. 0 Max. 50 Unit C Notes Table 31. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. TBD Max. TBD Unit V Notes TBD Figure 16. Typical output vs.temperature TBD Figure 17. Typical output vs. VDD 6.7 Timers See General Switching Specifications. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 45 Communication interfaces 6.8 Communication interfaces 6.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes slew rate control is disabled and high drive strength is enabled for SPI output pins. Table 32. SPI master mode timing Num. 1 Symbol fop Description Frequency of operation Min. fBUS/2048 Max. fBUS/2 Unit Hz Comment fBUS is the bus clock as defined in Table 8. tBUS = 1/ fBUS -- -- -- -- -- -- -- -- 2 3 4 5 6 7 8 9 10 tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 2 x tBUS 1/2 1/2 tBUS - 30 21 0 -- 0 -- 2048 x tBUS -- -- 1024 x tBUS -- -- 25 -- tBUS - 25 ns tSPSCK tSPSCK ns ns ns ns ns ns 11 tRO tFO -- 25 ns -- MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 46 Preliminary Freescale Semiconductor, Inc. Communication interfaces SS1 (OUTPUT) 3 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 2 5 5 10 11 4 10 11 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 8 LSB IN 9 LSB OUT MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. SPI master mode timing (CPHA=0) SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 3 10 11 4 5 5 10 11 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 9 LSB IN 8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT 1.If configured as output BIT 6 . . . 1 MASTER LSB OUT PORT DATA 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI master mode timing (CPHA=1) Table 33. SPI slave mode timing Num. 1 Symbol fop Description Frequency of operation Min. 0 Max. fBUS/4 Unit Hz Comment fBUS is the bus clock as defined in Table 8. Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 47 Communication interfaces Table 33. SPI slave mode timing (continued) Num. 2 3 4 5 6 7 8 Symbol tSPSCK tLead tLag tWSPSCK tSU tHI ta Description SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time Min. 4 x tBUS 1 1 tBUS - 30 19.5 0 -- Max. -- -- -- -- -- -- tBUS Unit ns tBUS tBUS ns ns ns ns Comment tBUS = 1/ fBUS -- -- -- -- -- Time to data active from highimpedanc e state Hold time to highimpedanc e state -- -- -- 9 tdis Slave MISO disable time -- tBUS ns 10 11 12 tv tHO tRI tFI Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output -- 0 -- 27 -- tBUS - 25 ns ns ns 13 tRO tFO -- 25 ns -- SS (INPUT) 2 12 13 4 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) 3 5 5 12 13 9 8 MISO (OUTPUT) see note 6 MOSI (INPUT) NOTE: Not defined! SLAVE MSB 7 MSB IN 10 BIT 6 . . . 1 11 11 SEE NOTE SLAVE LSB OUT BIT 6 . . . 1 LSB IN Figure 20. SPI slave mode timing (CPHA=0) MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 48 Preliminary Freescale Semiconductor, Inc. Human-machine interfaces (HMI) SS (INPUT) 2 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) 4 12 13 3 5 5 12 13 10 MISO (OUTPUT) MOSI (INPUT) NOTE: Not defined! see note 8 SLAVE 6 MSB IN MSB OUT 7 11 BIT 6 . . . 1 SLAVE LSB OUT 9 BIT 6 . . . 1 LSB IN Figure 21. SPI slave mode timing (CPHA=1) 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 34. TSI electrical specifications Symbol VDDTSI CELE fREFmax fELEmax CREF VDELTA IREF IELE Pres5 Pres20 Pres100 Description Operating voltage Target electrode capacitance range Reference oscillator frequency Electrode oscillator frequency Internal reference capacitor Oscillator delta voltage Reference oscillator current source base current Electrode oscillator current source base current Electrode capacitance measurement precision Electrode capacitance measurement precision Electrode capacitance measurement precision Min. 1.71 1 -- -- TBD TBD -- -- -- -- -- 0.003 0.003 -- Table continues on the next page... Typ. -- 20 5.5 0.5 1 600 1.133 1.133 TBD TBD TBD 0.25 -- -- Max. 3.6 500 TBD TBD TBD TBD TBD TBD TBD TBD TBD -- -- 16 Unit V pF MHz MHz pF mV A A % % % fF/count fF/count bits 4 3, 5 3, 5 6 7 8 9 10 1 2 3 Notes MaxSens2 Maximum sensitivity @ 20 pF electrode 0 MaxSens Res Maximum sensitivity Resolution MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 49 Dimensions Table 34. TSI electrical specifications (continued) Symbol TCon20 ITSI_RUN ITSI_LP 1. 2. 3. 4. 5. 6. 7. 8. 9. Description Response time @ 20 pF Current added in run mode Low power mode current adder Min. 8 -- -- Typ. 15 55 1.3 Max. 25 -- TBD Unit s A A 12 Notes 11 The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 A, REFCHRG = 4), PS = 128, NSCN = 2; Iext = 16 (EXTCHRG = 15). 10. Typical value depends on the configuration used. 11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, DELVOL = 2, EXTCHRG = 15. 12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package 32-pin QFN 44-pin Laminate QFN 48-pin LQFP 64-pin Laminate QFN 64-pin LQFP Then use this document number 98ARE10566D 98ASA00239D 98ASH00962A 98ASA00279D 98ASS23234W MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 50 Preliminary Freescale Semiconductor, Inc. Pinout 8 Pinout 8.1 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Mux Control module is responsible for selecting which ALT functionality is available on each pin. NOTE * On PTB0, EZP_MS_b is active only during reset. Refer to the detailed boot description. * PTC1 is open drain. 64pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 48pin -- -- -- -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 44pin -- -- -- -- -- -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32pin -- -- -- -- -- -- 1 2 3 4 5 6 7 -- -- -- 8 9 10 11 12 13 Default VDD VSS Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled ALT0 VDD VSS Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled PTC6 PTC7 PTD0 PTD1 PTA0 PTA1 PTA2 PTA3 UART1_TX UART1_RX UART1_CT S_b UART1_RT S_b I2C2_SCL I2C2_SDA UART0_TX UART0_RX UART0_CT S_b UART0_RT S_b I2C0_SCL I2C0_SDA I2C1_SDA I2C1_SCL I2C2_SCL I2C2_SDA RGPIO6 RGPIO7 RGPIO8 RGPIO9 FTM1_CH0 FTM1_CH1 FTM1_CH2 FTM1_CH3 FTM1_CH4 FTM1_CH5 SPI1_SS SPI1_SCLK SPI1_MISO SPI1_MOSI CLKOUT EZP_CLK EZP_DI EZP_DO SPI1_MOSI FBa_AD11 SPI1_MISO FBa_AD12 SPI1_SCLK FBa_AD13 SPI1_SS SPI0_SS FBa_AD14 FBa_AD15 FBa_AD16 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort ADC0_DP1/ ADC0_DP1/ PTA4 ADC0_SE2 ADC0_SE2 ADC0_DM1/ ADC0_DM1/ PTA5 ADC0_SE3 ADC0_SE3 VDDA VREFH VREFL VSSA VDDA VREFH VREFL VSSA VREF_OUT VREF_OUT DAC0_OUT DAC0_OUT ADC0_DP0/ ADC0_DP0/ ADC0_SE0 ADC0_SE0 ADC0_DM0/ ADC0_DM0/ ADC0_SE1 ADC0_SE1 VREGIN VOUT33 VREGIN VOUT33 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 51 Pinout 64pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 48pin 19 20 21 -- 22 -- -- 23 24 -- -- -- 25 26 -- -- 44pin 17 18 19 -- 20 -- -- 21 22 -- -- -- 23 24 -- -- 32pin 14 -- 15 -- -- -- -- 16 -- -- -- -- 17 18 -- -- Default VSS VDD ALT0 VSS VDD LPTMR_AL T1 FTM0_QD_ PHA FTM0_QD_ PHB RGPIO10 RGPIO11 RGPIO12 RGPIO13 UART0_TX UART0_RX UART0_CT S_b UART0_RT S_b SPI0_SS I2C0_SCL SPI0_SCLK I2C0_SDA I2C3_SCL SPI0_MOSI I2C3_SDA FTM_FLT2 RGPIO14 I2C3_SCL I2C3_SDA FTM_FLT0 IRQ/ EZP_MS_b LPTMR_AL T2 FTM0_QD_ PHB FBa_D0 FBa_OE_b FB_CLKOU T RGPIO15 FTM0_QD_ PHA FTM_FLT1 FTM0_CH0 FTM0_CH1 FBa_D6 FBa_AD0 FBa_D7 FBa_D6 FBa_D5 FBa_D4 FBa_D3 FBa_D2 FBa_D1 EZP_CS_b FBa_D7 FBa_AD17 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort ADC0_SE8/ ADC0_SE8/ PTA6 TSI0_CH0 TSI0_CH0 ADC0_SE9/ ADC0_SE9/ PTD2 TSI0_CH1 TSI0_CH1 ADC0_SE1 ADC0_SE1 PTD3 0/TSI0_CH2 0/TSI0_CH2 ADC0_SE1 ADC0_SE1 PTD4 1/TSI0_CH3 1/TSI0_CH3 ADC0_SE1 ADC0_SE1 PTD5 2/TSI0_CH4 2/TSI0_CH4 ADC0_SE1 ADC0_SE1 PTA7 3/TSI0_CH5 3/TSI0_CH5 ADC0_SE1 ADC0_SE1 PTD6 4/TSI0_CH6 4/TSI0_CH6 ADC0_SE1 ADC0_SE1 PTD7 5/TSI0_CH7 5/TSI0_CH7 TSI0_CH8 TSI0_CH9 IRQ/ EZP_MS_b TSI0_CH10 TSI0_CH11 ADC0_SE1 6/ TSI0_CH12 ADC0_SE1 7/ TSI0_CH13 ADC0_SE1 8/ TSI0_CH14 ADC0_SE1 9/ TSI0_CH15 ADC0_SE2 0 ADC0_SE2 1 ADC0_SE2 2 BKGD/MS XTAL2 EXTAL2 TSI0_CH8 TSI0_CH9 Disabled TSI0_CH10 TSI0_CH11 ADC0_SE1 6/ TSI0_CH12 ADC0_SE1 7/ TSI0_CH13 ADC0_SE1 8/ TSI0_CH14 ADC0_SE1 9/ TSI0_CH15 ADC0_SE2 0 ADC0_SE2 1 ADC0_SE2 2 Disabled XTAL2 EXTAL2 PTE0 PTE1 PTB0 PTB1 PTE2 PTE3 39 27 25 19 PTB2 SPI0_MISO FBa_CS0_b 40 28 26 20 PTB3 SPI0_MOSI FBa_CS1_b FBa_ALE 41 29 -- -- PTE4 UART0_RT S_b UART0_CT S_b UART0_RX UART0_TX BKGD/MS LPTMR_AL T3 I2C1_SCL I2C1_SDA PDB0_EXT RG SPI1_SS FBa_AD1 42 43 44 45 46 47 30 -- 31 32 33 34 -- -- 27 28 29 30 -- -- -- 21 22 23 PTE5 PTE6 PTE7 PTB4 PTB5 PTB6 SPI1_SCLK SPI1_MISO SPI1_MOSI FBa_RW_b FBa_AD2 FBa_AD3 FBa_AD4 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 52 Preliminary Freescale Semiconductor, Inc. Pinout 64pin 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48pin 35 36 37 38 39 -- -- -- 40 41 42 43 44 45 46 47 48 44pin 31 32 33 34 35 -- -- -- 36 37 38 39 40 41 42 43 44 32pin 24 25 26 27 28 -- -- -- -- 29 -- -- -- -- 30 31 32 Default VDD VSS EXTAL1 XTAL1 RESET_b CMP0_IN0 Disabled CMP0_IN1 CMP0_IN2 CMP0_IN3 Disabled Disabled Disabled Disabled Disabled Disabled Disabled ALT0 VDD VSS EXTAL1 XTAL1 Disabled CMP0_IN0 Disabled CMP0_IN1 CMP0_IN2 CMP0_IN3 Disabled Disabled Disabled Disabled Disabled Disabled Disabled PTB7 PTC0 PTC1 PTF0 PTF1 PTF2 PTF3 PTC2 PTF4 PTF5 PTF6 PTF7 PTC3 PTC4 PTC5 RESET_b SPI0_SS SPI0_SCLK SPI0_MISO SPI0_MOSI UART1_RT S_b UART1_CT S_b UART1_RX UART1_TX UART0_RT S_b UART0_CT S_b UART0_RX UART0_TX RGPIO3 RGPIO4 RGPIO5 SPI1_SS SPI1_SCLK SPI1_MISO SPI1_MOSI SPI0_SS RGPIO1 RGPIO2 FBa_D3 FBa_D2 FBa_D1 FBa_D0 FBa_AD5 CMP0_OUT FBa_AD6 FBa_AD7 FBa_AD8 FBa_AD18 FBa_AD19 FBa_RW_b FBa_AD9 FBa_AD10 I2C1_SDA I2C1_SCL TMR_CLKI N1 TMR_CLKI N0 RGPIO0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort SPI0_SCLK CLKOUT SPI0_MISO PDB0_EXT RG SPI0_MOSI CMT_IRO 8.2 Pinout diagrams The following diagrams show pinouts for the 64-pin, 48-pin, 44-pin, and 32-pin packages. For each pin, the diagrams show the default function or (when disabled is the default) the ALT1 signal for a GPIO function. However, many signals may be multiplexed onto a single pin. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 53 Pinout CMP0_IN2 CMP0_IN1 CMP0_IN3 CMP0_IN0 RESET_b PTC5 PTC4 PTF1 EXTAL1 50 PTC3 PTF7 PTF5 PTF6 PTF4 XTAL1 61 62 59 55 52 51 58 63 60 56 57 VDD VSS PTC6 PTC7 PTD0 PTD1 PTA0 PTA1 PTA2 PTA3 ADC0_DP1/ADC0_SE2 ADC0_DM1/ADC0_SE3 VDDA VREFH VREF_OUT VREFL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 25 26 23 24 27 28 29 31 17 18 19 20 30 64 54 53 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 VSS VDD EXTAL2 XTAL2 BKGD/MS ADC0_SE22 ADC0_SE21 ADC0_SE20 ADC0_SE19/TSI0_CH15 ADC0_SE18/TSI0_CH14 ADC0_SE17/TSI0_CH13 ADC0_SE16/TSI0_CH12 TSI0_CH11 TSI0_CH10 IRQ/EZP_MS_b TSI0_CH9 TSI0_CH8 ADC0_DP0/ADC0_SE0 DAC0_OUT ADC0_DM0/ADC0_SE1 VSSA VREGIN ADC0_SE11/TSI0_CH3 ADC0_SE12/TSI0_CH4 ADC0_SE14/TSI0_CH6 VOUT33 ADC0_SE8/TSI0_CH0 ADC0_SE9/TSI0_CH1 ADC0_SE10/TSI0_CH2 Figure 22. 64-pin Laminate QFN (pinout identical for 64-pin LQFP) MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 54 Preliminary ADC0_SE13/TSI0_CH5 ADC0_SE15/TSI0_CH7 VDD VSS Freescale Semiconductor, Inc. Pinout CMP0_IN3 CMP0_IN2 RESET_b 48 46 45 47 44 43 42 41 39 40 38 37 EXTAL1 XTAL1 PTC5 PTC4 PTC3 PTF7 PTF6 PTF5 PTF4 PTD0 PTD1 PTA0 PTA1 PTA2 PTA3 ADC0_DP1/ADC0_SE2 ADC0_DM1/ADC0_SE3 VDDA VREFH VREF_OUT VREFL 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 13 14 15 16 17 18 19 20 24 36 35 34 33 32 31 30 29 28 27 26 25 VSS VDD EXTAL2 XTAL2 BKGD/MS ADC0_SE22 ADC0_SE20 ADC0_SE19/TSI0_CH15 ADC0_SE18/TSI0_CH14 ADC0_SE17/TSI0_CH13 TSI0_CH10 IRQ/EZP_MS_b ADC0_DP0/ADC0_SE0 ADC0_DM0/ADC0_SE1 VOUT33 VSS DAC0_OUT VREGIN VSSA VDD ADC0_SE8/TSI0_CH0 ADC0_SE10/TSI0_CH2 ADC0_SE13/TSI0_CH5 Figure 23. 48-pin LQFP MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary ADC0_SE14/TSI0_CH6 55 Pinout CMP0_IN3 CMP0_IN2 RESET_b 35 44 43 42 41 39 40 38 37 36 34 XTAL1 PTC5 PTC4 PTC3 PTF7 PTF6 PTF5 PTF4 PTA0 PTA1 PTA2 PTA3 ADC0_DP1/ADC0_SE2 ADC0_DM1/ADC0_SE3 VDDA VREFH VREF_OUT VREFL VSSA 1 2 3 4 5 6 7 8 9 10 11 21 12 13 14 15 16 17 18 19 20 22 33 32 31 30 29 28 27 26 25 24 23 EXTAL1 VSS VDD EXTAL2 XTAL2 BKGD/MS ADC0_SE22 ADC0_SE18/TSI0_CH14 ADC0_SE17/TSI0_CH13 TSI0_CH10 IRQ/EZP_MS_b DAC0_OUT ADC0_SE8/TSI0_CH0 VREGIN VOUT33 VDD ADC0_DM0/ADC0_SE1 ADC0_SE10/TSI0_CH2 ADC0_DP0/ADC0_SE0 VSS ADC0_SE13/TSI0_CH5 Figure 24. 44-pin Laminate QFN MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 56 Preliminary ADC0_SE14/TSI0_CH6 Freescale Semiconductor, Inc. Pinout CMP0_IN3 RESET_b PTC5 PTC4 PTC3 EXTAL1 26 XTAL1 32 31 29 30 28 27 25 VSS PTA0 PTA1 PTA2 PTA3 ADC0_DP1/ADC0_SE2 ADC0_DM1/ADC0_SE3 VDDA VSSA 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 24 23 22 21 20 19 18 17 VDD EXTAL2 XTAL2 BKGD/MS ADC0_SE18/TSI0_CH14 ADC0_SE17/TSI0_CH13 TSI0_CH10 IRQ/EZP_MS_b ADC0_DM0/ADC0_SE1 VREGIN ADC0_SE8/TSI0_CH0 DAC0_OUT Figure 25. 32-pin QFN 8.3 Module-by-module signals NOTE * On PTB0, EZP_MS_b is active only during reset. Refer to the detailed boot description. * PTC1 is open drain. Table 35. Module signals by GPIO port and pin 64-pin 48-pin 44-pin 32-pin Port Module signal(s) Power and ground 1 24 20 18 Table continues on the next page... VDD VDD MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary ADC0_SE13/TSI0_CH5 ADC0_DP0/ADC0_SE0 VOUT33 VSS 57 Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 48 2 23 49 19 36 17 32 System 45 12 62 10 11 12 35 52 32 8 46 6 7 8 25 39 28 6 42 4 5 6 23 35 OSC 50 47 51 46 37 34 38 33 33 30 34 29 LLWU 4 6 12 30 32 35 36 39 44 45 55 56 57 59 62 40 41 43 46 36 37 39 42 30 29 25 26 27 31 32 23 24 25 27 28 21 17 18 19 2 8 23 6 21 6 16 PTC7 PTD1 PTA5 PTA7 PTD7 PTB0 PTB1 PTB2 PTE7 PTB4 PTF2 PTF3 PTC2 PTF5 PTC3 LLWU_P0 LLWU_P1 LLWU_P2 LLWU_P3 LLWU_P4 LLWU_P5 LLWU_P6 LLWU_P7 LLWU_P8 LLWU_P9 LLWU_P10 LLWU_P11 LLWU_P12 LLWU_P13 LLWU_P14 26 23 27 22 PTB7 PTB6 PTC0 PTB5 EXTAL1 EXTAL2 XTAL1 XTAL2 21 6 30 4 5 6 17 28 PTB4 PTA5 PTC3 PTA3 PTA4 PTA5 PTB0 PTC1 BKGD/MS CLKOUT CLKOUT EZP_CLK EZP_DI EZP_DO IRQ/EZP_MS_b, EZP_CS_b RESET_b 14 25 48-pin 35 44-pin 31 32-pin 24 Port Module signal(s) VDD VSS VSS VSS Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 58 Preliminary Freescale Semiconductor, Inc. Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 63 48-pin 47 44-pin 43 RGPIO 51 56 57 62 63 64 3 4 5 6 26 27 28 29 31 32 LPTMR 25 36 41 21 26 29 LPTMR-TOD 50 47 25 36 41 51 46 37 34 21 26 29 38 33 34 29 PTA 7 8 9 10 3 4 5 6 1 2 3 4 1 2 3 4 PTA0 PTA1 PTA2 PTA3 PTA0 PTA1 PTA2 PTA3 27 22 33 30 19 24 26 23 15 18 PTB7 PTB6 PTA6 PTB1 PTE4 PTC0 PTB5 EXTAL1 EXTAL2 LPTMR_ALT1 LPTMR_ALT2 LPTMR_ALT3 XTAL1 XTAL2 19 24 15 18 PTA6 PTB1 PTE4 LPTMR_ALT1 LPTMR_ALT2 LPTMR_ALT3 24 22 22 20 1 2 38 40 41 46 47 48 34 36 37 42 43 44 29 30 31 32 27 PTC0 PTF3 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 RGPIO0 RGPIO1 RGPIO2 RGPIO3 RGPIO4 RGPIO5 RGPIO6 RGPIO7 RGPIO8 RGPIO9 RGPIO10 RGPIO11 RGPIO12 RGPIO13 RGPIO14 RGPIO15 32-pin 31 Port PTC4 Module signal(s) LLWU_P15 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 59 Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 11 12 25 30 48-pin 7 8 21 23 44-pin 5 6 19 21 PTB 35 36 39 40 45 46 47 50 25 26 27 28 32 33 34 37 23 24 25 26 28 29 30 33 PTC 51 52 57 62 63 64 3 4 PTD 5 6 26 27 28 29 31 32 PTE 33 34 38 Table continues on the next page... PTE0 PTE1 PTE3 PTE0 PTE1 PTE2 24 22 22 20 1 2 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 38 39 41 46 47 48 34 35 37 42 43 44 27 28 29 30 31 32 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 17 18 19 20 21 22 23 26 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 32-pin 5 6 15 16 Port PTA4 PTA5 PTA6 PTA7 Module signal(s) PTA4 PTA5 PTA6 PTA7 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 60 Preliminary Freescale Semiconductor, Inc. Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 39 41 42 43 44 31 27 PTF 53 54 55 56 58 59 60 61 40 42 43 44 45 36 38 39 40 41 5 V VREG 22 21 18 17 16 15 ADC0 19 20 11 12 25 26 27 28 29 30 31 32 38 39 27 25 19 23 24 21 22 16 22 20 15 16 7 8 21 13 14 5 6 19 10 11 5 6 15 PTA4 PTA5 PTA6 PTD2 PTD3 PTD4 PTD5 PTA7 PTD6 PTD7 PTE3 PTB2 ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE1 ADC0_DP1/ ADC0_SE2 ADC0_DM1/ ADC0_SE3 ADC0_SE8 ADC0_SE9 ADC0_SE10 ADC0_SE11 ADC0_SE12 ADC0_SE13 ADC0_SE14 ADC0_SE15 ADC0_SE16 ADC0_SE17 13 12 VOUT33 VREGIN PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 48-pin 27 29 30 44-pin 25 32-pin 19 Port PTB2 PTE4 PTE5 PTE6 PTE7 Module signal(s) PTE3 PTE4 PTE5 PTE6 PTE7 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 61 Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 40 41 42 43 44 13 14 16 17 31 9 10 12 13 27 7 8 10 11 DAC0 18 14 12 VREF 15 11 9 CMP0 53 55 56 57 54 CMT 64 48 44 TSI0 25 26 27 28 29 30 31 32 33 34 36 37 38 Table continues on the next page... 26 24 18 23 24 21 22 16 22 20 21 19 15 PTA6 PTD2 PTD3 PTD4 PTD5 PTA7 PTD6 PTD7 PTE0 PTE1 PTB1 PTE2 PTE3 TSI0_CH0 TSI0_CH1 TSI0_CH2 TSI0_CH3 TSI0_CH4 TSI0_CH5 TSI0_CH6 TSI0_CH7 TSI0_CH8 TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 32 PTC5 CMT_IRO 40 41 36 37 29 PTF0 PTF2 PTF3 PTC2 PTF1 CMP0_IN0 CMP0_IN1 CMP0_IN2 CMP0_IN3 CMP0_OUT VREF_OUT 9 DAC0_OUT 8 7 48-pin 28 29 30 44-pin 26 32-pin 20 Port PTB3 PTE4 PTE5 PTE6 PTE7 Module signal(s) ADC0_SE18 ADC0_SE19 ADC0_SE20 ADC0_SE21 ADC0_SE22 VDDA VREFH VREFL VSSA MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 62 Preliminary Freescale Semiconductor, Inc. Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 39 40 41 48-pin 27 28 29 PDB0 44 63 31 47 27 43 FTM0 34 25 36 26 27 30 51 50 22 23 38 37 20 21 34 33 FTM1 34 25 36 7 8 9 10 11 12 51 50 21 26 3 4 5 6 7 8 38 37 19 24 1 2 3 4 5 6 34 33 MTIM 51 50 38 37 34 33 Mini-FlexBus 36 27 26 22 24 20 Table continues on the next page... 18 PTB1 PTD3 FB_CLKOUT FBa_AD0 27 26 PTC0 PTB7 TMR_CLKIN0 TMR_CLKIN1 15 18 1 2 3 4 5 6 27 26 PTE1 PTA6 PTB1 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTC0 PTB7 FTM_FLT0 FTM_FLT1 FTM_FLT2 FTM1_CH0 FTM1_CH1 FTM1_CH2 FTM1_CH3 FTM1_CH4 FTM1_CH5 TMR_CLKIN0 TMR_CLKIN1 16 27 26 21 26 19 24 15 18 PTE1 PTA6 PTB1 PTD2 PTD3 PTA7 PTC0 PTB7 FTM_FLT0 FTM_FLT1 FTM_FLT2 / FTM0_QD_PHB FTM0_CH0/ FTM0_QD_PHA FTM0_CH1 / FTM0_QD_PHB FTM0_QD_PHA TMR_CLKIN0 TMR_CLKIN1 31 PTE7 PTC4 PDB0_EXTRG PDB0_EXTRG 44-pin 25 26 32-pin 19 20 Port PTB2 PTB3 PTE4 Module signal(s) TSI0_CH13 TSI0_CH14 TSI0_CH15 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 63 Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 41 42 43 44 53 54 55 56 60 61 3 4 5 6 7 8 25 57 58 40 39 37 34 33 32 31 30 29 28 38 59 43 39 DATA_BUS 8 39 61 4 27 45 2 25 41 Table continues on the next page... 2 19 PTA1 PTB2 PTF7 FBa_AD16 FBa_CS0_b FBa_D0 24 23 22 21 16 1 2 3 4 21 41 42 28 27 1 2 19 37 38 26 25 20 19 1 2 15 29 40 44 45 36 40 41 31 27 48-pin 29 30 44-pin 32-pin Port PTE4 PTE5 PTE6 PTE7 PTF0 PTF1 PTF2 PTF3 PTF6 PTF7 PTC6 PTC7 PTD0 PTD1 PTA0 PTA1 PTA6 PTC2 PTF4 PTB3 PTB2 PTE2 PTE1 PTE0 PTD7 PTD6 PTA7 PTD5 PTD4 PTE3 PTF5 Module signal(s) FBa_AD1 FBa_AD2 FBa_AD3 FBa_AD4 FBa_AD5 FBa_AD6 FBa_AD7 FBa_AD8 FBa_AD9 FBa_AD10 FBa_AD11 FBa_AD12 FBa_AD13 FBa_AD14 FBa_AD15 FBa_AD16 FBa_AD17 FBa_AD18 FBa_AD19 FBa_ALE FBa_CS0_b FBa_D0 FBa_D1 FBa_D2 FBa_D3 FBa_D4 FBa_D5 FBa_D6 FBa_D7 FBa_OE_b FBa_RW_b MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 64 Preliminary Freescale Semiconductor, Inc. Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 60 59 58 31 30 27 25 44 48-pin 44 43 42 24 23 22 21 31 44-pin 40 39 38 22 21 20 19 27 I2C0 and I2C1 3 35 4 36 6 42 51 5 43 50 37 33 I2C2 and I2C3 7 11 8 12 32 37 33 38 SPI0 39 55 63 38 40 56 28 40 26 36 Table continues on the next page... 20 47 43 31 27 25 19 PTB2 PTF2 PTC4 PTE3 PTB3 PTF3 SPI0_MISO SPI0_MISO SPI0_MISO SPI0_MOSI SPI0_MOSI SPI0_MOSI 3 7 4 8 1 5 2 6 1 5 2 6 PTA0 PTA4 PTA1 PTA5 PTD7 PTE2 PTE0 PTE3 I2C2_SCL I2C2_SCL I2C2_SDA I2C2_SDA I2C3_SCL I2C3_SCL I2C3_SDA I2C3_SDA 26 26 2 30 38 1 34 27 24 18 25 23 17 PTC6 PTB0 PTC7 PTB1 PTD1 PTE5 PTC0 PTD0 PTE6 PTB7 I2C0_SCL I2C0_SCL I2C0_SDA I2C0_SDA I2C1_SCL I2C1_SCL I2C1_SCL I2C1_SDA I2C1_SDA I2C1_SDA 15 16 32-pin Port PTF6 PTF5 PTF4 PTD6 PTA7 PTD3 PTA6 PTE7 Module signal(s) FBa_D1 FBa_D2 FBa_D3 FBa_D4 FBa_D5 FBa_D6 FBa_D7 FBa_RW_b MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 65 Pinout Table 35. Module signals by GPIO port and pin (continued) 64-pin 64 36 54 62 7 34 53 61 45 41 SPI1 4 11 43 59 3 12 44 60 5 10 42 58 6 9 41 57 8 31 44 1 6 30 42 2 5 29 41 37 UART0 5 32 42 62 6 33 41 61 4 Table continues on the next page... 29 45 41 30 46 2 42 30 1 PTD0 PTD7 PTE5 PTC3 PTD1 PTE0 PTE4 PTF7 PTC7 UART0_CTS_b UART0_CTS_b UART0_CTS_b UART0_CTS_b UART0_RTS_b UART0_RTS_b UART0_RTS_b UART0_RTS_b UART0_RX 29 3 3 38 4 4 6 27 40 6 43 39 7 5 5 PTC7 PTA4 PTE6 PTF5 PTC6 PTA5 PTE7 PTF6 PTD0 PTA3 PTE5 PTF4 PTD1 PTA2 PTE4 PTC2 SPI1_MISO SPI1_MISO SPI1_MISO SPI1_MISO SPI1_MOSI SPI1_MOSI SPI1_MOSI SPI1_MOSI SPI1_SCLK SPI1_SCLK SPI1_SCLK SPI1_SCLK SPI1_SS SPI1_SS SPI1_SS SPI1_SS 46 3 42 1 30 1 48-pin 48 26 44-pin 44 24 32-pin 32 18 Port PTC5 PTB1 PTF1 PTC3 PTA0 PTE1 PTF0 PTF7 Module signal(s) SPI0_MOSI SPI0_SCLK SPI0_SCLK SPI0_SCLK SPI0_SS SPI0_SS SPI0_SS SPI0_SS MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 66 Preliminary Freescale Semiconductor, Inc. Revision History Table 35. Module signals by GPIO port and pin (continued) 64-pin 31 43 63 3 30 44 64 23 31 48 21 27 44 UART1 11 58 12 57 10 59 9 60 7 42 8 41 6 43 5 44 5 38 6 37 4 39 3 40 3 6 29 4 5 PTA4 PTF4 PTA5 PTC2 PTA3 PTF5 PTA2 PTF6 UART1_CTS_b UART1_CTS_b UART1_RTS_b UART1_RTS_b UART1_RX UART1_RX UART1_TX UART1_TX 32 16 47 43 31 48-pin 24 44-pin 22 32-pin Port PTD6 PTE6 PTC4 PTC6 PTA7 PTE7 PTC5 Module signal(s) UART0_RX UART0_RX UART0_RX UART0_TX UART0_TX UART0_TX UART0_TX 9 Revision History The following table provides a revision history for this document. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 67 Revision History Table 36. Revision History Rev. No. 2 Date 05/2011 Substantial Changes ESD handling ratings: Updated ambient temperature Voltage and current operating behaviors: * Added temperature conditions for input leakage current * Updated minimum value for pullup/pulldown resistors Power mode transition operating behaviors: Changed Max value to TBD for VLLS1 RUN, VLLS2 RUN, and VLLS3 RUN Power consumption operating behaviors: * Provided or updated typical values for: * IDD_RUN (all peripheral clocks enabled, code executing from RAM) * IDD_WAIT (25 MHz core and system clocks) * IDD_STOP * IDD_VLPR (both sets of conditions) * IDD_VLPW * IDD_VLPS * IDD_VLLS2 (-40C to 25C) * IDD_VLLS1 (-40C to 25C) * Added row for Wait mode current with 50 MHz core and system clock * Updated note for IDD_VLPR (all peripheral clocks disabled) Device clock specifications: Added LPTMR clock in both Normal run mode and VLPR mode Thermal attributes: Updated entire table Updated information for the following peripheral modules: * MCG * OSC (DC electrical specifications and frequency specifications) * EzPort * Mini-FlexBus * ADC * 12-bit DAC * CMP * VREF * VREG * TSI Obtaining package dimensions: Added document number for 64-pin Laminate QFN package MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 68 Preliminary Freescale Semiconductor, Inc. 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