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P83C557E4/P80C557E4/P89C557E4 Single-chip 8-bit microcontroller
Product specification Supersedes data of 1999 Feb 15 1999 Mar 02
Philips Semiconductors
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
1. FEATURES
* * * * * * * * * * * * * * * * * * * * *
80C51 central processing unit 32 K x 8 ROM respectively FEEPROM (Flash-EEPROM), expandable externally to 64 Kbytes ROM/FEEPROM Code protection 1024 x 8 RAM, expandable externally to 64 Kbytes Two standard 16-bit timer/counters An additional 16-bit timer/counter coupled to four capture registers and three compare registers A 10-bit ADC with eight multiplexed analog inputs and programmable autoscan Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs I2C-bus serial I/O port with byte oriented master and slave functions Full-duplex UART compatible with the standard 80C51 On-chip watchdog timer 15 interrupt sources with 2 priority levels (2 to 6 external sources possible) Extended temperature range (-40 to +85C) 4.5 to 5.5 V supply voltage range Frequency range for 80C51-family standard oscillator: 3.5 MHz to 16 MHz PLL oscillator with 32 kHz reference and software-selectable system clock frequency Seconds Timer Software enable/disable of ALE output pulse Electromagnetic compatibility improvements Wake-up from Power-down by external or seconds interrupt
2. GENERAL DESCRIPTION
The P80C557E4/P83C557E4/P89C557E4 (hereafter generically referred to as P8xC557E4) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The P8xC557E4 has the same instruction set as the 80C51. Three versions of the derivative exist:
* * *
P83C557E4 -- 32 Kbytes mask programmable ROM P80C557E4 -- ROMless version of the P83C557E4 P89C557E4 -- 32 Kbytes FEEPROM (Flash-EEPROM)
The P8xC557E4 contains a non-volatile 32 Kbytes mask programmable ROM (P83C557E4) or electrically erasable FEEPROM respectively (P89C557E4), a volatile 1024 x 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer, an on-chip oscillator and timing circuits. For systems that require extra capability the P8xC557E4 can be expanded using standard TTL compatible memories and logic. In addition, the P8xC557E4 has two software selectable modes of power reduction -- Idle Mode and power-down mode. The Idle Mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic as well as bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system clock, 58% of the instructions are executed in 0.75 s and 40% in 1.5 s. Multiply and divide instructions require 3 s.
1999 Mar 02
2
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
3. ORDERING INFORMATION
EXTENDED TYPE NUMBER ROMless P80C557E4EBB P80C557E4EFB ROM coded P83C557E4EBB/YYY1 P83C557E4EFB/YYY1 FEEPROM P89C557E4EBB P89C557E4EFB QFP80 QFP80 Plastic Quad Flat Pack; 80 leads Plastic Quad Flat Pack; 80 leads SOT318-1 SOT318-1 3.5 to 16 3.5 to 16 0 to +70 -40 to +85 QFP80 QFP80 Plastic Quad Flat Pack; 80 leads Plastic Quad Flat Pack; 80 leads SOT318-1 SOT318-1 3.5 to 16 3.5 to 16 0 to +70 -40 to +85 QFP80 QFP80 Plastic Quad Flat Pack; 80 leads Plastic Quad Flat Pack; 80 leads SOT318-1 SOT318-1 3.5 to 16 3.5 to 16 0 to +70 -40 to +85 PACKAGE NAME DESCRIPTION CODE FREQUENCY RANGE (MHz) TEMPERATURE RANGE (C)
NOTE: 1. YYY denotes the ROM code number
T0 3
T1 3
INT0 3
INT1 3 VDD VSS
PWM0 PWM1 AV SS
AVREF
ADC0-7 SDA 5
SCL
+-
AVDD
ADEXS
SELXTAL1 6 7 DATA MEMORY 256 x 8 RAM + 768 x 8 RAM DUAL PWM I2C SERIAL I/O
RSTIN
XTAL1 XTAL2 EA ALE PSEN 3 WR 3 RD
T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS
CPU
PROGRAM MEMORY 32 K x 8 ROM /FEEPROM,
1Kx8 boot ROM
ADC
80C51 CORE EXCLUDING ROM/RAM
8-BIT INTERNAL BUS
0 AD0-7 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORTS FOUR 16-BIT CAPTURE LATCHES 16 T2 16-BIT TIMER/ EVENT COUNTERS T2 16-BIT COMPARATORS WITH REGISTERS
16
COMPARATOR OUTPUT SELECTION
T3 WATCH- DOG TIMER
PLL oscillator + "seconds" timer
3 P0 P1 P2 P3 TxD
3 RxD P5 P4
1 CT0I-CT3I
1 T2 RT2
1
4 EW XTAL3 XTAL4 CMSR0-CMSR5 RSTOUT CMT0, CMT1
0 1 2
ALTERNATE FUNCTION OF PORT0 ALTERNATE FUNCTION OF PORT1 ALTERNATE FUNCTION OF PORT2
3 4 5
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
6 7
NOT PRESENT IN P80C557E4 ONLY PRESENT IN P89C557E4
Figure 1. Block diagram P8xC557E4
1999 Mar 02
3
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
VSS VDD XTAL1 XTAL2 EA ALE/WE * PSEN AVSS AVDD AVref+ AVref- ADEXS PWM0 PWM1 SCL SDA 0 1 2 3 4 5 6 7 P8xC557E4 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
XTAL3 XTAL4 SELXTAL1 0 1 2 3 4 5 6 7
PORT 0
LOW ORDER ADDRESS AND DATA BUS AD0-7
CT0I/INT2 CT1I/INT3 CT2I/INT4 PORT 1 CT3I/INT5 T2 RT2
ADC0-7 PORT 5
CMSR0-5 PORT 4
PORT 3
CMT0 CMT1 RSTIN RSTOUT EW
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
PORT 2
HIGH ORDER ADDRESS BUS A8-15
0 1 2 3 4 5 6 7
RXD/DATA TXD/CLOCK INT0 INT1 T0 T1 WR RD
*) only P89C557E4 with alternate function WE Figure 2. Functional diagram
1999 Mar 02
4
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
4. PINNING
SELXTAL1 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7
XTAL4
XTAL3
AVDD2
AVSS2
V DD4 66
V SS4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
AVref- AVref+ AVSS
1 AVDD1
1 2 3 4 5 6 7 8 9 10
65 64 63 62 61 60 59 58 57 56 55 54
EA
ALE/WE * PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 VSS3 VDD3 XTAL1 XTAL2 n.c. n.c. P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TXD P3.0/RXD
P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2
P5.1/ADC1 11 P5.0/ADC0 VSS1 VDD1 12 13 14
P8xC557E4
53 52 51 50 49 48 47 46 45 44 43 42 41
ADEXS 15 PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3 RSTOUT P4.4/CSMR4 16 17 18 19 20 21 22 23 24 P1.0/CT0I/INT2 31 28 29 P4.5/CMSR5 25 P4.6/CMT0 26 P4.7/CMT1 27 30 P1.1/CT1I/INT3 32 P1.2/CT2I/INT4 33 P1.3/CT3I/INT5 34 P1.4/T2 35 P1.5/RT2 36 37 38 39 SCL 40 SDA
P1.6
V DD2
n.c. *
= not connected = only P89C557E4 with alternate function WE Figure 3. Pinning diagram for QFP80 (SOT318)
RSTIN
V SS2
1999 Mar 02
5
P1.7
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
4.1
PIN DESCRIPTION
PIN 1 2 3 4 77 76 5 - 12 DESCRIPTION Low end of analog to digital conversion reference resistor High end of analog to digital conversion reference resistor. Analog ground for ADC Analog power supply (+5 V) for ADC Analog ground; for PLL oscillator Analog power supply; (+5 V) for PLL oscillator Port 5 8-bit input port Port pin P5.0-P5.7 Alternative function Eight input channels to ADC (ADC0-ADC7)
SYMBOL AVref- AVref+ AVSS1 AVDD1 AVSS2 AVDD2 P5.7 - P5.0
VDD1, VDD2, VDD3, VDD4 VSS1, VSS2 VSS3, VSS4 ADEXS PWM0 PWM1 EW
14, 28, 53, 66 13, 29, 54, 67 15 16 17 18
Digital power supply: +5 V power supply pins during normal operation and power reduction modes. All pins must be connected. Digital ground: circuit ground potential. All pins must be connected. Start ADC operation: Input starting analog to digital conversion triggered by a programmable edge (ADC operation can also be started by software). This pin must not float Pulse width modulation output 0 Pulse width modulation output 1 Enable watchdog timer: Enable for T3 watchdog timer and disable Power-down Mode.This pin must not float. Port 4 8-bit quasi-bidirectional I/O port Port pin P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 Alternative function CMSR0 } CMSR1 } CMSR2 } compare and set/reset CMSR3 } outputs on a match with timer T2 CMSR4 } CMSR5 } CMT0 } compare and toggle outputs CMT1 } on a match with timer T2
P4.0 - P4.7
19 - 22 24 - 27
RSTIN RSTOUT P1.0 - P1.7
30 23 31 - 38
Reset: Input to reset the P8xC557E4. Reset: Output of the P8xC557E4 for resetting peripheral devices during initialization and Watchdog Timer overflow. Port 1 8-bit quasi-bidirectional I/O port Port pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Alternative function CT0I/INT2} CT1I/INT3} : CT2I/INT4} CT3I/INT5} T2 : RT2 : Capture timer inputs for timer T2 or external interrupt inputs T2 event input, rising edge triggered T2 timer reset input, rising edge triggered
SCL SDA
39 40
I2C-bus serial clock I/O port I2C-bus serial data I/O port If SCL and SDA are not used, they must be connected to VSS.
1999 Mar 02
6
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
PIN DESCRIPTION (Continued)
SYMBOL P3.0 - P3.7 PIN 41 - 48 DESCRIPTION 8-bit quasi-bidirectional I/O port Port pin Alternative function P3.0 RXD : Serial input port P3.1 TXD : Serial output port : External interrupt P3.2 INT0 P3.3 INT1 : External interrupt P3.4 T0 : Timer 0 external input P3.5 T1 : Timer 1 external input : External data memory write strobe P3.6 WR P3.7 RD : External data memory read strobe Not connected pins. Crystal pin 2: output of the inverting amplifier that forms the oscillator. Left open-circuit when an external oscillator clock is used. Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external oscillator clock signal when an external oscillator is used. Must be connected to logic HIGH if the PLL oscillator is selected (SELXTAL1 = LOW). Port2: 8-bit quasi-bidirectional I/O port with internal pull-ups.During access to external memories (RAM/ROM) that use 16-bit addresses (MOVX@DPTR) Port 2 emits the high order address byte. The alternative function of P2.7 for the P89C557E4 is the output enable signal for verify/read modes (active low). Port 2 can sink/source one TTL (=4 LSTTL) input. It can drive CMOS inputs without external pull-ups. PSEN 63 Program Store Enable output: read strobe to the external program memory via Port 0 and 2. Is activated twice each machine cycle during fetches from external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Address Latch Enable output: latches the low byte of the address during access of external memory in normal operation. It is activated every six oscillator periods except during an external data memory access. ALE/WE can sink/-source 8 LSTTL inputs. It can drive CMOS inputs without an external pull-up. The alternative function for the P89C557E4 is the programming pulse input WE. To prohibit the toggling of ALE pin (RFI noise reduction) the bit RFI in the PCON Register (PCON.5) must be set by software. This bit is cleared on RESET and can be set and cleared by software. When set, ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE if external memory is accessed. ALE will retain its normal high value during Idle Mode and a low value during Power-down Mode while in the "RFI" mode. Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal program memory size. During external access (EA = 0) ALE will always toggle normally, whether the flag "RFI" is set or not. EA 65 External Access Input: If, during RESET, EA is held at a TTL level HIGH the CPU executes out of the internal program memory, provided the program counter is less than 32768. If, during RESET, EA is held at a TTL level LOW the CPU executes out of external program memory via Port 0 and Port 2. EA is not allowed to float. EA is latched during RESET and don't care after RESET. Port 0: 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address and data bus during accesses to external memory (during theses accesses internal pull-ups are activated). Port 0 can sink/source 8 LSTTL inputs. Crystal pin, output of the inverting amplifier that forms the 32 kHz oscillator Crystal pin, input to the inverting amplifier that forms the 32 kHz oscillator. XTAL3 and XTAL4 are pulled LOW if the PLL oscillator is not selected (SELXTAL1 = HIGH) or if Reset is active. Must be connected to logic HIGH level to select the HF oscillator, using the XTAL1/XTAL2 crystal. If pulled low the PLL is selected for clocking of the controller, using the XTAL3/ XTAL4 crystal.
N.C. XTAL2 XTAL1
49 - 50 51 52
P2.0 - P2.7
55 - 62
ALE/WE
64
P0.7-P0.0
68 -75
XTAL3 XTAL4 SELXTAL1
78 79 80
NOTE: 1. To avoid a `latch-up' effect at Power-on, the voltage at any pin at any time must not be higher or lower than VDD+ 0.5 V or VSS- 0.5 V respectively.
1999 Mar 02
7
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
5. ELECTROMAGNETIC COMPATIBILITY (EMC) IMPROVEMENTS
Primary attention was paid on the reduction of electromagnetic emission of the microcontroller P8xC557E4. The following features effect in reducing the electromagnetic emission and additionally improve the electromagnetic susceptibility:
6. FUNCTIONAL DESCRIPTION 6.1 General
The P8xC557E4 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications. The P8xC557E4 is a control-oriented CPU with on-chip program and data memory. It can be extended with external program memory up to 64 Kbytes. It can also access up to 64 Kbytes of external data memory. For systems requiring extra capability, the P8xC557E4 can be expanded using standard memories and peripherals. The P8xC557E4 has two software selectable modes of reduced activity for further power reduction - Idle and Power-down. The Idle Mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. The Power-down Mode can be terminated by an external Reset, by the seconds interrupt and by any one of the two external interrupts. (See description Wake-up from Power-down Mode.)
* * * *
Four supply voltage pins (VDD) and four ground pins (VSS) with pairs of VDD and VSS at two adjacent pins at each side of the package. Separated VDD pins for the internal logic and the port buffers Internal decoupling capacitance improves the EMC radiation behavior and the EMC immunity External capacitors are to be located as close as possible between pins VDD1 and VSS1, VDD2 and VSS2, VDD3 and VSS3 as well as VDD4 and VSS4 ; ceramic chip capacitors are recommended (100nF).
Useful in applications that require no external memory or temporarily no external memory:
*
The ALE output signal (pulses at a frequency of fCLK/6) can be disabled under software control (bit 5 in the SFR PCON: "RFI"); if disabled, no ALE pulse will occur. ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE (external data memory is accessed). ALE will retain its normal HIGH value during Idle Mode and a LOW value during Power-down mode while in the "RFI" reduction mode. Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal program memory size. During external access (EA = 0) ALE will always toggle normally, whether the flag "RFI" is set or not.
6.2 Memory organization
The central processing unit (CPU) manipulates operands in three memory spaces; these are the 64 Kbytes external data memory, 1024 bytes internal data memory (consisting of 256 bytes standard RAM and 768 bytes AUX-RAM) and the 32 Kbytes internal and/or 64 Kbytes external program memory (see Figure 4).
64 K 64 K
External
32768 Overlapped Space 32767 32767 255 Internal (EA = 1) External (EA = 0) 127 DIRECT AND INDIRECT 0 0 0 AUXILIARY RAM 0 INDIRECT ONLY Special Function Registers
768 (ARD = 0) (ARD = 1)
Program Memory
Internal Data Memory
External Data Memory
Figure 4. Memory map & address space
1999 Mar 02
8
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.2.1 Program Memory The program memory of the P8xC557E4 consists of 32 Kbytes ROM respectively FEEPROM ("Flash Memory") on-chip, externally expandable up to 64 Kbytes. If, during RESET, the EA pin was held HIGH, the P8xC557E4 executes out of the internal program memory unless the address exceeds 7FFFH. Locations 8000H through 0FFFFH are then fetched from the external program memory. If the EA pin was held LOW during RESET the P8xC557E4 fetches all instructions from the external program memory. The EA input is latched during RESET and is don't care after RESET. The internal program memory content is protected, by setting a mask programmable security bit (ROM) or by the software programmable security byte (FEEPROM) respectively, i.e. it cannot be read out at any time by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is 'don't care' after RESET. This implementation prevents from reading internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 1 lists the access to the internal and external program memory with MOVC instructions when the security feature has been activated. 6.2.2 Internal Data Memory The internal data memory is divided into three physically separated parts: 256 bytes of RAM, 768 bytes of AUX-RAM, and a 128 bytes special function area. These can be addressed each in a different way (see also Table 2). - RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected registerbank.
- RAM 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected registerbank. - AUX-RAM 0 to 767 is also indirectly addressable as external DATA MEMORY locations 0 to 767 via MOVX-Datapointer instruction, unless it is disabled by setting ARD = 1. AUX-RAM 0 to 767 is indirectly addressable via pageregister (XRAMP) and MOVX-Ri instructions, unless it is disabled by setting ARD = 1 (see Figure 5). When executing from internal program memory, an access to AUX-RAM 0 to 767 will not affect the ports P0, P2, P3.6 and P3.7. An access to external DATA MEMORY locations higher than 767 will be performed with the MOVX @ DPTR instructions in the same way as in the 80C51 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that the external DATA MEMORY cannot be accessed with R0 and R1 as address pointer if the AUX-RAM is enabled (ARD = 0, default). - The Special Function Registers (SFR) can only be addressed directly in the address range from 128 to 255 (see Table 5). - Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.The stack can be located anywhere in the internal 256 bytes RAM.The stack depth is only limited by the available internal RAM space of 256 bytes (see Figure 7). All registers except the program counter and the four register banks reside in the Special Function Register address space.
Table 1. Memory Access by the MOVC Instruction for Protected ROMs
MOVC LOCATION MOVC in internal program memory MOVC in external program memory ACCESS TO INTERNAL PROGRAM MEMORY YES NO ACCESS TO EXTERNAL PROGRAM MEMORY YES YES
NOTE: 1. If the security feature has not been activated, there are no restrictions for MOVC instructions.
Table 2. Internal Data Memory Map
LOCATION RAM AUX-RAM RAM SFR 0 to 127 0 to 767 128 to 255 128 to 255 ADDRESSED Direct and indirect Indirect only with MOVX Indirect only Direct only
1999 Mar 02
9
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
255 (XRAMP) = 02 H 0 255 MOVX @Ri, A MOVX A, @Ri 0 255 (XRAMP) = 00 H 0 (XRAMP) = 01 H
767
512 511 MOVX @DPTR,A MOVX A,@DPTR 256 255
0
Figure 5. Indirect addressing of AUX-RAM (768 Bytes), ARD bit in PCON = 0 6.2.2.1 AUX-RAM Page Register XRAMP The AUX-RAM Page Register is used to select one of three 256 bytes pages of the internal 768 bytes AUX-RAM for MOVX-accesses via R0 or R1. Its reset value is (XXXXXX00).
7 XRAMP (FAH) x
6 x
5 x
4 x
3 x
2 x
1 XRAMP1
0 XRAMP0
x: undefined during read, a write operation must write "0" to these locations Figure 6. AUX-RAM page register.
Table 3. Description of XRAMP Bits
BIT XRAMP.2-7 XRAMP.1 XRAMP.0 SYMBOL XRAMPx XRAMP1 XRAMP0 FUNCTION reserved for future use AUX-RAM page select bit 1 AUX-RAM page select bit 0
Table 4. Memory Locations for All Possible MOVX Accesses
ARD1 0 0 0 0 1 XRAMP1 0 0 1 1 X XRAMP0 0 1 0 1 X MOVX @Ri,A and MOVX A,@Ri instructions access: AUX-RAM AUX-RAM AUX-RAM locations 0 .. 255 (reset condition)
locations 256 .. 511 locations 512 .. 767
no valid memory access; reserved for future use External RAM locations 0 .. 255
MOVX @DPTR,A and MOVX A,@DPTR instructions access: 0 1 X X X X AUX-RAM locations 0 .. 767 (reset condition) External RAM locations 768 .. 65535 External RAM locations 0 .. 65535
NOTE: 1. ARD (AUX-RAM Disable) is a bit in the Special Function Register PCON
1999 Mar 02
10
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 5. Special Function Register Memory Map and Reset Values
HIGH NIBBLE OF SFR ADDRESS LOW 0 1 2 3 4 5 6 7 8 9 A B C D E F NOTES: %= # = X = * = ADRSL0 # XXXXXXXX PCON 00000000 TCON % 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 S0CON % 00000000 S0BUF XXXXXXXX IEN0 % 00000000 CML0 00000000 CML1 00000000 CML2 00000000 CTL0 # XXXXXXXX CTL1 # XXXXXXXX CTL2 # XXXXXXXX CTL3 # XXXXXXXX Bit addressable register Read only register Undefined FMCON only in P89C557E4 Access to memory addresses is as follows: or Register-Indirect addressing IP0 % X0000000 ADRSL1 # XXXXXXXX ADRSL2 # XXXXXXXX ADRSL3 # XXXXXXXX ADRSL4 # XXXXXXXX P5 # XXXXXXXX TM2IR % 00000000 CMH0 00000000 CMH1 00000000 CMH2 00000000 CTH0 # XXXXXXXX CTH1 # XXXXXXXX CTH2 # XXXXXXXX CTH3 # XXXXXXXX ADRSL5 # XXXXXXXX ADCON 00000000 S1CON % 00000000 S1STA # 11111000 S1DAT 00000000 S1ADR 00000000 TM2CON 00000000 CTCON 00000000 TML2 # 00000000 TMH2 # 00000000 STE 11000000 RTE 00000000 ADRSL6 # XXXXXXXX ADPSS 00000000 IEN1 % 00000000 ADRSL7 # XXXXXXXX ADRSH # 000000XX IP1 % 00000000 PLLCON 00001101 XRAMP XXXXXX00 FMCON * 000X0000 PWM0 00000000 PWM1 00000000 PWMP 00000000 T3 00000000 8 P0 % 11111111 SP 00000111 DPL 00000000 DPH 00000000 9 P1 % 11111111 A P2 % 11111111 B P3 % 11111111 C P4 % 11111111 D PSW % 00000000 E ACC % 00000000 F B% 00000000
6.3 Addressing
The P8xC557E4 has five methods for addressing:
* Register * Direct * Register-Indirect * Immediate * Base-Register plus Index-Register-Indirect
* Register in one of the four register banks through Register, Direct * 1024 bytes of internal RAM through Direct or Register-Indirect
addressing. - Bytes 0-127 of internal RAM may be addressed directly/indirectly. Bytes 128-255 of internal RAM share their address location with the SFRs and so may only be addressed indirectly as data RAM. - Bytes 0-767 of AUX-RAM can only be addressed indirectly via MOVX.
The first three methods can be used for addressing destination operands. Most instructions have a "destination/source" field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.
* Special Function Register through direct addressing at address
locations 128-255 (see Figure 8).
* External data memory through Register-Indirect addressing * Program memory look-up tables through Base-Register plus
Index-Register-Indirect addressing 11
1999 Mar 02
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
BYTE ADDRESS (HEX)
BIT ADDRESS (HEX)
BYTE ADDRESS (DECIMAL)
FFH
(MSB)
(LSB)
255
2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH
7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07
7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06
7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05
7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04
7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03
7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02
79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01
78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Bank 3 18H 17H Bank 2 10H 0FH Bank 1 08H 07H Bank 0 00H 0 8 7 16 15 24 23
Figure 7. RAM bit addresses
1999 Mar 02
12
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
DIRECT BYTE ADDRESS (HEX)
BIT ADDRESS (HEX)
REGISTER MNEMONIC
FFH
(MSB)
(LSB)
PT2 F8H FF
PCM2 FE
PCM1 FD
PCM0 FC
PCT3 FB
PCT2 FA
PCT1 F9
PCT0 F8 IP1
F0H
F7 ET2
F6 ECM2 EE
F5 ECM1 ED
F4 ECM0 EC
F3 ECT3 EB
F2 ECT2 EA
F1 ECT1 E9
F0 ECT0 E8
B
E8H
EF
IEN1
E0H
E7 CR2
E6 ENS1 DE AC D6 CMI2 CE
E5 STA DD F0 D5 CMI1 CD
E4 STO DC RS1 D4 CMI0 CC
E3 SI DB RS0 D3 CTI3 CB
E2 AA DA OV D2 CTI2 CA
E1 CR1 D9 F1 D1 CTI1 C9
E0 CR0 D8 P D0 CTI0 C8
ACC
D8H
DF CY
S1CON PSW
D0H
D7 T2OV
C8H
CF
TM2IR
C0H
C7 -
C6 PAD BE
C5 PS1 BD
C4 PS0 BC
C3 PT1 BB
C2 PX1 BA
C1 PT0 B9
C0 PX0 B8
P4
B8H
BF
IP0
B0H
B7 EA
B6 EAD AE
B5 ES1 AD
B4 ES0 AC
B3 ET1 AB
B2 EX1 AA
B1 ET0 A9
B0 EX0 A8
P3
A8H
AF
IEN0
A0H
A7 SM0
A6 SM1 9E
A5 SM2 9D
A4 REN 9C
A3 TB8 9B
A2 RB8 9A
A1 TI 99
A0 RI 98
P2
98H
9F
S0CON
90H
97 TF1
96 TR1 8E
95 TF0 8D
94 TR0 8C
93 IE1 8B
92 IT1 8A
91 IE0 89
90 IT0 88
P1
88H
8F
TCON
80H
87
86
85
84
83
82
81
80
P0
Figure 8. Special Function Register bit addresses
1999 Mar 02
13
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.4 I/O Facilities
The P8xC557E4 has six 8-bit ports. Ports 0 to 3 are the same as in the 80C51, with the exception of the additional functions of Port 1. The parallel I/O function of Port 4 is equal to that of Ports 1, 2 and 3. Port 5 has a parallel input port function, but has no function as an output port. The SDA and SCL lines serve the serial port SIO1 (I2C). Because the I2C-bus may be active while the device is disconnected from VDD, these pins, are provided with open drain drivers. Ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions: Port 0 : provides the multiplexed low-order address and data bus used for expanding the P8xC557E4 with standard memories and peripherals. Port 1 is used for a number of special functions: 4 capture inputs (or external interrupt request inputs if capture information is not utilized) - external counter input - external counter reset input Port 2 : provides the high-order address bus when the P8xC557E4 is expanded with external Program Memory and/or external Data Memory. pins can be configured individually to provide: - external interrupt request inputs - counter inputs - receiver input and transmitter output of seri port SIO 0 (UART) - control signals to read and write external Data Memory
Port 4 : Port 5 :
can be configured to provide signals indicating a match between timer counter T2 and its compare registers. may be used in conjunction with the ADC interface. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. Channel to channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to Port 5 (see DC characteristics).
All ports are bidirectional with the exception of Port 5 which is an input port. Pins of which the alternative function is not used may be used as normal bidirectional I/Os. The generation or use of a Port 1, Port 3 or Port 4 pin as an alternative function is carried out automatically by the P8xC557E4 provided the associated Special Function Register bit is set HIGH. The pull-up arrangements of Ports 1 - 4 are shown in Figure 9.
Port 1 :
Port 3 :
VDD 2 System Clock Periods
P1
VDD
VDD
P2
P3
Port Pin QN From Port Latch n
Input Data Read Port Pin P1 is turned on for 2 system clock periods after QN makes a 1-to-0 transition. During this time, P1 also turns on P3 through the inverter to form an additional pull up. Figure 9. I/O buffers in the P8xC557E4 (Ports 1, 2, 3 and 4)
1999 Mar 02
14
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.5 Pulse Width Modulated Outputs
The P8xC557E4 contains two pulse width modulated output channels (see Figure 13). These channels generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts module 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0/255 to 255/255 and may be programmed in increments of 1/255. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWMn. The PWM outputs may also be configured as a dual DAC. In this application, the PWM outputs must be integrated using
conventional operational amplifier circuitry. If the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before they are integrated. The repetition frequency fpwm, at the PWMn outputs is give by: fpwm + f CLK (1 ) PWMP)
2
255
This gives a repetition frequency range of 123 Hz to 31.4 kHz (fCLK = 16 MHz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose.
7 PWMP (FEH) PWMP.7
6 PWMP.6
5 PWMP.5
4 PWMP.4
3 PWMP.3
2 PWMP.2
1 PWMP.1
0 PWMP.0
Figure 10. Prescaler frequency control register PWMP.
Table 6. Description of PWMP Bits
BIT PWMP.0 to 7 Prescaler division factor = (PWMP) + 1 FUNCTION
NOTE: 1. Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
7 PWM0 (FCH) PWM0.7
6 PWM0.6
5 PWM0.5
4 PWM0.4
3 PWM0.3
2 PWM0.2
1 PWM0.1
0 PWM0.0
Figure 11. Pulse width register PWM0.
Table 7. Description of PWM0 bits
BIT PWM0.0 to 7 LOW/HIGH ration of PWM0 signal = FUNCTION (PWM0) 255 - (PWM0)
1999 Mar 02
15
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 PWM1 (FDH) PWM1.7
6 PWM1.6
5 PWM1.5
4 PWM1.4
3 PWM1.3
2 PWM1.2
1 PWM1.1
0 PWM1.0
Figure 12. Pulse width register PWM1.
Table 8. Description of PWM1 bits
BIT PWM1.0 to 7 LOW/HIGH ration of PWM1 signal = FUNCTION (PWM1) 255 - (PWM1)
PWM0
8-Bit Comparator fCLK
Internal Bus
Output Buffer
PWM0
1/2
Prescaler PWMP
8-Bit Counter
8-Bit Comparator
Output Buffer
PWM1
PWM1
Figure 13. Functional Diagram of Pulse Width Modulated Outputs.
1999 Mar 02
16
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.6 Analog/Digital Converter (ADC)
The P8xC557E4 A/D Converter is a 10-bit, successive approximation ADC with 8 multiplexed analog input channels. It additionally contains a high input impedance comparator, a DAC built with 1024 series resistors and analog switches, registers and control logic. Input voltage range is from AVref- (typical 0V) to AVref+ (typical +5V). A set of 8 buffer registers (10-bit) store the conversion results of the proper analog input channel each. 11 Special Function Registers (SFR) perform the user software interface to the ADC: a control SFR (ADCON), an analog port scan-select SFR (ADPSS), 8 input channel related conversion result SFR with the 8 lower result bits (ADRSL0...ADRSL7), one common result SFR for the upper 2 result bits (ADRSH). An extra SFR (P5) allows for reading digital input port data as an alternative function of the 8 analog input pins. In order to have a minimum of ADC service overhead in the microcontroller program, the ADC is able to operate autonomously within its user configurable autoscan function. The functional diagram of the ADC is shown in Figure 15. Feature Overview:
* Start of a conversion by software or with an external signal. * Eight 10-bit buffer registers, one register for each analog input
channel.
* Interrupt request after one channel scan loop. * Programmable prescaler (dividing by 2, 4, 6, 8) to adapt to
different system clock frequencies.
* 10-bit resolution. * 8 multiplexed analog inputs. * Programmable autoscan of the analog inputs. * Bit oriented 8-bit scan-select register to select analog inputs. * Continuous scan or one time scan configurable from 1 to 8 analog
inputs.
* Conversion time for one A/D conversion: 15 s ... 50 s * Differential non-linearity : DLe 1 LSB. * Integral non-linearity : ILe 2 LSB. * Offset error : OSe 2LSB. * Gain error : Ge 0.4 %. * Absolute voltage error : Ae 3 LSB. * Channel to channel matching : Mctc 1LSB. * Crosstalk between analog inputs : Ct < -60dB. @100 kHz. * Monotonic and no missing codes. * Separated analog (AVDD, AVSS) and digital (VDD, VSS) supply
voltages.
* Reference voltage at two special pins : AVREF- and AVREF+.
For further information on the ADC characteristics, refer to the "DC CHARACTERISTICS" section.
6.1.1 Functional description:
Table 9. A/D Special Function Registers
SYMBOL ADCON ADPSS ADRSLn ADRSH P5 NAME A/D control register Analog port scan-select register 8 A/D result registers, the 8 lower bits (n: 0...7) A/D result register, the 2 higher bits Digital input port (shared with analog inputs) ACCESS read/write read/write read only read only read only
A/D Control Register ADCON
The Special Function Register ADCON contains control and status bits for the A/D Converter peripheral block. The reset value of ADCON is (00000000). Its hardware address is D7H. ADCON is not bit addressable.
7 ADCON (D7H) ADPR1
6 ADPR0
5 ADPOS
4 ADINT
3 ADSST
2 ADCSA
1 ADSRE
0 ADSFE
Figure 14. ADC control register.
1999 Mar 02
17
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
ADC0 ANALOG Mux. COMPARATOR + - ADC7 AVref+ DAC AVref- AVDD1 AVSS1 ADEXS 2 SCAN LOGIC 2 LATCHES Read ADRSLn 2 INTERNAL BUS Figure 15. Functional diagram of AD converter. 8 10 10 10 SAR
8x 10-bit result registers
ADPSS 8
ADCON Read ADRSH 8
8
Table 10. Description of ADCON bits
SYMBOL ADCON.7 ADCON.6 BIT ADPR1 ADPR0 FUNCTION Control bit for the prescaler. Control bit for the prescaler. ADPR1=0 ADPR0=0 Prescaler divides by 2 (default by reset) ADPR1=0 ADPR0=1 Prescaler divides by 4 ADPR1=1 ADPR0=0 Prescaler divides by 6 ADPR1=1 ADPR0=1 Prescaler divides by 8 ADPOS is reserved for future use. Must be '0' if ADCON is written. ADC interrupt flag. This flag is set when all selected analog inputs are converted, as well in continuous scan as in one-time scan mode. An interrupt is invoked if this interrupt is enabled. ADINT must be cleared by software. It cannot be set by software. ADC start and status. Setting this bit by software or by hardware (via ADEXS input) starts the A/D conversion of the selected analog inputs. ADSST stays a `one' in continuous scan mode. In one-time scan mode, ADSST is cleared by hardware when the last selected analog input channel has been converted. As long as ADSST is '1', new start commands to the ADC-block are ignored. An A/D conversion in progress is aborted if ADSST is cleared by software. 1 0 1 0 1 0 = = = = = = Continuous scan of the selected analog inputs after a start of an A/D conversion. One-time scan of the selected analog inputs after a start of an A/D conversion. A rising edge at input ADEXS will start the A/D conversion and generate a capture signal. A rising edge at input ADEXS has no effect. A falling edge at input ADEXS will start the A/D conversion and generate a capture signal. A falling edge at input ADEXS has no effect.
ADCON.5 ADCON.4
ADPOS ADINT
ADCON.3
ADSST
ADCON.2 ADCON.1 ADCON.0
ADCSA ADSRE ADSFE
1999 Mar 02
18
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
A/D Input Port Scan-Select Register ADPSS
The Special Function Register ADPSS contains control bits to select the analog input channel(s) to be scanned for A/D conversion. The reset value of ADPSS is (00000000). Its hardware address is E7H. ADPSS is not bit addressable. If all bits are `0' then no A/D conversion can be started. If ADPSS is written while an A/D conversion is in progress (ADSST in the ADCON register is `1') then the autoscan loop with the previous selected analog inputs is completed first. The next autoscan loop is performed with the new selected analog inputs.
7 ADPSS (E7H) ADPSS7-0 ADPSS7
6 ADPSS6
5 ADPSS5 0 1
4 ADPSS4
3 ADPSS3
2 ADPSS2
1 ADPSS1
0 ADPSS0
For each individual bit position:
= The corresponding analog input is skipped in the auto-scan loop. = The corresponding analog input is included in the auto-scan loop.
Figure 16. A/D input port scan-select register.
A/D Result Registers ADRSLn and ADRSH:
The binary result code of A/D conversions is accessed by these Special Function Registers. The result SFR are read only registers. The read value after reset is indeterminate. Their data are not affected by chip reset. They are not bit addressable. There are 8 Special Function Registers ADRSLn (ADRSL0...ADRSL7) - A/D Result Low byte - and one general SFR ADRSH - A/D Result High byte - . Each of ADRSLn is associated with the coincidently indexed analog input channel ADCn (ADC0/P5.0...ADC7/P5.7). Reading an ADRSLn register by software copies at the same time the two highest bits of the 10-bit conversion result into two latches, thus preserving them until the next read of any ADRSLn register. These two latches form bit positions 0 and 1 of SFR ADRSH, the upper 6 bits of ADRSH are always read as '0'. Thus it is ensured to get the 10-bit result of the same single A/D conversion by reading any register ADRSLn first and after it the register ADRSH.
7 ADRSLn ADRSn.7
6 ADRSn.6
5 ADRSn.5
4 ADRSn.4
3 ADRSn.3
2 ADRSn.2
1 ADRSn.1
0 ADRSn.0
(n: 0...7)
7 ADRSH 0
6 0
5 0
4 0
3 0
2 0
1 ADRSn.9
0 ADRSn.8
Figure 17.
A/D Result Registers.
1999 Mar 02
19
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Digital Input Port Register P5
Port 5 Special Function Register P5 always represents the binary value of the logic level at input pins P5.0/ADC0...P5.7/ADC7. P5 is not affected by chip reset. P5 is a read only register. Its hardware address is C7H. P5 is not bit addressable. Reading Special Function Register P5 does not affect A/D conversions. But it is recommended to use the digital input port function of the hardware Port 5 only as an alternative to analog input voltage conversions. Simultaneous mixed operation is discouraged for the sake of A/D conversion result reliability and accuracy. For further information on Port 5, refer to the "I/O facilities" section. For further information on A/D Special Function Registers, refer to the "Internal Data Memory" section.
7 P5 (C7H) P5.7
6 P5.6
5 P5.5
4 P5.4
3 P5.3
2 P5.2
1 P5.1
0 P5.0
Figure 18. Digital input port register P5.
Reset
After a RESET of the microcontroller the ADCON and ADPSS register bits are initialized to zero. Registers ADRSLn and ADRSH are not initialized by a RESET.
For conversion times outside the limits for tconv the specified ADC characteristics are not guaranteed; (prohibited conversion times are put in brackets):
Idle and Power-down Mode
The A/D Converter is active only when the microcontroller is in normal operating mode. If the Idle or Power-down Mode is activated, then the ADC is switched off and put into a power saving idle state - a conversion in progress is aborted, a previously set ADSST flag is cleared and the internal clock is halted. The conversion result registers are not affected. The interrupt flag ADINT will not be set by activation of Idle or Power-down Mode. A previously set flag ADINT will not be cleared by the hardware. (Note: ADINT cannot be cleared by hardware at all, except for a RESET - it must be cleared by the user software.) After a wakeup from Idle or Power-down Mode a set flag ADINT indicates that at least one autoscan loop was finished completely before the microcontroller was put into the respective power reduction mode and it indicates that the stored result data may be fetched now - if desired. For further information on Idle and Power-down Mode, refer to the "Power reduction modes" section.
Table 11. Conversion time configuration examples (tconv/s)
fCLK m 2 4 6 8 6 MHz 26 50 [74] [98] 8 MHz 19.5 37.5 [55.5] [73.5] 12 MHz [13] 25 37 49 16 MHz [9.75] 18.75 27.75 36.75
Conversion time tconv = (6 m + 1) machine cycles A conversion time tconv consists of one sample time period (which equals two bit conversion times), 10 bit conversion time periods and one machine cycle to store the result. After result storage an extra initializing time period follows to select the next analog input channel (according to the contents of SFR ADPSS), before the input signal is sampled. Thus the time period between two adjacent conversions within an autoscan loop is larger than the pure time tconv. This autoscan cycle time is ( 7 m ) machine cycles. At the start of an autoscan conversion the time between writing to SFR ADCON and the first analog input signal sampling depends on the current prescaler value (m) and the relative time offset between this write operation and the internal (divided) ADC clock. This gives a variation range for the A/D conversion start time of ( m / 2 ) machine cycles.
Timing
A programmable prescaler is controlled by the bits ADPR1 and ADPR0 in register ADCON to adapt the conversion time for different microcontroller clock frequencies. Table 11 shows conversion times (tconv) for one A/D conversion at some convenient system clock frequencies (fclk) and ADC prescaler divisors (m), which are user selectable by the bits ADCON.7/ADPR1 and ADCON.6/ADPR0.
1999 Mar 02
20
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.6.2 Configuration and Operation Every A/D conversion is an autoscan conversion. The two user selectable general operation modes are continuous scan and one-time scan mode. The desired analog input port channel/s for conversion is/are selected by programming A/D input port scan-select bits in SFR ADPSS. An analog input channel is included in the autoscan loop if the corresponding bit in ADPSS is 1, a channel is skipped if the corresponding bit in ADPSS is 0. An autoscan is always started according to the lowest bit position of ADPSS that contains a 1. An autoscan conversion is started by setting the flag ADSST in register ADCON either by software or by an external start signal at input pin ADEXS, if enabled. Either no edge (external start totally disabled), a rising edge or/and a falling edge of ADEXS is selectable for external conversion start by the bits ADSRE and ADSFE in register ADCON. After completion of an A/D conversion the 10-bit result is stored in the corresponding 10-bit buffer register. Then the next analog input is selected according to the next higher set bit position in ADPSS, converted and stored, and so on. When the result of the last conversion of this autoscan loop is stored, flag ADCON.4/ADINT, the ADC interrupt flag, is set. It is not cleared by interrupt hardware - it must be cleared by software. In continuous scan mode (ADCON.2/ADCSA=1) the ADC start and status flag ADCON.3/ADSST retains the set state and the autoscan loop restarts from the beginning. In one-time scan mode (ADCSA=0) conversions stop after the last selected analog input was converted, ADINT is set and ADSST is cleared automatically. ADSST cannot be set (neither externally nor by software) as long as ADINT=1, i.e. as long as ADINT is set, a new conversion start - by setting flag ADSST - is inhibited; actually it is only delayed until ADINT is cleared. (If a `1' is written to ADSST while ADINT=1, this new value is internally latched and preserved, not setting ADSST until ADCON.4/ADINT=0. In this state, a read of SFR ADCON will display ADCON.3/ADSST=0, because always the effective ADC status is read.) Note that under software control the analog inputs can also be converted in arbitrary order, when one-time scan mode is selected and in SFR ADPSS only one bit is set at a time. In this case ADINT is set and ADSST is cleared after every conversion. 6.6.3 Resolution and Characteristics The ADC system has its own analog supply pins AVDD and AVSS. It is referenced by two special reference voltage input pins sourcing the resistance ladder of the DAC: AVref+ and AVref-. The voltage between AVREF+ and AVREF- defines the full-scale range. Due to the 10-bit resolution the full scale range is divided into 1024 unit steps. The unit step voltage is 1 LSB, which is typically 5 mV (AVref+ = 5.12 V, AVref- = 0 V = AVSS). The DAC's resistance ladder has 1023 equally spaced taps, separated by a unit resistance 'R'. The first tap is located 0.5 x R above AVref-, the last tap is located 1.5 x R below AVref+. This results in a total ladder resistance of 1024 x R. This structure ensures that the DAC is monotonic and results in a symmetrical quantization error. For input voltages between AVref- and (AVref- + 1/2 LSB) the 10-bit conversion result code will be 00 0000 0000 B = 000H = 0D. For input voltages between
(AVref+ - 3/2 LSB) and AVref+ the 10-bit conversion result code will be 11 1111 1111 B = 3FFH = 1023D. The result code corresponding to an analog input voltage (AVin) can be calculated from the formula: ResultCode + 1024 AV IN * AV ref* AV ref) * AV ref*
The analog input voltage should be stable when it is sampled for conversion. At any times the input voltage slew rate must be less than 10 V/ms (5 V conversion range) in order to prevent an undefined result. This maximum input voltage slew rate can be ensured by an RC low pass filter with R = 2k2 and C = 100 nF. The capacitor between analog input pin and analog ground pin shall be placed close to the pins in order to have maximum effect in minimizing input noise coupling.
6.7 Timer/Counters
The P8xC557E4 contains three 16-bit timer/event counters: Timer 0, Timer 1 and Timer T2 and one 8-bit timer, T3. Timer 0 and Timer 1 may be programmed to carry out the following functions:
* Measure time intervals and pulse durations * Count events * Generate interrupt requests
6.7.1 Timer 0 and Timer 1 Timers 0 and 1 each have a control bit in SFR TMOD that selects the timer or counter function of the corresponding timer. In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the counter function, the register is incremented in response to a 1-to-0 transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition. There are no restrictions on the duty cycle of the external input signal, but to insure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer 0 and Timer 1 can be programmed independently to operate in one of four modes: 8-bit timer or 8-bit counter each with divide-by-32 prescaler
* Mode 0: * Mode 1:
16-bit time-interval or event counter
* Mode 2:
8-bit time-interval or event counter with automatic reload upon overflow
* Mode 3:
-Timer 0: one 8-bit time-interval or event counter and one 8-bit time-interval counter -Timer 1: stopped
1999 Mar 02
21
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag or generate an interrupt. However the overflow from Timer 1 can be used to pulse the serial port baud-rate generator. With a 16 MHz crystal, the counting frequency of these timer/counters is as follows:
Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. When configured as a counter, the register is incremented on every falling edge on the corresponding input pin, T0 or T1. The incremented register value can be read earliest during the second machine cycle after that one, during which the incrementing pulse occurred. The counters are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all HIGHs to all LOWs (or automatic reload value), with the exception of mode 3 as previously described.
* In the timer function, the timer is incremented at a frequency of
1.33 MHz - a division by 12 of the system clock frequency
* 0 Hz to an upper limit of 0.66 MHz (1/24 of the system clock
frequency) when programmed for external inputs
7 TMOD (89H) GATE
6 C/T
5 M1
4 M0
3 GATE
2 C/T
1 M1
0 M0
Timer 1 Figure 19. Timer/Counter mode control (TMOD) register.
Timer 0
Table 12. Description of TMOD bits
SYMBOL Gate C/T M1 M0 BIT TMOD.7 TMOD.3 TMOD.6 TMOD.2 TMOD.5 TMOD.1 TMOD.4 TMOD.0 FUNCTION Gating control when set. Timer/Counter "x" is enabled only while "INTx" pin is high and "TRx" control pin is set. When cleared Timer "x" is enabled whenever "TRx" control bit is set. Timer or Counter Selector cleared for Timer operation (input from internal system clock). Set for Counter operation (input from "Tx" input pin). Timer 0, Timer 1 mode select see Table 13.
Table 13. Timer 0 / Timer 1 operation select
M1 0 0 1 1 1 M0 0 1 0 1 1 8048 Timer "TLx" serves as 5-bit prescaler. 16-bit Timer/Counter "THx" and "TLx" are cascaded; there is no prescaler. 8-bit auto-reload Timer/Counter "THx" holds a value which is to be reloaded into "TLx" each time it overflows. (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/Counter 1 stopped. OPERATING
1999 Mar 02
22
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 TCON (88H) TF1
6 TR1
5 TF0
4 TR0
3 IE1
2 IT1
1 IE0
0 IT0
Figure 20. Timer/Counter mode control (TCON) register.
Table 14. Description of TCON bits
SYMBOL TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 BIT TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 FUNCTION Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off. Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
1999 Mar 02
23
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.7.2 Timer T2 Timer T2 is a 16 bit timer/counter which has capture and compare facilities. The operational diagram is shown in Figure 21. The 16 bit timer/counter is clocked via a prescaler with a programmable division factor of 1, 2, 4 or 8. The input of the prescaler is clocked with 1/12 of the clock frequency, or by an external source connected to the T2 input, or it is switched off. The maximum repetition rate of the external clock source is fCLK/12, twice that of Timer 0 and Timer 1. The prescaler is incremented on a rising edge. It is cleared if its division factor or its input source is changed, or if the timer/counter is reset (see also Figure 22: TM2CON). T2 is readable 'on the fly', without any extra read latches; this means that software precautions have to be taken against misinterpretation at overflow from least to most significant
CT0I INT CT1I INT
byte while T2 is being read. T2 is not loadable and is reset by the RST signal or at the positive edge of the input signal RT2, if enabled. In the Idle or Power-down Mode the timer/counter and prescaler are reset and halted. T2 is connected to four 16-bit Capture Registers: CT0, CT1, CT2 and CT3. A rising or falling edge on the inputs CT0I, CT1I, CT2I or CT3I (alternative function of Port 1) results in loading the contents of T2 into the respective Capture Registers and an interrupt request. Using the Capture Register CTCON (see Figure 23), these inputs may invoke capture and interrupt request on a positive, a negative edge or on both edges. If neither a positive nor a negative edge is selected for capture input, no capture or interrupt request can be generated by this input.
CT2I
INT
CT3I
INT
CTI0
CTI1
CTI2
CTI3
CT0
CT1
CT2
CT3
off 8-bit overflow interrupt fCLK T2 RT2 1/12 Prescaler T2 Counter 16-bit overflow interrupt
T2ER External reset enable COMP S S S S S S TG TG STE R R R R R R T T RTE P4.0 P4.1 P4.2 P4.3 P4.4 S P4.5 P4.6 P4.7 = set T2 SFR address: TML2 = lower 8 bits TMH2 = higher 8 bits R = reset T = toggle I/O port 4 CMO (S) CM1 (R) CM2 (T) INT COMP INT COMP INT
TG = toggle status
Figure 21. Block diagram of Timer 2.
1999 Mar 02
24
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 TM2CON (EAH) T2IS1
6 T2IS0
5 T2ER
4 T2BO
3 T2P1
2 T2P0
1 T2MS1
0 T2MS0
Figure 22. T2 control register (TM2CON).
Table 15. Description of TM2CON bits
SYMBOL T2IS1 T2IS0 T2ER T2BO T2P1 T2P0 T2MS1 T2MS0 BIT TM2CON.7 TM2CON.6 TM2CON.5 TM2CON.4 TM2CON.3 TM2CON.2 TM2CON.1 TM2CON.0 Timer T2 mode select Timer T2 16-bit overflow interrupt select Timer T2 byte overflow interrupt select Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising edge on RT2 (P1.5). Timer T2 byte overflow interrupt flag Timer T2 prescaler select FUNCTION
Table 16. Timer 2 prescaler select
T2P1 0 0 1 1 T2P0 0 1 0 1 Clock source Clock source/2 Clock source/4 Clock source/8 TIMER T2 CLOCK
Table 17. Timer 2 mode select
T2MS1 0 0 1 1 T2MS0 0 1 0 1 Timer T2 halted (off) T2 clock source = fCLK/12 Test mode; do not use T2 clock source = pin T2 MODE SELECTED
1999 Mar 02
25
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 CTCON (EBH) CTN3
6 CTP3
5 CTN2
4 CTP2
3 CTN1
2 CTP1
1 CTN0
0 CTP0
Figure 23. Capture control register (CTCON).
Table 18. Description of CTCON bits
SYMBOL CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0 BIT CTCON.7 CTCON.6 CTCON.5 CTCON.4 CTCON.3 CTCON.2 CTCON.1 CTCON.0 FUNCTION Capture Register 3 triggered by a falling edge on CT3I Capture Register 3 triggered by a rising edge on CT3I Capture Register 2 triggered by a falling edge on CT2I Capture Register 2 triggered by a rising edge on CT2I Capture Register 1 triggered by a falling edge on CT1I Capture Register 1 triggered by a rising edge on CT1I Capture Register 0 triggered by a falling edge on CT0I Capture Register 0 triggered by a rising edge on CT0I
The contents of the Compare Registers CM0, CM1 and CM2 are continuously compared with the counter value of Timer T2. When a match occurs, an interrupt may be invoked. A match of CM0 sets the bits 0-5 of Port 4, a CM1 match resets these bits and a CM2 match toggles bits 6 and 7 of Port 4, provided these functions are enabled by the STE respectively RTE registers. A match of CM0 and CM1 at the same time results in resetting bits 0-5 of Port 4. CM0, CM1 and CM2 are reset by the RSTIN signal.
7 TM2IR (C8H) T2OV
6 CMI2
5 CMI1
4 CMI0
3 CTI3
2 CTI2
1 CTI1
0 CTI0
Figure 24. Interrupt flag register (TM2IR).
Table 19. Description of TM2IR bits
SYMBOL T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0 BIT TM2IR.7 TM2IR.6 TM2IR.5 TM2IR.4 TM2IR.3 TM2IR.2 TM2IR.1 TM2IR.0 FUNCTION Timer T2 16-bit overflow interrupt flag CM2 interrupt flag CM1 interrupt flag CM0 interrupt flag CT3 interrupt flag CT2 interrupt flag CT1 interrupt flag CT0 interrupt flag
1999 Mar 02
26
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 STE (EEH) TG47
6 TG46
5 SP45
4 SP44
3 SP43
2 SP42
1 SP41
0 SP40
Figure 25. Set enable register (STE).
Table 20. Description of STE bits
SYMBOL TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40 BIT STE.7 STE.6 STE.5 STE.4 STE.3 STE.2 STE.1 STE.0 FUNCTION If "1" then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle If "1" then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle If "1" then P4.5 is set on a match between CM0 and Timer T2 If "1" then P4.4 is set on a match between CM0 and Timer T2 If "1" then P4.3 is set on a match between CM0 and Timer T2 If "1" then P4.2 is set on a match between CM0 and Timer T2 If "1" then P4.1 is set on a match between CM0 and Timer T2 If "1" then P4.0 is set on a match between CM0 and Timer T2
7 RTE (EFH) TP47
6 TP46
5 RP45
4 RP44
3 RP43
2 RP42
1 RP41
0 RP40
Figure 26. Reset/Toggle enable register (RTE).
Table 21. Description of RTE bits
SYMBOL TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40 BIT RTE.7 RTE.6 RTE.5 RTE.4 RTE.3 RTE.2 RTE.1 RTE.0 FUNCTION If "1" then P4.7 toggles on a match between CM2 and Timer T2 If "1" then P4.6 toggles on a match between CM2 and Timer T2 If "1" then P4.5 toggles on a match between CM1 and Timer T2 If "1" then P4.4 toggles on a match between CM1 and Timer T2 If "1" then P4.3 toggles on a match between CM1 and Timer T2 If "1" then P4.2 toggles on a match between CM1 and Timer T2 If "1" then P4.1 toggles on a match between CM1 and Timer T2 If "1" then P4.0 toggles on a match between CM1 and Timer T2
For more information concerning the TM2CON, CTCON, TM2IR and the STE/RTE registers see IC20 handbook, chapter "80C51 family hardware description". Port 4 can be read and written by software without affecting the toggle, set and reset signals. At a byte overflow of the least
significant byte, or at a 16-bit overflow of the timer/counter, an interrupt sharing the same interrupt vector is requested. Either one or both of these overflows can be programmed to request an interrupt. All interrupt flags must be reset by software.
1999 Mar 02
27
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.8 Watchdog Timer T3
In addition to Timer T2 and the standard timers, a watchdog timer (T3) consisting of an 11-bit prescaler and an 8-bit timer is also incorporated (see Figure 27). The timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following: f timer + 12 f CLK 2048
produce a reset upon overflow thus preventing the processor running out of control. The watchdog timer can only be reloaded if the condition flag WLE = PCON.4 has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. The time interval between the timer's reloading and the occurrence of a reset depends on the reloaded value. For example, this may range from 1.5 ms to 0.375 s when using an oscillator frequency of 16 MHz. In the Idle state the watchdog timer and reset circuitry remain active. The watchdog timer is controlled by the watchdog enable pin (EW). A LOW level enables the watchdog timer and disables the Power-down Mode. A HIGH level disables the watchdog timer and enables the Power-down Mode.
When a timer overflow occurs, the microcontroller is reset and a reset output pulse is generated at pin RSTOUT. Also the PLL control register is reset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will
Internal Bus
fCLK/12
Prescaler (11-bit) Clear
Timer T3 (8-bit)
LOAD LOADEN
to reset circuitry (see Figure 46)
Write T3
Clear WLE
PCON.4 EW Internal Bus
PD LOADEN PCON.1
Figure 27. Watchdog timer.
1999 Mar 02
28
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.9 Serial I/O
The P8xC557E4 is equipped with two independent serial ports: SIO0 and SI01. SIO0 is the full duplex UART port, identical to the PCB80C51 serial port. SIO1 is an I2C-bus serial I/O interface with byte oriented master and slave functions. 6.9.1 SIO0 (UART) SIO 0 is a full duplex serial I/O port - it can transmit and receive simultaneously. This serial port is also receive-buffered. It can commence reception of a second byte before the previously received byte has been read from the receive register. If, however, the first byte has still not been read by the time reception of the second byte is complete, one of the bytes will be lost. The SIO0 receive and transmit registers are both accessed via the S0BUF special function register. Writing to S0BUF loads the transmit register, and reading S0BUF accesses to a physically separate receive register. SIO0 can operate in 4 modes: Mode 0: Serial data is transmitted and received through RXD. TXD outputs the shift clock. 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. A write into S0CON should be avoided during a transmission to avoid spikes on RXD/TXD. 10 bits are transmitted via TXD or received through RXD: a start bit (0), 8 data bits (LSB first), and a stop bit(1). On receive, the stop bit is put into RB8 (S0CON special function register). The baud rate is variable.
Mode 2:
11 bits are transmitted through TXD or received through RXD: a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of 0 or 1. With nominal software, TB8 can be the parity bit (P in PSW). During a receive, the 9th data bit is stored in RB8 (S0CON), and the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. 11 bits are transmitted through TXD or received through RXD: a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). Mode 3 is the same as Mode 2 except the baud rate which is variable in Mode 3.
Mode 3:
In all four modes, transmission is initiated by any instruction that writes to the S0BUF function register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. In the other three modes, reception is initiated by the incoming start bit provided that REN = 1. Modes 2 and 3 are provided for multiprocessor communications. In these modes, 9 data bits are received with the 9th bit written to RB8. The 9th bit is followed by the stop bit. The port can be programmed so that with receiving the stop bit, the serial port interrupt will be activated if, and only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. This feature may be used in multiprocessor systems. For more information about how to use the UART in combination with the registers S0CON, PCON, IEN0, S0BUF and Timer register refer to the 80C51 Data Handbook IC20.
Mode 1:
7 S0CON (98H) SM0
6 SM1
5 SM2
4 REN
3 TB8
2 RB8
1 TI
0 RI
Figure 28. Serial port control (S0CON) register.
Table 22. Description of S0CON bits
SYMBOL SM0 SM1 SM2 BIT S0CON.7 S0CON.6 S0CON.5 FUNCTION This bit is used to select the serial port mode. See Table 23. This bit is used to select the serial port mode. See Table 23. Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. The transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. The receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN TB8 RB8 TI RI
S0CON.4 S0CON.3 S0CON.2 S0CON.1 S0CON.0
1999 Mar 02
29
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 23. Description of S0CON bits
SM0 0 0 1 1 SM1 0 1 0 1 MODE 0 1 2 3 Shift register 8-bit UART 9-bit UART 9-bit UART DESCRIPTION fCLK/12 variable fCLK/64 or fCLK/32 variable BAUD RATE
6.9.2 SIO1 (I2C-bus Interface) The SIO1 of the P8xC557E4 provides the fast-mode, which allows a fourthfold increase of the bitrate up to 400 kHz. Nevertheless it is downward compatible, i.e. it can be used in a 0 to 100 Kbit/s I2C bus system. Except from the bit rate selection (see Table 25) and the timing of the SCL and SDA signals (see AC electrical characteristics in section 11) the SIO circuit is the same as described in detail in the 80C51 Data Handbook IC20 for the 8xC552 microcontroller. The I2C-bus is a simple bidirectional 2-wire bus for efficient inter-IC data exchange. Features of the I2C-bus are:
The on-chip I2C logic provides a serial interface that meets the I2C-bus specification, supporting all I2C-bus modes of operation, they are:
* Master transmitter * Master receiver * Slave transmitter * Slave receiver
* Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA) unique address
* Each device connected to the bus is software addressable by a * Masters can operate as Master-transmitter or as Master-receiver * It's a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer
The SI01 logic performs a byte oriented data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. Via two pins the external I2C-bus is interfaced to the SIO1 logic: SCL serial clock I/O and SDA serial data I/O, (see Special Function Register bit S1CON.6/ENS1 for enabling the SIO1 logic). The SIO1 logic handles byte transfer autonomously. It keeps track of the serial transfers, and a status register (S1STA) reflects the status of SIO1 and the I2C-bus. Via the following four Special Function Registers the CPU interfaces to the I2C logic. S1CON S1STA control register. Bit addressable by the CPU status register whose contents may be used as a vector to service routines. data shift register. The data byte is stable as long as S1CON.3/SI=1. slave address register. It's LSB enables/ disables general call address recognition.
* Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus
* ICs can be added to or removed from an
affecting any other circuit on the bus immediately traced
I2C-bus
system without S1DAT S1ADR
* Fault diagnostics and debugging are simple; malfunctions can be
For more information on the I2C-bus specification (including fast-mode) please refer to the Philips publication number 9398 393 40011 and/or the 80C51 Data Handbook IC20.
1999 Mar 02
30
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 SLAVE ADDRESS S1ADR 7 SDA ARBITRATION + SYNC LOGIC SCL 7 S1DAT SHIFT REGISTER
1
0 GC
0
BUS CLOCK GENERATOR 0
S1CON 7
0
S1STA Figure 29. Block diagram of I2C serial I/O interface.
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31
INTERNAL BUS
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
The Control Register, S1CON: The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENS1 = 0.
7 S1CON (D8H) CR2
6 ENS1
5 STA
4 STO
3 SI
2 AA
1 CR1
0 CR0
Figure 30. Serial control (S1CON) register.
Table 24. Description of S1CON bits
SYMBOL CR2 ENS1 STA BIT S1CON.7 S1CON.6 S1CON.5 Clock rate bit 2, see Table 25. ENS1 = 0: ENS1 = 1: Serial I/O Serial I/O disabled and reset. SDA and SCL outputs are high-Z. enabled. FUNCTION
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set, and an interrupt request is generated, after any of the following events occur: - A START condition is generated in master mode. - The own slave address has been received during AA = 1. - The general call address has been received while S1ADR.0 and AA = 1. - A data byte has been received or transmitted in master mode (even if arbitration is lost). - A data byte has been received or transmitted as selected slave. - A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions: - Own slave address is received. - General call address is received (S1ADR.0 = 1). - A data byte is received, while the device is programmed to be a master receiver. - A data byte is received. while the device is a selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. Clock rate bits 1 and 0, see Table 25.
STO
S1CON.4
SI
S1CON.3
AA
S1CON.2
CR1 CR0
S1CON.1 S1CON.0
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32
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
When SIO1 is in a master mode serial clock frequency is determined by the clock rate bits CR2, CR1 and CR0. The various bit rates are shown in Table 25.
Table 25.
Selection of I2C-bus bit rate
BIT RATE (kHz) at fCLK CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 12MHz 50 3.75 75 100 200 1 7.5 300 1 400 1 16MHz 66.7 5 100 - 266.7 1 10 400 1 -
CR2 1 1 1 1 0 0 0 0
NOTE: 1. These bit rates are for "fast-mode" I2C bus applications and cannot be used for bit rates up to 100 kbit/sec. The data shown in Table 25 do not apply to SIO1 in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 400kHz. Serial status register S1STA S1STA is a read only register. The contents of the status register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus.
7 S1STA (D9H) SC4
6 SC3
5 SC2
4 SC1
3 SC0
2 0
1 0
0 0
Figure 31. Serial status (S1STA) register.
Table 26. Description of S1STA bits
BIT S1STA.7 to 3 S1STA.2 to 0 5-bit status code These bits are held LOW (for service routine vector increment 8) FUNCTION
The following is a list of the status codes:
Table 27. MST/TRX mode
S1STA VALUE 08H 10H 18H 20H 28H 30H 38H A START condition has been transmitted A repeated START condition has been transmitted SLA and W have been transmitted, ACK has been received SLA and W have been transmitted, ACK received DATA and S1DAT has been transmitted, ACK received DATA and S1DAT has been transmitted, ACK received Arbitration lost in SLA, R/W or DATA DESCRIPTION
1999 Mar 02
33
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 28. MST/REC mode
S1STA VALUE 38H 40H 48H 50H 58H Arbitration lost while returning ACK SLA and R have been transmitted, ACK received SLA and R have been transmitted, ACK received DATA has been received, ACK returned DATA has been received, ACK returned DESCRIPTION
Table 29. SLV/REC mode
S1STA VALUE 60H 68H 70H 78H 80H 88H 90H 98H A0H DESCRIPTION Own SLA and W have been received, ACK returned Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned General CALL has been received, ACK returned Arbitration lost in SLA, R/W as MST. General call has been received Previously addressed with own SLA. DATA byte received, ACK returned Previously addressed with own SLA. DATA byte received, ACK returned Previously addressed with general call. DATA byte has been received, ACK has been returned Previously addressed with general call. DATA byte has been received, ACK has been returned A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX
Table 30. SLV/TRX mode
S1STA VALUE A8H B0H B8H C0H C8H DESCRIPTION Own SLA and R have been received, ACK returned Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned DATA byte has been transmitted, ACK returned DATA byte has been transmitted, ACK returned Last DATA byte has been transmitted (AA = logic 0), ACK received
Table 31. Miscellaneous
S1STA VALUE 00H F8H DESCRIPTION Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition No relevant information available, SI not set
Abbreviations used: SLA : 7-bit slave address R : Read bit W : Write bit ACK : Acknowledgement (acknowledge bit = 0) ACK : Not acknowledgement (acknowledge bit = 1) DATA : 8-bit data byte to or from I2C-bus MST : Master SLV : Slave TRX : Transmitter REC : Receiver
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34
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
The data shift register S1DAT This register contains the serial data to be transmitted or data which has been received. Bit 7 is transmitted or received first; i.e., data is shifted from right to left.
7 S1DAT (DAH) S1DAT.7
6 S1DAT.6
5 S1DAT.5
4 S1DAT.4
3 S1DAT.3
2 S1DAT.2
1 S1DAT.1
0 S1DAT.0
Figure 32. Data shift register.
The address register S1ADR This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. The LSB (GC) is used to determine whether the general call address is recognized.
7 S1ADR (DBH) SLA6
6 SLA5
5 SLA4
4 SLA3
3 SLA2
2 SLA1
1 SLA0
0 GC
Figure 33. Address register.
Table 32. Description of S1ADR bits
SYMBOL SLA6 to 0 GC BIT S1ADR.7 to 1 S1ADR.0 Own slave address 0 = general call address is not recognized 1 = general call address is recognized FUNCTION
1999 Mar 02
35
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.10 Interrupt System
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronously to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response time in a single-interrupt system is in the range from 2.25s to 6.75s when using a 16MHz crystal. The latency time depends on the sequence of instructions executed directly after an interrupt request. The P8xC557E4 acknowledges interrupt requests from 15 sources as follows (see Figure 34):
The ADC Interrupt is generated by bit ADINT, which is set when of all selected analog inputs to be scanned, the conversion is finished. ADINT must be cleared by software. It cannot be set by software. The 'Seconds' timer Interrupt is generated by bit SECINT in register PLLCON. This flag has to be cleared by software. Note that the 'Seconds' timer can only be used with the 32 kHz PLL oscillator. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware (except the ADC interrupt request flag ADINT, which cannot be set by software). That is, interrupts can be generated or pending interrupts can be cancelled in software. The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are capable to terminate the Idle Mode.
* INT0 and INT1 external interrupts * Timer 0 and Timer 1 internal timer/counter interrupts * Timer 2 internal timer/counter byte and/or 16-bit overflow, 3
compare and 4 capture interrupts (or 4 additional external interrupts) 1
Interrupt Enable Registers
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function registers IEN0 and IEN1. All interrupt sources can also be globally disabled by clearing bit EA in IEN0. The interrupt enable registers are described in Figures 34 and 36.
* UART serial I/O port receive/transmit interrupt * I2C-bus interface serial I/O interrupt * ADC autoscan completion interrupt * `Seconds' timer interrupt SEC (ored with INT1).
For details about seconds timer interrupts, please refer to chapter 6.13.4. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level-activated then the interrupt request flag remains set until the external interrupt pin INTx goes high. Consequently the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. As these external interrupts are active LOW a "wire-ORing" of several interrupt sources to one input pin allows expansion. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. The eight Timer/Counter T2 Interrupt sources are: 4 capture Interrupts (1), 3 compare interrupts and an overflow interrupt. The appropriate interrupt request flags must be cleared by software. The UART Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware. The service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared by software. The I2C Interrupt is generated by bit SI in register S1CON. This flag has to be cleared by software.
Interrupt Priority Structure
Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function registers IP0 and IP1. IP0 and IP1 are described in Figures 37 and 38. Interrupt priority levels are as follows: "0"--low priority "1"--high priority A low priority interrupt may be interrupted by a high priority interrupt. A high priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. This second priority structure is shown in Table 37.
Interrupt Handling
The interrupt sources are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware- generated LCALL is not blocked by any of the following conditions: 1. An interrupt of higher or equal priority level is already in progress. 2. The current machine cycle is not the final cycle in the execution of the instruction in progress. (No interrupt request will be serviced until the instruction in progress is completed.) 3. The instruction in progress is RETI or any access to the interrupt priority or interrupt enable registers. (No interrupt will be serviced after RETI or after a read or write to IP0, IP1, IE0, or IE1 until at least one other instruction has been subsequently executed.)
NOTE: 1. If a capture register is unused and it's contents is of no interest, then the corresponding input pin CTnI/P1.n (n: 0...3) may be used as a (configurable) positive and/or negative edge triggered additional external interrupt input (INT2, INT3, INT4, INT5). 1999 Mar 02 36
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
The polling cycle is repeated with every machine cycle, and the values polled are the values present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but is not being responded to because of one of the above conditions, and if the flag is inactive when the blocking condition is removed, then the blocked interrupt will not be serviced. Thus, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate service routine. In some cases it also clears the flag which generated the interrupt, and in others it does not. It clears the Timer 0, Timer 1, and external
interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if it was transition-activated. All other interrupt flags are not cleared by hardware and must be cleared by the software. The LCALL pushes the contents of the program counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 38. Execution proceeds from the vector address until the RETI instruction is encountered. The RETI instruction clears the "priority level active" flip-flop that was set when this interrupt was acknowledged. It then pops the top two bytes from the stack and reloads the program counter. Execution of the interrupted program continues from where it was interrupted.
7 IEN0 (A8H) EA
6 EAD
5 ES1
4 ES0
3 ET1
2 EX1
1 ET0
0 EX0
Figure 34. Interrupt enable register (IEN0).
Table 33. Description of IEN0 bits
SYMBOL EA BIT IEN0.7 FUNCTION Global enable/disable control 0= No interrupt is enabled 1= Any individually enabled interrupt will be accepted Enable ADC interrupt Enable SIO1 (I2C) interrupt Enable SIO0 (UART) interrupt Enable Timer 1 interrupt Enable External interrupt 1 / Seconds interrupt Enable Timer 0 interrupt Enable External interrupt 0
EAD ES1 ES0 ET1 EX1 ET0 EX0
IEN0.6 IEN0.5 IEN0.4 IEN0.3 IEN0.2 IEN0.1 IEN0.0
1999 Mar 02
37
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Interrupt enable registers Interrupt sources INT0 External Interrupt Request 0 I2C Serial Port Source enable Global enable Interrupt priority registers a1 a2 b1 b2 c1 ADC c2 Timer 0 Overflow d1 d2 CT0I Timer 2 Capture 0 e1 e2 Timer 2 Compare 0 External Interrupt Request 1 'seconds' Interrupt Timer 2 Capture 1 f1 f2 n1 g1 g2 h1 h2 a2 i1 Timer 2 Compare 1 b2 i2 j1 j2 CT2I k1 g2 k2 h2 Timer 2 Compare 2 l1 i2 l2 UART Serial Port CT3I T R m1 m2 n1 n2 Timer T2 Overflow o1 o2 j2 k2 l2 m2 n2 o2 Source Identification Vector Low priority interrupt request c2 d2 e2 f2 Timer 2 Capture 2 o1 Source Identification Vector a1 b1 c1 d1 e1 f1 g1 h1 i1 j1 k1 l1 m1 Polling hardware
High priority interrupt request
INT1
CT1I
Timer 1 Overflow
Timer 2 Capture 3
Figure 35. The interrupt system.
1999 Mar 02
38
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 IEN1 (E8H) ET2
6 ECM2
5 ECM1
4 ECM0
3 ECT3
2 ECT2
1 ECT1
0 ECT0
Figure 36. Interrupt enable register (IEN1).
Table 34. Description of IEN1 bits
SYMBOL ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0 BIT IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0 Enable T2 overflow interrupt(s) Enable T2 comparator 2 interrupt Enable T2 comparator 1 interrupt Enable T2 comparator 0 interrupt Enable T2 capture register 3 interrupt Enable T2 capture register 2 interrupt Enable T2 capture register 1 interrupt Enable T2 capture register 0 interrupt FUNCTION
If the enable bit is 0, then the interrupt is disabled, if the enable bit is 1, then the interrupt is enabled.
7 IP0 (B8H) -
6 PAD
5 PS1
4 PS0
3 PT1
2 PX1
1 PT0
0 PX0
Figure 37. Interrupt priority register (IP0).
Table 35. Description of IP0 bits
SYMBOL - PAD PS1 PS0 PT1 PX1 PT0 PX0 BIT IP0.7 IP0.6 IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 Reserved for future use ADC interrupt priority level SIO1 (I2C) interrupt priority level SIO0 (UART) interrupt priority level Timer 1 interrupt priority level External interrupt 1/Seconds interrupt priority level Timer 0 interrupt priority level External interrupt 0 priority level FUNCTION
1999 Mar 02
39
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 IP1 (F8H) PT2
6 PCM2
5 PCM1
4 PCM0
3 PCT3
2 PCT2
1 PCT1
0 PCT0
Figure 38. Interrupt priority register (IP1).
Table 36. Description of IP1 bits
SYMBOL PT2 PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 BIT IP1.7 IP1.6 IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 T2 overflow interrupt(s) priority level T2 comparator 2 interrupt priority level T2 comparator 1 interrupt priority level T2 comparator 0 interrupt priority level T2 capture register 3 interrupt priority level T2 capture register 2 interrupt priority level T2 capture register 1 interrupt priority level T2 capture register 0 interrupt priority level FUNCTION
Table 37. Interrupt Priority Structure
SOURCE External interrupt 0 SIO1 (I2C) ADC completion Timer 0 overflow Timer 2 capture 0 Timer 2 compare 0 External interrupt 1/Seconds interrupt Timer 2 capture 1 Timer 2 compare 1 Timer 1 overflow Timer 2 capture 2 Timer 2 compare 2 SIO0 (UART) Timer 2 capture 3 Timer 2 overflow NAME X0 S1 ADC T0 CT0 CM0 X1/SEC CT1 CM1 T1 CT2 CM2 S0 CT3 T2 PRIORITY WITHIN LEVEL (highest)
(lowest)
Table 38. Interrupt Vector Addresses
SOURCE External interrupt 0 Timer 0 overflow External interrupt 1/Seconds interrupt Timer 1 overflow SIO0 (UART) SIO1 (I2C) Timer 2 capture 0 Timer 2 capture 1 Timer 2 capture 2 Timer 2 capture 3 ADC completion Timer 2 compare 0 Timer 2 compare 1 Timer 2 compare 2 Timer 2 overflow 1999 Mar 02 40 NAME X0 T0 X1/SEC T1 S0 S1 CT0 CT1 CT2 CT3 ADC CM0 CM1 CM2 T2 VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 PCON (87H) SMOD
6 ARD
5 RFI
4 WLE
3 GF1
2 GF0
1 PD
0 IDL
Figure 39. Power control register (PCON).
Table 39. Description of PCON bits
SYMBOL SMOD ARD RFI WLE GF1 GF0 PD IDL BIT PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 FUNCTION Double Baud rate bit. When set to logic 1 the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2, or 3. AUX-RAM disable bit. When set to a 1 the internal 768 bytes AUX-RAM is disabled, so that all MOVX-Instructions access the external data memory - as it is with the standard PCB80C51. Reduced radio frequency interference bit. When set to a 1 the toggling of ALE pin is prohibited. This bit is cleared on RESET (see also sections Features (EMC) and Pinning). Watchdog load enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is cleared when timer T3 is loaded. General-purpose flag bit General-purpose flag bit Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high. Idle Mode bit. Setting this bit activates the Idle Mode.
6.11 Power Reduction Modes
Two software-selectable modes of reduced power consumption are implemented. These are the Idle Mode and the Power-down Mode. Idle Mode operation permits the interrupt, serial ports and timer blocks T0, T1 and T3 to function while the CPU is halted. The following functions are switched off when the microcontroller enters the Idle Mode:
The following functions remain active during Idle Mode. These functions may generate an interrupt or reset and thus terminate the Idle Mode:
* CPU * Timer 2 * PWM0, PWM1 * ADC
(halted) (stopped and reset) (reset, output = HIGH) (aborted if conversion in progress)
* Timer 0, Timer 1, Timer 3 (Watchdog timer) * UART * I2C * External interrupt * Seconds Timer
In Power-down Mode the system clock is halted. If the PLL oscillator is selected (SELXTAL1 = 0) and the RUN32 bit is set, the 32 kHz oscillator keeps running, otherwise it is stopped. If the HF-oscillator (SELXTAL1 = 1) is selected, it is stopped after setting the bit PD in the PCON register.
Table 40. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down MEMORY Internal External Internal ALE 1 1 0 PSEN 1 1 0 PORT 0 data high-Z data PORT 1 data data data PORT 2 data address data PORT 3 data data data PORT 4 data data data SCL/SDA operative (1) operative (1) high-Z PWM0/PWM1 HIGH HIGH HIGH
Power-down External 0 0 high-Z data data data data high-Z HIGH NOTE: 1. In Idle Mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0) these pins are in a high-impedance state.
1999 Mar 02
41
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
XTAL4
32 kHz
SELXTAL1 XTAL3
PLL Osc fCLK Clock Gen. Interrupts, Serial Ports, T0, T1, T3 CPU T2 ADC PWM XTAL2 PD IDL
Seconds timer
Osc
XTAL1
3.5 to 16 MHz
Figure 40. Idle and Power Down Hardware for Clock Generation
Internal timing stopped Power-down Mode XTAL1,2 oscillator stopped 32 kHz oscillator stopped running INT0 INT1 oscillator start_up > 10 ms > 560 ms > 10 ms
C1
C1 Idle Mode
C1 LCALL
C2
interrupts are polled INT0 : 2 cycles INT1 : 1 cycle
Interrupt routine
set External Interrupt latch Figure 41. Wake-up by interrupt 6.11.1 Power Control Register The modes Idle and Power-down are activated by software via the Special Function Register PCON. Its hardware address is 87H. PCON is not bit addressable. The reset value of PCON is (00000000). 6.11.2 Idle Mode The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle Mode is activated. Once in the Idle Mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during Idle Mode. The status of external pins during Idle Mode is shown in Table 40. There are three ways to terminate the Idle Mode: Activation of any enabled interrupt X0, T0, X1, SEC, T1, S0 or S1 will cause PCON.0 to be cleared by hardware terminating Idle Mode but only, if there is no interrupt in service with the same or higher priority. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during Idle Mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle Mode is terminated by an interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle Mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 HF oscillator periods) to complete the reset operation if the HF oscillator is selected. When the PLL oscillator is selected a hardware reset of > 1 sec (but no longer than 10 ms) is required and the microcontroller will typically restart within 63 msec after the reset has finished. The third way of terminating the Idle Mode is by internal watchdog reset. The microcontroller restarts after 3 machine cycles in all cases.
1999 Mar 02
42
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.11.3 Power-down Mode The instruction that sets PCON.1 is the last executed prior to going into the Power-down Mode. Once in Power-down Mode, the HF oscillator is stopped. The 32 kHz oscillator may stay running. The content of the on-chip RAM and the Special Function Registers are preserved. Note that the Power-down Mode can not be entered when the watchdog has been enabled. The Power-down Mode can be terminated by an external RESET in the same way as in the 80C51 (RAM is saved, but SFRs are cleared due to RESET) or in addition by any one of the external interrupts (INT0, INT1) or Seconds interrupt. The status of the external pins during Power-down Mode is shown in Table 40. If the Power-down Mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a logic1, the port pin is held HIGH during the Power-down Mode by the strong pull-up transistor P1 (see Figure 9). The Power-down Mode should not be entered within an interrupt routine because Wake-up with an external or `Seconds' interrupt is not possible in that case. 6.11.4 Wake-up from Power-down Mode The Power-down Mode of the P8xC557E4 can also be terminated by any one of the three enabled interrupts, INT0, INT1 or Seconds interrupt. If there is an interrupt already in service, which has same or higher priority as the Wake-up interrupt, Power-down Mode will switch over to Idle Mode and stay there until an interrupt of higher priority terminates Idle Mode. A termination with these interrupts does not affect the internal data memory and does not affect the Special Function Registers. This
gives the possibility to exit Power-down without changing the port output levels. To terminate the Power-down Mode with an external interrupt, INT0 or INT1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT0 or INT1 must be kept LOW till the oscillator has restarted and stabilized (see Figure 41). A Seconds interrupt will terminate the Power-down Mode if it is enabled and INT1 is level sensitive. In order to prevent any interrupt priority problems during Wake-up, the priority of the desired Wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. The instruction following the one that put the device into the Power-down Mode will be the first one which will be executed after the interrupt routine has been serviced.
6.12 Oscillator Circuits
The input signal SELXTAL1 connected to logic "1" selects the XTAL1, 2 oscillator (standard 80C51) instead of the XTAL3, 4 oscillator, which is halted and XTAL3, 4 must not be connected. 6.12.1 XTAL1, 2 Oscillator circuit (standard 80C51) The oscillator circuit of the P8xC557E4 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between the XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output (see Figure 42). To drive the P8xC557E4 externally, XTAL1 is driven from an external source and XTAL2 left open-circuit (see Figure 43). 6.12.2 XTAL3, 4 Circuitry Please refer to chapter 6.13.1
1
SELXTAL1 External clock signal
1
SELXTAL1
XTAL1
XTAL1 Quartz crystal or ceramic resonator C1
C2 XTAL2
(NC)
XTAL2
VSS C1 = C2 = 20pF VSS
Figure 42. Using the On-Chip Oscillator.
Figure 43. Using an external clock.
1999 Mar 02
43
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.13 32kHz PLL Oscillator with Seconds Timer
6.13.1 XTAL3,4 Oscillator Circuitry The input signal SELXTAL1 connected to logic "0" selects the 32kHz oscillator together with the PLL instead of the XTAL1,2 oscillator, which is halted. XTAL2 is floating in that case. The 32kHz oscillator consists of an inverter, which forms a Pierce oscillator with the on-chip components C1,C2,Rf and an external crystal of 32768 Hz. During the following situations, the inverter is switched to tristate and XTAL3 is pulled to Vss :
The system clock frequency fCLK is derived from fCCO under control of the PLLCON bits FSEL(4:0) (see Table 41). If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about 1us until the new frequency is available. Changing the system clock frequency has to be done in two steps. From HIGH to LOW frequencies: First change (FSEL(4:2), then FSEL (1:0). From LOW to HIGH frequencies: First change only FSEL (1:0) and after a stabilization phase of 10 ms change FSEL (4:2). 6.13.3 PLL Control Register - PLLCON PLLCON is a special function register, which can be read and written by software. It contains the control bits:
* during Power-down Mode, when the PLL control register bit
RUN32 (PLLCON.7) was set to '0';
* during Reset (RSTIN = HIGH) ; * when the XTAL1,2 oscillator is selected (SELXTAL1 = HIGH).
6.13.2 PLL CCO A current controlled oscillator (CCO) generates a clock frequency fCCO of approx. 32 , 38 , 44 or 50 MHz , controlled by the PLL, with the 32kHz oscillator as the reference clock. The system clock frequency fCLK can be varied under software control by changing the contents of the PLL control register (PLLCON): fCCO can be changed via the PLLCON bits FSEL(1:0) (see Table 41). The maximum locking time is 10 ms1. During the stabilization phase, no time critical routines should be executed.
* to select one of several system clock frequencies (see Table 41); * the seconds interrupt flag: SECINT * to enable the seconds interrupt flag: ENSECI * the RUN32 bit, which defines if during Power-down Mode the
32kHz oscillator is halted or stays running. PLLCON is initialized to 0DH upon Reset (RSTIN = `1') or Watchdog Timer Overflow. PLLCON = 0DH corresponds to a system clock frequency of 11.01 MHz.
7 PLLCON (F9H) RUN32
6 ENSECI
5 SECINT
4 FSEL.4
3 FSEL.3
2 FSEL.2
1 FSEL.1
0 FSEL.0
Figure 44. PLL control register (PLLCON).
Table 41. PLLCON
SYMBOL RUN32 ENSECI SECINT FSEL.4 to FSEL.0 BIT PLLCON.7 PLLCON.6 PLLCON.5 PLLCON.4 to PLLCON.0 FUNCTION RUN32 = 0: The 32 kHz oscillator halts during Power-down. RUN32 = 1: The 32 kHz oscillator stays running during Power-down. Enable the seconds interrupt. (enabling INT1 is also required) Seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing a `1' to this bit. SECINT can only be cleared by writing a '0' to this bit . System clock frequency in MHz FSEL[4:2] 100 11 10 01 00 3.93 4.72 5.51 6.29 011 7.86 9.44 11.01 12.58 010 15.73
FSEL[1:0]
Other combinations, than mentioned above, are reserved and may not be selected. This allows to generate the standard baudrates 19200, 9600, 4800, 2400 and 1200 Baud, when using the UART and Timer1. NOTE: 1. This parameter is characterized. 1999 Mar 02 44
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.13.4 Seconds Timer This counter provides an overflow signal every second, when the 32kHz oscillator is running. The overflow output sets the interrupt flag SECINT. This interrupt can be disabled/enabled by ENSECI. If SECINT is enabled, it is logically ORed with INT1 (external interrupt 1). Seconds interrupt and INT1 therefor share the same priority and vector. The software has to check both flags SECINT (PLLCON.5) and IE1 (TCON.3), to distinguish between the two interrupt sources. SECINT can only be cleared via writing a `0' to this bit . The external interrupts INT0 , INT1 or the seconds interrupt can Wake-up the PLL oscillator and the microcontroller as described in chapter "Wake-up from Power-down Mode". For a Wake-up via INT1 or seconds interrupt, IE1 must be enabled and level-sensitive. A further function of the seconds timer is to control the start-up timing of the microcontroller after Reset or after Wake-up from
Power-down. It controls the stretching of the reset pulse to the microcontroller and controls releasing the system clock to the microcontroller. A RSTIN signal of 1us at minimum will reset the microcontroller. In case of Reset or Wake-up with halted 32kHz oscillator: From RSTIN falling edge or Wake-up interrupt it takes 560ms at maximum for the start-up of the 32kHz oscillator itself and the stabilization of the PLL's. In case of Wake-up with running 32kHz oscillator: From Wake-up interrupt it takes about 1ms for the stabilization of the PLL's. After this start-up time, the microcontroller is supplied with the system clock and - in case of a reset - the internally stretched reset signal overlaps about 45us, to guarantee a proper initialization of the microcontroller. For further information refer to section 6.11 Power reduction modes.
32.768 KHz
XTAL4
C1
C2
XTAL3 PD
Rf
32 kHz Oscillator Programmable divider Stretched Reset RUN32 PD SECONDS TIMER system clock Phase comparator Loop filter CCO
Reset to controller PLLCON 'Seconds' Interrupt request
RSTIN Internal Bus PD = power down
Figure 45. Block diagram PLL
1999 Mar 02
45
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
6.14 Reset Circuitry
The reset input pin RSTIN is connected to a Schmitt trigger for noise reduction (see Figure 46). Is the HF-oscillator selected a Reset is accomplished by holding the RSTIN pin HIGH for at least 2 machine cycles (24 system clock periods). Is the PLL-oscillator selected the RSTIN-pulse must have a width of 1 s at least, independent of the 32 kHz-oscillator is running or not (see PLL description). The CPU responds by executing an internal reset. The RSTOUT pin represents the signal resetting the CPU and can be used to reset peripheral devices. The RSTOUT level also could be high due to a Watchdog timer overflow. The length of the output pulse from T3 is 3 machine cycles. A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. During Reset, ALE and PSEN output a HIGH level. In order to perform a correct reset, this level must not be affected by external elements. A Reset leaves the internal registers as shown in Table 5. The internal RAM is not affected by Reset. At power-on, the RAM content is indeterminate.
6.15 Power-on Reset
An automatic Reset can be obtained by switching on VDD, if the RSTIN pin is connected to VDD via a capacitor, as shown in Figure 47. Is the HF oscillator selected the VDD rise time must not exceed 10 ms and the capacitor should be at least 2.2 F. The decrease of the RSTIN pin voltage depends on the capacitor and the internal resistor RRST. That voltage must remain above the lower threshold for at minimum the HF-oscillator start-up time plus 2 machine cycles. Is the PLL-oscillator selected a 0.1 F capacitor is sufficient to obtain an automatic reset.
VDD
Schmitt Trigger
PLL OSC Internal Reset MUX RSTOUT
VDD
Capacitor for HF-Osc.: PLL-Osc.:
RSTIN
F 0.1 F
2.2
8xC557E4
On-chip resistor
RRST
RST RRST
SELXTAL1
Overflow timer T3
Figure 46. On-chip Reset Configuration
Figure 47. Power-on Reset
1999 Mar 02
46
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7. INSTRUCTION SET
The P8xC557E4 uses the powerful instruction set of the PCB80C51. It consists of 49 single-byte, 45 two-byte and 17 three-byte instructions. Using a 16 MHz quartz, 64 of the instructions are executed in 0.75 s, 45 in 1,5 s and the multiply, divide instructions in 3 s. A summary of the instruction set is given in Table 43. The P8xC557E4 has additional Special Function Registers to control the on-chip peripherals.
7.1.1 80C51 Family Instruction Set
Table 42. Instruction that affect Flag settings1
INSTRUCTION C ADD ADDC SUBB MUL DIV DA RRC RLC SETB C CLR C CPL C ANL C, bit ANL C,/bit ANL C, bit ORL C, bit MOV C, bit CJNE X X X 0 0 X X X 1 0 X X X X X X X FLAG OV X X X X X X AC X X X
7.1 Addressing Modes
Most instructions have a "destination, source" field that specifies the data type, addressing modes and operands involved. For all these instructions, except for MOVs, the destination operand is also the source operand (e.g., ADD A,R7). There are five kinds of addressing modes:
* Register Addressing * Direct Addressing
- R0 - R7 (4 banks) - A,B,C (bit), AB (2 bytes), DPTR (double byte)
- lower 128 bytes of internal Main RAM (including the 4 R0-R7 register banks) - Special Function Registers - 128 bits in a subset of the internal Main RAM - 128 bits in a subset of the Special Function Registers
NOTES: 1. Note that operations on SFR byte address 208 or bit addresses 209-215 (i.e., the PSW or bits in the PSW) will also affect flag settings.
*
Notes on instruction set and addressing modes:
Rn direct Register R7-R0 of the currently selected Register Bank. 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)]. 8-bit RAM location addressed indirectly through register R1 or R0 of the actual register bank. 8-bit constant included in the instruction. 16-bit constant included in the instruction 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64 Kbytes Program Memory address space. 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 Kbytes page of program memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Direct Addressed bit in Internal Data RAM or Special Function Register.
Register-Indirect Addressing - internal Main RAM (@R0, @R1, @SP [PUSH/POP]) - internal Auxiliary RAM (@R0, @R1, @DPTR) - external Data Memory (@R0, @R1, @DPTR)
* *
Immediate Addressing - Program Memory (in-code 8 bit or 16 bit constant) Base-Register-plus Index-Register-Indirect Addressing - Program Memory look-up table (@DPTR+A, @PC+A) #data #data 16 addr 16 @Ri
The first three addressing modes are usable for destination operands.
addr 11
rel
bit
Hexadecimal opcode cross-reference to Table 43: * ** *** : : : 8, 9, A, B, C, D, E. F. 11, 31, 51, 71, 91, B1, D1, F1. 01, 21, 41, 61, 81, A1, C1, E1.
1999 Mar 02
47
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 43. 80C51 Instruction Set Summary
MNEMONIC ARITHMETIC OPERATIONS ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with carry Add direct byte to Accumulator with carry Add indirect RAM to Accumulator with carry Add immediate data to ACC with carry Subtract Register from ACC with borrow Subtract direct byte from ACC with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from ACC with borrow Increment Accumulator Increment register Increment direct byte Increment indirect RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal Adjust Accumulator 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTE / CYCLES OPCODE (HEX.)
LOGICAL OPERATIONS ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67
1999 Mar 02
48
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 43.
80C51 Instruction Set Summary (Continued)
MNEMONIC DESCRIPTION BYTE / CYCLES OPCODE (HEX.)
LOGICAL OPERATIONS (Continued) XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,#data direct,A direct,#data A A A A A A A Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator left Rotate Accumulator left through the carry Rotate Accumulator right Rotate Accumulator right through the carry Swap nibbles within the Accumulator 2 2 3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 64 62 63 E4 F4 23 33 03 13 C4
DATA TRANSFER MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD A,Rn A,direct A,@Ri A,#data Rn,A Rn,direct RN,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data DPTR,#data16 A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rn A,direct A,@Ri A,@Ri Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to ACC Move Code byte relative to PC to ACC Move AUX-RAM (8-bit addr) to ACC Move AUX-RAM (16-bit addr) to ACC Move ACC to AUX-RAM (8-bit addr) Move ACC to AUX-RAM (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order digit indirect RAM with ACC 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
1999 Mar 02
49
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 43.
80C51 Instruction Set Summary (Continued)
MNEMONIC DESCRIPTION BYTE / CYCLES OPCODE (HEX.)
BOOLEAN VARIABLE MANIPULATION CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV JC JNC JB JNB JBC C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C rel rel rel rel bit,rel Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND complement of direct bit to carry OR direct bit to carry OR complement of direct bit to carry Move direct bit to carry Move carry to direct bit Jump if carry is set Jump if carry not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit 1 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 3 1 1 1 1 1 1 2 2 2 2 1 2 2 2 2 2 2 C3 C2 D3 D2 B3 B2 B2 B0 72 A0 A2 92 40 50 20 30 10
PROGRAM BRANCHING ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE CJNE CJNE CJNE DJNZ DJNZ NOP NOTE: 1. All mnemonics copyrighted addr11 addr16 rel @A+DPTR rel rel A,direct,rel A,#data,rel RN,#data,rel @Ri,#data,rel Rn,rel direct,rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Compare direct byte to ACC and jump if not equal Compare immediate to ACC and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 **1addr 12 22 32 ***1addr 02 80 73 60 70 B5 B4 B* B6, B7 D* D5 00
(c) Intel Corporation 1980
1999 Mar 02
50
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Table 44. Instruction map P8xC557E4
second hexadecimal character of opcode
0 0 NOP 1 AJMP addr11 1 JBC bit, rel 2 JB bit, rel 3 JNB bit, rel 4 JC rel ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL ORL dir, A ANL dir, A XRL dir, A ORL C, bit ANL C, bit MOV bit, C MOV C, bit CPL bit CLR bit SETB bit RETI 2 LJMP addr16 LCALL addr16 RET 3 RR A RRC A RL A RLC A ORL dir, #data ANL dir, #data XRL dir, #data JMP @A+DPTR MOVC A, @A+PC MOVC A,@A+DPTR INC DPTR CPL C CLR C SETB C 4 INC A DEC A ADD A, #data ADDC A, #data ORL A, #data ANL A, #data XRL A, #data MOV A, #data DIV AB SUBB A, #data MUL AB CJNE A,#data,rel SWAP A DA A CLR A CPL A CJNE A,dir, rel XCH A, dir DNJZ dir, rel MOV A, dir *) MOV dir, A 0 0 MOV @ Ri, A 1 0 1 2 0 MOV A, @ Ri 1 0 1 2 0 XCHD A, @ Ri 1 0 1 0 5 INC dir DEC dir ADD A, dir ADDC A, dir ORL A, dir ANL A, dir XRL A, dir MOV dir,#data 0 MOV dir, dir SUBB A, dir 0 MOV @ Ri, dir 1 0 1 0 SUBB A, @ Ri 1 0 1 MOV dir, @ Ri 1 0 1 0 0 XRL A, @ Ri 1 MOV @ Ri, #data 1 0 1 0 1 2 0 ANL A, @ Ri 1 0 1 2 0 ORL A, @ Ri 1 0 1 2 0 ADDC A, @ Ri 1 0 1 0 ADD A, @ Ri 1 0 1 0 DEC @ Ri 1 0 1 2 6 INC @ Ri 1 0 1 2 7 8 9 A B C D E F
INC Rr 3 4 5 6 7
DEC Rr 3 4 5 6 7
ADD A, Rr 2 3 4 5 6 7
ADDC A, Rr 2 3 4 5 6 7
ORL A, Rr 3 4 5 6 7
first hexadecimal character of opcode
5
JNC rel
ANL A, Rr 3 4 5 6 7
6
JZ rel
XRL A, Rr 3 4 5 6 7
7
JNZ rel
MOV Rr, #data 2 3 4 5 6 7
8
SJMP rel
MOV dir, Rr 2 3 4 5 6 7
9
MOV
SUBB A, Rr 2 3 4 5 6 7
DPTR,#data16 addr11 A ORL C,/bit B ANL C,/bit C PUSH dir D POP dir E MOVX A, @DPTR F MOVX @DPTR, A AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11
MOV Rr, dir 2 3 4 5 6 7
CJNE @Ri,#data,rel 0 XCH A, @ Ri 1 0 1 0
CJNE Rr, #data, rel 1 2 3 4 5 6 7
XCH A, Rr 1 2 3 4 5 6 7
DJNZ Rr, rel 2 3 4 5 6 7
MOVX A, @Ri 0 1
MOV A, Rr 3 4 5 6 7
MOVX A, @Ri, A 0 1
MOV Rr, A 3 4 5 6 7
*) MOV A, ACC is not a valid instruction
1999 Mar 02
51
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
8. FLASH EEPROM 8.1 General
* 32 Kbytes electrically erasable internal program memory with
Block-and Page-Erase option ("Flash Memory").
* Internal fixed boot ROM. * Up to 32 Kbytes external program memory in combination with the
internal FEEPROM (EA=1).
User program memory selection If UBS1 and UBS0 are both 0, then the user program memory is mapped into the 64 K program memory space and the boot ROM cannot be selected. This is the situation after a reset when PSEN and ALE have not been pulled down during reset. Program execution starts at 0000H in the internal FEEPROM or in the external program memory dependent on the level of EA during reset. Boot ROM selection After a reset program execution starts in the boot ROM when during reset PSEN and EA are pulled down while ALE stay high. The boot ROM size is 1 Kbyte. Besides the serial in-circuit programming routine the boot ROM contains the routines for erase, write and verify of the FEEPROM, which can be called by the user program (LCALL to the address space between 63 K and 64 K). Switching between user program memory and boot ROM Switching between user program memory (internal or external) and boot ROM is possible if UBS1 and UBS0 are 0,1. Then in the program memory address space between 0 and 63k the user program memory is selected and in the memory space between 63 K and 64 K the boot ROM is selected. To switch from user program memory to boot ROM first UBS0 must be set (UBS1 stay 0) and a jump or call instruction to a location >63 K must be executed. At the moment of crossing the 63 K address border by a return instruction the switching from boot ROM to user memory (internal or external) is performed. After crossing the 63 K address border UBS1 and UBS0 are cleared and the total 64 K memory space is mapped as user program memory. By clearing UBS1 and UBS0, no special requirements to the user program are necessary to do that after a read or erase or write routine. A small restriction for memory switching is that no memory switching is allowed from or to the address space between 63 K and 64 K of the user program memory because the UBS bits must stay 0 in this range. This restriction can be avoided if the memory switching is always done by a subroutine in the address range between 0 and 63 K. Description The user program code in the FEEPROM is executed as in the standard 80C51 microcontroller. Erase and write cycles in the FEEPROM are always performed under control of the boot program in the boot ROM in the address space between 63 K and 64 K. Address and data parameters are passed via DPTR and accumulator A respectively. During an erase or write cycle in the FEEPROM no other access or program execution in the FEEPROM is possible. All interrupts must be disabled when the user program calls a user routine in the boot ROM. The boot routine for serial programming takes care of addressing, data transfer, verify, high voltage control, error message and return to the user program memory. It also contains the serial communication routine. The FEEPROM control register FMCON is a special function register. It contains the control bits for verify, write, erase and boot ROM switching.
* Up to 64 Kbytes external program memory if the internal program
memory is switched off (EA=0). The FEEPROM can be read and written byte-wise. Full Erase, Block Erase, and Page erase will erase 32 Kbytes, 256 bytes and 32 bytes respectively. In-circuit programming and out-of-circuit programming is possible. On-chip erase and write timing generation and on chip high voltage generation contribute to a user friendly interface.
8.2 Features
* Read: * *
byte-wise Write: byte-wise within 2.5 ms. (previously erased by a page, block or full erase). Erase: Page Erase (32 bytes) within 5 ms. Block Erase (256 bytes) within 5 ms. Full Erase (32 Kbytes) within 5 ms. Erased bytes contain FFH. Endurance: 100 erase and write cycles each byte at Tamb = 22C Retention: 10 years Out-of-circuit programming: Parallel programming with 87C51 compatible hardware Interface to programmer. In-circuit programming: Serial programming via RS232 interface under boot ROM program control. Auto baud rate selection. Intel Hex Object file Format. The user program can call routines in the boot ROM for erase, write and verify of the FEEPROM. High programming voltage generation: on chip Zero point on-chip oscillator and timer to generate the write and erase time durations. Programmable security for the code in the FEEPROM to prevent software piracy. The Security Byte is located in the highest address (7FFFH) of the FEEPROM. Supply voltage monitoring circuit on-chip to prevent loss of information in the FEEPROM during power-on and power-off.
* * * *
* * * *
8.3 Memory Map
Figure 48 shows the memory map of the user program memory and the boot ROM. They are located in the same program address space. Two bits UBS1 and UBS0 of the FEEPROM control special function register FMCON select between the two memory blocks.
1999 Mar 02
52
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
64 K 63 K *
64 K 63 K BOOTROM External Program Memory (EA = X) 32 K Security Byte Internal Program Memory (EA = 1) 0,0 External Program Memory (EA = 0) (EA = 1) 0 Security Byte Internal Program Memory 0,1
External Program Memory (EA = X) 32 K 7FFFH External Program Memory (EA = 0) 0
X,X *
= UBS1, UBS0
User-Boot selection bits in FMCON
In the program execution between 63k and 64k setting of UBS bits is not allowed.
USER MODE
BOOT MODE
RST
PSEN
ALE/WE internal EA external UBS1, UBS0 0,0 1,1 Start in BOOTROM
High Level
Low Level
Start at 0000H in user program
Figure 48. Program memory map and operation modes
1999 Mar 02
53
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
7 FMCON (FB) UBS1
6 UBS0
5 HV
4 -
1)
3 FCB3
2 FCB2
1 FCB1
0 FCB0
Figure 49. FEEPROM control register. NOTE: 1. Reserved for future use; a write operation must write "0" to the location.
Table 45. Description of FMCON bits
UBS1 0 0 1 1 UBS0 0 1 0 1 User - Boot selection bits User memory mapped from 0 to 64 K. User memory mapped from 0 to 63 K. Boot ROM mapped from 63 K to 64 K. User memory mapped from 0 to 63 K, but UBS1 bit cleared by hardware in this user address range. Boot ROM mapped from 63 K to 64 K. User software should not write "1" UBS1. Boot ROM mapped from 0 to 64 K. User software should not write "1" UBS1.
HV
High voltage indication bit. Read only. Is "1" as long as the high voltage for an erase or write operation is present.
FCB3 0 0 1 0 1
FCB2 0 1 1 0 0
FCB1 0 0 0 1 1
FCB0 0 1 0 1 0
Function Code Bits Value after Reset. Byte Write or byte read (verify) Page Erase (32 bytes boundaries). Block Erase (256 bytes boundaries). Full Erase (32 Kbytes). For calling a user routine in the boot ROM first all interrupts must be disabled and the DPTR and A have to be loaded with the desired values. After setting UBS0 = 1 and UBS1 = 0 and selecting the function via FCB-bits the respective user routine has to be called. The table below lists the boot ROM user routines, which can be called by the user program. The content of FMCON, A and DPTR before the call is described by "(IN)" and the contents after the return is described by "(OUT)". The boot ROM user routines do not change other registers or Data memory. ACC (IN) XXH BYTE XXH XXH XXH ACC (OUT) BYTE BYTE 08H 02H 0AH
(V)
The four FCB bits are write protected if the security feature is activated. Then only instructions in the internal program memory (FEEPROM) are able to write FCB (3-0), boot ROM and external program memory instructions cannot change FCB (3-0) except the full erase code can be loaded. The duration of a write or erase operation is determined by the FEEPROM timer. This timer includes a zero point RC oscillator and cannot be controlled by software.
BOOT-ROM ROUTINE BYTE_READ BYTE_WRITE PAGE_ERASE BLOCK_ERASE FULL_ERASE X V 1) 2) 3) 4)
CALL ADDRESS FFBAH FFADH FFAAH FFA5H FFA0H
FMCON (IN) 45H 45H 4CH 43H 4AH
FMCON (OUT) 15H 15H 1CH 13H 1AH
DPTR (IN) BYTE ADDRESS BYTE ADDRESS PAGE ADDRESS 1) BLOCK ADDRESS XXXXH
3)
DPTR (OUT) BYTE ADDRESS BYTE ADDRESS PAGE ADDRESS 2) BLOCK ADDRESS 4) 0018H
= don't care or not defined = verified byte (read back) = 5 LSB's of DPTR are don't care = 5 LSB's of DPTR are "0" = 8 LSB's of DPTR are don't care = 8 LSB's of DPTR contain 08H.
1999 Mar 02
54
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Example of user software (internal or external) that calls the Page Erase routine in the boot ROM to erase a page in the FEEPROM (32 bytes) starting at address location 1260H. CLR EA MOV DPTR, # 1260H MOV FMCON, # 4CH LCALL 0FFAAH ; Disable all interrupts ; Load page-address ; Load Page-Erase code ; Call Page-Erase routine ; in boot ROM (inherent delay 5 ms) ; Clear FMCON for security ; Enable interrupts again
8.4 Security
The security feature protects against software piracy and prevents that the content of the FEEPROM can be read undesirable. The Security Byte is located in the highest address location 7FFFH of the FEEPROM. The Security Byte should be 50H to activate and 00H or FFH to deactivate the security feature. This security code is chosen in such a way that single bit failures will not deactivate the security feature. If the security feature is deactivated, then there are no access restrictions to the FEEPROM. If the security feature is activated, then the external program memory has no access to the FEEPROM with the MOVC instructions. Also bits FCB (3-0) of FMCON cannot be written by external program code or boot ROM code. This prevents in-circuit programming and verification. Only the Full Erase code can be written to FCB (0-3) of FMCON. Note that for the internal program code no restrictions exist if the security feature is activated. At the end of a full erase operation the security feature is deactivated. Also parallel programming and verify is inhibited if the security feature is activated, only a full erase is possible. Note that the security mode does not change immediately when the security code is written into the security byte 7FFFH, but after a reset or power-on. This allows the verification of the loaded code in the FEEPROM, including the Security Byte.
MOV FMCON, #00H SETB EA
Example of user software (internal or external) that calls the Byte-Write routine in the boot ROM to write the content of R5 into the FEEPROM address location 1263H. CLR EA MOV DPTR, # 1263H MOV A, R5 MOV FMCON, # 45H LCALL 0FFADH ; Disable all interrupts ; Load byte address ; Load byte to be written ; Load byte-write code ; Call byte-write routine ; in boot ROM (inherent delay 2.5 ms) ; Clear FMCON for security ; Enable interrupts again ; Compare the "read-back" byte ; Jump if verify error
MOV FMCON, #00H SETB EA XRL A, R5 JNZ ERROR
8.5 Parallel Programming
Unlike standard EPROM programming, no high programming supply voltage must be applied to the EA pin and only one programming pulse must be applied to the ALE/WE pin. The parallel programming mode is entered with the steady signals RST=1, PSEN=0, EA=1 and SELXTAL1 = 1. The XTAL1,2 clock must have a frequency between 4 and 6MHz. The following table shows the logic levels for programming, erasing, verifying and read signature. P2.7 1 1 P2.6 1 0 0 0 P3.7 0 1 1 0 P3.6 1 1 1 0
MODE Full erase Program FEEPROM Verify FEEPROM Read signature ALE/WE P2.6, P2.7, P3.6, P3.7 Data and address bits: P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.5, P3.4
ALE/WE
1 1
0 0
Write Enable signal (program/erase), active low control signals
: : :
D0 - D7 A0 - A7 A8 - A14
Program data input / verify or read data output Input low order address bits. Input high order address bits.
The P89C557E4 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. These bytes are read by the same procedure as for a normal verification of locations 30H and 31H, except that P3.6 and P3.7 need to be pulled to LOW. ADDRESS 30H 31H CONTENT 15H B5H MEANING Philips P89C557E4
1999 Mar 02
55
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
+5 V
1 DON'T CARE 1 1 0
SELXTAL1 P1 RSTIN P3.6 P3.7 XTAL2
VDD P0 EA ALE/WE DON'T CARE 1 5 ms LOW PULSE 0 1 1 DON'T CARE DON'T CARE
P89C557E4
PSEN P2.7 P2.6
4-6MHz XTAL1 VSS
P2.0-P2.5 P3.4
Figure 50. Erase Configuration
+5 V
1 A0-A7 1 1 1
SELXTAL1 P1 RSTIN P3.6 P3.7 XTAL2
VDD P0 EA ALE/WE PGM DATA 1 2.5 ms LOW PULSE 0 1 0 A8-A13 A14
P89C557E4
PSEN P2.7 P2.6
4-6MHz XTAL1 VSS
P2.0-P2.5 P3.4
Figure 51. Programming Configuration
+5 V
1 A0-A7 1 1 1
SELXTAL1 P1 RSTIN P3.6 P3.7 XTAL2
8 x 10 K VDD P0 EA ALE/WE PGM DATA 1 1 0 0 (ENABLE) 0 A8-A13 A14
P89C557E4
PSEN P2.7 P2.6
4-6MHz XTAL1 VSS
P2.0-P2.5 P3.4
Figure 52. Program Verification
1999 Mar 02
56
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
FEEPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = -40 C to +85 C, VDD = 5 V 10%, VSS = 0 V (see Figure 53)
SYMBOL 1/tCLK tAVWL tWHAX tDVWL tWHDX tEHWL tWHEL tWLWHp tWLWHe tAVQV tELQV tEHQZ PARAMETER System clock frequency (standard oscillator) Address setup to WE LOW Address hold after WE HIGH Data setup to WE LOW Data hold after WE HIGH P2.7 (ENABLE) HIGH to WE LOW WE HIGH to P2.7 (ENABLE) LOW WE width (programming) WE width (erase) Address to data valid P2.7 (ENABLE) Low to data valid Data float after P2.7 (ENABLE) HIGH MIN 4 48tCLK 48tCLK 48tCLK 48tCLK 48tCLK 48tCLK 2.25 4.5 - - 0 MAX 6 - - - - - - 2.75 5.5 48tCLK 48tCLK 48tCLK VERIFICATION* ADDRESS tAVQV DATA IN (programing) tDVWL ALE/WE tAVWL tWHDX tWHAX DATA OUT ms ms UNIT MHz
PROGRAMMING*/Erase* P1.0-P1.7 P2.0-P2.5 P3.4 P0.0-P0.7 ADDRESS (programming)
tWLWHp tWLWHe
tEHWL P2.7 ENABLE
tWHEL
tELQV
tEHQZ
* For ERASE conditions see Figure 50. For PROGRAM conditions see Figure 51. For VERIFY conditions see Figure 52.
Figure 53. FEEPROM Programming/Erase and Verification Waveforms
1999 Mar 02
57
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
+5 V
VDD EW ALL OTHER PINS ARE DON'T CARE 1
P89C557E4
P3.0/RxD RS232 interface P3.1/TxD
RST
0
SELXTAL1 XTAL3 ALE output of ALE pulses
32.768 kHz
1) XTAL4
3K3
PSEN VSS EA
1) Alternative XTAL1, 2 may be selected (SELXTAL1 = 1) Figure 54. Serial programming (boot mode) Configuration
8.6 Serial Programming of FEEPROM
Serial in-circuit programming (boot-mode) is entered if during and after RESET PSEN and EA are pulled down, PSEN via a resistor of 3.3 k Ohm to VSS. The two UBS bits are set to 1 by hardware and program execution starts at 0000H of the boot ROM. P3.0 (RXD) and P3.1 (TXD) form the serial RS232 interface. A baud rate of 4800 or 9600 Baud is possible, if the PLL oscillator is selected. The receive and transmit channel have the same baudrate. The format is: Startbit, 8 data bits (last bit always 0), no parity bit and at least one stopbit. The boot routine inputs the Intel Hex Object Format. The baud rate will be selected automatically after reception of the first character (:) of the object file. No other characters are allowed to preceed the first (:) character. Programming is only started if the first received record has the right type indication (TT). If the security feature is activated (contents of the security byte = 50H) then the programming starts with a Full Erase, otherwise only the addressed page(s) will be erased and the not altered bytes are rewritten. During the erase or write operation the next string of bytes can be received. Xon and Xoff handshake codes are used to control the serial transfer. At the end of the programming a message that indicates a successful or not successful programming, will be returned over the RS232 interface channel. If the programming was successful then the user program can be started up at 0000H in FEEPROM by a reset for user mode (EA = high, PSEN not affected). If the programming was not successful the boot program halts and a retry can be started by a reset for the boot mode.
8.7 Boot Routine
The boot routine transmits the next "one ASCII character" messages via the RS232 interface: "." "X" "Y" "Z" "R" "V" After each record type TT = 00H indication in the HEX file. Checksum error of a record in the HEX file detected. Wrong record type received Buffer overflow error (Check Xon/Xoff of terminal) Verification error (of last written byte) End record received and programming of FEEPROM was successful
No messages are transmitted if the baud rate of the first character (:) can not be detected. The boot routine can also be started by the internal or external user program (LJMP FC07H). FMCON must be loaded previously with 40H. Interrupt registers, stack pointer, Timer 0, UART, P3.0 and P3.1 must be in the reset state. EA and PSEN must not be affected. A reset is needed to restart the user program after programming. The following baudrates will be detected automatically within the specified C clock range in MHz. Baudrate 1200 2400 4800 9600 19200 fCLK (min) 1 1) 2
1)
fCLK (max) 3.6 7.3 14.7 29.5 1) 59 1)
4 7.9 15.7
NOTE: 1. Value outside the specified clock range Note that the boot routines can (re) program any number of bytes from 1 byte to 32 Kbytes, independent in which order or at which location, but if the security feature is activated, a full erase is performed and all not programmed bytes become FFH.
1999 Mar 02
58
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Definitions: : BC AAAA TT HH CC - - - - - - Record start character Byte Count. The hexadecimal number of data bytes in the record. This may theoretically be any number from 0 to 255, although many assemblers prefer to deal with 16 data bytes per record (as shown in the example below). Load address in hexadecimal of first data byte in this record. Record type. The record type is 00 for data records and 01 for the end record. One hexadecimal data byte. Record checksum. This is the 2's complement of the summation of all of the bytes in the record from the byte count through the last data byte. While the summation is calculated, it is always truncated to a one byte result. Thus, if all of the bytes in the record are summed, including the checksum itself, the result will always be 00 if the record is valid.
Construction of data records (using the notation defined above, each letter corresponds to one hexadecimal digit in ASCII representation) is as follows: : BCAAAATTHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHCC The last record in a file is the end record and contains no data. Usually the end record will appear as shown in the first example below. However, in some cases a 16 bit checksum of all of the data bytes in the entire file may be inserted in the address field of the end record. This checksum would correspond to one generated by an EPROM programmer during file load, and its inclusion does not violate the rules for this format. This is shown in the second example. :00000001FF :00B12C0122 Successive hex records need not appear in sequential address order . For instance, a record for address 0000H might appear after a record for address 7FE0H. All of the bytes in a single record, however, must be in sequence. Any characters that appear outside of a record (i.e. after a checksum, but before the next ":") will be ignored, if present. An example of a valid hex file follows: :10010000C2F0E53030E704F404D2F08531F030F786 :100110000763F0FF05F0B2F0A430F00A63F0FFF4DB :0C0120002401500205F085F032F5332276 :00000001FF
9. ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS 1, 2, 3
PARAMETER Storage temperature range Voltage on VDD to VSS and SCL, SDA to VSS Input / output current on any I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING -65 to +150 -0.5 to +6.5 10 1.0 UNIT
C
V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions are taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1999 Mar 02
59
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
10. DC CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS
VDD = 5V ( 10%), VSS = 0V, Tamb = 0C to +70C (P8xC557E4EBx). All voltages with respect to VSS unless otherwise specified. TEST SYMBOL VDD IDD PARAMETER Supply voltage Supply current operating : P89C557E4 P83C557E4 Supply current Idle Mode : P89C557E4 P83C557E4 Supply current Power-down mode IPD Supply current Power-down mode: 32 kHz / PLL operation See notes 1 and 2 fCLK = 16MHz VDD = 5.5 V See notes 1 and 3 fCLK = 16MHz VDD = 5.5 V See note 4 2 V < VPD < VDDmax See note 17 VDD = 5.5 V CONDITIONS MIN 4.5 LIMITS MAX 5.5 40 40 15 12 100 100 UNIT V mA mA mA mA A A
IID
Inputs VIL VIL1 VIL2 VIH VIH1 VIH2 IIL ITL ILI1 ILI2 ILI3 Outputs VOL VOL1 VOL2 Output low voltage, Ports 1, 2, 3, 4 Output low voltage, Port 0, ALE, PSEN, PWM0, PWM1, RSTOUT Output low voltage, SCL, SDA IOL = 1.6mA7 IOL = 3.2mA7 0.45 0.45 0.4 0.6 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD 0.05VDD 20 V V V V V V V V V V Input LOW voltage, except EA, SCL, SDA Input LOW voltage to EA Input LOW voltage to SCL, SDA 5 Input HIGH voltage, except XTAL1, RSTIN, SCL, SDA, ADEXS Input HIGH voltage, XTAL1, RSTIN, ADEXS Input HIGH voltage, SCL, SDA
5
-0.5 -0.5 -0.5 0.2VDD+0.9 0.7VDD 0.7VDD VIN = 0.45 V See note 6 0.45 V < VI < VDD 0 V < VI < 6 V 0 V < VDD < 5.5 V 0.45 V < VI < VDD
0.2VDD-0.1 0.2VDD-0.3 0.3VDD VDD+0.5 VDD+0.5 6.0 -50 -650 10 10 1
V V V V V V A A A A A
Input current LOW level, Ports 1, 2, 3, 4 Transition current HIGH to LOW, Ports 1, 2, 3, 4 Input leakage current, Port 0, EA, ADEXS, EW, SELXTAL1 Input leakage current, SCL, SDA Input leakage current, Port 5
IOL = 3.0mA7, 19 IOL = 6.0mA7, 19 VDD = 5 V 10% -IOH = 60A -IOH = 25A -IOH = 10A VDD = 5 V 10% -IOH = 800A -IOH = 300A -IOH = 80A
VOH
Output high voltage, Ports 1, 2, 3, 4
VOH1
Output high voltage (Port 0 in external bus mode, ALE, PSEN, PWM0, PWM1, RSTOUT) 8
VHYS Hysteresis of Schmitt Trigger inputs SCL, SDA (Fast-mode) NOTES: See Page 62.
1999 Mar 02
60
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
DC ELECTRICAL CHARACTERISTICS (Continued)
VDD = 5 V ( 10%), VSS = 0 V, Tamb = -40C to +85C (P8xC557E4EFx). DC parameters not included here are the same as in the P8xC557E4EBx, DC electrical characteristics All voltages with respect to VSS unless otherwise specified. TEST SYMBOL RRST CIO Inputs VIL VIL1 VIH VIH1 IIL Input LOW voltage, except EA, SCL, SDA Input LOW voltage to EA Input HIGH voltage, except XTAL1, RSTIN, SCL, SDA, ADEXS Input HIGH voltage, XTAL1, RSTIN, ADEXS Input current LOW level, Ports 1, 2, 3, 4 VIN = 0.45 V See note 6 -0.5 -0.5 0.2VDD+1.0 0.7VDD+0.1 0.2VDD-0.15 0.2VDD-0.35 VDD+0.5 VDD+0.5 -75 -750 V V V V A A PARAMETER Internal reset pull-down resistor Pin capacitance Test freq = 1MHz, Tamb = 25 C CONDITIONS MIN 50 LIMITS MAX 150 10 UNIT k pF
ITL Transition current HIGH to LOW, Ports 1, 2, 3, 4 NOTES: See Page 62.
DC ELECTRICAL CHARACTERISTICS ANALOG
AVDD = 5 V ( 10%), AVSS = 0 V, Tamb = 0 C to +70 C (P8xC557E4EBx). AVDD = 5 V ( 10%), AVSS = 0 V, Tamb = -40 C to +85 C (P8xC557E4EFx). All voltages with respect to VSS unless otherwise specified. TEST SYMBOL AVDD Analog supply voltage Analog supply current operating AIDD Analog supply current operating: 32 kHz/PLL operation Analog supply current Idle Mode AIID Analog supply current Idle Mode: 32 kHz/PLL operation Supply current Power-down mode AIPD Supply current Power-down mode: 32 kHz / PLL operation Analog input voltage Reference voltage: AVREF- AVREF+ Resistance between AVREF+ and AVREF- Analog input capacitance Differential non-linearity 9, 10, 11, Integral non-linearity 9, 12 Offset error 9, 13 Gain error 9, 14 Absolute voltage error 9, 15 Channel to channel matching 0-100kHz PARAMETER CONDITIONS AVDD = VDD 0.2 V Port 5 = 0 to AVDD see notes 1 and 2 Port 5 = 0 to AVDD see note 17, 18 see notes 1 and 3 see note 17 2 V < VPD < VDDmax see note 4 VDD = 5.5V see note 17 AVSS-0.2 AVSS-0.2 AVDD+0.2 10 50 15 1 2 2 0.4 3 1 -60 MIN 4.5 LIMITS MAX 5.5 1.2 7.2 70 6.0 50 200 UNIT V mA mA mA mA A A
Analog Inputs AVIN AVREF AVDD+0.2 V V V k pF LSB LSB LSB % LSB LSB dB
RREF CIA DLe ILe OSe Ge Ae MCTC
Ct Crosstalk between inputs of port 5 16 NOTES: See Page 62.
1999 Mar 02
61
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 55 and 57 through 59 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2, XTAL3 not connected; EA = RSTIN = Port 0 = EW = SCL = SDA = SELXTAL1 = VDD; ADEXS = XTAL4 = VSS. 3. The Idle Mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2, XTAL3 not connected; Port 0 = EW = SCL = SDA = SELXTAL 1 = VDD; EA = RSTIN = ADEXS = XTAL4 = VSS. 4. The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = SCL = SDA = SELXTAL 1 = VDD; EA = RSTIN = ADEXS = XTAL1 = XTAL4 = VSS. 5. The input threshold voltage of SCL and SDA (SIO1) meets the I2C specification, so an input voltage below 0.3 VDD will be recognized as a logic 0 while an input voltage above 0.7 VDD will be recognized as a logic 1. 6. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from HIGH to LOW. The transition current reaches its maximum value when VIN is approximately 2 V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 9. Conditions: AVREF- = 0 V; AVDD = 5.0 V, AVREF+ = 5.12 V. VDD = 5.0 V, VSS = 0 V, ADC is monotonic with no missing codes. Measurement by continuous conversion of AVIN = -20mV to 5.12 V in steps of 0.5mV, derivating parameters from collected conversion results of ADC. ADC prescaler programmed according to the actual oscillator frequency, resulting in a conversion time within the specified range for tconv (15s ... 50s). 10. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. 11. The ADC is monotonic; there are no missing codes. 12. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. 13. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. The offset error is constant at every point of the actual transfer curve. 14. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. 15. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 16. This should be considered when both analog and digital signals are simultaneously input to port 5. 17. The supply current with 32 kHz oscillator running and PLL operation (SELXTAL1 = 0) is measured with all output pins disconnected; XTAL4 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = EW = SCL = SDA = VDD; EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = VSS. 18. Not 100% tested; sum of AIID (PLL) and AIDD (HF-Oscillator). 19. The parameter meets the I2C bus specification for standard-mode and fast-mode devices. 20. Not 100% tested.
1999 Mar 02
62
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
50
40
(1) (2)
30 IDD (mA) 20 (3) (4) 10
0 0 4 8 f (MHz) 12 16
(1) (2) (3) (4)
Maximum operating mode P89C557E4 Maximum operating mode P83C557E4/P80C557E4 Maximum Idle Mode P89C557E4 Maximum Idle Mode P83C557E4/P80C557E4
: : : :
VDD = 5.5 V VDD = 5.5 V VDD = 5.5 V VDD = 5.5 V
Figure 55. Supply Current (IDD) as a Function of Frequency at XTAL1
1999 Mar 02
63
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Offset error OSe 1023 1022 1021 1020 1019 1018
Gain error Ge
(2)
7 Code Out (1) 6 5 (5) 4 (4) 3 2 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 (3)
1 LSB (ideal)
AVIN (LSBideal) Offset error OSe
AVREF+ - AVREF-
1 LSB =
1024
(1) (2) (3) (4) (5)
Example of an actual transfer curve. The ideal transfer curve. Differential non-linearity (DLe). Integral non-linearity (ILe). Center of a step of the actual transfer curve.
Figure 56. ADC Conversion Characteristic 64
1999 Mar 02
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
11. AC CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS
VDD = 5 V 10% (EBx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency) VDD = 5 V 10% (EFx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency) Tamb = 0 C to +70 C, tCLK min = 63 ns for P8xC557E4EBx Tamb = -40 C to +85 C, tCLK min = 63 ns for P8xC557E4EFx C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified. 12MHz CLOCK SYMBOL 1/tCLK tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH 61, 62 61, 62 61 62 61 61 61 61 61 61, 62 61, 62 62 62 62 61 61, 62 Address valid to ALE LOW Address hold after ALE LOW RD pulse width WR pulse width RD LOW to valid data in Data hold after RD Data float after RD ALE LOW to valid data in Address to valid data in ALE LOW to RD or WR LOW Address valid to WR LOW or RD LOW Data valid to WR transition Data before WR Data hold after WR RD low to address float RD or WR HIGH to ALE HIGH 43 200 203 33 433 33 0 123 23 0 97 517 585 300 138 120 13 288 13 0 103 tCLK-40 43 48 400 400 252 0 55 350 398 238 3tCLK-50 4tCLK-130 tCLK-50 7tCLK-150 tCLK-50 0 tCLK+40 23 28 275 275 148 0 2tCLK-70 8tCLK-150 9tCLK-165 3tCLK+50 tCLK-40 tCLK-35 6tCLK-100 6tCLK-100 5tCLK-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns 10tCLK-133 ns FIGURE 60 60 60 60 60 60 60 60 60 60 60 60 PARAMETER System clock frequency ALE pulse width Address valid to ALE LOW Address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN LOW to address float 0 59 312 10 53 205 145 0 38 208 10 127 43 53 234 33 143 83 0 tCLK-25 5tCLK-105 10 85 23 33 150 tCLK-30 3tCLK-45 3tCLK-105 MIN MAX 16MHz CLOCK MIN MAX VARIABLE CLOCK MIN 3.5 2tCLK-40 tCLK-40 tCLK-30 4tCLK-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
UART Timing - Shift Register Mode (Test Conditions: Tamb = 0 C to +70 C; VSS = 0 V; Load Capacitance = 80pF) tXLXL tQVXH tXHQX tXHDX tXHDV 64 64 64 64 64 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid 1.0 700 50 0 700 0.75 492 8 0 492 12tCLK 10tCLK-133 2tCLK-117 0
1999 Mar 02
65
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER Standard-mode I2C-bus MIN I2C Interface timing (refer to Figure 63) fSCL tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock High period of the SCL clock Set-up time for a repeated START condition Data hold time: for CBUS competible masters (see Section 9, Notes 1, 3) for I2C-bus devices Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter 0 4.7 4.0 4.7 4.0 4.7 5.0 01 250 - - 4.0 - - - 1000 300 - 400 - 100 - - - - - 0 1.3 0.6 1.3 0.6 0.6 - 01 1003 20 + 0.1Cb4 20 + 0.1Cb4 0.6 - 0 400 - - - - - - 0.92 - 300 300 - 400 50 ns ns ns s pF ns kHz s s s s s s MAX Fast-mode I2C-bus MIN MAX UNIT
tSU; DAT tFD, tFC tFD, tFC tSU; STO Cb tSP
All values referred to VIH and VIL max levels. NOTES: 1. A device must internally provide a hold time of at least 300 ns from the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. The maximum tHD,DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU,DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU,DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 4. Cb = total capacitance of one bus line in pF.
Table 46. External clock drive XTAL1 (refer to Figure 57)
SYMBOL PARAMETER VARIABLE CLOCK fCLK = 3.5 to 16 MHz MIN tCLK tCLKH tCLKL tCLKR tCLKF tCYC 1) XTAL1 Period XTAL1 HIGH time XTAL1 LOW time XTAL1 rise time XTAL1 fall time Controller cycle time 63 20 20 - - 0.75 MAX 286 - - 20 20 3.4 ns ns ns ns ns s UNIT
NOTE: 1. tCYC = 12 fCLK
1999 Mar 02
66
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
tCLKH VIH1 VIH1
0.8V
tCLKR VIH1
0.8V
tCLKF VIH1
tCLKL tCLK Figure 57. External Clock Drive waveform
Float 2.4 V 2.0 V Test Points 0.8 V 0.45 V NOTE: AC inputs during testing are driven at 2.4V for a logic `HIGH' and 0.45V for a logic `LOW'. Timing measurements are made at 2.0 V for a logic `HIGH' and 0.8 V for a logic `LOW'. 0.8 V 0.45 V 0.8 V 0.8 V 0.45 V 2.0 V 2.4 V 2.0 V 2.0 V 2.4 V
NOTE: The float state is defined as the point at which a port 0 pins sinks 3.2 mA or sources 400mA at the voltage test levels.
Figure 58. AC Testing Input/Output
Figure 59. AC Testing, Float Waveform
tLHLL
ALE
tAVLL
PSEN
tLLPL tLLIV
tPLPH
tPLIV tLLAX tPLAZ tPXIX
INSTR IN A0-A7
tPXIZ
PORT 0
A0-A7
tAVIV
PORT 2 A8-A15 A8-A15
Figure 60. External Program Memory Read Cycle
1999 Mar 02
67
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX
tRLDV tRLAZ tRHDX
DATA IN
tRHDZ
A0-A7 FROM RI OR DPL
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
Figure 61. External Data Memory Read Cycle
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
A0-A7 FROM RI OR DPL
tQVWX tQVWH
DATA OUT
tWHQX
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Figure 62. External Data Memory Write Cycle
1999 Mar 02
68
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
repeated START condition START or repeated START condition tRD SDA (INPUT/OUTPUT) tBUF tFD SCL (INPUT/OUTPUT) tRC tFC tSP tSU; STO 0.7 VDD 0.3 VDD tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 STOP condition 0.7 VDD 0.3 VDD tSU;STA START condition
Figure 63. Timing SIO1 (I2C) Interface
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1
2
3
4
5
6
7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
VALID VALID VALID VALID VALID
SET TI VALID
SET RI
Figure 64. UART waveforms in Shift Register Mode
1999 Mar 02
69
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
One Machine Cycle
One Machine Cycle
XTAL1 INPUT
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
dotted lines are valid when RD or WR are active only active during a read from external data memory only active during a write to external data memory
ALE
PSEN RD WR
external program memory fetch
Bus (Port 0)
Int. in
address A0-A7
Int. in
address A0-A7
Int. in
address A0-A7
Int. in
address A0-A7
Port 2
address A8-A15
address A8-A15
address A8-A15
address A8-A15
read or write of external data memory
Bus (Port 0) Port 2
Int. in
address A0-A7
Int. in
address A0-A7
data output or data input
address A0-A7
address A8-A15
address A8-A15 or Port2 out
address A8-A15
PORT OUTPUT PORT INPUT
old data
new data
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL PORT CLOCK
Figure 65. Instruction cycle timing
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Mar 02
70
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT318-1
1999 Mar 02
71
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
P83C557E4/P80C557E4/P89C557E4
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 03-99 Document order number: 9397 750 05357
Philips Semiconductors
1999 Mar 02 72

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