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OXFW900
IEEE1394 to ATA/ATAPI Native Bridge
FEATURES
* * * * * * * * * S400 compliant 1394-1995 Link and Transaction layers Compatible with 1394-1995 and 1394A Phys. Buffer Manager with max. RAM bandwidth of 800Mbps Microsoft Win98-Second Edition, Win2000 and Apple MacOS 8.5 generic driver support SBP-2 Target Revision 4 compliant interface Fully ATA-4 compliant (see T13-1153D) Sustained IDE transfer rate of 25 Mbytes per second, Peak transfer rate of 50Mbytes per second. Supports PIO modes 0 to 4, DMA modes 0 to 2 and Ultra DMA modes 0 to 2 Integrated 32-bit RISC processor (ARM7TDMI) with on-chip scratch RAM * * * * * * * * *
Data Sheet
ORB co-processor to accelerate translation of ORBs to ATAPI commands Supports ORB chaining for increased performance High performance ATA command translation in firmware using Reduced Block Command (RBC) set Optional External Serial ROM interface for configuration data, user serial number, etc. Blank Flash memory programming feature via 1394 bus 3.3 Volts operation Low Power CMOS Firmware and Flash Programming Utilities supplied by Oxford Semiconductor ultra-thin 128-TQFP package (14mm x 14mm x 1mm )
DESCRIPTION
The OXFW900 is a high-performance 1394 to ATA/ATAPI (IDE) native bridge with an integrated target Serial Bus Protocol (SBP-2 ) controller. By supporting the SBP-2 protocol, the device can use generic SBP-2 drivers available in the Microsoft Windows 98SE, Microsoft Windows 2000, Microsoft Millennium and Apple MacOS operating systems. The device is ideally suited for smart-cable or tailgate interface applications for removable-media drives, compact flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM and hard disk drives, allowing IDE drives to be connected to a 1394 serial bus in a plug-and-play fashion. Both ATA and ATAPI devices are supported using the same firmware. This highly integrated device offers a three-chip solution to native bridge applications using an external 1394 PHY and Flash ROM. A slow 32Kx8 Flash ROM (up to 120ns) is sufficient for most optical media applications. For applications that need a sustained data rate in excess of 10Mbytes per second, for example high performance disk drives, an 8-bit 50ns FLASH or faster is recommended. The device is compatible with both 1394-1995 and 1394A PHYs. The LINK controller complies with S400 1394-1995 specification. The 1394 transaction layer and SBP-2 protocol is implemented using a combination of the ARM7TDMI (low-power 32-bit RISC processor), an ORB (Operational Request Block) hardware co-processor and a high performance buffer manager. Oxford Semiconductor Ltd. 69 Milton Park, Abingdon, Oxon, OX14 4RX, UK Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141 The Buffer Manager has a RAM bandwidth of 800Mbps. It provides storage for 1394 and ATA/ATAPI packets, automatically storing them and passing them to the appropriate destinations, without any intervention from the processor. It also provides storage and manages the sequencing of ORB fetching to reduce latency and improve data throughput. The configuration data including the IEEE OUI (Organisational Unique Identifier) and device serial number is stored in the Flash ROM which may be uploaded from the 1394 bus, even when blank. The device also facilitates firmware uploads from the 1394 bus. The ORB co-processor translates ORBs as defined in the SBP-2 protocol into ATA/ATAPI commands, and automatically stores error/status messages at an address specified by the host. Concurrent operation of the ATA/ATAPI and 1394 interfaces are facilitated using the high throughput Buffer Manager where LINK, ATAPI manager and ARM7TDMI can perform interleaved accesses to the on-chip RAM buffer. The high performance processor ensures that no significant latency is incurred. The ATA command translation is performed in firmware to meet RBC (Reduced Block Commands) standard, T10-1228D. The ATA/ATAPI Manager supports PIO modes 0 to 4, DMA modes 0 to 2 and Ultra DMA mode 0 to 2 and provides the interface to the IDE bus. It is compliant with T13-1153D, ATA-4 specification. (c) Oxford Semiconductor 1999 OXFW900 Data Sheet Revision 1.0 - Nov 1999 Part No. OXFW900-TQ-A
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OXFW900
CONTENTS
FEATURES ..........................................................................................................................................................1 DESCRIPTION.....................................................................................................................................................1 CONTENTS..........................................................................................................................................................2 1 2 3 4 5 6
5.1 6.1 6.2 6.3
BLOCK DIAGRAM ......................................................................................................................................3 PIN INFORMATION .....................................................................................................................................4 PIN DESCRIPTIONS ...................................................................................................................................5 OPERATING CONDITIONS........................................................................................................................7 DC ELECTRICAL CHARACTERISTICS....................................................................................................7 AC ELECTRICAL CHARACTERISTICS....................................................................................................8
I/O BUFFERS.......................................................................................................................................................... 7 IDE INTERFACE ..................................................................................................................................................... 8 1394 LINK-PHY INTERFACE ................................................................................................................................ 11 EXTERNAL PROCESSOR INTERFACE................................................................................................................ 12
7 8 9
TIMING WAVEFORMS..............................................................................................................................13 PACKAGE INFORMATION.......................................................................................................................27 ORDERING INFORMATION .....................................................................................................................28
NOTES ...............................................................................................................................................................29 CONTACT DETAILS.........................................................................................................................................30 DISCLAIMER.....................................................................................................................................................30
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OXFW900
1
BLOCK DIAGRAM
Buffer RAM
PD[7:0] CTL[1:0] PHY_CLK LINK_ON LPS LREQ ATA/ ATAPI manager Internal ARM7TDMI bus Link-Phy interface RAM Manager
IDE_OE# RTS[3:0]# ID[15:0] DMARQ DIOW# DIOR# IORDY DMACK#
D[15:0] A[16:0] CS#[3:0] OE# WE# BWE#[1:0] WIDTH16 INT# External ROM interface
INTRQ# IA[2:0] ORB Coprocessor IDE_CS#[2:0]
XTALO XTALI CKIN CKOUT Clock generator
ARM7TDMI
EE_DO EE_DI EE_CK EE_CS EEPROM interface SCRATCH RAM
Figure 1: OXFW900 Block Diagram
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2
PIN INFORMATION
IA1 IA0 IA2 ICS0# ICS1# LINKON LPS PD7 PD6 GND GND PD5 PD4 PD3 PD2 5VBIAS CKOUT VDD PD1 PD0 CTL1 CTL0 GND PHYCLK VDD LREQ FORCE# TEST0 TEST1 GPO1 GPO2 GPO3
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
INTRQ DMACK# VDD GND IORDY DIOR# DIOW# DMARQ VDD GND ID15 ID0 VDD GND ID14 ID1 ID13 ID2 ID12 ID3 5VBIAS GND ID11 ID4 ID10 ID5 ID9 ID6 GND GND ID8 ID7
OXFW900-TQ-A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IRESET IDE_OE# WIDTH16 INT# A0 VDD XTLO XTLI CKIN GND A1 A2 A3 A4 A5 A6 A7 VDD GND A8 A9 A10 A11 A12 A13 GND 5VBIAS A14 A15 A16 WE# BWR0#
Data Sheet Revision 1.0
GPI D15 D14 D13 D12 D11 D10 GND 5VBIAS D9 D8 D7 D6 D5 D4 GND VDD D3 D2 D1 D0 GND RESET# VDD CS3# CS2# GND VDD CS1# CS0# OE# BWR#
Figure 2: Pinout (package = 128 TQFP)
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3
PIN DESCRIPTIONS
Dir1 I/O I/O I O IU O T_I/O T_O T_O T_O T_O T_O ID T_IU T_I/O T_O T_O T_O T_O T_I T_O T_O T_O T_O T_I O O IU O I Name PD[7:0] CTL[1:0] PHYCLK LREQ LINKON LPS D[15:0] A[16:0] CS#[3:0] OE# BWR#[1:0] WE# WIDTH16 INT# ID[15:0] IA[2:0] ICS#[1:0] IDE_OE#[ IRESET DMARQ DIOW# DIOR# IORDY DMACK# INTRQ GPO3 GPO1 GPI GPO2 XTLI Description Phy-Link Data Bus Phy-Link Control Bus 49.152 MHz clock sourced by PHY Link Request Requests link to power up when in a low power mode Indicates to phy that link is powered and ready ARM external data bus ARM external address bus ARM external chip selects. CS0# is always used for program ROM. ARM external output enable. Active when reading data from external devices including program ROM Byte Write enables. For future expansion Write Enable. Active when writing to external devices `1' = 16 bit external ROM `0' = 8 bit external ROM (pulldown) External ARM interrupt IDE data bus IDE address bus IDE chip select. Selects IDE drive 0 or 1 IDE output enable. Only used when external buffering is required to drive IDE data bus IDE interface reset IDE interface write strobe IDE interface read strobe
1394 PHY-LINK interface 104, 105, 108, 109, 110, 111, 115, 116 117,118 120 122 102 103 ARM external interface 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15, 18, 19, 20, 21 35, 36, 37, 40, 41, 42, 43, 44, 45, 48, 49, 50, 51, 52, 53, 54, 60 25, 26, 29, 30 31 32, 33 34 62 61 IDE interface 65, 66, 69, 70, 71, 72, 73, 74, 77, 78, 79, 80, 81, 82, 85, 86 97, 98, 99 100, 101 63 64 89 90 91 92 95 96 EEPROM interface 128 126 1 127 Miscellaneous Pins 57
General Purpose Output 3 General Purpose Output 1 General Purpose Input General Purpose Output 2 Crystal Oscillator input. 24.576 MHz crystal required. If a clock module is used rather than a crystal then this input must be tied high for the OXFW900 to operate, and the clock module output connected to the CKIN pin. IMPORTANT See Application Notes regarding clocking Crystal Oscillator output. IMPORTANT - See Application Notes regarding clocking.
58
O
XTLO
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56 I CKIN
OXFW900
Direct clock input. Used in conjunction with an external crystal oscillator of 24.576MHz. If a crystal is connected to XTLI and XTLO this input must be tied low for the OXFW900 to operate. Mark space ratio of crystal oscillator must be 45:55 or better. IMPORTANT - Please refer to Application Notes regarding clocking Global reset for the OXFW900. Active Low. Clock output. 24.576 MHz clock output. IMPORTANT - Please refer to Application Notes regarding clocking This input is used to allow the OXFW900 to reprogram a flash which has been loaded with a bad program. A bad program is defined as one that does not have the correct interlocking mechanism for reprogramming flash. This pin forces the ARM watchdog timer to trigger thus allowing the flash to be reprogrammed over the 1394 bus as if the flash were blank. `11' = NORMAL OPERATION. These pins have internal pullup resistors and must be left unconnected. Other settings are for foundry test purposes only. Supplies power to output buffers in switching (AC) state Power supply. Supplies power to core logic, input buffers and output buffers in steady state Supplies 5V reference bias to all 5V tolerant I/O. All four MUST be connected to 5V rail. Supplies GND to output buffers in switching (AC) state Ground (0 volts). Supplies GND to core logic, input buffers and output buffers in steady state
23 113 123
IU T_O IU
RESET# CKOUT FORCE#
124, 125 Power and ground2 28, 47, 94, 114 17, 24, 59, 84, 88, 121 9, 38, 76, 112 8, 27, 46, 67, 75, 93, 106 16, 22, 39, 55, 68, 83, 87, 107, 119
IU
TEST[1:0]
3V3 3V3 5V G G
3.3V AC VDD 3.3V DC VDD 5V BIAS VDD AC GND DC GND
Table 1: Pin Descriptions Note 1: Direction key: I IU ID O I/O T_I Input Input with internal pull-up Input with external pull-down Output Bi-directional 5V tolerant input T_O T_I/O G 3V3 5V 5V tolerant output 5V tolerant bi-directional Ground 3.3V power 5V bias power
Note 2: Power & Ground There are two GND and three VDD rails internally. One set of rails supply power and ground to output buffers while in switching state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail). A third rail provides 5V bias voltage to 5V tolerant IO. The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation from the chip.
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OXFW900
Configuration & Operation
4
OPERATING CONDITIONS
Symbol VDD VIN IIN TSTG Parameter DC supply voltage DC input voltage DC input current Storage temperature Table 2: Absolute maximum ratings Symbol VDD VBB TC Parameter DC supply voltage 5V PMOS bulk bias Temperature Min 3.0 4.75 0 Table 3: Recommended operating conditions Max 3.6 5.25 70 Units V V C Min -0.3 -0.3 -40 Max 4.6 VDD + 0.3 +/- 10 125 Units V V mA C
5
5.1
DC ELECTRICAL CHARACTERISTICS
I/O Buffers
Symbol VDD VIH VIL CIL COL IIH IIL VOH VOH VOL VOL IOZ Symbol Parameter Supply voltage Input high voltage Input low voltage Cap of input buffers Cap of output buffers Input high leakage current Input low leakage current Output high voltage Output high voltage Output low voltage Output low voltage 3-state output leakage current Parameter Operating supply current in normal mode Operating supply current in Power-down mode Condition Commercial CMOS Interface CMOS Schmitt trig CMOS Interface 1 CMOS Schmitt trig Vin = VDD Vin = VSS IOH = -1 A IOH = -1mA to -24mA IOL = 1 A IOL = 1mA to 24mA Min 3.0 0.7 x Vdd 2.1 Max 3.6 0.3 x Vdd 0.8 5.0 10.0 10 10 Units V V V pF pF A A V V V V A Units
-10 -10
VDD - 0.05
2.4 0.05 0.4 10 Max
-10 Condition Typical
ICC
mA
Table 4: Characteristics of OXFW900 I/O buffers
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6
6.1
AC ELECTRICAL CHARACTERISTICS
IDE interface
Symbol t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 tRD tA tB tA
Parameter Cycle Time Address Valid to DIOR# / DIOW# setup DIOR# / DIOW# pulse width DIOR# / DIOW# recovery time DIOW# data setup (min ) DIOW# data hold DIOR# data setup ( min ) DIOR# data hold ( min ) DIOR# data tristate (max ) DIOR# / DIOW# to address valid hold Read Data Valid to IORDY active if IORDY initially low after tA IORDY Setup time IORDY Pulse Width ( max ) IORDY assertion to release
Mode 0 600 80 320 60 40 50 5 30 40 0 35 1250 5
Mode 1 400 80 320 45 40 35 5 30 40 0 35 1250 5
Mode 2 360 40 320 30 40 20 5 30 40 0 35 1250 5
Mode 3 200 40 80 80 30 40 20 5 30 40 0 35 1250 5
Mode 4 120 40 80 40 20 40 20 5 30 40 0 35 1250 5
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 5: OXFW900 IDE PIO / Register Transfers
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Symbol t0 tD tE tF tG tH tI tJ tKr tKw tLr tLw tM tN tZ
Parameter Cycle time DIOR# / DIOW# DIOR# data access ( max ) DIOR# data hold ( min ) DIOR# / DIOW# data setup DIOW# data hold DMACK to DIOR# / DIOW# setup ( min ) DIOR# / DIOW# to DMACK hold ( min ) DIOR# negated pulse width DIOW# negated pulse width DIOR# to DMARQ delay ( max ) DIOW# to DMARQ delay ( max ) IDCS[1:0] valid to DIOR# / DIOW# IDCS[1:0] hold DMACK to tristate ( max )
Mode 0 480 240 150 5 100 20 0 20 80 240 120 40 80 40 20
Mode 1 160 80 60 5 30 15 0 5 80 80 40 40 40 40 25
Mode 2 120 80 50 5 20 10 0 5 40 40 35 35 40 40 25
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 6: OXFW900 Multiword DMA timings
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Symbol t2cyc tcyc t2cyc tds tdh tdvs tdvh tfs tli tmli tui taz tzah tzad tenv tsr trfs
Parameter Typical sustained average two cycle time Cycle time allowing for clock variations ( refer to ATA spec) Two cycle time allowing for clock variations ( refer to ATA spec ) Data setup time at recipient Data hold time at recipient Data valid setup time at sender (from data bus being valid until STROBE edge ) Data valid hold time at sender (from STROBE edge until data may become invalid First STROBE time (for device to first negate DSTROBE from STOP during a data-in burst) Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release (from being asserted or negated) Minimum delay time required for output drivers to assert or negate (from released state) Envelope time ( from DMACK# to STOP and HDMARDY# during data-out burst initiation STROBE to DMARDY time ( refer to ATA spec Ready-to-final-STROBE time ( no STROBE edges shall be sent this long after the negation of DDMARDY# Ready-to-pause time ( time that recipient shall wait to initiate pause after negating DMARDY# ) Pull-up time before allowing IORDY to be released Minimum time a device shall wait before driving IORDY Setup and hold times for DMACK# (before assertion or negation ) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst )
Mode 0 min 240 114 235 15 5 70 6 0 0 20 0
Mode 0 max
Mode 1 min 160 75 156 10 5 48 6
Mode1 max
Mode 2 min 120 55 117 7 5 34 6
Mode 2 max
Units ns ns ns ns ns ns ns
230 150 10
0 0 20 0
200 150 10
0 0 20 0
170 150 10
ns ns ns ns ns ns
20 0 20 20 75 70
20 0 20 25 60 70
20 0 20 25 50 70
ns ns ns
trp tiordyz tziordy tack tss
160 20 0 20 50
125 20 0 20 50
100 20 0 20 50
ns ns ns ns ns
Table 7: OXFW900 Ultra DMA timings
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6.2
1394 Link-Phy interface
The timings for 1394 Link - Phy are shown below : Symbol tlsu tlh Tld1 Tld2 Tld3 Parameter Setup Time, PD[7:0] and CTL[1:0] before PhyClk Hold Time, PD[7:0] and CTL[1:0] after PhyClk Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0] and Lreq outputs valid Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0], CTL[1:0] and Lreq outputs valid Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs invalid (high impedance) Table 8: OXFW900 Link-Phy interface timings Min 6 0 TBD TBD TBD Max TBD TBD TBD Units ns ns ns ns ns
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6.3
Name tas tcss tws taddr1 taddr2 tiorl tah tdsa tdha tdsb tdhb dsa1 dha1 dsb1 dhb1 dsa2 dha2 dsb2 dhb2 tahr tasr tiorh tds tdh tcsh tcsa twel tah tas1 tah1 tas2 tah2 tweh
External Processor Interface
Description Common Timings Address valid to CSx# and OE# falling CSx# and OE# falling to WE# or IOR# falling Wait State Additional Delay Not Last Address Valid Last Address Valid Common Read Timings IOR# valid Address hold after CSx# or OE# rising Single Access Read Timings Data valid and stable to CSx# and OE# rising Data hold after CSx# and OE# rising Data valid and stable to IOR# rising Data hold after IOR# rising Multiple Access Read Timings Data valid and stable to CSx# and OE# rising (not last access) Data hold after CSx# and OE# rising (not last access) Data valid and stable to IOR# rising (not last access) Data hold after IOR# rising (not last access) Data valid and stable to CSx# and OE# rising (last access) Data hold after CSx# and OE# rising (last access) Data valid and stable to IOR# rising (last access) Data hold after IOR# rising (last access) IOR# rising to next address valid Address valid to IOR# falling IOR# inactive between reads Common Write Timings Data valid to WE# rising Data hold after WE# rising CS# hold after WE# rising CS# hold after Address invalid WE# valid Single Access Write Timings Address hold after WE# rising Multiple Access Write Timings Address valid to CSx# and OE# falling Address hold after WE# rising (not last access) WE# falling after next address valid Address hold after WE# rising (last access) WE# inactive between writes Table 9: External Processor Interface timings min (ns) 0.3 16 0 0 0 0 0 0 0 typ (ns) 0 max (ns) 2.5 18.5 600 -
39+tws 13 20 1 19 -
-
17 2.5
-
60 -
All timings are preliminary and are subject to change
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TIMING WAVEFORMS
t0 ADDR valid DIOR# / DIOW# t1
t2
t9 t2i t3 t4
ID[7:0] (WRITE) t5 ID[7:0] (READ) IORDY (Note1) IORDY (Note2) IORDY (Note3) tB tRD tC t6z t6
tA
tC
Figure 3: PIO / Register Transfer to / from IDE device Notes : Negation of IORDY by the drive is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after tA from the Assertion of DIOR# or DIOW#. The assertion and negation of IORDY are described in the following three cases : 1) 2) 3) Device never negates IORDY and no wait is generated. Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before release : no wait generated. Device negated IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before release : wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR# is asserted, the device shall place read data on DD[7:0] for tRD before asserting IORDY
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TIMING WAVEFORMS
CS0# / CS1# tM DMARQ DMACK# t0 tN
tL
tI
tD
tK
tJ
DIOR# / DIOW# tE READ ID[15:0] tZ
tG WRITE ID[15:0] tG
tF
tH
Figure 4: MultiWord DMA transfer to / from IDE device
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DMARQ (device) tui tack DMACK(host) STOP(host) (DIOW#) HDMARDY(host) (DIOR#) tziordy DSTROBE(device) (IORDY) taz ID[15:0] IA[2:0], ICS#[1:0] tack tdvs tdvh tzad tenv tfs
Figure 5: Initiating an Ultra DMA data-in burst
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t2cyc tcyc DSTROBE(device) (IORDY) tdvh ID[15:0] (device) DSTROBE(host) IORDY tds tdh ID[15:0] (host) tdh tds tdh tdvs tdvh tdvs tdvh tcyc
Figure 6: Sustained Ultra DMA data-in burst
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DMARQ(device) DMACK(host) STOP(host) DIOW# DSTROBE(device) IORDY trfs DSTROBE(device) IORDY
trp
tsr
ID[15:0] (host)
Figure 7: Host pausing an Ultra DMA data-in burst
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DMARQ(device) DMACK(host) tli STOP(host) DIOW# HDMARDY(host) DIOR# tss DSTROBE(device) IORDY taz ID[15:0] (host) tzah tiordyz tli tmli
tack
CRC
tack
IA[2:0], ICS[1:0]
Figure 8: Device terminating an Ultra DMA data-in burst
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DMARQ(device) DMACK(host) trp STOP(host) DIOW# HDMARDY(host) DIOR# trfs DSTROBE(device) IORDY tdvs ID[15:0] (host) tli tmli tiordyz taz tack tzah
tdvh
CRC
tack
IA[2:0], ICS[1:0]
Figure 9: Host terminating an Ultra DMA data-in burst
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DMARQ (device) tui tack DMACK(host) STOP(host) (DIOW#) HSTROBE(host) (DIOR#) tziordy DDMARDY(device) (IORDY) tdvs ID[15:0] IA[2:0], ICS#[1:0] tack tdvh tli tui tenv
Figure 10: Initiating an Ultra DMA data-out burst
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t2cyc tcyc HSTROBE(host) tdvh ID[15:0] (host) tdvs tdvh tdvs tdvh tcyc
HSTROBE(device) tds tdh ID[15:0] (device) tdh tds tdh
Figure 11: Sustained Ultra DMA data-out burst
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DMARQ(device) trp DMACK(host) STOP(host) DIOW# DDMARDY(device) IORDY# trfs HSTROBE(host) DIOR#
tsr
ID[15:0] (host)
Figure 12: Device pausing an Ultra DMA data-in burst
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DMARQ(device) DMACK(host) tli STOP(host) DIOW# DDMARDY(device) IORDY# tss HSTROBE(host) DIOR# tdvs ID[15:0] (host) tdvh tiordyz tli tmli
tack
CRC
tack
IA[2:0], ICS[1:0]
Figure 13: Host Terminating an Ultra DMA data-out burst
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tli DMARQ(device) DMACK(host) trp STOP(host) DIOW# DDMARDY(device) IORDY# trfs HSTROBE(device) DIOR# tdvs ID[15:0] (host) tdvh tli tmli tiordyz
tack
CRC
tack
IA[2:0], ICS[1:0]
Figure 14: Device Terminating an Ultra DMA data-out burst
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CLK
1 2 3 4
PD[7:0] CTL[1:0] LReq
tlsu tlh
Figure 15: Phy to Link timings
CLK
1 2 3 4
PD[7:0] CTL[1:0] LReq
tld1 tld2 tld3
Figure 16: Link to Phy timings
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tws Address tdsb Data tdhb
tas
tcss tdsa tdha
CS# tah OE#
WE#
IOR#
tiorl
taddr1 Address dsb1 Data tas tcss CS# dsa1 dha1 dhb1
taddr2
dsb2
dhb2
dsa2
dha2
tah OE#
WE# tahr IOR# tiorl tiorh tasr tiorl
tws
tws
Figure 17: External Processor Bus timings
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8
PACKAGE INFORMATION
Figure 18: 128 TQFP package information
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9
ORDERING INFORMATION
OXFW900-TQ - A
Revision Package Type - 128 TQFP
Data Sheet Revision 1.0
Page 28
OXFORD www..com
SEMICONDUCTOR LTD.
OXFW900
NOTES
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Data Sheet Revision 1.0
Page 29
OXFORD www..com
SEMICONDUCTOR LTD.
OXFW900
CONTACT DETAILS
Oxford Semiconductor Ltd. 69 Milton Park Abingdon Oxfordshire OX14 4RX United Kingdom Telephone: Fax: Sales e-mail: 1394 Tech support e-mail: Web site: +44 (0)1235 824900 +44 (0)1235 821141 sales@oxsemi.com 1394_support@oxsemi.com http://www.oxsemi.com
DISCLAIMER
Oxford Semiconductor believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of Oxford Semiconductor Ltd. Oxford Semiconductor's terms and conditions of sale apply at all times. Data Sheet Revision 1.0 Page 30

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