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| a FEATURES Single 3 V Supply Operation (2.7 V to 3.6 V) SNR = 70 dBc to Nyquist at 65 MSPS SFDR = 85 dBc to Nyquist at 65 MSPS Low Power: 300 mW at 65 MSPS Differential Input with 500 MHz Bandwidth On-Chip Reference and SHA DNL = 0.4 LSB Flexible Analog Input: 1 V p-p to 2 V p-p Range Offset Binary or Twos Complement Data Format Clock Duty Cycle Stabilizer APPLICATIONS Ultrasound Equipment IF Sampling in Communications Receivers: IS-95, CDMA-One, IMT-2000 Battery-Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes VIN+ SHA VIN- REFT REFB 12-Bit, 20/40/65 MSPS 3 V A/D Converter AD9235 FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD MDAC1 4 A/D 8-STAGE 1 1/2-BIT PIPELINE 16 A/D 3 CORRECTION LOGIC 12 OUTPUT BUFFERS OTR D11 D0 CLOCK DUTY CYCLE STABLIZER REF SELECT AGND 0.5V CLK PDWN MODE DGND MODE SELECT AD9235 VREF SENSE PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters. This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead thin shrink small outline package (TSSOP) and a 32-lead chip scale package (LFCSP) and is specified over the industrial temperature range (-40C to +85C). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. 1. The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 4. The AD9235 pinout is similar to the AD9214-65, a 10-bit, 65 MSPS ADC. This allows a simplified upgrade path from 10 bits to 12 bits for 65 MSPS systems. 5. The clock DCS maintains overall ADC performance over a wide range of clock pulsewidths. 6. The OTR output bit indicates when the signal is beyond the selected input range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9235-SPECIFICATIONS DC SPECIFICATIONS 1.0 V internal reference, T Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL) 2 TEMPERATURE DRIFT Offset Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input4 Sine Wave Input2 Standby Power5 Temp Full Full Full Full Full 25C Full 25C Full Full Test Level VI VI VI VI IV I IV I V V (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input, MIN to TMAX, unless otherwise noted.) AD9235BRU-20 Min Typ Max 12 12 0.30 0.30 0.35 0.35 0.45 0.40 2 12 1.20 2.40 0.65 0.80 AD9235BRU-40 Min Typ Max 12 12 0.50 0.50 0.35 0.35 0.50 0.40 2 12 1.20 2.50 0.75 0.90 AD9235BRU/BCP-65 Min Typ Max Unit 12 12 0.50 0.50 0.40 0.35 0.70 0.45 3 12 1.20 2.60 0.80 1.30 Bits Bits % FSR % FSR LSB LSB LSB LSB ppm/C ppm/C Full Full Full Full 25C 25C Full Full Full Full VI V V V V V IV IV V V 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 mV mV mV mV LSB rms LSB rms V p-p V p-p pF k Full Full Full Full Full Full Full Full IV IV V V V V VI V 2.7 3.0 2.25 3.0 30 2 0.01 90 95 1.0 3.6 3.6 2.7 3.0 2.25 3.0 55 5 0.01 165 180 1.0 3.6 3.6 2.7 3.0 2.25 3.0 100 7 0.01 300 320 1.0 3.6 3.6 V V mA mA % FSR mW mW mW 110 205 350 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate, f IN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). Specifications subject to change without notice. -2- REV. B DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS* DRVDD = 3.3 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) DRVDD = 2.5 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) Temp Full Full Full Full Full Test Level IV IV IV IV V AD9235BRU-20 Min Typ Max 2.0 -10 -10 2 0.8 +10 +10 2.0 -10 -10 2 0.8 +10 +10 2.0 -10 -10 2 0.8 +10 +10 AD9235 AD9235BRU-40 AD9235BRU/BCP-65 Min Typ Max Min Typ Max Unit V V A A pF Full Full Full Full IV IV IV IV 3.29 3.25 0.2 0.05 3.29 3.25 0.2 0.05 3.29 3.25 0.2 0.05 V V V V Full Full Full Full IV IV IV IV 2.49 2.45 0.2 0.05 2.49 2.45 0.2 0.05 2.49 2.45 0.2 0.05 V V V V *Output voltage levels measured with 5 pF load on each output. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulsewidth High1 CLK Pulsewidth Low1 DATA OUTPUT PARAMETERS Output Delay2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty Jitter (t J) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME Temp Full Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V V V V V V V AD9235BRU-20 Min Typ Max 20 1 50.0 15.0 15.0 3.5 7 1.0 0.5 3.0 1 25.0 8.8 8.8 3.5 7 1.0 0.5 3.0 1 AD9235BRU-40 Min Typ Max 40 1 15.4 6.2 6.2 3.5 7 1.0 0.5 3.0 2 AD9235BRU/BCP-65 Min Typ Max Unit 65 1 MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles NOTES 1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB. Specifications subject to change without notice. N N-1 ANALOG INPUT tA N+1 N+2 N+3 N+4 N+5 N+7 N+6 N+8 CLK DATA OUT N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 2.0ns MIN N-1 N tPD = 6.0ns MAX Figure 1. Timing Diagram REV. B -3- AD9235-SPECIFICATIONS AC SPECIFICATIONS 1.0 V internal reference, T Parameter SIGNAL-TO-NOISE RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz TOTAL HARMONIC DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz WORST HARMONIC (Second or Third) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz SPURIOUS FREE DYNAMIC RANGE fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz Temp 25C Full 25C Full 25C Full 25C 25C Test Level V IV I IV I IV I V (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input, AIN = -0.5 dBFS, MIN to TMAX, unless otherwise noted.) AD9235BRU-20 Min Typ Max 70.8 70.4 70.6 69.9 AD9235BRU-40 AD9235BRU/BCP-65 Min Typ Max Min Typ Max Unit 70.6 70.5 dBc dBc dBc dBc dBc dBc dBc dBc 70.0 70.3 70.4 68.7 69.7 70.1 68.3 68.7 68.5 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V 69.9 70.6 70.3 70.5 69.7 70.5 70.4 70.2 70.3 68.3 69.5 69.9 67.8 68.6 68.3 dBc dBc dBc dBc dBc dBc dBc dBc 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V -88.0 -86.0 -87.4 -89.0 -79.0 -85.5 -86.0 -79.0 -87.5 -84.0 -82.5 -81.8 -82.0 -78.0 -74.0 dBc dBc dBc dBc dBc dBc dBc dBc Full Full Full IV IV IV -90.0 -80.0 -90.0 -80.0 -83.5 -74.0 dBc dBc dBc 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V 80.0 92.0 88.5 91.0 80.0 92.0 92.0 89.0 90.0 74.0 83.0 85.0 80.5 dBc dBc dBc dBc dBc dBc dBc 84.0 85.0 dBc Specifications subject to change without notice. -4- REV. B AD9235 ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, MODE VIN+, VIN- VREF SENSE REFB, REFT PDWN With Respect to Min AGND DGND DGND DRVDD DGND AGND AGND AGND AGND AGND AGND -0.3 -0.3 -0.3 -3.9 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 I Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150 Unit V V V V V V V V V V V C C C C 100% production tested. II 100% production tested at 25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature -65 NOTES 1 Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (28-lead TSSOP), JA = 67.7C/W; (32-lead LFCSP), JA = 32.5C/W, JC = 32.71C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1. ORDERING GUIDE Model AD9235BRU-20 AD9235BRU-40 AD9235BRU-65 AD9235BCP-20* AD9235BCP-40* AD9235BCP-65* AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB Temperature Range Package Description -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory) 32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory) 32-Lead Lead Frame Chip Scale Package (LFCSP) TSSOP Evaluation Board TSSOP Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board (Contact Factory) LFCSP Evaluation Board (Contact Factory) LFCSP Evaluation Board Package Option RU-28 RU-28 RU-28 CP-32 CP-32 CP-32 *It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9235 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B -5- AD9235 PIN CONFIGURATION 28-Lead TSSOP OTR 1 MODE 2 SENSE 3 VREF 4 REFB 5 28 D11 (MSB) 27 D10 26 D9 25 D8 DNC 1 CLK 2 DNC 3 PDWN 4 DNC 5 DNC 6 (LSB)D0 7 D1 8 32-Lead LFCSP 32 AVDD 31 AGND 30 VIN- 29 VIN+ 28 AGND 27 AVDD 26 REFT 25 REFB REFT 6 TOP VIEW 23 DGND AVDD 7 (Not to Scale) 22 D7 AGND 8 VIN+ 9 VIN- 10 AGND 11 AVDD 12 CLK 13 PDWN 14 21 D6 20 D5 19 D4 18 D3 17 D2 16 D1 15 D0 (LSB) AD9235 24 DRVDD PIN 1 INDICATOR AD9235 TOP VIEW (Not to Scale) 24 VREF 23 SENSE 22 MODE 21 OTR 20 D11(MSB) 19 D10 18 D9 17 D8 PIN FUNCTION DESCRIPTIONS Pin Number 28-Lead TSSOP 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14 15-22, 25-28 23 24 32-Lead LFCSP 21 22 23 24 25 26 27, 32 28, 31 29 30 2 4 7-14, 17-20 15 16 1, 3, 5, 6 Mnemonic Description OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- CLK PDWN D0 (LSB)-D11(MSB) DGND DRVDD DNC Out-of-Range Indicator. Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. Reference Mode Selection. Voltage Reference Input/Output. Differential Reference (-). Differential Reference (+). Analog Power Supply. Analog Ground. Analog Input Pin (+). Analog Input Pin (-). Clock Input Pin. Power-Down Function Selection (Active High). Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 F capacitor. Recommended decoupling is 0.1 F in parallel with 10 F. Do Not Connect. -6- D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 DGND 15 DRVDD 16 REV. B AD9235 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) Signal-to-Noise and Distortion (SINAD)* The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Jitter (tJ) The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula N = (SINAD - 1.76) 6.02 Signal-to-Noise Ratio (SNR)* The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious Free Dynamic Range (SFDR)* The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Two-Tone SFDR* An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulsewidth and Duty Cycle The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Gain Error Pulsewidth high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulsewidth low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The delay between the clock logic threshold and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD)* The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. *AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). REV. B -7- AD9235 Equivalent Circuits DRVDD AVDD D11-D0, OTR VIN+, VIN- Figure 2. Equivalent Analog Input Circuit AVDD Figure 4. Equivalent Digital Output Circuit AVDD MODE 20k CLK, PDWN Figure 3. Equivalent MODE Input Circuit Figure 5. Equivalent Digital Input Circuit -8- REV. B Typical Performance Characteristics AD9235 (AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS Disabled, TA = 25 C, 2 V Differential Input, AIN = -0.5 dBFS, VREF = 1.0 V, unless otherwise noted.) 0 SNR = 70.3dBc SINAD = 70.2dBc ENOB = 11.4 BITS THD = -86.3dBc SFDR = 89.9dBc 100 95 90 85 SFDR (2V DIFF) -20 MAGNITUDE (dBFS) SNR/SFDR (dBc) -40 80 75 SNR (2V SE) -60 70 65 60 55 SFDR (2V SE) 45 50 55 -80 SNR (2V DIFF) -100 -120 0.0 6.5 13.0 19.5 FREQUENCY (MHz) 26.0 32.5 50 40 60 65 SAMPLE RATE (MSPS) TPC 1. Single Tone 8K FFT with fIN = 10 MHz TPC 4. AD9235-65: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (32.5 MHz) 100 0 -20 SNR = 69.4dBc SINAD = 69.1dBc ENOB = 11.2 BITS THD = -81.0dBc SFDR = 83.8dBc 95 90 85 MAGNITUDE (dBFS) SNR/SFDR (dBc) -40 SFDR (2V DIFF) 80 SNR (2V SE) 75 SNR (2V DIFF) -60 70 65 60 SFDR (2V SE) -80 -100 55 -120 65.0 71.5 78.0 84.5 FREQUENCY (MHz) 91.0 50 20 25 30 SAMPLE RATE (MSPS) 35 40 TPC 2. Single Tone 8K FFT with fIN = 70 MHz TPC 5. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz) 0 -20 SNR = 68.5dBc SINAD = 66.5dBc ENOB = 10.8 BITS THD = -71.0dBc SFDR = 71.2dBc 100 95 90 85 SFDR (2V DIFF) MAGNITUDE (dBFS) SNR/SFD (dBc) -40 SFDR (2V SE) 80 75 70 65 -60 SNR (2V SE) -80 SNR (2V DIFF) -100 60 55 -120 97.5 50 104.0 110.5 117.0 FREQUENCY (MHz) 123.5 130.0 0 5 10 15 SAMPLE RATE (MSPS) 20 TPC 3. Single Tone 8K FFT with fIN = 100 MHz TPC 6. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz) REV. B -9- AD9235 95 100 SFDR SINGLE-ENDED (dBFS) SFDR DIFFERENTIAL (dBc) SFDR DIFFERENTIAL (dBFS) 90 SFDR 90 SNR/SFDR (dBFS and dBc) 80 SNR/SFDR (dBc) SNR DIFFERENTIAL (dBFS) 85 70 SNR SINGLE-ENDED (dBFS) 80 75 SNR 70 60 SFDR SINGLE-ENDED (dBc) SNR SINGLE-ENDED (dBc) 50 SNR DIFFERENTIAL (dBc) 65 40 -30 -25 -20 -15 A IN (dBFS) -10 -5 20 0 25 50 75 100 125 Input Frequency (MHz) TPC 7. AD9235-65: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (32.5 MHz) 95 SFDR DIFFERENTIAL (dBFS) TPC 10. AD9235-65: SNR/SFDR vs. fIN 100 90 90 SFDR DIFFERENTIAL SNR DIFFERENTIAL (dBc) (dBFS) SFDR SINGLE-ENDED (dBFS) SFDR SNR/SFDR (dBFS and dBc) 80 SNR/SFDR (dBc) 85 70 SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL (dBc) SFDR SINGLE-ENDED (dBc) 80 75 SNR 70 50 SNR SINGLE-ENDED (dBc) 40 -30 -25 -20 -15 AIN (dBFS) -10 -5 0 65 0 25 50 75 100 125 Input Frequency (MHz) TPC 8. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz) 100 SFDR DIFFERENTIAL (dBFS) 90 SFDR DIFFERENTIAL (dBc) TPC 11. AD9235-40: SNR/SFDR vs. fIN 95 90 SFDR SNR/SFDR (dBFS and dBc) SFDR SINGLE-ENDED (dBFS) 80 SNR DIFFERENTIAL (dBFS) SNR/SFDR (dBc) SFDR SINGLE-ENDED (dBc) 85 70 SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL (dBc) SNR SINGLE-ENDED (dBc) 40 -30 -25 -20 -15 -10 AIN (dBFS) -5 0 80 75 SNR 70 50 65 0 25 50 75 100 125 Input Frequency (MHz) TPC 9. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz) TPC 12. AD9235-20: SNR/SFDR vs. fIN -10- REV. B AD9235 0 SNR = 64.6dBFS SFDR = 81.6dBFS -20 95 90 2V SFDR MAGNITUDE (dBFS) 85 1V SFDR -40 SNR/SFDR (dBFS) 80 75 2V SNR 1V SNR -60 -80 70 -100 65 60 -24 -120 32.5 39.0 45.5 52.0 FREQUENCY (MHz) 58.5 65.0 -21 -18 -15 AIN (dBFS) -12 -9 -6 TPC 13. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz TPC 16. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz 0 SNR = 64.3dBFS SFDR = 81.1dBFS -20 95 2V SFDR 90 1V SFDR MAGNITUDE (dBFS) 85 -40 SNR/SFDR (dBFS) 80 75 2V SNR 1V SNR -60 -80 70 -100 65 60 -24 -120 65.0 71.5 78.0 84.5 FREQUENCY (MHz) 91.0 97.5 -21 -18 -15 AIN (dBFS) -12 -9 -6 TPC 14. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz TPC 17. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz 0 SNR = 62.5dBFS SFDR = 75.6dBFS -20 95 90 2V SFDR 1V SFDR MAGNITUDE (dBFS) 85 SNR/SFDR (dBFS) -40 80 75 2V SNR 1V SNR -60 -80 70 -100 65 60 -24 -120 130.0 136.5 143.0 149.5 FREQUENCY (MHz) 156.0 162.5 -21 -18 -15 AIN (dBFS) -12 -9 -6 TPC 15. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz TPC 18. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz REV. B -11- AD9235 75 12.2 20 15 72 AD9235-20: 2V SINAD AD9235-40: 2V SINAD AD9235-65: 2V SINAD 11.7 10 GAIN DRIFT (ppm / C) ENOB - BITS SINAD (dBc) 69 AD9235-20: 1V SINAD AD9235-40: 1V SINAD 66 AD9235-65: 1V SINAD 63 11.2 5 0 -5 10.7 -10 10.2 -15 60 9.7 0 10 20 30 40 SAMPLE RATE (MSPS) 50 60 -20 -40 -20 0 20 40 TEMPERATURE ( C) 60 80 TPC 19. SINAD vs. fCLK with fIN = Nyquist TPC 22. A/D Gain vs. Temperature Using an External Reference 1.0 90 SFDR: DCS ON 0.8 80 SFDR: DCS OFF SINAD/SFDR (dBc) 0.6 0.4 0.2 SINAD: DCS ON 70 INL (LSB) 60 SINAD: DCS OFF 0.0 -0.2 -0.4 -0.6 50 40 -0.8 30 35 40 45 50 55 DUTY CYCLE (%) 60 65 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 TPC 20. SINAD/SFDR vs. Clock Duty Cycle TPC 23. Typical INL 90 85 80 SFDR 2V DIFF 1.0 0.8 0.6 SINAD/SFDR (dBc) SFDR 1V DIFF 75 70 65 60 55 50 -40 -30 -20 -10 SINAD 1V DIFF SINAD 2V DIFF 0.4 DNL (LSB) 60 70 80 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 10 20 30 40 50 SAMPLE RATE (MSPS) -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 TPC 21. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz TPC 24. Typical DNL -12- REV. B AD9235 APPLYING THE AD9235 THEORY OF OPERATION H The AD9235 architecture consists of a front-end sample and hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. ANALOG INPUT T 5pF VIN+ CPAR T T 5pF VIN- CPAR T H Figure 6. Switched-Capacitor SHA Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as follows: REFT = 1 2 ( AVDD + VREF ) REFB = 1 2 ( AVDD - VREF ) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. 90 THD 2.5MHz 2V DIFF 85 80 THD 35MHz 2V DIFF THD - dBc SNR (dBc) The analog input to the AD9235 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 7. An input common-mode voltage of midsupply will minimize signal-dependant errors and provide optimum performance. Referring to Figure 6, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network will create a low-pass filter at the ADC's input; therefore, the precise values are dependant upon the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors will be reduced by the common-mode rejection of the ADC. -90 -85 -80 -75 -70 SNR 35MHz 2V DIFF -65 -60 -55 -50 3.0 75 70 65 60 55 50 0.0 SNR 2.5MHz 2V DIFF 0.5 1.0 1.5 2.0 COMMON-MODE LEVEL (V) 2.5 Figure 7. AD9235-65: SNR, THD vs. Common-Mode Level The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance will be achieved with the AD9235 set to the largest input span of 2 V p-p. The relative SNR degradation will be 3 dB when changing from 2 V p-p mode to 1 V p-p mode. REV. B -13- AD9235 The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as follows: The signal characteristics must be considered when selecting a transformer. Most RF transformers will saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration VCM MIN = VREF / 2 VCM MAX = ( AVDD + VREF )/ 2 The minimum common-mode input level allows the AD9235 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN-. In this configuration, one input will accept the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN-. The AD9235 will then accept an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect will be less noticeable at lower input frequencies and in the lower speed grade models (AD9235-40 and AD9235-20). Differential Input Configurations A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there will be a degradation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 10 details a typical single-ended input configuration. AVDD VIN+ 2Vp-p 49.9 0.33 F 1k 1k + 10 F 0.1 F 1k 15pF 15pF 22 VIN- AGND 1k 22 AD9235 Figure 10. Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS As previously detailed, optimum performance will be achieved while driving the AD9235 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal. 1Vp-p 49.9 499 22 499 15pF 22 523 AVDD VIN+ Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9235. As shown in TPC 20, noise and distortion performance are nearly flat over a 30% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency will require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated with the following equation. SNR Degradation = 20 x log 10 [1 2 x x f INPUT x t J ] In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9235. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 1k 0.1 F 1k AD8138 AD9235 VIN- 499 15pF AGND Figure 8. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers will not be adequate to achieve the true performance of the AD9235. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 9. AVDD 22 VIN+ 2V p-p 49.9 15pF 22 VIN- 15pF 1k 0.1 F 1k AGND AD9235 Figure 9. Differential Transformer-Coupled Configuration -14- REV. B AD9235 POWER DISSIPATION AND STANDBY MODE As shown in Figure 11, the power dissipated by the AD9235 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as I DRVDD = VDRVDD x CLOAD x fCLK x N where N is the number of output bits, 12 in the case of the AD9235. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current will be established by the average number of output bits switching, which will be determined by the encode rate and the characteristics of the analog input signal. 325 Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode, and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode and shorter standby cycles will result in proportionally shorter wake-up times. With the recommended 0.1 F and 10 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation. DIGITAL OUTPUTS 300 AD9235-65 275 TOTAL POWER (mW) The AD9235 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. As detailed in Table II, the data format can be selected for either offset binary or twos complement. Timing 250 225 200 175 150 125 100 75 50 0.0 10 20 30 40 SAMPLE RATE (MSPS) 50 60 AD9235-40 The AD9235 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 1 for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9235; these transients can detract from the converter's dynamic performance. The lowest typical conversion rate of the AD9235 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. VOLTAGE REFERENCE AD9235-20 Figure 11. Total Power vs. Sample Rate with fIN = 10 MHz For the AD9235-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 11 was taken with a 5 pF load on each output driver. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. By asserting the PDWN pin high, the AD9235 is placed in standby mode. In this state, the ADC will typically dissipate 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9235 into its normal operational mode. A stable and accurate 0.5 V voltage reference is built into the AD9235. The input range can be adjusted by varying the reference voltage applied to the AD9235, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (commonmode voltage). Internal Reference Connection A comparator within the AD9235 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table I. If SENSE is grounded, Table I. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Internal Switch Position N/A SENSE SENSE Internal Divider Resulting VREF (V) N/A 0.5 0.5 x (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF (See Figure 13) 2.0 REV. B -15- AD9235 reference amplifier switch is connected to the internal resistor divider (see Figure 12), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 13, the switch will again be set to the SENSE pin. This will put the reference amplifier in a noninverting mode with the VREF output defined as follows. VREF = 0.5 x (1 + R 2 R 1) VIN+ VIN- REFT 0.1 F ADC CORE 10 F 0.1 F REFB 0.1 F VREF 10 F 0.1 F SELECT LOGIC SENSE 0.5V External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 14 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. 1.2 1.0 VREF = 1.0V VREF ERROR (%) 0.8 VREF = 0.5V 0.6 0.4 0.2 0.0 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE ( C) 60 70 80 AD9235 Figure 14. Typical VREF Drift Figure 12. Internal Reference Configuration In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ VIN- REFT 0.1 F ADC CORE 10 F 0.1 F REFB 0.1 F VREF 10 F 0.1 F R2 SENSE R1 SELECT LOGIC 0.5V When the SENSE pin is tied to AVDD, the internal reference will be disabled, allowing the use of an external reference. An internal reference buffer will load the external reference with an equivalent 7 k load. The internal buffer will still generate the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span will always be twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9235 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 15 depicts how the internal reference voltage is affected by loading. 0.05 0.00 -0.05 ERROR (%) 0.5V ERROR (%) -0.10 1V ERROR (%) -0.15 AD9235 -0.20 Figure 13. Programmable Reference Configuration -0.25 0.0 0.5 1.0 1.5 LOAD (mA) 2.0 2.5 3.0 Figure 15. VREF Accuracy vs. Load -16- REV. B AD9235 OPERATIONAL MODE SELECTION As discussed earlier, the AD9235 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (DCS). The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined below. Table II. Mode Selection MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance (i.e., IF undersampling characterization). It allows the user to apply a clock input signal that is 4x the target sample rate of the AD9235. A low-jitter, differential divide-by-4 counter, the MC100LVEL33D, provides a 1x clock output that is subsequently returned back to the CLK input via JP9. For example, a 260 MHz signal (sinusoid) will be divided down to a 65 MHz signal for clocking the ADC. Note that R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4x that of a 1x signal of equal amplitude. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. LFCSP EVALUATION BOARD The MODE pin is internally pulled down to AGND by a 20 k resistor. TSSOP EVALUATION BOARD The AD9235 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an AD8138 driver or a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 16 shows the typical bench characterization setup used to evaluate the ac performance of the AD9235. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. The typical bench setup used to evaluate the ac performance of the AD9235 is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The AD9235 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9235 allows the user to optimize the frequency response of the op amp for the application. 3V - + - 3V + - 3V + - 3V + REFIN HP8644, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER AVDD GND DUT GND DUT S4 AVDD DRVDD XFMR INPUT AD9235 TSSOP EVALUATION BOARD S1 CLOCK DVDD DATA CAPTURE AND PROCESSING J1 10MHz HP8644, 2V p-p REFOUT CLOCK SYNTHESIZER CLOCK DIVIDER Figure 16. TSSOP Evaluation Board Connections REV. B -17- AD9235 D0O D1O D10O D11O WHT TP5 JP23 DUTAVDD OTR R3 10k DUTAVDD JP24 C36 0.1 F C22 10 F 10V C57 0.1 F JP25 C39 0.001 F JP22 1 RP6 22 2 RP6 22 3 RP6 22 8 7 6 5 OTRO L1 1 JP12 TP2 RED 4 RP6 22 4 RP5 22 5 7 6 8 D2O 1 RP3 22 2 RP3 22 3 RP3 22 D8O D9O D9 D10 D11 8 7 6 1 RP5 22 2 RP5 22 3 RP5 22 D8 D3O 4 RP3 22 5 D0 D1 D2 D3 8 1 RP4 22 2 RP4 22 3 RP4 22 7 6 D4 D5 D6 D4O D5O D6O D7O 4 RP4 22 5 D7 DUTAVDDIN TB1 2 R4 10k C21 10 F 10V C35 0.1 F WHT TP17 7 FBEAD 2 C58 22 F 25V C59 0.1 F AGND TB1 3 TP1 RED AVDD JP13 AVDD C52 0.1 F R27 5k C20 10 F 10V C32 0.1 F JP7 JP6 JP1 JP2 R20 1k C33 0.1 F SHEET 3 C50 0.1 F VIN+ VIN- AVDD C34 0.1 F AD9235 AVDD AGND SENSE 8 3 4 14 5 6 2 9 10 VREF PDWN REFB OTRO AVDDIN TB1 1 FBEAD 2 L2 1 D0O D1O D2O D3O D4O D5O D6O REFT MODE U1 VIN+ VIN- AGND AVDD DGND DRVDD 11 12 23 24 D4 20 D3 19 D2 D1 D0 CLK D7O D8O D9O Figure 17. TSSOP Evaluation Board Schematic, DUT -18- L3 1 JP11 D UTDRVDD C53 0.1 F DUTAVDD R17 1k TP3 RED L4 1 C23 10 F 10V C38 0.1 F R42 1k TP4 RED DVDD TP10 TP15 TP16 TP9 BLK BLK BLK BLK TP11 TP12 TP13 TP14 BLK BLK BLK BLK C14 0.1 F C47 22 F 25V OTR D11 1 28 D10 D9 27 26 D8 25 D7 22 D6 D5 21 DRVDDIN TB1 5 FBEAD 2 C48 22 F 25V 18 17 16 15 13 D10O D11O DUTCLK WHT TP6 DUTDRVDD C37 0.1 F C41 0.001 F C1 10 F 10V C40 0.001 F AGND TB1 4 DVDDIN TB1 6 FBEAD 2 C6 22 F 25V REV. B 1N5712 G1 G2 20 VCC GND 10 JP9 U7 74VHC541 HDR40RAM J1 R19 500 R18 500 AVDD AVDD; 14 AVDD; 7 U8 2 74VHC04 JP4 U8 4 JP3 74VHC04 5 6 R9 22 R7 22 DUTCLK OTR TP7 U8 1 C13 0.1 F WHT CW R2 10 CLOCK S1 D8 D9 D10 D11 1 2 R1 49.9 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 3 74VHC04 U8 12 74VHC04 U8 10 U8 9 Figure 18. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering 13 AVDD 11 C10 0.1 F 8 74VHC04 U8 DECOUPLING C3 10 F 10V HEADER RIGHT ANGLE MALE NO EJECTORS 1 RP2 22 16 DD0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 2 RP2 22 3 RP2 22 4 RP2 22 5 RP2 22 6 RP2 22 7 RP2 22 8 RP2 22 RP2 22 RP2 22 18 17 16 15 14 13 12 11 REV. B R25 10k AVDD C12 0.1 F DVDD 6 T1-1T 1 AUXCLK S5 1 1N5712 2 5 4 T2 2 1 19 G1 G2 U6 74VHC541 R26 10k D0 D1 D2 D3 D4 D5 D6 D7 C11 0.1 F VCC 20 GND 10 1 2 3 R11 49.9 D2 D1 C4 10 F 10V AVDD AVDD AVDD AVDD C28 10 F 10V MC100LVEL33D 8 VCC NC 7 OUT INA U3 6 REF INB 5 VEE INCOM 1 2 3 4 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 1 3 5 7 9 11 2 4 6 8 10 12 14 R12 113 R13 113 C24 0.1 F U3 DECOUPLING C27 0.1 F DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 1 2 3 4 5 6 7 RP2 RP2 RP2 RP2 22 22 22 22 RP2 22 8 RP2 22 -19- R15 90 1 19 C26 0.1 F 2 C5 10 F 10V 1 DOTR DACLK R14 90 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 13 15 17 19 21 23 25 27 29 31 33 35 37 39 16 18 20 22 24 26 28 30 32 34 36 38 40 AD9235 AD9235 JP5 R23 1k SINGLE INPUT 1 S3 2 C9 0.33 F R5 49.9 AVDD JP40 R41 1k JP42 C44 15pF AVDD C7 0.1 F AVDD 2 R32 1k C15 10 F 10V 1 JP45 R21 22 VIN + 0.1 F C69 C44B C2 VAL R33 1k C8 0.1 F JP46 JP41 R22 22 VIN- R37 499 3 R6 40 C42 VAL Figure 19. TSSOP Evaluation Board Schematic, Analog Inputs JP43 -20- -IN 1 VCC 4 2 U2 VO+VOC VOVEE 8 +IN 5 R34 523 C43 15pF AMP INPUT R10 40 6 S2 1 R35 499 2 R31 49.9 C45 VAL R36 499 VAL C17 AD8138 C18 0.1 F AVDD C19 10 F 10V 1 ALT VEE TP8 RED R24 49.9 XFMR INPUT 1 S4 2 R16 1k 6 T1-1T 1 5 4 T2 2 3 R8 1k C25 0.33 F 2 2 AB 1 3 JP8 C16 0.1 F REV. B AD9235 DACLK DVDD C30 0.1 F C31 0.01 F C29 0.1 F C46 0.01 F TP18 WHT S6 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MSB-DB11 CLOCK DB10 DVDD DB19 DCOM DB8 AD9762 NC3 DB7 AVDD DB6 COMP2 DB5 IOUTA U4 DB4 IOUTB DB3 ACOM DB2 COMP1 DB1 FSADJ DB0 REFIO NC1 REFLO NC2 SLEEP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C56 0.1 F R29 49.9 C51 R30 2k C49 0.1 F 0.1 F C55 22pF R28 49.9 C54 22pF Figure 20. TSSOP Evaluation Board Schematic, Optional D/A Converter Figure 21. TSSOP Evaluation Board Layout, Primary Side REV. B -21- AD9235 Figure 22. TSSOP Evaluation Board Layout, Secondary Side Figure 23. TSSOP Evaluation Board Layout, Ground Plane -22- REV. B AD9235 _ Figure 24. TSSOP Evaluation Board Power Plane Figure 25. TSSOP Evaluation Board Layout, Primary Silkscreen REV. B -23- AD9235 Figure 26. TSSOP Evaluation Board Layout, Secondary Silkscreen -24- REV. B GND H1 MTHOLE6 H2 MTHOLE6 1 2 6 3 4 5 H3 MTHOLE6 H4 MTHOLE6 EXTREF 1V MAX E1 AVDD P6 R5 1k C13 0.10 F 2 C22 10 F 1 R1 10k AVDD GND P11 P9 P8 AVDD 3.0V 2.5V DRVDD 2.5V R9 10k R6 1k C9 0.10 F 4 C29 10 F 0.1 F C11 (MSB) GND P4 GND OVERRANGE BIT C8 0.1 F 0.1 F C12 P3 3 GND GND 5.0V RP2 220 1 2 3 16 15 14 4 5 6 7 8 13 12 11 10 9 p10 R7 1k GND VAMP GND GND GND GND E VDL P7 A B P1 C D MODE 2 P5 P2 24 23 22 C7 0.1 F 21 GND R42 0 AVDD AMPIN R12 0 XOUT C21 10pF GND AVDD GND GND 31 AGND 32 AVDD R4 33 VIN- AVDD GND VIN+ 28 AGND 29 VIN+ 30 VINR36 1k R26 1k U4 GND 25 REFB 26 REFT 27 AVDD D11 20 D10 19 D9 18 D8 17 VREF SENSE MODE OTR 1 DNC 2 CLK 3 DNC 4 PDWN GND GND GND C23 10pF R15 33 XOUTB R3 0 AMPINB R11 36 C5 0.1 F 5 DNC 6 DNC 7 D0 8 D1 REV. B DRX D13X D12X D11X D10X D9X D8X D7X 16 15 14 13 D5 12 D4 11 D3 10 D2 9 (LSB) DRVDD GND DRVDD DGND D7 D6 C6 0.1 F Figure 27. LFCSP Evaluation Board Schematic, Analog Inputs and DUT AD9235 R10 36 E 45 C26 10pF GND R2 XX C16 0.1 F C19 15pF OR L1 FOR FILTER CLK R8 1k P14 AVDD AVDD GND R13 1k R25 1k P13 GND E TO A E TO B E TO C E TO D R18 25 GND C18 0.1 F R SINGLE ENDED 5 5 5 5 TO TO TO TO 1 2 3 4 -25- 1 2 3 4 5 6 7 8 RP1 220 16 15 14 13 12 11 10 9 D6X D5X D4X D3X D2X D1X D0X J1 L1 10nH T1 AD T 1-1 WT C15 AMP 0.1 F XFRIN1 1 5 NC 3 GND 6 2 CT 4 PRI SEC OPTIONAL XFR T2 FT C1-1-13 5 1 XOUT X FRIN 2 CT 3 4 GND XOUTB SENSE PIN SOLDERABLE JUMPER PRI SEC EXTERNAL VOLTAGE DIVIDER INTERNAL 1V REFERENCE (DEFAULT) EXTERNAL REFERENCE INTERNAL 0.5V REFERENCE AD9235 R3, R17, R18 ONLY ONE SHOULD BE ON BOARD AT A TIME MODE PIN SOLDERABLE JUMPER TWOS COMPLEMENT/DCS OFF TWOS COMPLEMENT/DCS OFF OFFSET BINARY/DCS ON OFFSET BINARY/DCS OFF 74LVTH162374 U1 25 2QB DRY GND 2 4 6 8 10 11 11 9 9 7 7 3 5 3 5 1 GND MSB GND 8 10 12 DRVDD DR 4 6 2 1 24 2CLK 2OE GND HEADER 40 AD9235 CLKAT/DAC MSB DRX D13X GND D12X D11X DRVDD D10X D9X GND GND D8X D7X D6X GND D5X GND D4X D3X CC CC 2DB 26 2D7 27 GND 28 2D6 29 2D5 30 V 31 CC 2D4 32 2D3 33 GND 34 2D2 35 2D1 36 1D8 37 1D7 38 GND 39 1D6 40 1D5 41 V 23 2Q7 22 GND 21 2Q6 20 2Q5 19 VCC 18 2Q4 17 2Q3 16 GND 15 2Q2 14 2Q1 13 1Q8 12 1Q7 11 GND 10 1Q6 9 1Q5 8 V DRVDD DRY GND 1Q4 7 6 DRVDD D2X D1X LSB 1 OUT R38 1k R39 1k GND VAMP C24 10 F POWER DOWN USE R40 OR R41 GND C44 0.1 F VAMP GND VAMP GND GND D0X 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 36 36 38 38 40 40 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 35 35 37 37 39 39 GND GND CLKLAT/DAC IN 42 1D4 43 1D3 44 GND 45 1D2 46 1D1 47 1CLK 48 1Q3 5 GND 4 1Q2 3 1Q1 2 1OE 1 Figure 28. LFCSP Evaluation Board Schematic, Digital Path -26- GND GND C45 0.1 F R41 10k R40 10k U3 AD8351 10 VOCM 9 VPOS 8 OPH1 7 OPLO 6 COMM R34 1.2k AMP IN INHI 3 INLO 4 C35 0.10 F R35 25 R33 RPG2 5 25 AMP C28 0.1 F PWDN 1 RGP1 2 R14 25 AMPINB R16 0 C27 0.1 F R19 50 GND R17 0 C17 0.1 F AMPIN GND GND REV. B VDL DRVDD VDL C2 22 F C49 0.001 F C20 10 F GND DIGITAL BYPASSING LATCH BYPASSING C37 0.1 F GND ANALOG BYPASSING C30 0.001 F C31 0.1 F C34 0.1 F C36 0.1 F C38 0.001 F C47 0.1 F C39 C1 0.001 F 0.1 F C48 0.001 F C32 0.001 F C33 C14 0.1 F 0.001 F C41 0.1 F DRVDD AVDD REV. B C40 0.001 F VAMP C46 10 F GND R28 0 ENC 74VCX86 ENCX 3 6 7 GND GND AVDD C10 22 F C4 10 F C3 10 F C25 10 F GND GND DUT BYPASSING CLOCK TIMING ADJUSTMENTS FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 CLK ENCX ENC E50 1 1A 2 1B 4 2A 1Y 2Y 3Y 14 4Y U5 R31 1k GND E31 R21 1k VDL E43 E44 GND E35 VDL R20 1k PWR R27 0 R32 1k R23 0 CLKAT/DAC VDL E51 SCHEMATIC SHOWS TWO GATE DELAY SETUP FOR ONE DELAY REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0 ) 2B 8 11 R37 25 Rx DNP DR Figure 29. LFCSP Evaluation Board Schematic, Clock Input VDL GND 5 9 10 12 13 -27- 3A 3B 4A 4B E52 E53 R30 1k R24 1k VDL GND VDL R22 0 ENCODE C43 0.1 F J2 R29 50 GND GND GND AD9235 AD9235 Figure 30. LFCSP Evaluation Board Layout, Primary Side Figure 32. LFCSP Evaluation Board Layout, Ground Plane Figure 31. LFCSP Evaluation Board Layout, Secondary Side Figure 33. LFCSP Evaluation Board Layout, Power Plane -28- REV. B AD9235 Figure 34. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 35. LFCSP Evaluation Board Layout, Secondary Silkscreen REV. B -29- AD9235 Table III. LFCSP Evaluation Board Bill of Materials Item Qty. Omit1 Reference Designator Device Package Value 0.1 F Recommended Vendor/Part Number Supplied by ADI 1 18 8 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 C6, C18, C27, C17, C28, C35, C45, C44 C2, C3, C4, C10, C20, C22, C25, C29 C46, C24 C14, C30, C32, C38, C39, C40, C48, C49 C19, C21, C23 C26 E31, E35, E43, E44, E50, E51, E52, E53 E1, E45 J1, J2 Chip Capacitor 0603 2 8 2 Tantalum Capacitor TAJD 10 F 3 8 Chip Capacitor 0603 0.001 F 10 pF 10 pF Jumper Blocks 4 5 6 3 1 9 2 Chip Capacitor Chip Capacitor Header 0603 0603 EHOLE 7 8 2 1 SMA Connector/50 Inductor SMA 0603 10 nH Coilcraft/0603CS10NXGBU Wieland/25.602.2653.0, z5-530-0625-0 Digi-Key S2131-20-ND 0 L1 9 1 P2 Terminal Block TB6 10 1 P12 Header Dual 20-Pin RT Angle Chip Resistor HEADER40 11 5 6 R3, R12, R23, R28, RX R37, R22, R42, R16, R17, R27 R4, R15 R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 R19 RP1, RP2 0603 12 13 2 14 Chip Resistor Chip Resistor 0603 0603 33 1 k 14 15 2 1 1 Chip Resistor Chip Resistor 0603 0603 36 50 220 Digi-Key CTS/742C163220JTR Mini-Circuits 16 2 Resistor Pack R_742 17 18 1 1 T1 U1 ADT1-1WT 74LVTH162374 CMOS Register AD9235BCP ADC (DUT) 74VCX86M AD92XXBCP/PCB AD8351 Op Amp MACOM Transformer Chip Resistor Chip Resistor AWT1-1T TSSOP-48 19 20 21 22 23 24 25 1 1 1 1 1 5 3 U4 U5 PCB U3 T2 R9, R1, R2, R38, R39 R18, R14, R35 CSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 1-1 TX SELECT 25 Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. MACOM/ETC1-1-13 X X X -30- REV. B AD9235 Table III. LFCSP Evaluation Board Bill of Materials (continued) Item Qty. Omit1 Reference Designator Device Package Value Recommended Vendor/Part Number Supplied by ADI 26 27 28 Total 1 2 1 1 82 34 R40, R41 R34 R33 Chip Resistor Chip Resistor Chip Resistor 0603 10 k 1.2 k 100 These items are included in the PCB design but are omitted at assembly. OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 14 6.40 BSC PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX COPLANARITY 0.10 SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC BOTTOM VIEW 3.25 3.10 SQ 2.95 8 0.50 0.40 0.30 17 16 9 12 MAX 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM 3.50 REF 1.00 0.90 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 REV. B -31- AD9235 Revision History Location 5/03--Data Sheet changed from REV. A to REV. B. Page Added CP-32 Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Replaced Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 New DEFINITIONS OF SPECIFICATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to TPCs 1-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to THEORY OF OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to ANALOG INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to Single-ended Input Configuration section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Replaced Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to CLOCK INPUT CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to POWER DISSIPATION AND STANDBY MODE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to DIGITAL OUTPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to Timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Changes to Figures 16-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Added LFCSP Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Inserted Figures 27-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Added Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8/02--Data Sheet changed from REV. 0 to REV. A. C02461-0-5/03(B) Changes to Several Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL Updated RU-28 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 -32- REV. B |
Price & Availability of AD9235BRU-20
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