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| 512K x 8 SRAM MODULE SYS8512RKX-70/85/10/12 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Issue 1.0 : March 1999 Features * Access Times of 70/85/100/120 ns. * 36 Pin Single-In-Line package (SIL) . * 5 Volt Supply 10%. * Low Power Operation 80mW (typical). Low Power Standby 0.4mW (typical). -L Version 0.04mW (typical). * Completely Static Operation. * Equal Access and Cycle Times. * All Inputs and Outputs Directly TTL compatible * On-board Supply Decoupling Capacitors. * Battery back-up capability. Description The SYS8512RKX is plastic 4M Static RAM Module housed in a standard 36 pin Single-In-Line package, organised as 512K x 8. The module utilises four 128K x 8 SRAMs housed in TSOP packages, and is pin compatible with SYS81000RKXB and SYS82000RKX. The module has Chip Select, Write Enable and Output Enable control inputs; the Output Enable pin allows faster access times than address access during a Read Cycle. Block Diagram AO - A18 16 D0 - D7 WE Pin Definition NC Vcc WE D2 D3 D0 A1 A2 A3 A4 GND D5 A10 A11 A5 A13 A14 NC CS A15 A16 A12 A18 A6 D1 GND A0 A7 A8 A9 D7 D4 D6 A17 Vcc OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OE 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS DECODER A17 CS A18 Pin Functions Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground A0 - A18 D0 - D7 CS WE OE NC VCC GND Package Details Plastic 36 Pin Single-In-Line (SIL) SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature Notes : Symbol VT PT TSTG min -0.5 -55 typ 1 - max +7 +150 unit V W o C (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Vt can be -3.5V pulse of less than 20ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol V CC VIH VIL TA TAI min 4.5 2.2 -0.3 0 -40 typ 5.0 - max 5.5 6.0 0.8 70 85 unit V V V o o C C (L) DC Electrical Characteristics (VCC=5V10%) TA 0 to 70OC Parameter I/P Leakage Current A0~A16, OE D0~D7 Symbol Test Condition ILI1 ILO ICC TTL levels ICC1 ICC2 ISB ISB1 ISB2 VOL VOH 0V - VIN - VCC CS = VIH,VI/O = GND to VCC CS = VIL ,II/O = 0mA,VIL-VIN-VCC-2.1V Min. Cycle, CS = VIL, VIN = VIL/VCC-2.1V min - typ(2) max Unit 16 70 24 5 0.2 10 8 8 A A Output Leakage Current Operating Supply Current Average Supply Current 44 mA 110 mA 40 mA 12 mA 8 mA CMOS levels Standby Supply Current TTL levels CMOS levels -L Part Output Voltage Min. Cycle, CS - 0.2V, VIN = 0.2V/VCC-0.2V CS = VCC-2.1V, VIL - VIN - VCC-2.1V CS = VCC-0.2V, 0.2 - VIN - VCC-0.2V As above IOL=2.1mA IOH = -1.0mA - 500 A 0.4 V V 2.4 Typical values are at VCC=5.0V,TA=25oC and specified loading. 2 SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 Capacitance (VCC=5V10%,TA=25oC) Note: Capacitance calculated, not measured. Parameter Input Capacitance (CS, A17, A18) I/P Capacitance (other) I/O Capacitance Symbol CIN1 CIN2 CI/O Test Condition VIN = 0V VIN = 0V VI/O = 0V max 8 32 40 Unit pF pF pF Operation Truth Table CS H L L L OE X L L H WE X H L L DATA PINS High Impedance Data Out Data In Data In SUPPLY CURRENT ISB1 , ISB2 ICC1 , ICC2 ICC1 , ICC2 ICC1 , ICC2 MODE Standby Read Write Write Notes : H = VIH : L =VIL : X = VIH or VIL Low Vcc Data Retention Characteristics - L Version Only -L Part Parameter VCC for Data Retention Data Retention Current ICCDR1 (2) ICCDR2 ICCDR3 Chip Deselect to Data Retention Time Operation Recovery Time t CDR tR See Retention Waveform See Retention Waveform Symbol Test Condition V DR CS - VCC-0.2V VCC = 3.0V, CS = VCC-0.2V TOP = 0C to 40C TOP = 0C to 70C TOP = TAI min 2.0 typ(1) - max - Unit V - 9 9 - 100 200 280 A A A - 0 5 - - ns ms Notes (1) Typical figures are measured at 25C. (2) This parameter is guaranteed not tested. AC Test Conditions * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V10% Output Load I/O Pin 645 1.76V 100pF 3 SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 AC OPERATING CONDITIONS Read Cycle -70 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z Output Disable to Output in High Z Symbol t RC tAA tACS tOE tOH tCLZ tOLZ t CHZ t OHZ min 70 10 10 5 0 0 max 70 70 40 30 30 -85 min 85 10 10 5 0 0 max 85 85 45 30 30 -10 min 100 10 10 5 0 0 max 100 100 50 35 35 -12 min 120 10 10 5 0 0 max 120 120 55 40 40 Unit ns ns ns ns ns ns ns ns ns Write Cycle -70 Parameter Write Cycle Time Chip Selection to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write Symbol t WC t CW tAS tAW tWP t WR t WHZ t DW t DH tOW min 70 60 0 60 55 5 0 30 0 5 max 25 min 85 75 0 75 65 5 0 35 0 5 -85 max 30 - -10 min 100 80 0 80 70 5 0 40 0 5 max 35 - -12 min 120 100 0 100 80 5 0 45 0 5 max 40 Unit ns ns ns ns ns ns ns ns ns ns * 70 ns not available at industrial temperature 4 SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ t ACS t CLZ t OHZ Don't care. CS Dout Data Valid t CHZ Notes (1) WE is High for Read Cycle. (2) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform tWC Address t WR (4) OE t AS (3) t AW t CW (2) (6) CS Don't Care WE t OHZ (5) t WP (1) High-Z tDW t DH tOW Dout High-Z Din 5 SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 Write Cycle No.2 Timing Waveform tWC Address t AS (3) t CW (2) t WR (4) CS t AW tWP (1) WE tWHZ(5) t OW High-Z t DW tOH (7) (8) Don't Care Dout High-Z t DH Din AC Characteristics Notes (1) A write occurs during the overlap (tWP) of a low CS and a low WE. (2) tCW is measured from the earlier of CS or WE going high to the end of write cycle. (3) tAS is measured from the address valid to the beginning of write. (4) tWR is measured from the earliest of CS or WE going high to the end of write. (5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state. (7) DOUT is in the same phase as written data of this write cycle. (8) DOUT is the read data of next address. (9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/ O pins. (10) This parameter is sampled and not 100% tested. (11) tWHZ is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. Data Retention Waveform Vcc DATA RETENTION MODE 4.5V 4.5V t CDR 2.2V tR 2.2V V DR CS > Vcc -0.2V 0V CS 6 SYS8512RKX-70/85/10/12 ISSUE 1.0 March 1999 Package Information Dimensions in mm Plastic 36 Pin Single-In-Line 97.25 MAX 3.20MAX 0.50 TYP. 2.54 TYP. 3.50 +/- 0.50 Ordering Information SYS8512RKXLI - 70 Speed 70 85 10 12 = 70 ns = 85 ns = 100 ns = 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Blank = Standard Part L = Low Power Part RKX = Plastic 36 pin SIL 8512 = 512K x 8 SYS = Static RAM Power Consumption Package Organization Memory Type Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 7 14.60 MAX |
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