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| Preliminary Information AMD-761 System Controller TM Data Sheet Publication # 24088 Rev: B Issue Date: August 2001 Preliminary Information (c) 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-760, AMD-761, and AMD-766 are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Contents Revision History 1 Features 1.1 1.2 1.3 1.4 1.5 xi 1 AMD AthlonTM Processor System Bus . . . . . . . . . . . . . . . . . . . 2 Integrated Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 2 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 AGP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Functional Operation 2.1 Processor Interface 7 .................................. 7 2.1.1 Out of Order, Split Transaction . . . . . . . . . . . . . . . . . . . 7 2.1.2 Point-to-Point, Source Synchronized . . . . . . . . . . . . . . . 8 2.1.3 Push-Pull Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 DRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 DDR Data Strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 Memory Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Southbridge Signals . . . . . . . . . . . . . . . . . . . . . . . . PCI Parity/ECC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Accesses by an Initiator . . . . . . . . . . . . . . . . . . . . . WSC# Pin Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 18 19 19 19 20 Table of Contents iii Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 2.4 2.5 2.6 Accelerated Graphics Port (AGP) . . . . . . . . . . . . . . . . . . . . . 21 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 Full-On (C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt (C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Grant (C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Suspend (S1) . . . . . . . . . . . . . . . . . . . . . . . . . Suspend to RAM (S3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 27 30 3 Test 3.1 Board (Three-State) Test Mode 35 . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.1 Board Test Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 3.3 3.4 NAND Tree Test Mode PLL Bypass Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Output Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Electrical Data 4.1 4.2 4.3 4.4 4.5 Absolute Ratings 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Switching Characteristics and Requirements . . . . . . . . . . . . 51 4.5.1 4.5.2 4.5.3 4.5.4 Clock Switching Requirements . . . . . . . . . . . . . . . . . . . DDR Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . AGP/PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMD Athlon Processor System Bus Timings . . . . . . . . 51 53 61 68 iv Table of Contents Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 5 6 7 Package Specifications Pin Designations Signal Descriptions 7.1 7.2 7.3 Initialization Pinstrapping 69 73 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Pin States at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8 Ordering Information 95 97 Conventions, Abbreviations, and References Table of Contents v Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 vi Table of Contents Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. AMD-760TM Chipset System Block Diagram . . . . . . . . . . . . . . . 5 Push-Pull Transmission Line Example . . . . . . . . . . . . . . . . . . . 9 Dummy Load with External Compensation Resistors . . . . . . . 9 AMD-761TM System Controller Connection to Unbuffered DIMMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AMD-761 System Controller Connection to Registered DIMMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Management Signal Connections. . . . . . . . . . . . . . . . . 25 Power On Suspend System Timing Diagram Example . . . . . 29 Suspend to RAM System Timing Diagram Example . . . . . . . 32 SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AGPCLK and PCICLK Waveform . . . . . . . . . . . . . . . . . . . . . . 53 Clock Skew Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DDR Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AMD-761 System Controller DDR Interface Outputs Conceptual Block Diagram . . . . . . . . . . . . . . . . . . . . 57 Address/Command and Memory Write Cycle Timing . . . . . . 58 AMD-761 System Controller DDR Interface Inputs Conceptual Block Diagram . . . . . . . . . . . . . . . . . . . . . . 59 Memory Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Setup, Hold, and Valid Delay Timings . . . . . . . . . . . . . . . . . . 61 AGP 2x Strobe/Data Turnaround Timings . . . . . . . . . . . . . . . 64 AGP 2x Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 AGP 4x Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 AGP 4x Strobe/Data Turnaround Timing . . . . . . . . . . . . . . . . 66 569-Ball Plastic Ball Grid Array (PBGA) Package . . . . . . . . . 69 List of Figures vii Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 viii List of Figures Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet List of Tables Table 1. Table 2. Table 3. Table 4: Table 5: Table 6: Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23: Table 24. Table 25. Table 26. Table 27. Total Memory Sizes With Unbuffered DIMMs . . . . . . . . . . . . . 11 Total Memory Sizes With Registered DIMMs . . . . . . . . . . . . . . 14 AMD AthlonTM System Bus NAND Tree Ordering . . . . . . . . . . 38 AMD-761TM System Controller AGP NAND Tree Ordering . . . 39 AMD-761 System Controller DDR NAND Tree Ordering . . . . 40 AMD-761 PCI NAND Tree Ordering. . . . . . . . . . . . . . . . . . . . . . 42 Clocking Options in PLL Bypass Test Mode . . . . . . . . . . . . . . . 43 Clock Output Test Mode Options . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DC Characteristics (IDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC Characteristics for DDR Interface . . . . . . . . . . . . . . . . . . . . 47 DC Characteristics for PCI I/Os . . . . . . . . . . . . . . . . . . . . . . . . . 48 AGP 1x Mode DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 48 AGP 2x and 4x Mode DC Specifications . . . . . . . . . . . . . . . . . . 49 Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . . 50 SYSCLK Switching Requirements . . . . . . . . . . . . . . . . . . . . . . . 52 AGPCLK Switching Requirements for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PCICLK Switching Requirements for 33-MHz PCI Bus . . . . . . 53 DDR Clock Switching Characteristics for 100-MHz DDR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DDR Clock Switching Characteristics for 133-MHz DDR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AMD-761 System Controller Preliminary DDR Timing Information (100 MHz) . . . . . . . . . . . . . . . . . . . . . 55 AMD-761 System Controller Preliminary DDR Timing Information(133 MHz) . . . . . . . . . . . . . . . . . . . . . . 56 AGP 1x Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AGP 2x Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 AGP 4x Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 List of Tables ix Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. AMD Athlon Processor System Bus/ AMD-761 System Controller AC Specification . . . . . . . . . . . . . 68 Symbol Notes (unless specified otherwise) . . . . . . . . . . . . . . . . 70 569-Pin PBGA 37.50-mm by 37.50-mm Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Geometric Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 AMD-761 System Controller Pin Functional Grouping (1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 AMD-761 System Controller Pin Functional Grouping (2 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 AMD-761 System Controller Pin Functional Grouping (3 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Signal Descriptions Table Definitions . . . . . . . . . . . . . . . . . . . . 77 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Initialization Pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Pin Multiplexing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Reset Pin States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 x List of Tables Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Revision History Date 8/2001 5/2001 2/2001 11/2000 Rev B Description Public release with added bidirectional WSC# feature description. Added electricals. A-2 Modified descriptions of WSC# pin. NDA version only. A-1 Initial public release. A Initial release (NDA). Revision History xi Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 xii Revision History Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 1 Features The AMD AthlonTM processor powers the next generation in computing platforms, delivering the ultimate performance for cutting-edge applications and an unprecedented computing experience. The AMD-760TM chipset is a highly integrated system logic so lut io n t h a t d e livers e n h a n c e d p er fo rm a n c e for t h e AMD AthlonTM processor and other AMD Athlon system bus-compatible processors. The AMD-760 chipset consists of the AMD-761TM system controller in a 569-pin plastic ball-grid array (PBGA) package and the AMD-766TM peripheral bus controller. The AMD-761 system controller features the A M D A t h l o n s y s t e m b u s , s y s t e m m e m o ry c o n t ro l l e r, Accelerated Graphics Port (AGP) controller, and Peripheral Component Interconnect (PCI) bus controller. Figure 1 on page 5 shows a block diagram for the AMD-760 chipset. The AMD-761 system controller is designed with the following features: n n n n The AMD Athlon system bus supports the high-speed, splittransaction AMD Athlon system bus interface. This bus is designed to operate at 100/200-MHz or 133/266-MHz doubledata rate. The 33-MHz 32-bit PCI 2.2-compliant bus interface supports up to seven bus masters plus the AMD-766 peripheral bus controller. The 66-MHz AGP 2.0-compliant interface supports 1x, 2x, and 4x data transfer mode. High-speed memory--The AMD-761 system controller is designed to support DDR SDRAM DIMMs, operating at either 100/200-MHz or 133/266-MHz double-data rate. Note that the DDR interface speed is locked to the front-side bus speed. This document describes the features and operation of the AMD-761 system controller. For a description of the AMD-766 peripheral bus controller, see the AMD-766TM Peripheral Bus Controller Data Sheet, order# 23167. Key features of the AMD-761 system controller are provided in this section. Chapter 1 Features 1 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 1.1 AMD AthlonTM Processor System Bus The AMD Athlon processor system bus has the following features: n n n n n High-performance point-to-point system bus topology Source-synchronous clocking for high-speed transfers 200- or 266-MHz, split-transaction AMD Athlon system bus interface 1.6 Gbytes/s peak data transfer rates at 100/200 MHz, 2.1 Gbytes at 133/266 MHz Large 64-byte (cache line) data burst transfers 1.2 Integrated Memory Controller The integrated memory controller has the following features: n n n n n n n n n The AMD-761 system controller supports the following concurrencies: * Processor-to-main-memory with PCI-to-main-memory * Processor-to-main-memory with AGP-to-main-memory * Processor-to-PCI with PCI-to-main-memory or AGP-to-main-memory Memory error correcting code (ECC) support Supports the following DRAM: * Up to two unbuffered DIMMs or four registered DIMMs * 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit technology * 64-bit data width, plus 8-bit ECC paths * Flexible row and column addressing Supports up to 4 Gbytes of memory Four open pages within one CS (device selected by chip select) BIOS-configurable memory-timing parameters and configuration parameters 2.5-V memory interface operation with no external buffers or PLLs Concurrent DRAM writeback and read-around-write Burst read and write transactions Features Chapter 1 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet n n Decoupled and burst DRAM refresh with staggered CS timing Provides the following refresh options: * Programmable refresh rate * CAS-before-RAS * Populated banks only * Automatic refresh of idle slots--improves bus availability for memory access by the processor or system 1.3 PCI Bus Controller The PCI bus controller has the following features: n n n n n n n n n Compliance with PCI Local Bus Specification, Revision 2.2 Supports seven PCI bus masters plus the AMD-766 peripheral bus controller 32-bit interface, compatible with 3.3-V and 5-V PCI I/O Synchronous PCI bus operation up to 33 MHz PCI-initiator peer concurrency Automatic processor-to-PCI burst cycle detection Zero wait-state PCI initiator and target burst transfers PCI-to-DRAM data streaming up to 132 Mbytes/s Enhanced PCI command optimization, such as Memory Read Line (MRL), Memory Read Multiple (MRM), and Memory-Write-and-Invalidate (MWI) 1.4 AGP Features The AGP features include the following: n Bus Features * Compliance with Accelerated Graphics Port Interface Specification, Revision 2.0 * Synchronous 66-MHz 1x, 2x, and 4x data-transfer modes * Multiplexed and demultiplexed transfers * Up to four pipelined grants * Support of Sideband Address (SBA) bus Features 3 Chapter 1 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 n Request Queue Features * Separate read-request and write-request queues * Reordering of high-priority requests over low-priority requests in queue * Simultaneous issuing of requests from both the write queue and read queue GART (Graphics Address Remapping Table) Features * Conventional (two-level) GART scheme * Eight-entry, fully associative GART table cache * Three fully associative GART directory caches One 4-entry for PCI One 8-entry for the processor One 16-entry for AGP n 1.5 Power Management The power management features include the following: n n Compliance support for both Advanced Configuration and Power Interface (ACPI) and Microsoft(R) PC 99 power management The AMD-761 system controller supports the following power states: * Processor halt/stop grant/sleep states (ACPI C1, C2) * ACPI S1 (power on suspend) and S3 (suspend to RAM) sleep states * Clock throttling with the processor's STPCLK#/stop grant mechanism Refer to Figure 1 on page 5 for a block diagram of the AMD-760 chipset. 4 Features Chapter 1 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet AMD AthlonTM Processor 266-MHz Athlon System Bus 66 MHz AMD-761TM System Controller CPU Support Signals AGP 4X Slot DDR Memory 266 MHz PCI Bus (33 MHz/32 bit) PS/2 Keyboard PS/2 Mouse Serial Port Parallel Port SIO FLASH Figure 1. Chapter 1 SLOT SLOT SLOT AMD-760TM Chipset System Block Diagram SLOT SLOT SIO SLOT SMBus GPIO/Flash/ROM Interface GPIO Logic FLASH AMD-766TM Peripheral Bus Controller 2 EIDE (33/66/100) USB 4 LPC Bus Features 5 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 6 Features Chapter 1 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 2 Functional Operation This chapter describes the functional operation of the AMD-761TM system controller. 2.1 Processor Interface T h e A M D A t h l o n TM p ro c e s s o r s y s t e m b u s i s a h i g h performance, out-of-order, split-transaction bus, capable of transferring one processor command and one probe response, one chip-set response and one probe request, and one data packet simultaneously. Data and command packets are transferred as packets of two, four, or eight datums on each edge of the 100-MHz or 133-MHz clock. 2.1.1 Out of Order, Split Transaction The split transaction bus separates the transfer of the command and the associated data into different transactions on different buses. Data may be returned in a different order than it was requested, subject to ordering rules. A read transaction consists of a Read command sent from the processor to the memory system over the SADDOUT bus. When the memory system is ready to return data, a ReadData command is sent to the processor over the SADDIN bus to alert the processor that data is coming and identify the associated data request. The data is sent to the processor over the SDATA bus a programmable number of clocks later. Similarly, a write transaction is sent to the chipset over the SADDOUT bus, the chipset requests the associated write data over the SADDIN bus, and the data is transferred over the SDATA bus a programmable number of clocks later. Probes and probe responses are piggybacked with the other commands on the SADDIN and SADDOUT bus. The split transaction scheme provides a high degree of parallelism between the various buses and facilitates pipeline flow or memory requests and responses. Chapter 2 Functional Operation 7 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 2.1.2 Point-to-Point, Source Synchronized All of the AMD Athlon processor system bus signals use a terminated, point-to-point topology--that is, there is one signal connection plus termination on each end of each wire. The terminated point-to-point topology allows the use of incident wave signalling, eliminating much of the time for transmission line reflections. This feature allows high-transfer speeds while maintaining high signal integrity. All data transfer is synchronized by a clock generated at the data source. The clock and data propagate over matched length paths, minimizing skew between clock and data, and the data is sampled at the destination using this forwarded clock. Data is sampled into a FIFO at the receiver synchronous to the forwarded clock and read out of FIFO a programmable number of processor clocks later, reducing all metastability concerns. The initialization procedure establishes the location of a common ClockN on both ends of the wire to within the system wide, clock distribution skew. A data object, transmitted from one end of the wire on ClockM, is sampled into the FIFO at the other end of the wire by ClockM forwarded with the data. It is read from the FIFO by ClockM+X that is generated in the receivers clock domain, X clocks later. X is a programmed constant that accounts for the worst case propagation delay. A detailed description of the AMD Athlon system bus, including operations, initialization, and timing can be found in the AMD AthlonTM System Bus Specification, order# 21902, and the AMD AthlonTM System Bus Design Guide, order# 22666. 2.1.3 Push-Pull Compensation The AMD-761 system controller provides push-pull driver configuration. The push-pull driver scheme implements drivers with a user-defined output impedance. This feature allows the point-to-point signals to be source-terminated without any external devices, simplifying layout and reducing cost. In current semiconductor technology, it is not possible to implement a transistor with a tightly controlled impedance over realistic voltage, temperature, and process parameters. Fo r t h i s re a s o n , a dy n a m i c c o m p e n s a t i o n s ch e m e i s implemented. For a push-pull transmission line example, see Figure 2 on page 9. 8 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Many Segments VTT Part of Output Transistors INP Transmission Line + INN VTT/2 OUT Driver Receiver Figure 2. Push-Pull Transmission Line Example The dynamic compensation scheme implements a dummy driver with characteristics exactly matching the normal driver. An external precision resistor is attached, and the voltage of the resulting voltage divider is compared to VTT/2. The drive strength is then adjusted until a voltage near VTT/2 is achieved. The output impedance then roughly matches the resistor value. Separate compensation is performe d for the N and P transistors. The drive strength is changed in small steps when no data is being driven. Refer to Figure 3. VTT 50 ohms + 1% INP + VTT/2 INN 50 ohms + 1% Dummy Driver Figure 3. Dummy Load with External Compensation Resistors Chapter 2 Functional Operation 9 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 2.2 Memory Interface The AMD-761 memory controller arbitrates and optimizes incoming memory requests, handles ECC and Graphics Address Remapping Table (GART), and controls up to four double-data-rate (DDR) SDRAM DIMMs. The AMD-761 system controller memory interface is designed to support both unbuffered and registered DDR DIMMs. Up to two unbuffered DIMMs or four registered DIMMs can be supported by the AMD-761 system controller. The AMD-761 system controller does not allow DIMM types to be mixed on the same motherboard. All DIMMs on the motherboard must be either unbuffered or registered. The AMD-761 system controller supports 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8, and x16 are supported (x4 supported only for registered DIMMs). Mixed banks are supported, meaning that a x8 DIMM can coexist with x4 and x16, etc. DDR timing parameters are programmable via the AMD-761 system controller's memory controller configuration registers, allowing support of different DIMM configurations and loading. Refresh is also programmable, with support of various refresh rates as well as the ability to queue up to four outstanding refreshes. Clock pairs can also be selectively disabled to unpopulated DIMM slots via configuration register bits in the memory controller. The memory controller supports up to four open pages in the active chip select. All pages in a chip select are closed when an access to another chip select is detected. Memory page operation can be further optimized by programming the nu m b e r o f i d l e cy c l e s t o a b a n k b e f o re t h e b a n k i s automatically precharged. Unbuffered DIMMs Support Refer to Table 1 on page 11 for the total memory sizes for various unbuffered DIMM configurations. A total of 2 Gbytes is supported with unbuffered DIMMs. 10 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 1. Total Memory Sizes With Unbuffered DIMMs 1 DIMM (2 Rows) x64/x72 128 Mbytes 64 Mbytes 256 Mbytes 128 Mbytes 512 Mbytes 256 Mbytes 1 Gbytes 512 Mbytes 2 DIMMs (2 Rows Each) x64/x72 256 Mbytes 128 Mbytes 512 Mbytes 256 Mbytes 1 Gbytes 512 Mbytes 2 Gbytes 1 Gbytes Devices Used On DIMM 64 Mbit (2M x 8 x 4 banks) 64 Mbit (1M x 16 x 4 banks) 128 Mbit (4M x 8 x 4 banks) 128 Mbit (2M x 16 x 4 banks) 256 Mbit (8M x 8 x 4 banks) 256 Mbit (4M x 16 x 4 banks) 512 Mbit (16M x 8 x 4 banks) 512 Mbit (8M x 16 x 4 banks) Figure 4 on page 12 shows the AMD-761 system controller connection to unbuffered DIMMS. Unbuffered DIMM support requires only four chip selects to support a maximum of two DIMMs. Only two unbuffered DIMMs are supported due to the heavy loading of the DDR signals by unbuffered DIMMs. The AMD-761 system controller provides six differential clock pairs, three for each unbuffered DIMM. Chapter 2 Functional Operation 11 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 System Clock Differential Clock Pairs (3 per DIMM) CLKOUTL[5],CLKOUTH[5] CLKOUTL[4],CLKOUTH[4] CLKOUTL[3],CLKOUTH[3] CLKOUTL[2],CLKOUTH[2] CLKOUTL[1],CLKOUTH[1] CLKOUTL[0],CLKOUTH[0] MAA[14:00] MAB[14:00] MDAT[63:00], MECC[7:0] AMD-761TM System Controller UnBuffered DDR SDRAM 184-DIMM UnBuffered DDR SDRAM 184-DIMM DIMM 1 DQS[8:0] DM[8:0] RASA#, CASA#, WEA# RASB#, CASB#, WEB# CKEA CKEB CS[1:0]# CS[3:2]# DIMM 0 Figure 4. AMD-761TM System Controller Connection to Unbuffered DIMMs Support of four registered DIMMs is accomplished by the AMD-761 system controller's eight DDR chip-select pins (CS[7:0]#), which allow DIMMs with two chip selects, as illustrated in Figure 5 on page 13. In this example, each DIMM contains two physical DRAM banks, thus two chip selects are routed to the DIMM. The AMD-761 system controller provides one differential clock pair for each registered DIMM. Registered DIMMs Support 12 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet System Clock Differential Clock Pairs (1 per DIMM) CLKOUTL[3],CLKOUTH[3] CLKOUTL[2],CLKOUTH[2] CLKOUTL[1],CLKOUTH[1] CLKOUTL[0],CLKOUTH[0] (MAA to even DIMMs, MAB to odd DIMMs) MAA[14:00], MAB[14:00] MDAT[63:00], MECC[7:0] DQS[8:0] Registered DDR SDRAM 184-DIMM DM[8:0] RASA#, CASA#, WEA# RASB#, CASB#, WEB# CKEA CKEB CS[3:0]# CS[7:4]# (Up to one pair of CS per DIMM) DIMMs 0,1 AMD-761TM System Controller DIMMs 2,3 Figure 5. AMD-761TM System Controller Connection to Registered DIMMs A total of 4 Gbytes is supported with registered DIMMs. Refer to Table 2 on page 14 for the total memory sizes for various registered DIMM configurations. Chapter 2 Functional Operation Registered DDR SDRAM 184-DIMM 13 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 2. Total Memory Sizes With Registered DIMMs 1 DIMM (2 rows) x64/x72 256 Mbytes 128 Mbytes 64 Mbytes 512 Mbytes 256 Mbytes 128 Mbytes 1 Gbytes 512 Mbytes 256 Mbytes 2 Gbytes 1 Gbytes 512 Mbytes 2 DIMMs (2 rows each) x64/x72 512 Mbytes 256 Mbytes 128 Mbytes 1 Gbytes 512 Mbytes 256 Mbytes 2 Gbytes 1 Gbytes 512 Mbytes 4 Gbytes 2 Gbytes 1 Gbytes 3 DIMMs (2 rows each) x64/x72 768 Mbytes 384 Mbytes 192 Mbytes 1.5 Gbytes 768 Mbytes 384 Mbytes 3 Gbytes 1.5 Gbytes 768 Mbytes 4 Gbytes 3 Gbytes 1.5 Gbytes 4 DIMMs (2 rows each) x64/x72 1 Gbytes 512 Mbytes 256 Mbytes 2 Gbytes 1 Gbytes 512 Mbytes 4 Gbytes 2 Gbytes 1 Gbytes 4 Gbytes 4 Gbytes 2 Gbytes Devices used on DIMM 64 Mbit (4M x 4 x 4 banks) 64 Mbit (2M x 8 x 4 banks) 64 Mbit (1M x 16 x 4 banks) 128 Mbit (8M x 4 x 4 banks) 128 Mbit (4M x 8 x 4 banks) 128 Mbit (2M x 16 x 4 banks) 256 Mbit (16M x 4 x 4 banks) 256 Mbit (8M x 8 x 4 banks) 256 Mbit (4M x 16 x 4 banks) 512 Mbit (32M x 4 x 4 banks) 512 Mbit (16M x 8 x 4 banks) 512 Mbit (8M x 16 x 4 banks) Note: . The maximum address space supported by the AMD-761 system controller is 4 Gbytes. 2.2.1 DRAM Refresh The AMD-761 system controller keeps track of when each of C S[ 7 : 0 ] n e e ds t o b e re f re s he d. E a ch C S i s re f re s h e d independently. Refresh is only performed on rows that are populated. A concurrent refresh cycle can be executed in parallel with other read and write requests, if there is no CS conflict and the command bus is free. Figure 6 on page 15 shows DRAM refresh timing. Refresh rates are programmable by BIOS and can accommodate various rates at 100-MHz or 133-MHz system bus speeds. 14 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet CLKOUTH MAx[14:0] RASx# CASx# CS[7:0]# CS0 CS1 Figure 6. DRAM Refresh Timing 2.2.2 DDR Data Strobes Unlike single data rate SDRAMs, Double Data Rate (DDR) does not latch data on the rising edge of the memory clock. Instead, DDR devices specify bidirectional data strobes (DQS pins) between the system memory controller and the DDR memories that are used to capture data. The data strobes are source-synchronous, which means that the DQS signals are driven by the device that is currently driving the data bus. The AMD-761 system controller provides one DQS pin per byte when using x8 and x16 DIMMs, or one per nibble when using x4 DIMMs. The data mask (DM) pins provide the additional DQS strobe function when accessing a x4 DIMM. The DM pins no longer provide a mask function when performing a write access to a x4 DIMM. Therefore, a read-modify-write cycle occurs for partial write accesses (partial implying an incomplete quadword of data). In the case of writes to memory, the AMD-761 system controller must drive DQS such that each edge is centered in the write-data valid window to allow the DDR DRAMs to capture the data on each edge of the strobe. For memory reads, the devices drive the DQS pins edge-aligned with the memory clock, and the AMD-761 system controller must center the DQS with the incoming data. Delaying the DQS accordingly for each byte or nibble is required. Because this t i m i n g i s ve ry t i g h t , t h e A M D -7 6 1 s y s t e m c o n t ro l l e r implements programmable delay lines (PDLs) to accomplish this centering of DQS with the data. A separate PDL is implemented for each DQS pin. Chapter 2 Functional Operation 15 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Because the propagation delay of an individual buffer internal to the AMD-761 system controller is a function of process, voltage, and temperature (PVT), a mechanism is required to compensate for these three variables. As mentioned previously, the delay value is known, but the number of buffers that provides this delay value is not known for a given PVT point. The calibration mechanism provides this piece of information. The mechanism used is a simple measurement of how many buffer delays are required to equal the system clock period. Because the system clock is generated by a PLL in the AMD-761 system controller that is already compensated for PVT, the system clock period is guaranteed to be independent of PVT. Therefore, the clock period can be assumed to be a constant and can be used to correlate the PDL values to units of time. The calibration is automatically performed once after reset and once after self-refresh exit (before acknowledging self-refresh exit), and the resultant value is transferred to each PDL. Recalibration can be initiated via software. The AMD-761 system controller also has a mode that enables periodic autocalibration. 2.3 PCI Bus Controller The AMD-761 system controller drives the 32-bit PCI bus synchronously with the PCI clock (PCICLK) supplied by the system clock generator. The AMD-761 system controller converts the 64-bit processor data to 32-bit PCI data and re g e n e ra t e s c o m m a n d s w i t h m i n i m a l ove r h e a d . A processor-to-PCI posted write buffer enables the processor and PCI to operate concurrently. The AMD-761 system controller converts consecutive processor addresses to burst PCI cycles. A PCI-to-DRAM posted write buffer and a DRAM-to-PCI prefetch buffer enable concurrent PCI bus and processor-DRAM accesses during PCI-initiator transactions. When the processor drives an I/O cycle to an address other than the AMD-761 system controller configuration register addresses, the AMD-761 system controller passes the I/O cycle to the PCI bus and responds to the CPU only after the PCI cycle completes. The AMD-761 system controller does not respond to I/O cycles driven by PCI initiators on the PCI bus. The AMD-761 system controller allows these cycles to complete 16 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet on the PCI bus. A memory write is the only transaction permitted from PCI to AGP. The PCI block can be broken up into two sub-blocks--the PCI target module and the PCI master module. The PCI target module handles cycles initiated by an external master on the PCI bus. The AMD-761 system controller responds to cycles that are directed to main memory or writes that are sent to the other PCI interface (the AGP interface). This module contains write buffers (PCI-to-memory and PCI-to-PCI), read buffers from memory, and a target sequencer that keeps track of the bus while the AMD-761 system controller is a PCI target. The PCI master module handles processor-to-PCI bus cycles. Within a processor stream, no reordering is done. 2.3.1 Memory Coherency The AMD-761 system controller assures that all data accesses remain coherent: * All PCI/AGP accesses not in the GART range generate processor probes assuring that reads receive only the latest version of the data and that writes update only the latest version of the data. Writes are always performed in order. The GART range is by definition not cacheable. As a result, all PCI/AGP accesses that are in the GART range are subject to non-cacheable ordering rules--that is, they do not generate probes to the processor, writes are performed in order, and reads receive the results of all earlier writes. Processor accesses to addresses mapped by the GART range can either use the GART for the final address translation or map the addresses through its page tables as a noncacheable memory type. * * Chapter 2 Functional Operation 17 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 2.3.2 PCI Arbitration The AMD-761 system controller contains arbitration logic that al loc a t es ow ne rs hip of the PCI bus am on g it se lf, t he AMD-766TM peripheral bus controller, and seven other PCI initiators. Access priority rotates between the Southbridge and CPU/PCI bus masters (GNT[6:0]#) such that the following arbitration sequence could be seen in a busy system: 1. Southbridge 2. CPU 3. Southbridge 4. PCI master (one of GNT[6:0]#) 5. Repeat step 1 When there are no requests for the bus, ownership defaults to the processor through the AMD-761 system controller. This mode is controlled by the PCI Arbitration Control register (Dev 0:F0, 0x84, bit 0). 2.3.3 PCI Configuration The AMD-761 system controller uses PCI configuration mechanism #1 to select all of the options available for interaction with the processor, DRAM, and the PCI bus. This mechanism is defined in the PCI Local Bus Specification, Revision 2.2. All configuration functions for the AMD-761 system controller are performed by using two I/O-mapped configuration registers --IO_CNTRL (I/O address 0CF8h) and IO_DATA (I/O address 0CFCh). These two registers are used to access all the other internal configuration registers of the AMD-761 system controller. The AMD-761 system controller decodes accesses to these two I/O addresses and handles them internally. A read to a nonexistent configuration register returns a value of FFh. Accesses to all other I/O addresses are forwarded to the PCI bus as regular I/O cycles. Read and write cycles involving the AMD-761 system controller configuration registers are only distinguished by the address and command that is sent. 18 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet The AMD-761 system controller implements the following configuration spaces: n n n Device 0:Function 0 (host bridge configuration registers) Device 0:Function 1 (DDR I/O and PDL configuration) Device 1:Function 0 (PCI-PCI bridge, AGP configuration) The Device 0:Function 1 space is disabled by default, and must be enabled by writing to a specific bit in the PCI Control register (Dev 0:F0:0x4C). The normal reserved PCI header space (0x00-0x3F) in this function returns all 1s. 2.3.4 PCI Southbridge Signals The AMD-761 system controller supports one pair of PCI request/grant signals, SBREQ# and SBGNT#, to connect to a Southbridge device such as an ISA/EISA bridge. These signals are generally used when a PCI device, an ISA master, or a DMA device requires ownership of the system main memory. The ISA bus device asserts SBREQ# to request the bus. The AMD-761 system controller grants the request after all of its write buffers have been flushed by asserting SBGNT#. Note: The AMD-761 system controller allows a Southbridge device to hold SBREQ# for an extended time in order to complete an ISA transfer and avoid a potential deadlock condition. 2.3.5 PCI Parity/ECC Errors The AMD-761 system controller indicates that an ECC error occurred on the memory bus by setting a bit in the status register and optionally asserting the PCI SERR# signal. This action results in the error being reported by the Southbridge. The AMD-761 system controller does not check parity on the PCI bus. The status bit (Dev 0:04h, bit 31) is always 0. 2.3.6 PCI Accesses by an Initiator A PCI initiator begins a memory read or write cycle by asserting FRAME# and placing the memory address on AD[31:00]. The AMD-761 system controller decodes the address. If the address is within the memory region as defined by PCI Top of Memory (Dev 0:F0:0x9C), the AMD-761 system controller accepts the cycle and responds as a PCI target by Chapter 2 Functional Operation 19 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 asserting DEVSEL#. If the address is not within the defined memory region, the AMD-761TM system controller ignores the cycle and allows it to complete on the PCI. Read requests from PCI masters to the memory subsystem are full cache lines only. After fetching the initial cache line, the AMD-761 system controller can optionally start prefetching the next cache line. Prefetching the next cache line is preferred, because the PCI master typically reads more than one line, but can waste DRAM bandwidth if this line is thrown away. The length of a read request is always 8 quadwords (one cache line). During writes, the AMD-761 system controller attempts to accumulate an entire cache line. If the start address is not cache aligned, the AMD-761 system controller makes single write requests until it reaches a cache-aligned address. When aligned, it makes a request every 8 quadwords. If a partial cache line write is detected, no more data is accumulated, and a request is issued to the memory subsystem. 2.3.7 WSC# Pin Assertion The Write Snoop Complete (WSC#) pin is used to indicate to the Southbridge that all probe activity for the last PCI to DRAM write has been completed and that an interrupt message can now be sent by the APIC. The AMD-761 system controller supports both bidirectional and unidirectional modes of operation for the WSC# pin as described below. Note: The unidirectional WSC# mode is available only in silicon revisions B4 and above. All other revisions support only the bidirectional WSC# mode. Bidirectional WSC# The default mode for WSC# operation is bidirectional for the AMD-761 system controller. This is selected by writing a 0 to the WSC_DIR bit in the PCI Control register (Dev 0:F0:0x4C, bit 3). In this mode, the Southbridge first drives the WSC# pin low for a single PCICLK period when an APIC interrupt message must be sent to the processor. This action alerts the AMD-761 system controller that posted PCI-to-DRAM writes must be flushed to coherent memory. The AMD-761 system controller then asserts the WSC# pin for two PCICLK periods after the probe activity for the last PCI-to-DRAM write has 20 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet completed. This action instructs the Southbridge that it can now send an APIC message over the interrupt messaging bus. The bidirectional WSC# mode is supported by the AMD-766TM peripheral bus controller. Unidirectional WSC# The unidirectional WSC# mode is selected by setting the WSC_DIR bit in the PCI Control register (Dev 0:F0:0x4C, bit 3). In this mode, the WSC# pin is always an output of the AMD-761 system controller and is driven Low when there are no pending probes due to PCI-to-DRAM writes. The WSC# pin is High when there are any outstanding probes due to PCI-to-DRAM writes. Note: The unidirectional WSC# mode is available only in silicon revisions B4 and above. All other revisions support only the bidirectional WSC# mode. 2.4 Accelerated Graphics Port (AGP) The Accelerated Graphics Port (AGP) is a point-to-point connection between a graphics adapter (AGP initiator) and the AMD-761 memory controller (AGP target), which enables the adapter to store and use graphics data in main memory. This connection relieves graphics traffic from the PCI bus and greatly accelerates video performance. The AMD-761 system controller functions as an AGP target, providing all the signals, buffers, and logic required for compliance with the Accelerated Graphics Port Interface Specification, Revision 2.0. While AGP relieves traffic on the PCI bus and frees up graphics adapter memory, the greatest impact on system performance comes from the many innovations AGP brings to data transfer operations. These improvements include the following: n n Split Transactions--Requests to read or write data are separate from the data transfers. Pipelined Requests--Requests can be issued contiguously and stored in the AMD-761 system controller request queue. Pipelining allows AGP to achieve high levels of concurrency with PCI and the processor. Chapter 2 Functional Operation 21 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 n n Pipeline Grants--Pipelined GNT# signals for up to four write transactions. Prioritizing (reordering)--Read and write requests can be assigned a high priority or a low priority to ensure that more urgent requests are serviced first. Defined-Length Requests--The amount of data requested is indicated in the AGP command, rather than the duration of an asserted signal, such as FRAME# in PCI. An 8-byte minimum data size for AGP 2x/4x transfers, which provides an efficient method for moving the large amount of data typical in a graphics request. A separate, optional Sideband Address (SBA) bus that enables concurrent transmissions of requests and data transfers. Optional 2x/4x modes that increase the AGP graphics adapter data transfer rate. Freedom from the coherency requirements of PCI, which eliminates the latency resulting from cache snooping. PCI 2.2 capability, which enables the AMD-761 system controller to pass programming information from the processor to the graphics adapter. A Graphics Address Remapping Table (GART). n n n n n n n The AGP request queue is split up into two queues--one for read requests and one for write requests. Because there is a reordering FIFO in the address module, the request queues do not have to be large. The read queue is big enough to hold all outstanding read requests, which avoids stalling writes that run on the bus while the reads occur to memory. Requests from the SBA bus are multiplexed with PIPE# requests and written to the same queues. High-priority requests are inserted in front of low-priority requests so that the request to be serviced is at the top of the queue. This reordering is done dynamically as a new request is written into the queue. Requests from each of the queues can be read out of both the queues at the same time. The reads start fetching data from memory and the write data is sent across the AGP bus at the same time. 22 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet The AGP ordering rules specify that writes are ordered ahead of reads. Reads are serviced only when all the preceding writes have been written to memory, which is only required for low-priority requests and does not affect high-priority read requests. When a low-priority request is the next one to be serviced from the read queue, the tag of that request is compared with all valid entries in the write queue. If any entry matches, then the read request is blocked. Only after the write requests are serviced will the read requests be allowed to proceed. AGP Request Queue. In general, the AGP request queue services AGP requests in the order received, subject to their priority (write High, read High, write, read). Ordering Rules. The request queue is subject to the following AGP ordering rules: n n n n n High-priority write requests are processed in the order they are received. High-priority read requests are processed in the order they are received. Low-priority write requests are processed in the order they are received. Low-priority read requests are processed in the order they are received. Low-priority reads push low-priority writes, meaning that a write request is serviced before a subsequently received read request is serviced. Low-priority writes can pass low-priority reads, meaning that a write request can be serviced before a previously received read request. There are no ordering restrictions between AGP and PCI transactions on the AGP bus. PCI transactions on the AGP bus follow the PCI ordering rules described in the PCI Local Bus Specification, Revision 2.2. High-priority requests are re-ordered in front of low-priority requests. There is no ordering relationship between high-priority reads, high-priority writes, and any other transfer type, such as low-priority reads, low-priority writes, PCI reads, or PCI writes. Functional Operation 23 n n n n n Chapter 2 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 I f a l ow -p r i o r i t y d a t a t ra n s f e r i s i n p rog re s s w h e n a high-priority request is received, the data transfer completes before the high-priority request is serviced--that is, a request cannot be preempted. A high-priority request supersedes a low-priority request on a request boundary only. 2.5 System Clocking The AMD-761 system controller requires the following system clocks: n SYSCLK, used for clocking the AMD Athlon system bus and the DDR DRAM interface. This clock is typically either 100 MHz or 133 MHz. This clock is also used to create the DDR DRAM clock outputs (CLKOUT[5:0], CLKOUT[5:0]#). AGPCLK, 66 MHz, used for clocking the AGP and PCI internal logic. PCICLK, provides the 33-MHz PCI bus clock and is used to synchronize the PCI bus I/O signals to the 33-MHz PCI signal domain. n n The AMD-761 system controller implements two internal PLLs to control clock skew on-chip for the SYSCLK and AGPCLK domains. These PLLs can be bypassed for motherboard testing. Refer to Chapter 3 for further details of PLL bypass testing. 2.6 Power Management The AMD-761 system controller supports the advanced configuration power interface (ACPI) specification, On-Now, and PC 99 requirements through a handshake mechanism with the processor. The ACPI-defined registers required for processor and system power management are contained in the AMD-766 peripheral bus controller companion device. SMM memory remapping is handled by a model-specific register in the AMD Athlon processor. See the AMD AthlonTM BIOS Developers Guide, order# 21656, for more information about the SMM remapping operation. Figure 7 on page 25 shows how the processor and system controller communicate power-state transitions. 24 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet DDR SDRAMs CLK CKE RESET# PCI BUS DCSTOP# AMD AthlonTM Processor AMD AthlonTM Processor System AMD-761TM System Bus Controller (Northbridge) AMD-766TM Peripheral Bus Controller (Southbridge) STPCLK# 66-MHz AGP Clock 33-MHz PCI Clocks 133-MHz System Clocks Clock Generator Figure 7. Power Management Signal Connections T h e p ro c e s s o r a n d t h e A M D -7 6 1 s y s t e m c o n t r o l l e r communicate power-state transitions through the AMD Athlon system bus connect/disconnect protocol and special cycles (masked writes to a defined AMD Athlon system bus address with specific data encoding). In general, the processor initiates a request for a disconnect with a special cycle, and the AMD-761 system controller may or may not actually disconnect the processor with the connect/disconnect protocol. The A M D -7 6 1 s y s t e m c o n t ro l l e r p e r fo r m s t h e re q u e s t e d connect/disconnect as part of the process of entering and exiting certain ACPI states. The following two special cycles are of interest: n Halt--Generated by the AMD Athlon processor in response to executing a HALT instruction. The AMD-761 system controller sends a Halt special cycle on the PCI bus and optionally (through a configuration register bit) initiates an AMD Athlon system bus disconnect to the processor. Functional Operation 25 Chapter 2 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 n Stop Grant--Generated by the AMD Athlon processor in response to assertion of STPCLK#. When the AMD-761 system controller receives a Stop Grant from the processor, it sends a Stop Grant special cycle on the PCI bus. The AMD-761 system controller initiates the following sequence of actions if the Stop Grant disconnect bit is set (Dev 0:F0:0x60): A. Disables PCI/AGP arbitration and waits for all queues to memory to be empty (including refresh requests). B. Completes the AMD Athlon system bus cycle. The AMD-761 system controller then initiates an AMD Athlon system bus disconnect to the processor, and causes the memory to enter self-refresh. C. The AMD-766 peripheral bus controller decodes the special cycle and enters the appropriate power state. The AMD-766 peripheral bus controller can then assert DCSTOP#. Halt special cycles are generally considered part of an ACPI state definition (C1). STPCLK#, however, can be asserted at random times while the processor is in the full-running state (C0), to conserve power (clock throttling). The AMD-761 system controller implements the following power states: 1. ACPI C0 full-on 2. ACPI C1 Halt 3. ACPI C2 Stop Grant (probed) 4. ACPI S1 power-on suspend 5. ACPI S3 suspend to RAM These power st ates are described in further detail in subsequent paragraphs. 2.6.1 Full-On (C0) In t his s ta t e, t he AMD -76 1 sys te m c ont rolle r i s f ully operational, all clock trees are running, all voltage planes are enabled, and the AMD-761 system controller provides normal refresh to DRAM. 26 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 2.6.2 Halt (C1) If the AMD-761 system controller detects a Halt special cycle from the processor, the Halt state (C1) is entered and the Halt special cycle is driven on the PCI bus. If the Halt disconnect configuration bit is set (Dev 0:F0:0x60), the AMD-761 system controller disconnects the processor. PCI and AGP masters continue to run normally. If the AMD-761 system controller detects a PCI DMA master transaction that requires a probe of the processor's cache, the processor is connected, and the probe cycle(s) run on the AMD Athlon system bus. If the processor does not start any non-NOP AMD Athlon system bus cycles while the probe is in progress, the AMD-761 system controller disconnects the AMD Athlon system bus following the completion of the probe. If the processor starts sending non-NOP AMD Athlon system bus cycles while connected, the AMD-761 system controller transitions to the full-on state. 2.6.3 Stop Grant (C2) If the AMD-761 system controller has detected a Stop Grant special cycle from the processor, the Stop Grant special cycle is driven on the PCI bus. If the Stop Grant disconnect bit is set (Dev 0:F0:0x60) when the Stop Grant special cycle is received, and there is no probe traffic, the AMD-761 system controller disconnects the processor and places system memory in selfrefresh mode before passing the Stop Grant special cycle to the PCI bus. If the AMD-761 system controller detects a PCI DMA master transaction that needs a snoop, the processor is connected, DRAM is taken out of self-refresh mode, and the probe cycle(s) is initiated on the AMD Athlon system bus. If the processor does not start any non-NOP AMD Athlon system bus cycles while the probe is in progress, the AMD-761 system controller disconnects the AMD Athlon system bus following the completion of the probe. If the processor starts sending non-NOP AMD Athlon system bus cycles while connected, the AMD-761 system controller transitions to the full-on state. 2.6.4 Power-On Suspend (S1) The S1 state achieves very low power by disconnecting the processor, entering self-refresh, and then gating off most of the internal high-speed clock trees in the AMD-761 system controller. Snooping is prevented by the peripheral device Chapter 2 Functional Operation 27 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 drivers prior to entering this state. The DDR DRAM clocks continue to be driven for registered DIMMs but are disabled (three-stated) for unbuffered DIMMs. Most internal clocks are gated off, allowing the AMD-761 system controller to achieve a low operating current. The S1 state is entered in a similar manner to C2, starting with a STPCLK# assertion and the Stop Grant state. The AMD-766 peripheral bus controller Southbridge then asserts the DCSTOP# signal, which is used by the AMD-761 system controller to gate off internal clock trees for lower power. All power supplies remain on, and the clock synthesizer chip on the motherboard continues to drive all clocks. The sequence of operation for entering the S1 state is listed below. Figure 8 on page 29 shows a power-on suspend system timing diagram example. S1 Sequence 1. The operating system communicates with all device drivers, causing them to disable their respective peripherals, thus preventing any new bus master activity (DMA) on the PCI and AGP buses. DMA activity already in progress in the AMD-761 system controller completes normally. 2. The Southbridge asserts STPCLK# to the AMD Athlon processor. 3. The processor flushes its buffers and generates a Stop Grant special bus cycle on the AMD Athlon system bus. 4. The AMD-761 system controller flushes all internal queues and initiates a disconnect cycle to the CPU by deasserting the CONNECT pin. The AMD Athlon responds by deasserting the PROCRDY signal. 5. After all queues are flushed, the AMD-761 system controller's power management logic requests the DRAM controller to place the DRAM in self-refresh mode. The DRAM controller initiates self-refresh, then acknowledges to the power management logic. * Self-refresh mode is initiated by generating an autorefresh cycle and deasserting the CKE pins. 6. The AMD-761 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge detects the Stop Grant special cycle on the PCI bus and asserts the DCSTOP# signal. 28 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 8. The AMD-761 system controller samples DCSTOP# active and gates off most of the internal clock trees. The DDR DRAM clocks and address/command outputs are threestated. The CKE pins remain driven Low. The external clock sources and the AMD-761 system controller PLLs continue to run. * Note that the DDR DRAM clocks (CLKOUT[5:0], CLKOUT[5:0]#) continue to run when registered DIMMs are installed. This action is required because the reset signal to the registered DIMMs is connected to the AMD-761 system controller's RESET# pin. The RESET# pin is not asserted in the S1 state, thus the clocks cannot be removed from the registered DIMMs. 240 mS STPCLK# CPU BUS PCI BUS DCSTOP# CKEA CKEB CLKOUTH[n] CLKOUTL[n] MAA[14:0] MAB[14:0] RASn#/CASn#/WEn# DQS[8:0] Driven by the AMD-761TM system controller during DRAM write cycles. 5 S1 Sleep State Enter Self-Refresh Note: Circled numbers correspond to "S1 Sequence" on page 28. Running Full Speed 8 Running Full Speed Three-Stated Running Full Speed Running Full Speed 7 Stop Grant Special Cycle 2 3 4 6 Stop Grant Special Cycle Figure 8. Power On Suspend System Timing Diagram Example Chapter 2 Functional Operation 29 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 This state is exited when the DCSTOP# signal is deasserted by the AMD-766 peripheral bus controller Southbridge, followed by a deassertion of STPCLK#. This action causes the AMD-761 system controller to enable the clock trees and prepare to reconnect the processor. The processor asserts PROCRDY, which causes the AMD-761 system controller to exit selfrefresh and reconnect the AMD Athlon system bus. The A M D -7 6 1 s y s t e m c o n t ro l l e r re t a i n s t h e s t a t e o f a l l configuration registers during the S1 state. 2.6.5 Suspend to RAM (S3) The S3 state is similar to S1. However, power is removed from most of t he motherboard except the A MD-761 system controller, DRAM, and a portion of the AMD-766 peripheral bus controller Southbridge. S3 is the lowest power sleep state, and allows very fast resume because system context is stored in memory instead of on disk. The S3 state is entered similarly to S1 with a Stop Grant special cycle and DCSTOP#. After entering S3 state with DCSTOP# assertion, the AMD-766 peripheral bus controller asserts the RESET# signal, which causes the AMD-761 system controller to gate off its I/O rings to accommodate the voltages being removed from the AMD Athlon system bus, PCI bus, and AGP bus. The AMD-761 system controller core remains powered (2.5 Vdc) as does the DDR I/O interface and the DDR DIMMs, to allow the memory to remain in self-refresh mode with the CKE pins driven Low. The sequence of operation for entering the S3 state is listed below. Figure 9 on page 32 shows a suspend to RAM system timing diagram example. S3 Sequence 1. As with the S1 state, the device drivers are called to place all devices into the D3 device state, which prevents them from trying to master on the bus they reside (or access system memory). 2. The ACPI driver (or BIOS under APM) writes to the appropriate registers in the AMD-766 peripheral bus controller to initiate the hardware sequence into the S3 state. In response to this write, the AMD-766 peripheral bus controller asserts STPCLK# to the AMD Athlon processor. Once STPCLK# has been asserted, the power management 30 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet state machine in the AMD-766 peripheral bus controller waits for a Stop Grant special cycle on the PCI bus before completing the transition into the S3 state. 3. The CPU recognizes that STPCLK# has been asserted, flushes internal buffers, and generates a Stop Grant cycle on the AMD Athlon system bus. 4. The AMD-761 system controller flushes all internal queues including outstanding probes, then deasserts the CONNECT pin. The CPU responds by deasserting its PROCRDY pin. 5. When the disconnect is complete, the AMD-761 system controller executes a self-refresh command to the DDR SDRAM and waits for it to complete (this action is accomplished by issuing an auto-refresh command and driving the CKE signals Low to the DRAM). 6. The AMD-761 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge asserts DCSTOP#. The AMD-761 system controller follows the normal DCSTOP# protocol as described in "S1 Sequence" on page 28, including gating most of the internal clocks off. The DDR clock pins are also three-stated at this time. * Note that if registered DIMMs are installed, the DDR output clocks (CLKOUT[5:0], CLKOUT[5:0]#) continue running for an additional six clock periods from the assertion of RESET#. This action is required because the DIMM reset signal on registered DIMMs is connected to the AMD-761 system controller RESET# pin, and the DIMM clocks must be running while the DIMM reset is first asserted. 8. The AMD-766 peripheral bus controller asserts PCIRST# (RESET# on the AMD-761 system controller). The AMD-761 system controller continues driving the CKE pins Low, and gates off the I/O pads to prevent driving 1s to the unpowered I/O ring and to inhibit floating inputs from the unpowered I/O rings to the powered core logic. The input clock pins (SYSCLK and AGPCLK) are also gated off because these input pins are floating when the motherboard's 3.3 Vdc is powered off. The two STR bits in the DRAM Mode/Status register (Dev 0:F0:0x58) are cleared to 0s. The state of all other memory controller configuration register bits is preserved. Chapter 2 Functional Operation 31 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 9. The AMD-766 peripheral bus controller signals the power supply (deasserts PWRON#) to shut down all but the 5-Vdc and 2.5-Vdc voltages. The motherboard clock generator chip shuts down, therefore the input clocks (SYSCLK and AGPCLK) float. 20-50 mS 30-60 mS 30 mS 30 mS 30-60 mS 1.5-2 mS 2.5 Vdc VREF & VTT K7_VCOREn VDD_AGP VDD_PCI PWRGD STPCLK# CPU Bus PCI Bus DCSTOP# RESET# SYSCLK (Pins) AGPCLK CKEA CKEB CLKOUTH[n] CLKOUTL[n] MAA[14:0] MAB[14:0] DRAM Command DDR DQS Self-Refresh 5 Running Full Speed Running Full Speed Running Full Speed Running Full Speed Running Full Speed Running Full Speed 3 Stop Grant Special Cycles 4 6 7 8 Running Full Speed Running Full Speed CPU Disconnect Occurs Here (SYSTEM) 2 9 Note: Circled numbers correspond to "S3 Sequence" on page 30. Figure 9. Suspend to RAM System Timing Diagram Example 32 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet The S3 state is exited when the AMD-766 peripheral bus controller detects an enabled resume event. The AMD-766 powers up all of the voltage planes that are off during the S3 state by asserting PWRON#. After all of the voltage planes in the system are within specification, and all of the outputs of the system clock generator are running within specification, PWRGD is asserted to the AMD-766 peripheral bus controller. Th e A M D -7 6 6 t h e n d e a s s e r t s D C S TO P # f o l l owe d by deassertion of PCIRST# (the RESET# pin on the AMD-761 system controller). This state is exited when the DCSTOP# signal is driven High (power supplies back on) followed by deassertion of RESET#. The AMD-761 system controller retains the state of the memory controller configuration registers, which allows BIOS to access memory to retrieve and restore the system context. There are two configuration bits that BIOS uses to allow the AMD-761 system controller to differentiate between S3 and all other states following an active to inactive transition on the RESET# pin. Upon exiting the S3 sleep state, BIOS writes the appropriate value to these bits, which causes the AMD-761 system controller to exit self-refresh. The two register bits (STR_Control) are in the DRAM Mode/Status register (Dev 0:F0:0x58) . Refer to the AMD-761TM System Controller Software/BIOS Design Guide, order# 24081, for detailed information on these bits. Chapter 2 Functional Operation 33 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 34 Functional Operation Chapter 2 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 3 Test The AMD-761TM system controller supports test modes that may be used in some cases for motherboard manufacturing test and debug. The following test modes are available on the AMD-761 system controller: * * * * Three-state test NAND tree test PLL bypass test Clock output test Three-state test and NAND tree test can be used to prevent the AMD-761 system controller from driving its pins and to verify connectivity of the AMD-761 system controller to the motherboard. The PLL bypass and clock output test modes are provided primarily for motherboard debug and can be used to verify system clocking and drive slower clocks into the system. Test modes are invoked in the AMD-761 system controller by the assertion of the TEST# pin in conjunction with enabling specific pinstraps on the PCI bus AD[31:0] pins, as described in each section. These pins can be used as pinstraps for various functions by connecting either a pullup or pulldown resistor as required to enable or disable the function (a 10-kohm resistor should be used). The pinstraps are sampled at reset and latched, and the value of most pinstraps can be read in the Configuration Status register (Dev 0:F0:0x88). Asserting the RESET# pin and de-asserting the TEST# pin causes the AMD-761 system controller to exit test modes. Chapter 3 Test 35 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 3.1 Board (Three-State) Test Mode Board test mode simply forces all AMD-761 system controller outputs to a high impedance to allow board-level test equipment to drive the nodes normally driven by AMD-761 system controller pins to test board connectivity. The outputs are three-stated after a maximum of six clocks are driven on the SYSCLK and AGPCLK pins. The minimum number of clocks is required due to some I/O cells that cannot be asynchronously forced into a three-state mode. Board test mode is entered when the AD[25] pin is asserted High simultaneous with the TEST# pin during RESET# assertion. The test mode is then latched coming out of reset. The AD[09] pin should also be pulled up to force the internal PLLs to be bypassed. Three-state mode can be exited by an assertion of the RESET# pin. This reset also disables the PLL bypass mode if it was entered. 3.1.1 Board Test Mode Clocking When entering three-state test mode, the PLLs should also be bypassed as described above. This procedure forces the clocks driven on the SYSCLK and AGPCLK input pins to be routed directly to the appropriate clock domains. The SYSCLK and AGPCLK pins must then be clocked for six clocks as required to force some AMD-761 system controller I/O pads to the threestate mode. 36 Test Chapter 3 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 3.2 NAND Tree Test Mode NAND tree testing is used on the tester and can also be used during board testing to test connectivity of AMD-761 system controller inputs. In this test mode, each AMD-761 system controller input can be asserted one pin at a time, and for each pin assertion there should be a change in state on the output of the respective NAND tree. The AMD-761 system controller p r ov i d e s m u l t i p l e NA N D t re e s , w h i ch s p e e d s u p characterization of the device, and also reduces motherboard test time. The AMD-761 system controller NAND trees are divided by I/O type, thus there are the following trees: n n n n AMD Athlon system bus NAND tree This tree includes all signals on the AMD AthlonTM system bus. SYSCLK is not included in the NAND tree. The output of this tree is the GNT[0]# pin. The ordering for this NAND tree is shown in Table 3 on page 38. AGP/APC NAND tree This tree includes AGPCLK, AGP, and the PCI-type signals that are included in the AGP interface. The output of this tree is the GNT[1]# pin. The ordering for this NAND tree is shown in Table 4 on page 39. DDR DRAM NAND tree This tree includes all signals in the DDR interface. The output of this tree is the GNT[3]# pin. The ordering for this NAND tree is shown in Table 5 on page 40. PCI NAND tree This tree includes PCICLK and PCI bus signals, except the RESET# input. The output of this tree is the GNT[2]# pin. The ordering for this NAND tree is shown in Table 6 on page 42. Chapter 3 Test 37 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 3. Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AMD AthlonTM System Bus NAND Tree Ordering Input Pin Name SADDOUT[09]# SADDOUT[07]# SADDOUT[14]# SADDOUT[12]# SADDOUT[06]# SADDOUT[13]# SADDOUT[05]# SADDOUTCLK# SADDOUT[10]# SADDOUT[08]# SADDOUT[11]# SADDOUT[02]# SADDOUT[04]# SADDOUT[03]# SDATA[55]# SCHECK[6]# SDATAOUTCLK[3]# SDATA[63]# SDATA[54]# SDATA[53]# SDATA[49]# SDATA[52]# SDATA[62]# SDATAINCLK[3]# SDATA[59]# SDATA[61]# SDATA[50]# SDATA[60]# SDATA[51]# SDATA[56]# SDATA[13]# SDATA[00]# SDATA[11]# SDATA[09]# SADDIN[11]# SADDIN[05]# SADDIN[06]# SADDIN[02]# Ball Order Input Pin Name N-3 39 SDATA[58]# M-3 40 SDATA[57]# L-1 41 SDATA[48]# N-2 42 SCHECK[7]# P-3 43 SDATA[39]# M-1 44 SDATA[45]# P-2 45 SDATA[36]# N-1 46 SDATA[37]# R-3 47 SDATA[47]# P-1 48 SDATA[44]# R-5 49 SDATA[46]# R-1 50 SDATA[43]# T-4 51 SDATA[38]# T-1 52 SCHECK[4]# T-5 53 SCHECK[5]# T-3 54 SDATAINCLK[2]# T-2 55 SDATA[35]# U-3 56 SDATA[33]# U-4 57 SDATA[40]# U-1 58 SDATA[42]# U-2 59 SDATAOUTCLK[2]# U-5 60 SDATA[34]# W-1 61 SDATA[41]# V-1 62 SDATA[32]# Y-1 63 SDATA[22]# V-3 64 SDATA[30]# V-5 65 SDATAOUTCLK[1]# W-2 66 SDATA[23]# W-4 67 SCHECK[3]# AB-1 68 SDATA[21]# AJ-10 69 SADDIN[07]# AJ-9 70 SADDIN[03]# AH-11 71 SDATAINVALID# AJ-11 72 SADDIN[09]# AH-12 73 SADDIN[08]# AG-12 74 SADDIN[04]# AG-13 75 SADDIN[10]# AJ-12 76 SADDIN[13]# Ball Order Input Pin Name Y-2 77 SDATA[31]# Y-3 78 SDATA[19]# W-5 79 SDATAINCLK[1]# W-3 80 SCHECK[2]# AA-1 81 SDATA[20]# AC-1 82 SDATA[28]# Y-4 83 SDATA[29]# AA-3 84 SDATA[18]# AB-2 85 SDATA[24]# AC-2 86 SDATA[27]# Y-5 87 SDATA[17]# AE-1 88 SDATA[25]# AB-3 89 SDATA[16]# AB-4 90 SDATA[26]# AD-1 91 SDATA[01]# AC-3 92 SDATA[07]# AA-5 93 SDATA[15]# AC-4 94 SCHECK[0]# AF-1 95 SDATA[05]# AE-2 96 SDATA[06]# AD-3 97 SDATAINCLK[0]# AB-5 98 SDATA[4]# AE-3 99 SDATA[10]# AC-5 100 SCHECK[1]# AG-3 101 SDATA[03]# AD-5 102 SDATA[12]# AF-2 103 SDATA[08]# AG-2 104 SDATA[02]# AF-5 105 SDATAOUTCLK[0]# AH-3 106 SDATA[14]# AE-13 107 CLKFWDRST AJ-13 108 SADDIN[14]# AF-14 109 SADDINCLK# AJ-14 110 CONNECT AE-14 111 PROCRDY AG-14 112 SADDIN[12]# AH-14 AG-15 Ball AE-4 AG-4 AE-6 AH-4 AJ-3 AE-7 AF-6 AH-5 AE-9 AE-8 AG-6 AF-8 AH-6 AG-7 AE-10 AJ-5 AF-9 AG-8 AJ-7 AJ-6 AG-9 AH-8 AE-12 AE-11 AH-9 AG-10 AF-11 AJ-8 AF-12 AG-11 AF-15 AJ-15 AH-15 AE-15 AJ-17 AJ-16 38 Test Chapter 3 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 4: AMD-761TM System Controller AGP NAND Tree Ordering Order Input Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A_GNT# SBA[1] PIPE# WBF# SBA[5] ST[1] A_REQ# ST[0] ST[2] SBA[7] A_AD[30] SBA[3] RBF# A_AD[28] CBE[3]# SBA[2] SBA[0] A_AD[26] A_AD[20] A_AD[22] SBA[4] SBSTB Ball AD-27 AB-25 AE-29 AC-26 AA-25 AD-28 AD-29 AC-27 AC-28 AA-26 Y-25 AB-27 AC-29 Y-26 V-25 AA-27 AB-29 W-25 U-25 V-26 Y-27 AA-28 Order 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Input Pin Name SBSTB# A_AD[24] A_AD[31] A_AD[18] A_AD[27] A_AD[29] SBA[6] A_AD[25] ADSTB[1] ADSTB[1]# A_AD[16] A_AD[23] A_AD[21] A_AD[19] A_IRDY# A_FRAME# A_CBE[2]# A_AD[17] A_CBE[1]# A_DEVSEL# A_SERR# A_STOP# Ball AA-29 W-27 Y-29 U-26 V-27 W-29 Y-28 V-28 U-27 V-29 T-27 U-28 U-29 T-29 R-29 R-26 R-28 R-27 P-29 P-27 P-28 P-26 Order Input Pin Name 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 A_AD[14] A_AD[10] A_AD[12] A_AD[15] A_AD[07] A_TRDY# A_AD[11] A_AD[08] A_PAR ADSTB[0] ADSTB[0]# A_AD[05] A_AD[03] A_AD[09] A_AD[06] A_CBE[0]# A_AD[01] A_AD[13] A_AD[04] A_AD[02] A_AD[00] PCICLK Ball N-29 M-29 M-28 N-27 L-29 P-25 M-26 L-28 N-25 M-27 L-27 K-29 J-29 L-25 K-27 L-26 J-28 M-25 K-25 J-26 J-25 F-28 Chapter 3 Test 39 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 5: AMD-761TM System Controller DDR NAND Tree Ordering Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Input Pin Name MDAT[59] MDAT[63] DQS[7] CLKOUT[5] DCSTOP# MDAT[58] MDAT[62] CLKOUT[2]# MDAT[57] DM[7] CLKOUT[2] CS[6]# MDAT[56] CLKOUT[5]# CS[5]# MDAT[60] CS[1]# MDAT[61] MDAT[51] MDAT[55] CS[7]# DM[6] MDAT[50] CASA# DQS[6] CS[4]# CASB# MDAT[54] MDAT[53] CS[3]# MAA[03] MAA[02] MDAT[25] MDAT[29] Ball E-29 E-27 D-29 F-26 G-25 E-28 C-29 F-25 C-27 C-28 E-26 D-25 B-28 D-27 E-24 B-27 E-23 C-26 A-27 C-25 E-25 C-24 A-26 E-22 B-25 D-24 E-21 A-25 B-24 C-23 C-8 D-9 A-7 B-7 Order 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Input Pin Name MDAT[49] CS[0]# WEA# MDAT[48] MDAT[52] CS[2]# WEB# MDAT[47] MAB[13] MDAT[43] RASA# MAA[14] RASB# MDAT[46] MDAT[42] DQS[5] MDAT[41] DM[5] MAA[13] MDAT[44] MDAT[45] MDAT[40] MDAT[35] MAA[10] MAB[14] DM[4] MAB[10] MDAT[34] MDAT[39] MDAT[38] MDAT[16] MAA[05] MAB[08] MAB[07] Ball A-24 D-22 E-20 C-22 A-23 D-21 C-20 B-22 E-18 A-22 E-19 E-17 D-19 C-21 B-21 A-21 C-19 A-20 D-18 C-18 B-19 A-19 B-18 E-16 C-17 B-16 D-16 C-16 A-18 A-17 B-3 E-5 D-4 F-5 Order 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Input Pin Name DQS[4] MDAT[36] MAB[00] MDAT[37] MDAT[33] MDAT[32] MECC[7] MECC[6] MECC[2] DQS[8] MECC[1] DM[8] MECC[5] MAA[00] MECC[3] CLKOUT[0]# MECC[0] MECC[4] CLKOUT[3] MDAT[31] MAA[01] MDAT[27] MDAT[30] CLKOUT[0] DM[3] DQS[3] MAB[01] CLKOUT[3]# MDAT[26] MAB[02] MAA[11] CKEA MDAT[02] MDAT[07] Ball A-16 A-15 E-15 B-15 C-15 A-14 C-14 A-13 B-13 A-12 B-12 C-13 A-11 E-14 D-13 E-13 C-12 A-10 C-11 B-10 E-11 C-10 B-9 D-12 C-9 A-8 D-10 E-12 A-9 E-10 H-4 K-5 H-3 G-1 40 Test Chapter 3 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 5: AMD-761TM System Controller DDR NAND Tree Ordering (Continued) Order 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Input Pin Name MAB[03] MDAT[28] MDAT[24] MAA[04] MDAT[22] MAB[04] MDAT[23] MDAT[19] MDAT[18] MAB[06] DM[2] MAA[06] DQS[2] MDAT[21] MAB[05] MDAT[17] MDAT[20] Ball E-9 C-7 A-6 D-7 A-5 E-8 C-6 B-6 A-4 D-6 B-4 E-7 C-5 A-3 E-6 C-4 C-3 Order 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Input Pin Name MAB[09] MDAT[11] MDAT[15] MDAT[10] DQS[1] MAA[08] MDAT[14] MAA[07] DM[1] MAB[11] MDAT[13] MAA[09] MAB[12] MDAT[09] MDAT[12] MDAT[08] MDAT[03] Ball G-5 B-2 D-3 C-1 E-3 E-4 D-2 F-3 D-1 H-5 E-2 G-4 J-5 E-1 F-1 G-3 G-2 Order 137 138 139 140 141 142 143 144 145 146 147 148 149 Input Pin Name MAA[12] CKEB MDAT[06] CLKOUT[1]# DQS[0] CLKOUT[4]# CLKOUT[1] CLKOUT[4] MDAT[01] DM[0] MDAT[04] MDAT[00] MDAT[05] Ball K-4 J-3 H-2 M-5 H-1 L-5 N-5 L-4 K-3 J-1 L-3 K-1 K-2 Chapter 3 Test 41 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 6: AMD-761TM PCI NAND Tree Ordering Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Input Pin Name AD[31] REQ[6]# GNT[5]# REQ[5]# GNT[6]# REQ[4]# AD[29] AD[27] REQ[3]# AD[25] GNT[4]# CBE[3]# AD[17] REQ[2]# REQ[1]# AD[21] REQ[0]# CBE[2]# AD[23] AD[30] IRDY# Ball AG-16 AH-17 AJ-18 AH-18 AG-17 AJ-19 AE-16 AF-17 AH-19 AE-17 AG-18 AF-18 AE-19 AH-20 AH-21 AF-19 AG-21 AF-20 AE-18 AH-22 AE-20 Order 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Input Pin Name CBE[1]# DEVSEL# AD[28] AD[26] SERR# AD[24] AD[19] AD[12] AD[18] AD[14] AD[22] AD[20] AD[16] TRDY# AD[08] STOP# AD[10] FRAME# PAR AD[07] AD[15] Ball AF-22 AF-21 AJ-23 AH-23 AE-21 AG-23 AJ-24 AF-23 AJ-25 AE-22 AH-24 AG-24 AH-25 AJ-26 AF-24 AH-26 AE-23 AG-25 AJ-27 AE-24 AH-27 Order 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Input Pin Name AD[05] AD[13] AD[03] AD[01] AD[11] AD[00] SBGNT# AD[09] WSC# AD[06] CBE[0]# SBREQ# AD[04] AD[02] Ball AF-25 AG-27 AE-25 AF-26 AH-28 AE-26 AD-25 AG-28 AC-25 AF-27 AG-29 AE-27 AF-28 AF-29 42 Test Chapter 3 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 3.3 PLL Bypass Test Mode PLL bypass test mode provides a method to clock the Northbridge core logic directly from an external source without the need for the internal PLLs of the AMD-761 system controller. This test mode is sometimes useful for motherboard debug and is required in the three-state and NAND tree test modes. PLL bypass mode is entered by asserting the TEST# pin Low and pulling the AD[09] pin High. There are two clocking options for PLL bypass mode as listed in Table 7. Because the AMD-761 system controller internal logic normally uses clocks that are 2x the SYSCLK input and 2x/4x the AGPCLK input, the PLL bypass mode requires that either 2x or 4x clocks be driven in this mode, but they can be driven at a much lower frequency for test purposes (see Table 7). Note that when operating in this mode, the minimum clock frequency most likely will be dictated by the surrounding logic, such as the DDR interface. Table 7. Mode Normal AGP-4x Testing Clocking Options in PLL Bypass Test Mode C/BE[1]# 0 1 SYSCLK 2x 2x AGPCLK 2x 4x Comments PLLs bypassed, drives a 2x clock to internal divider, and resulting 1x clock to internal logic. Same as above, except allows 4x clock to accommodate 4x AGP testing. The PLL reset function can be invoked by asserting a Low on the PCI IRDY# pin This procedure provides a synchronous reset for the clocking, but probably is not required when using this test mode for motherboard debug. Note: AD[29] must be pulled Low when entering PLL bypass test mode to enable the PLL reset function capability. Chapter 3 Test 43 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 3.4 Clock Output Test Mode The clock output test mode provides external visibility of the two PLLs used to generate the clocks for the processor/memory and AGP clock domains. In this test mode, the PLLs are running, and the output clocks are driven to GNT[6:5]# pins. System designers that intend to make use of this test feature should provide 0-ohm resistors on these pins to isolate the PCI peripherals when observing the clocks. This test mode is entered by the Low assertion of the TEST# pin while pulling the PCI bus PAR pin Low. Additional pinstraps are then used to select the various clock outputs as illustrated in Table 8. Table 8. AD[07:05] 000 001 010 011 100 101 110 111 Clock Output Test Mode Options SYSCLK PLL Output GNT[5]# Pin 1x SYSCLK clock after internal divide by two SYSCLK input Reserved, undefined Reserved, undefined 1x SYSCLK output from SYSCLK PLL Reserved, undefined Reserved, undefined Reserved, undefined AD[14:12] 000 001 010 011 100 101 110 111 AGPCLK PLL Output GNT[6]# Pin 1x AGPCLK clock after internal divide by two AGPCLK input Reserved, undefined Reserved, undefined 1x SYSCLK output from SYSCLK PLL Reserved, undefined Reserved, undefined Reserved, undefined 44 Test Chapter 3 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 4 Electrical Data This section provides electrical data for the AMD-761TM system controller. 4.1 Absolute Ratings The AMD-761 system controller is not designed to operate beyond the parameters shown in Table 9. Note: The absolute ratings in Table 9 and associated conditions must be adhered to in order to avoid damage to the AMD-761TM system controller and motherboard. Systems using the AMD-761 system controller must be designed to ensure that the power supply and system logic board guarantee that these parameters are not violated. VIOLATION OF THE ABSOLUTE RATINGS WILL VOID THE PRODUCT WARRANTY. Table 9. Absolute Ratings* Parameter VDD_CORE, A_VDD, K7_VCORE VDD_AGP, VDD_PCI REF_5V VPIN DDR VPIN AMD AthlonTM System Bus VPIN PCI VPIN AGP VPIN Miscellaneous TCASE (Under Bias) TSTORAGE * Minimum -0.5 V Maximum 3.6 V Comments Core, PLL, DDR I/O, and AMD AthlonTM System Bus I/O supplies AGP and PCI I/O supplies Voltage on any pin. Voltage on any pin. Voltage on any pin. Voltage on any pin. Voltage on any pin. -0.5 V -0.5 VI -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V -65 C 4.6 V 5.25 V 4.6 V 3.6 V 5.25 V 4.6 V 4.6 V 85 C 150 C This table contains preliminary information, which is subject to change. Chapter 4 Electrical Data 45 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 4.2 Operating Ranges The AMD-761 system controller is designed to provide f u n c t i o n a l o p e ra t i o n if t h e vo lt a g e a n d t e m p e ra t u re parameters are within the limits defined in Table 10. Table 10. Parameter REF_5V VDD_CORE, A_VDD K7_VCORE VDD_AGP VDD_AGP VDD_PCI TCASE never exceed the voltage applied to REF_5V. Operating Ranges* Minimum 4.75 2.375 V 1.50 V 1.425 V 3.135 V 3.135 V Typical 5.0 2.5 V 1.6 V 1.5 V 3.3 V 3.3 V Maximum 5.25 2.625 V 1.70 V 1.575 V 3.465 V 3.465 V 85C Comments For PCI 5-V tolerance Also includes DDR I/Os AMD AthlonTM system bus I/O VDD 1x/2x/4x modes 1x/2x modes only 3.3-V signalling environment only *This table contains preliminary information, which is subject to change. The voltage applied to VDD should- 46 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 4.3 DC Characteristics Table 11 shows DC characteristics (IDD). Table 12 shows the DC characteristics for the DDR Interface. Table 13 on page 48 shows DC characteristics for the PCI I/Os. Table 14 on page 48 shows DC characteristics for AGP I/Os in 1x mode. Table 15 on page 49 shows DC characteristics for AGP I/Os in 2x and 4x modes. Table 11. Symbol IDD1 IDD2 IDD3 IDD4 IDD5 * DC Characteristics (IDD)* Parameter Description VDD_CORE (2.5 V) Dynamic VDD_PCI (3.3 V) Dynamic VDD_AGP (1.5 V/3.3 V) Dynamic A_VDD (2.5 V) Dynamic K7_VCORE (Dynamic Preliminary Data Min 1.25 A 40 mA 10 mA 5 mA 125 mA Max 1.5 A 70 mA 20 mA 10 mA 250 mA Comments This table contains preliminary information, which is subject to change. Table 12. Symbol VIL VIH VOL VOH VREF ILI ILO CIN * DC Characteristics for DDR Interface* Parameter Description Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage DC Input Reference Voltage Input Leakage Current Three-state Leakage Current Input Capacitance 0.85 * VDD_CORE 1.15 V -10 A -10 A 4 pF 1.35 V 10 A 10 A 12 pF 0 < VIN < VDD_CORE Preliminary Data Min -300 mV VREF + 180 mV Max VREF - 180 mV 0.15 * VDD_CORE Comments Data, DQS pins VDD_CORE + 300 mV Data, DQS pins (15.2 mA/-15.2 mA) JEDEC Test conditions This table contains preliminary information, which is subject to change. Chapter 4 Electrical Data 47 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 13. Symbol VIH VIL IIL VOH VOL CIN Notes: DC Characteristics for PCI I/Os* Parameter Description Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance 0 < VIN < VCC IOUT = -500 A IOUT = 1500 A 0.9 VCC 0.1 VCC 10 Condition Min 0.5 VCC -0.5 Max VCC + 0.5 0.3 VCC Units V V Notes 10 A V V pF 1 2 * This table contains preliminary information, which is subject to change. 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with three-state outputs. 2. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices up to 16 pF in order to accommodate PGA packaging. Generally, this means that components for expansion boards need to use alternatives to ceramic PGA packaging--that is, PQFP, SGA, etc. Table 14. AGP 1x Mode DC Specifications* DC Specifications for AGP 1x Signalling at 3.3 Volts Symbol VIH VIL IIL VOH VOL CIN Symbol VIH VIL IIL VOH VOL CIN Notes: Parameter Description Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance Condition Min 0.5 VDDQ -0.5 Max VDDQ + 0.5 0.3 VDDQ Units V V Notes 0 < VIN < VDDQ IOUT = -500 A IOUT = 1500 A 0.9 VDDQ 10 0.1 VDDQ 8 A V V pF 1 DC Specifications for AGP 1x Signalling at 1.5 Volts Parameter Description Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance 0 < VIN < VDDQ IOUT = -200 A IOUT = 1000 A 0.85 VDDQ 0.15 VDDQ 8 Condition Min 0.6 VDDQ -0.5 Max VDDQ + 0.5 0.4 VDDQ Units V V Notes 10 A V V pF 1 * This table contains preliminary information, which is subject to change. 1. Absolute maximum pin capacitance for an AGP-compliant component input is 8 pF (except for CLK) with an exception granted to motherboard-only devices, which could be up to 16 pF in order to accommodate PGA packaging. Generally, this means that components for expansion boards need to use alternatives to ceramic PGA packaging--that is, PQFP, BGA, etc. 48 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 15 lists incremental parameters required for supporting AGP 2X with 3.3-V signalling and AGP 4X. Table 15. AGP 2x and 4x Mode DC Specifications* DC Specifications for 2x Mode Only at 3.3-Volt Signalling Symbol VREF IREF CIN Parameter Description Input Reference Voltage VREF Pin Input Current Input Pin Capacitance Strobe to Data Pin Capacitance Delta -1 0 < VIN < VDDQ Condition Min 0.39 VDDQ Max 0.41 VDDQ Units V Notes 1, 2 2 3 3, 4 10 8 2 A pF pF CIN DC Specifications for 2x or 4x Mode at 1.5-Volt Signalling Symbol VREF IREF CIN Parameter Description Input Reference Voltage VREF Pin Input Current Input Pin Capacitance Strobe to Data Pin Capacitance 2x Mode Delta 4x Mode -1 -1 0 < VIN < VDDQ Condition Min 0.48 VDDQ Max 0.52 VDDQ Units V Notes 1, 2 2 3 3, 4 5 8 2 1 A pF pF CIN Notes: * This table contains preliminary information, which is subject to change. 1. AGP allows differential input receivers to achieve the tighter timing tolerances needed for 133 Mbytes/s. Nominal value of VREF is 0.4 VDDQ for 3.3-V signalling and 0.5-VDDQ for 1.5-V signalling. VREF can be designed with 2% resistors to achieve the specified minimum and maximum values. The value of VREF is intended to specify the center point of the VIL/VIH range. For the 3.3-V signalling case, at nominal VDDQ (3.3 V), VREF is 1.32 V 2.5%. A single input interface buffer can be designed to meet the VIL/VIH levels of both the AGP and PCI specifications. As in other AGP specifications, note that the VDDQ references the I/O ring supply voltage and not the component supply. 2. Although a differential input buffer is not a required implementation, it is recommended especially at higher data transfer rates where there is less timing margin. All designs regardless of implementation style must meet all other specifications. Component designs requiring a reference are required to adhere to the VREF and IREF specifications and to facilitate a common reference circuit. (A common reference circuit is not applicable to add-in card designs, because VREF is not supplied via the connector.) 3. Capacitance specifications refer only to pin capacitance on the AGP-compliant components used on the AGP interface. 4. Delta CIN is required to restrict timing variations resulting from differences in input pin capacitance between the strobe and associated data pins. This delta only applies between signal groups and their associated strobes: AD_STB1, AD_STB1#=>AD[31::16], and C/BE[3::2]; AD_STB0, AD_STB0#=>AD[15::00], and C/BE[1::0]#; SB_STB, SB_STB#=>SBA[7::0]. (Complementary strobes apply to 4x mode only.) Chapter 4 Electrical Data 49 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 4.4 Power Dissipation Table 16 shows typical and maximum power dissipation of the AMD-761 system controller during normal and reduced power states. The measurements are taken with the VDD shown. Table 16. Typical and Maximum Power Dissipation* Normal Operation Supply Typical Maximum ACPI S1 State Unbuffered DIMMs 100 mW 133 mW Low-Power States ACPI S1 State Registered DIMMs 125 mW 165 mW ACPI S3 State VDD_CORE 100 MHz 133 MHz * 3W 4W 3.75 W 5W 50 mW 65 mW This table contains preliminary information, which is subject to change. 50 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 4.5 Switching Characteristics and Requirements The AMD-761 system controller signal switching characteristics and requirements are presented in Tables 17 through 28. All signal timings are based on the following conditions: n n The target signals are input or output signals that are switching from logical 0 to 1, or from logical 1 to 0. Measurements are taken from the time the reference signal (AGPCLK, PCICLK, CLKOUT, SYSCLK, or RESET#) passes through 1.5 V to the time the target signal passes through 1.5 V. Parameters are within the range of those listed in "Operating Ranges" on page 46. n 4.5.1 Clock Switching Requirements Table 17 on page 52 contains the switching characteristics of the SYSCLK input to the AMD-761 system controller for 100-MHz processor bus operation. These timings are all measured with respect to the voltage levels indicated by Table 10 on 52. Clock skew requirements are shown in Figure 12 on p a g e 5 3 . Tab le 1 8 o n p a g e 5 2 c o n t a i n s t h e sw i t ch i n g characteristics of the AGPCLK input for 66-MHz PCI bus operation. Table 19 on page 53 contains the switching characteristics of the PCICLK input for 33-MHz PCI bus operation. These timings are all measured with respect to the voltage levels indicated by Figure 11 on page 53. The clock period stability specifies the variance (jitter) allowed between successive periods of the clock inputs measured at appropriate reference voltage. This parameter must be considered as one of the elements of clock skew between the AMD-761 system controller and the system logic. Chapter 4 Electrical Data 51 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 17. Symbol 1/tCKlo t4 t5 SYSCLK Switching Requirements* Parameter Description Frequency 45% TBD TBD Preliminary Data Min Max 133 MHz 55% 1.0 V/ns 1.0 V/ns Figure 10 10 10 10 1.15-V reference 1.15-V reference Comments t3/tCKlo x 100 SYSCLK Duty Cycle SYSCLK Falling Edge Slew Rate SYSCLK Rising Edge Slew Rate SYSCLK Period Stability 100 MHz 133 MHz * 200 ps 150 ps This table contains preliminary information, which is subject to change. tCKlo t3 1.5 V 1.15 V 0.8 V t5 t4 Figure 10. Table 18. Symbol 1/tCKhi tCKlo t3 SYSCLK Waveform AGPCLK Switching Requirements for 66-MHz Bus Operation* Parameter Description Frequency AGPCLK High Time AGPCLK Low Time AGPCLK Fall Time AGPCLK Rise Time 6.0 ns 6.0 ns 0.15 ns 0.15 ns -500 ps 2 ns 2 ns 500 ps 12 Rising to rising edges 1.5-V reference Preliminary Data Min Max 66 MHz Figure 11 11 11 Comments tSKEW * SYSCLK to AGPCLK Skew AGPCLK Period Stability 300 ps This table contains preliminary information, which is subject to change. 52 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 19. Symbol tCKhi tCKlo t3 PCICLK Switching Requirements for 33-MHz PCI Bus* Parameter Description PCICLK Cycle PCICLK High Time PCICLK Low Time PCICLK Fall Time PCICLK Rise Time PCICLK Period Stability Preliminary Data Min 30 ns 11.0 ns 11.0 ns 1 V/ns 1 V/ns 2 V/ns 2 V/ns 300 ps Max Figure 11 11 11 Comments 1.5-V reference * This table contains preliminary information, which is subject to change. tCKlo .5 VDD_PCI .4 VDD_PCI 0.3 VDD_PCI t3 tCKhi Figure 11. AGPCLK and PCICLK Waveform SYSCLK 1.15 V AGPCLK 0.4 (VDD_PCI) tSkew tSkew Figure 12. Clock Skew Requirements 4.5.2 DDR Interface Timing Table 20 on page 54 and Table 21 on page 54 show the DDR SDRAM interface timings. Figure 13 on page 54 shows DDR clock specifications. The controller's DDR DRAM interface complies to JEDEC specifications for 100/133-MHz device timing. Chapter 4 Electrical Data 53 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 20. Symbol DDR Clock Switching Characteristics for 100-MHz DDR Operation* Parameter Description Frequency Preliminary Data Min 4.75 ns 4.75 ns 0.86 ns 0.86 ns 1.30 ns 1.30 ns Max 100 MHz 13 13 Drive strength: P = 3, N = 2; PSLEW = 5, NSLEW = 5 Relative to all other CLKOUTH/L pairs Figure Comments tCKhi tCKlo CLKOUTH/L[5:0] High Time CLKOUTH/L[5:0] Low Time CLKOUTH/L[5:0] Fall Time CLKOUTH/L[5:0] Rise Time CLKOUTH/L[5:0] Period Stability CLKOUTH/L[5:0] Skew 2% 0 0.12 ns * This table contains preliminary information, which is subject to change. Table 21. Symbol DDR Clock Switching Characteristics for 133-MHz DDR Operation* Parameter Description Frequency Preliminary Data Min 3.625 ns 3.625 ns 0.86 ns 0.86 ns 1.30 ns 1.30 ns Max 133 MHz 13 13 Drive strength: P = 3, N = 2; PSLEW = 5, NSLEW = 5 Relative to all other CLKOUTH/L pairs Figure Comments tCKhi tCKlo CLKOUTH/L[5:0] High Time CLKOUTH/L[5:0] Low Time CLKOUTH/L[5:0] Fall Time CLKOUTH/L[5:0] Rise Time CLKOUTH/L[5:0] Period Stability CLKOUTH/L[5:0] Skew 2% 0 0.12 ns * This table contains preliminary information, which is subject to change. tCKlo CLKOUTH[5:0] CLKOUTL[5:0]# tCKhi Figure 13. DDR Clock Specifications 54 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 22 and Table 23 on page 56 show the AMD-761 system controller preliminary timing information. Table 22. Symbol VIL (AC) VIH (AC) tADsu tADsu tADhld tADhld tDQsu tDQhld tWPREsu tWPREhld tWpostA tDSsu tDQSdly tDQSQrd tDQSQrd tQHrd tQHrd tDQS2ck Notes: AMD-761 System Controller Preliminary DDR Timing Information (100 MHz)* Parameter Description AC Input Low Voltage AC Input High Voltage ADDR/CMD Setup to CK (Delay Disabled)1 ADDR/CMD Setup to CK (Delay Enabled)1 ADDR/CMD Hold from CK (Delay Disabled)1 ADDR/CMD Hold from CK (Delay Enabled)1 DQ/DM Setup to DQS2 DQ/DM Hold from DQS2 Write Preamble Setup Write Preamble Hold Write Postamble DQS Falling Edge to Next CK Rising Edge Write Command to First DQS Latching Transition DQ Setup to DQS, Memory Reads (PDL = 0)3 DQ Setup to DQS, Memory Reads (PDL = default)3 DQ Hold from DQS, Memory Reads (PDL = 0)4 DQ Hold from DQS, Memory Reads (PDL = default)4 DQS to CK, Memory Controller Reads5 1.00 VREF + 0.35 6.20 5.90 2.00 2.30 1.70 1.50 1.30 5.30 4.70 3.50 9.90 0.40 1.50 2.22 2.30 3.90 11.30 5.50 Min Max VREF - 0.35 Unit V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 17 on page 60 Figure 15 on page 58 Figure * 1. 2. 3. 4. 5. This table contains preliminary information, which is subject to change. Timing reference load (applied to all chip-level outputs) used for all information contained herein is a 30-pF capacitance. Additional ADDR/CMD HOLD is provided by setting configuration bits Dev0:F0:0x54 [30:29]. The specified values apply for both x4 and non-x4 DQ/DM versus DQS write timing, thus includes timing when DM signals act as DQS signals during x4 DIMM write accesses. Minimum refers to DQS lagging DQ and maximum refers to DQS leading DQ. If the PDL is programmed to zero delay, the minimum specification requires that DQS lag DQ by the amount shown so as to meet setup requirements. If the PDL is programmed to the default delay, the maximum specification requires that DQS lead DQ by no more than the amount shown. If the PDL is programmed to zero delay, the maximum specification requires that DQS not lag DQ greater than the amount specified. If the PDL is programmed to the default delay, the maximum specification requires that DQS not lag DQ greater than the amount specified. A violation of this maximum results in the DQS missing the capture of data at the back end of the DQ data valid window. This timing is the minimum and maximum round trip loop timing. The minimum refers to the earliest that DQS can be returned relative to any CLKOUT signal, and the maximum refers to the latest that DQS can be returned relative to CLKOUT with the default specified PDL setting. Chapter 4 Electrical Data 55 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 23: AMD-761 System Controller Preliminary DDR Timing Information(133 MHz)* Symbol VIL (AC) VIH (AC) tADsu tADsu tADhld tADhld tDQsu tDQhld tWPREsu tWPREhld tWpostA tDSsu tDQSdly tDQSQrd tDQSQrd tQHrd tQHrd tDQS2ck Notes: Parameter Description AC Input Low Voltage AC Input High Voltage ADDR/CMD Setup to CK (Delay Disabled)1 ADDR/CMD Setup to CK (Delay Enabled)1 ADDR/CMD Hold from CK (Delay Disabled)1 ADDR/CMD Hold from CK (Delay Enabled)1 DQ/DM Setup to DQS2 DQ/DM Hold from DQS2 Write Preamble Setup Write Preamble Hold Write Postamble DQS Falling Edge to Next CK Rising Edge Write Command to First DQS Latching Transition DQ Setup to DQS, Memory Reads (PDL = 0)3 DQ Setup to DQS, Memory Reads (PDL = default)3 DQ Hold from DQS, Memory Reads (PDL = 0)4 DQ Hold from DQS, Memory Reads (PDL = default)4 DQS to CK, Memory Controller Reads5 Min VREF + 0.35 4.30 4.00 1.70 2.00 1.20 1.00 0.80 3.90 3.50 2.20 7.50 0.40 Max VREF - 0.35 Unit V V ns ns ns ns ns ns ns ns Figure Figure 15 on page 58 5.00 ns ns 8.80 ns ns 1.00 3.10 1.60 1.00 3.90 ns ns ns ns Figure 17 on page 60 * 1. 2. 3. 4. 5. This table contains preliminary information, which is subject to change. Timing reference load (applied to all chip-level outputs) used for all information contained herein is a 30-pF capacitance. A CL of 2.5 is used unless otherwise indicated. Additional ADDR/CMD HOLD is provided by setting configuration bits Dev0:F0:0x54 [30:29]. The specified values apply for both x4 and non-x4 DQ/DM versus DQS write timing, thus includes timing when DM signals act as DQS signals during x4 DIMM write accesses. Minimum refers to DQS lagging DQ and maximum refers to DQS leading DQ. If the PDL is programmed to zero delay, the minimum specification requires that DQS lag DQ by the amount shown so as to meet setup requirements. If the PDL is programmed to the default delay, the maximum specification requires that DQS lead DQ by no more than the amount shown. If the PDL is programmed to zero delay, the maximum specification requires that DQS not lag DQ greater than the amount specified. If the PDL is programmed to the default delay, the maximum specification requires that DQS not lag DQ greater than the amount specified. A violation of this maximum results in the DQS missing the capture of data at the back end of the DQ data valid window. This timing is the minimum and maximum round trip loop timing. The minimum refers to the earliest that DQS can be returned relative to any CLKOUT signal and the maximum refers to the latest that DQS can be returned relative to CLKOUT with the default specified PDL setting. 56 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet DDR Write Timing Figure 14 on page 57 shows a DDR interface output block diagram. Figure 15 on page 58 shows basic AC timing for DDR write cycles. Note: All information shown under DDR Write Timing is preliminary. To Chip I/O Buffers early_CCLK PLL CCLK2X D set Q Q CK CK/ clr unbuf_CCLK2X Clock Buffers D set Q Q ADDR/CMD unbuf_CCLK Clock Buffers clr D set Q Q Q Q DQS D clr set DQS_EN Memory Controller Logic clr D set Q Q DQ/DM clr Figure 14. AMD-761TM System Controller DDR Interface Outputs Conceptual Block Diagram Chapter 4 Electrical Data 57 58 tDQSdly tADsu CK tADhld tCK ADDR/CMD tDSsu tWPREhld tWpostA DQS tWPREsu AMD-761TM System Controller Data Sheet Preliminary Information Electrical Data Chapter 4 DQ/DM tDQsu tDQhld Note: Timing parameter symbols defined at controller interface, not at memory device interface. Figure 15. Address/Command and Memory Write Cycle Timing 24088B--August 2001 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet DDR Read Timing Figure 16 shows a block diagram of the AMD-761 system controller DDR interface inputs, and Figure 17 on page 60 shows memory read cycle timing. Note: All information shown under preliminary. DDR Read Timing is From Chip I/O Buffers CCLK From PLL DQ D set Q Q Q Q . DQS PDL D clr set Memory Controller Logic clr Figure 16. AMD-761TM System Controller DDR Interface Inputs Conceptual Block Diagram Chapter 4 Electrical Data 59 60 DQS tQHrd (max) Case 1: AMD-761TM System Controller Data Sheet tDQSQrd (min) DQ tCKhi tCKlo Preliminary Information Electrical Data Chapter 4 CK Read tDQSQ2CK ADDR/CMD DQS Case 2: tDQSQrd (max) 24088B--August 2001 DQ Note: Timing parameter symbols defined at controller interface, not at memory device interface (CAS latency = 2 shown unregistered). Figure 17. Memory Read Cycle Timing Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 4.5.3 AGP/PCI Signals The valid delay and float timings for output signals during functional operation are relative to the rising edge of the given clock. The maximum valid delay timings are provided to allow a system designer to determine if setup times can be met. Likewise, the minimum valid delay timings are used to analyze hold times. The setup and hold time requirements for the AMD-761 system controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-761 system controller. Figure 18 shows the relationship between the rising clock edge and setup, hold, and valid data timings. Valid Delay, Float, Setup, and Hold Timings Data In CLK tvd tsu th Data Out tvd Figure 18. Setup, Hold, and Valid Delay Timings The 4x AGP interface of the AMD-761 system controller can operate in three modes -- 1x, 2x, and 4x, and complies to the AGP specification parameters. The timings for the 1x mode, shown in Table 24 on page 62, are relative to AGPCLK. The timings for the 2x mode, shown in Table 25 on page 63, are relative to the respective strobe. The timings for the 4x mode, shown in Table 26 on page 64, apply only to the inner loop 4x clock mode signals (AD, C/BE#, and SBA). Figure 19 on page 64 shows an AGP 2x strobe/data turnaround timing diagram. Figure 20 on page 65 and Figure 21 on page 65 show AGP 2x and 4x timing diagrams, respectively. Figure 22 on page 66 shows an AGP 4x strobe/data turnaround timing diagram. AGP Interface Timing Chapter 4 Electrical Data 61 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 24. Symbol AGP 1x Mode Timings* Parameter Description Preliminary Data Min Max Input Signal Requirements 5.5 ns Figure Notes tsu th A_AD[31:0] Setup Time Setup time for A_FRAME#A_STOP# A_TRDY#A_DEVSEL# A_IRDY#A_C/BE[3:0]# A_REQ# ADSTB[1:0] SBA[7:0] SBSTB RBF#WBF# A_PAR PIPE# A_AD[31:0] Hold Time Hold time for A_FRAME#A_STOP# A_TRDY#A_DEVSEL# A_IRDY#A_C/BE[3:0]# A_REQ# ADSTB[1:0] SBA[7:0] SBSTB RBF#WBF# A_PAR A_SERR# PIPE# A_AD[31:0] Valid Delay A_C/BE[3:0]# Valid Delay Valid Delay for A_FRAME#A_STOP# A_TRDY#A_DEVSEL# A_IRDY#A_GNT# ST[2:0] Float Delay (Active to Float) 18 1 6 ns 18 1 0 ns 18 1 0 ns 18 1 Output Signal Characteristics 1 ns 6.0 ns 1 ns 5.5 ns 18 18 1 1 tvd 1 ns 5.5 ns 18 1 tfd ton Note: 1 ns 1 ns 14 ns 6 ns Turn-on Delay (Float to Active) * This table contains preliminary information, which is subject to change. 1. These signals are specified with a 10-pF load. 62 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 25. Symbol AGP 2x Mode Timings* Parameter Description Preliminary Data Min 6 ns 1 ns 1 ns 1 ns 2 ns 12 ns 20 ns 1.9 ns 1.7 ns 1 ns 6 ns -1 ns 12 ns 10 ns 9 ns 20 20 20 20 20 20 19 19 19 1 1 1 1 Max Figure Notes Input Signal Requirements tRSsu tRSH tDsu tDh tTSf tTSr tDVa tDVb tfd tOFFS toNd Note: Receive Strobe Setup Time to AGPCLK Receive Strobe Hold Time from AGPCLK Data Setup Time Relative to Strobe Data Hold Time Relative to Strobe AGPCLK to Transmit Strobe Falling AGPCLK to Transmit Strobe Rising Data Valid Delay after Strobe Data Valid before Strobe Float Delay (Active to Float) Strobe Rising Edge to Strobe Float Delay Turn-on Delay (Float to Active) Output Signal Characteristics * This table contains preliminary information, which is subject to change. 1. These signals are specified with a 10-pF load. Chapter 4 Electrical Data 63 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 26. Symbol AGP 4x Mode Timings* Parameter Description Preliminary Data Min Max Figure Notes Transmitter Output Signals tTSf tTSr tDvb tDva tONd tOFFd tONS tOFFS tRSsu tRSh tDsu tDhld Note: CLK to First Transmit Strobe Transition CLK to Fourth Transmit Strobe Transition Data Valid Before Strobe Data Valid After Strobe Float to Active Delay Active to Float Delay Strobe Active to First Strobe Edge Setup Last Strobe Edge to Strobe Float Delay 1.9 ns 8 ns 20 ns 21 21 21 21 -0.95 ns 1.15 ns -1 ns 1 ns 4 ns 4 ns 7 ns 14 ns 9 ns 9 ns 22 22 22 22 Receiver Input Signals Receive Strobe Setup Time to CLK Receive Strobe Hold Time from CLK Data to Strobe Setup Time Strobe to Data Hold Time 6 ns 0.5 ns 0.40 ns 0.70 ns 21 21 1 1 * This table contains preliminary information, which is subject to change. 1. These specifications refer to the setup and hold times for the strobe set started in the previous cycle. AGPCLK AD Strobe tOFFS tfd tONd tONS Figure 19. AGP 2x Strobe/Data Turnaround Timings 64 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet AGPCLK AMD-761TM Transmit Data tDVb AMD-761 Transmit Strobe ttTSf tTSr AMD-761 Receive Data AMD-761 Receive Strobe tDsu tDh tDSu tDh Data1 Data2 Data3 Data4 Data1 tDVa Data2 tDVb tDVa Data3 Data4 Figure 20. AGP 2x Timing Diagram AGPCLK tTSf (max) Transmit Strb/Strb# tDVb Transmit Data tDVa 1 2 31 4 5 6 7 8 tTSr (max) Receive Strb/Strb# tDSu Receive Data tDhld Figure 21. AGP 4x Timing Diagram Chapter 4 Electrical Data 65 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 AGPCLK AD Strobe tOFFS tOFFD tONd tONS Figure 22. AGP 4x Strobe/Data Turnaround Timing PCI Interface Timings Table 27 on page 67 shows the PCI interface timings. All of the timings are relative to PCLK. 66 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 27. PCI Interface Timings* Symbol Parameter Description AD[31:0] Setup Time SBREQ#, REQ[6:0]# Setup Time tsu Setup Time for FRAME# STOP# TRDY# DEVSEL# IRDY# C/BE[3:0]# WSC# PAR AD[31:0] Hold Time th Hold Time for FRAME# STOP# TRDY# DEVSEL# IRDY# C/BE[3:0]# SBREQ# REQ[3:0]# WSC# PAR AD[31:0] Valid Delay (address phase) AD[31:0] Valid Delay (data phase) tvd Valid Delay for FRAME# STOP# TRDY# DEVSEL# IRDY# C/BE[3:0]# GNT[3:0]# WSC# PAR SBGNT# Valid Delay tfd tpw Note: Preliminary Data Min 7 ns 12 ns Max Figure 18 18 Notes RESET# 7 ns 18 0 ns 18 0 ns 18 2 ns 2 ns 11 ns 11 ns 18 18 1 1 2 ns 11 ns 18 1 2 ns 12 ns 28 ns 18 1 18 Float Delay for FRAME# STOP# TRDY# DEVSEL# IRDY# C/BE[3:0]# WSC# RESET# Pulse Width 2 clks * This table contains preliminary information, which is subject to change. 1. Measurements are taken with no load for tmin, and 50 pF for tmax. Chapter 4 Electrical Data 67 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 4.5.4 AMD AthlonTM Processor System Bus Timings Table 28 on page 68 shows the AMD Athlon system bus timings. Table 28. Group AMD AthlonTM Processor System Bus/AMD-761TM System Controller AC Specification* Symbol TNB-SKEWSAMEEDGE Parameter Description Output skew with respect to the same clock edge Output skew with respect to a different clock edge Input Data Setup Time Input Data Hold Time Signal or Clock Rise Time Signal or Clock Fall Time Data Pin Capacitance Input Clock Capacitance SYSCLK to Synchronous Signal Output at Pad (CONNECT, CLKFWDRST) Input Setup Time for Synchronous Signal to SYSCLK (PROCRDY) Input Hold Time for Synchronous Signal to SYSCLK (PROCRDY) Minimum - - 500 800 1 1 4 4 2400 1500 1200 Nominal - - - - - - - - - - - Maximum 400 1025 - - 3 3 12 12 4800 - - Units ps ps ps ps V/ns V/ns pF pF ps ps ps 4, 5 4, 5 4, 5 Notes 1 1 1, 2 1, 2 Clock Forward Group Signals Sync Signals *3 Notes: TNB-SKEWDIFFEDGE TNB-SU TNB-HD TRISE TFALL CDATA CINCLK TO-PAD TNB-SYSCLKTNB-SETUPTNB-HOLD-FRO TO-SYSCLK M-SYSCLK * This table contains preliminary information, which is subject to change. 1. TNB-SKEW-SAMEEDGE is the maximum skew within a clock-forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. TNB-SKEW-DIFFEDGE is the maximum skew within a clock-forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 2. Input SU and HLD times are with respect to the appropriate clock forward group input clock. 3. The synchronous signals include PROCREADY, CONNECT, and CLKFWDRST. 4. This value is measured with respect to the rising edge of SYSCLKIN. 5. Test load = 25 pF. 68 Electrical Data Chapter 4 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 5 Package Specifications Figure 23 shows the package specifications for the AMD-761TM system controller. Tables 29, 30, and 31, starting on page 70, contain information about the symbols shown in the figures. Top View Bottom View Dwg rev AB; 11/99 Figure 23. 569-Ball Plastic Ball Grid Array (PBGA) Package Chapter 5 Package Specifications 69 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 29. 1 2 3 4 5 6 7 8 9 10 Symbol Notes (unless specified otherwise) Description Dimensions and tolerances conform to ASME Y14.5M-1994. All dimensions are in millimeters. Dimension `b' is measured at the maximum solder ball diameter on a plane parallel to Datum C. Datum C and the seating plane are defined by the spherical crowns of the solder balls. A1 corner I.D. is marked by ink. Number of peripheral rows or columns. Height from encapsulation to seating plane. "S" is measured with respect to datums A and B and defines the position of the solder balls nearest the package centerlines. When there is an odd number of solder balls in the outer row, "S" = .000. When there is an even number of solder balls in the outer row, the value "S" = e/2. Conforms to JEP-95, MO-151, Issue B, Variation BAT-1. Clearance from encapsulation edge to solder ball closest point to be 0.5 mm minimum. Symbol Table 30. Symbol A A1 A2 A3 7 D D1 E E1 M N MR 6 b e P S S 569-Pin PBGA 37.50-mm by 37.50-mm Package Specifications Minimum 2.20 0.50 0.51 0.20 Nominal 2.33 0.60 0.56 0.30 37.50 BSC. 35.56 BSC. 37.50 BSC. 35.56 BSC. 29 x 29 569 6 0.60 0.75 1.27 BSC. 34.50 REF. 0.635 BSC. 0.635 BSC. 0.90 Maximum 2.46 0.70 0.61 0.45 Description Overall thickness Ball height Body thickness Seating plane clearance Body size Ball footprint Body size Ball footprint Ball matrix size Total ball count Number of rows deep Ball diameter Ball pitch Encapsulation area Solder ball placement Solder ball placement 70 Package Specifications Chapter 5 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 31. Symbol aaa bbb ccc Geometric Tolerances Tolerance 0.15 0.15 0.15 Description Coplanarity Parallelism Flatness Chapter 5 Package Specifications 71 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 72 Package Specifications Chapter 5 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 6 1 A B C D E F G H J K L MDAT10 DM1 Pin Designations 2 3 4 5 6 7 8 9 10 11 MECC5 VSS25 12 DQS08 MECC1 13 14 15 16 17 18 19 20 DM5 21 22 23 24 25 26 27 28 29 A B MDAT62 DQS07 MDAT21 MDAT18 MDAT22 MDAT24 MDAT25 DQS03 MDAT26 MECC4 MDAT11 MDAT16 VSS33 DM2 VSS31 MDAT19 MDAT29 VSS32 MDAT30 MDAT31 DM3 MECC6 MDAT32 MDAT36 DQS04 MDAT38 MDAT39 MDAT40 MECC2 DM8 VSS26 MDAT37 DM4 DQS05 MDAT43 MDAT52 MDAT49 MDAT54 MDAT50 MDAT51 MDAT42 MDAT47 VSS29 MDAT53 DQS06 DM6 VSS30 MDAT60 MDAT56 DM7 VSS27 MDAT35 MDAT45 VSS28 WEB# MDAT20 MDAT17 DQS02 MDAT23 MDAT28 MAA03 MDAT27 CLKOUT3 MECC0 MECC7 MDAT33 MDAT34 MAB14 MDAT44 MDAT41 NC0 MAB10 VDD_COR MAA13 E2 MAA10 MAA14 MAB13 MDAT46 MDAT48 CS03# MDAT55 MDAT61 MDAT57 C D E F G H J K L MDAT14 MDAT15 MAB08 VDD_COR MAB06 E6 MAA08 MAA05 MAB05 VSS40 MAA04 VDD_COR MAA02 E7 MAA06 VSS41 MAB04 VSS42 MAB03 MAB01 VDD_COR CLKOUT0 MECC3 VDD_COR E0 E1 MAB02 MAA01 CLKOUT3# CLKOUT0# MAA00 RASB# VDD_COR CS02# E3 RASA# WEA# CASB# CS00# VDD_COR CS04# E4 CASA# VSS37 CS01# VSS38 CS05# CS06# VDD_COR CLKOUT5# VSS34 E5 MDAT09 MDAT13 DSQ01 MDAT12 VSS35 MAB00 CS07# CLKOUT2 MDAT63 MDAT58 MDAT59 PCICLK SYSCLK MAA07 VDD_COR MAB07 E14 MAB09 VSS43 VDD_COR VDD_COR VDD_COR E8 E9 E10 VDD_COR VDD_COR VDD_COR VSS36 E11 E12 E13 VSS39 CLKOUT2# CLKOUT5 AGPCLK MDAT07 MDAT03 MDAT08 MAA09 VSS46 VSS44 DCSTOP# VDD_COR S_CLKREF VSS45 AGP_CAL# E15 VSS47 TEST# RESET# AVDD AGP_CAL NC2 NC1 DQS00 MDAT06 MDAT02 MAA11 DM0 VSS49 MAB11 VSS48 VSS51 CKEB VDD_COR MAB12 E16 VSS50 A_AD00 A_AD02 A_AD01 A_AD03 MDAT00 MDAT05 MDAT01 MAA12 CKEA VDD_COR E17 VDD_AGP A_AD04 VDD_AGP A_AD06 VSS52 A_AD05 1 2 VDD_AGP A_AD09 A_CBE0# A_ADSTB0# A_AD08 A_AD07 3 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VDD_AGP A_AD13 A_AD11 A_ADSTB0 A_AD12 A_AD10 4 SADDROUT DDR_REF MDAT04 CLKOUT CLKOUT4# VDD_COR 14# 4 E18 SADDROUT VSS60 SADDROUT VDD_COR CLKOUT1# VDD_COR 13# 07# E E20 19 SAD- SADDROUTSADDROUT P0_CAL# CLKOUT1 DROUT- 12# 09# CLK# SADDROUT SADDROUTSADDROUT NC3 08# 05# 06# P0_CAL M M N VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 A_PAR VDD_AGP A_AD15 VSS68 A_AD14 5 N P R T U V W Y AA AB AC AD AE AF AG AH AJ VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 A_TRDY# A_STOP# A_DEVSEL# A_SERR# A_CBE1# P R T U V W Y SADDROUT VSS83 SADDROUTK7_VCORE SADDROUT 02# 10# 10 11# SADDROUT SDATAOUT SCHECK6# SADDROUT SDATA55# 03# CLK3# 04# SDATA53# SDATA49# SDATA63#SDATA54_SDATA52# SDATAINCL VSS106 SDATA61# K7_VCORE SDATA50#K7_VCORE K3# 11 12 SDATA62# SDATA60# SCHECK7# SDATA51# SDATA48#K7_VCORE 13 SDATA59# SDATA58# SDATA57# SDATA36# SDATA46#K7_VCORE 14 SDATA39# VSS0 SDATA37# K7_VCORE SDATA35# VSS2 0 SDATA56# SDATA47# SDATA38# SCHECK4# SDATA34# VSS5 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 AGP_VREFA_FRAME# A_AD17 A_CBE2# A_IRDY# VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 AGP_VREF VDD_AGP A_AD16 VSS91 4X 6 A_AD19 VSS92 VSS99 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 A_AD20 A_AD18 A_ADSTB1 A_AD23 A_AD21 VDD_AGP A_CBE3# A_AD22 A_AD27 A_AD25 A_ADSTB1# 7 VDD_AGP A_AD26 VDD_AGP A_AD24 VSS107 A_AD29 8 9 VDD_AGP A_AD30 A_AD28 A_SBA4 A_SBA6 A_AD31 10 VSS1 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 A_SBA5 A_SBA7 A_SBA2 A_SBSTB A_SBSTB# AA VSS3 A_SBA1 VDD_AGP A_SBA3 0 WSC# A_WBF# A_ST0 VSS4 A_SBA0 AB AC AD AE AF AG AH AJ SDATA45# SDATA44# SDATAIN SDATA33# SDATA32# VSS7 CLK2# SCHECK5# VSS8 SDATAOUT K7_VCORE SDATA30# VSS10 CLK2# 4 VSS11 VSS12 VSS13 K7_VCOREK7_VCOREK7_VCORE 1 2 3 AD29 AD25 VSS6 A_ST2 A_RBF# VDD_PCI0 VDD_PCI1 VDD_PCI2 VDD_PCI3 VDD_PCI4 VDD_PCI5 VSS9 SBGNT# REF_5V A_GNT# A_ST1 A_REQ# SDATA43# SDATA42# SDATA41# SDATA31# SI_VDD SDATAINCL SDATA28# SDATA27# SDATA24# SDATA01# SCHECK1# SDATA10# SADDRIN0 SADDRIN0 CONNECT K1# 7# 8# SDATA40# SDATAOUT VSS15 CLK1# AD23 AD17 IRDY# SERR# AD14 AD10 AD07 AD03 AD00 SBREQ# VSS14 A_PIPE# SI_VSS SCHECK3# SDATA29#K7_VCORE SDATA25# SDATA15# K7_VCORE SDATA08# SDATAOUT K7_VCORE SDATAIN- CLKFW- K7_VCORE AD27 8 5 CLK0# 6 VALID# DRST 7 GNT6# CBE3# AD21 CBE2# DEVSEL# CBE1# AD12 AD08 AD05 AD01 AD06 AD04 AD02 VSS16 SDATA23# SDATA22# SDATA19# K7_VCORE SDATA17# SDATA26# SCHECK0# SDATAINCL SDATA12# SDATA14# SADDRIN0 SADDRIN0 SADDRIN0 SADDRIN1 AD31 9 K0# 5# 6# 4# 3# P0_VREF SDATA21# SCHECK2# SDATA18# SDATA16# VSS23 SDATA04# SDATA03# VSS20 SDATA11# SADDRIN1 VSS21 SADDRIN1 SADDRIN- VSS22 1# 0# CLK# GNT4# VSS17 GNT2# REQ0# VSS18 AD24 AD20 FRAME# VSS19 AD13 AD09 CBE0# REQ6# REQ5# REQ3# REQ2# REQ1# AD30 AD26 AD22 AD16 STOP# AD15 AD11 SDATA20# VSS24 SDATA07# SDATA06# SDATA05# SDATA02# SDATA00# SDATA13# SDATA09# SADDRIN0 SADDRIN0 SADDRIN0 SADDRIN1 SADDRIN0 PROCRE- GNT5# 2# 3# 9# 4# 12# ADY REQ4# GNT3# GNT1# GNT0# AD28 AD19 AD18 TRDY# PAR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Chapter 6 Pin Designations 73 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 32. Name MAA[14] MAA[13] MAA[12] MAA[11] MAA[10] MAA[09] MAA[08] MAA[07] MAA[06] MAA[05] MAA[04] MAA[03] MAA[02] MAA[01] MAA[00] MAB[14] MAB[13] MAB[12] MAB[11] MAB[10] MAB[09] MAB[08] MAB[07] MAB[06] MAB[05] MAB[04] MAB[03] MAB[02] MAB[01] MAB[00] DM[8] DM[7] DM[6] DM[5] DM[4] DM[3] DM[2] DM[1] DM[0] CS[7]# CS[6]# CS[5]# CS[4]# CS[3]# CS[2]# CS[1]# AMD-761TM System Controller Pin Functional Grouping (1 of 3) No. E-17 D-18 K-4 H-4 E-16 G-4 E-4 F-3 E-7 E-5 D-7 C-8 D-9 E-11 E-14 C-17 E-18 J-5 H-5 D-16 G-5 D-4 F-5 D-6 E-6 E-8 E-9 E-10 D-10 E-15 C-13 C-28 C-24 A-20 B-16 C-9 B-4 D-1 J-1 E-25 D-25 E-24 D-24 C-23 D-21 E-23 Name CS[0]# RASB# RASA# CASB# CASA# WEB# WEA# CKEB CKEA DQS[8] DQS[7] DQS[6] DQS[5] DQS[4] DQS[3] DQS[2] DQS[1] DQS[0] CLKOUT[5] CLKOUT[5]# CLKOUT[4] CLKOUT[4]# CLKOUT[3] CLKOUT[3]# CLKOUT[2] CLKOUT[2]# CLKOUT[1] CLKOUT[1]# CLKOUT[0] CLKOUT[0]# MDAT[63] MDAT[62] MDAT[61] MDAT[60] MDAT[59] MDAT[58] MDAT[57] MDAT[56] MDAT[55] MDAT[54] MDAT[53] MDAT[52] MDAT[51] MDAT[50] MDAT[49] MDAT[48] DDR DRAM No. Name D-22 MDAT[47] D-19 MDAT[46] E-19 MDAT[45] E-21 MDAT[44] E-22 MDAT[43] C-20 MDAT[42] E-20 MDAT[41] J-3 MDAT[40] K-5 MDAT[39] A-12 MDAT[38] D-29 MDAT[37] B-25 MDAT[36] A-21 MDAT[35] A-16 MDAT[34] A-8 MDAT[33] C-5 MDAT[32] E-3 MDAT[31] H-1 MDAT[30] F-26 MDAT[29] D-27 MDAT[28] L-4 MDAT[27] L-5 MDAT[26] C-11 MDAT[25] E-12 MDAT[24] E-26 MDAT[23] F-25 MDAT[22] N-5 MDAT[21] M-5 MDAT[20] D-12 MDAT[19] E-13 MDAT[18] E-27 MDAT[17] C-29 MDAT[16] C-26 MDAT[15] B-27 MDAT[14] E-29 MDAT[13] E-28 MDAT[12] C-27 MDAT[11] B-28 MDAT[10] C-25 MDAT[09] A-25 MDAT[08] B-24 MDAT[07] A-23 MDAT[06] A-27 MDAT[05] A-26 MDAT[04] A-24 MDAT[03] C-22 MDAT[02] No. B-22 C-21 B-19 C-18 A-22 B-21 C-19 A-19 A-18 A-17 B-15 A-15 B-18 C-16 C-15 A-14 B-10 B-9 B-7 C-7 C-10 A-9 A-7 A-6 C-6 A-5 A-3 C-3 B-6 A-4 C-4 B-3 D-3 D-2 E-2 F-1 B-2 C-1 E-1 G-3 G-1 H-2 K-2 L-3 G-2 H-3 Name MDAT[01] MDAT[00] MECC[7] MECC[6] MECC[5] MECC[4] MECC[3] MECC[2] MECC[1] MECC[0] No. K-3 K-1 C-14 A-13 A-11 A-10 D-13 B-13 B-12 C-12 AGP Name ADSTB[1] ADSTB[1]# ADSTB[0] ADSTB[0]# SBSTB SBSTB# WBF# PIPE# RBF# SBA[0] SBA[1] SBA[2] SBA[3] SBA[4] SBA[5] SBA[6] SBA[7] ST[0] ST[1] ST[2] AGPCLK No. U-27 V-29 M-27 L-27 AA-28 AA-29 AC-26 AE-29 AC-29 AB-29 AB-25 AA-27 AB-27 Y-27 AA-25 Y-28 AA-26 AC-27 AD-28 AC-28 F-27 APCI Name A_AD[31] A_AD[30] A_AD[29] A_AD[28] A_AD[27] A_AD[26] A_AD[25] A_AD[24] A_AD[23] A_AD[22] A_AD[21] A_AD[20] A_AD[19] A_AD[18] A_AD[17] A_AD[16] A_AD[15] A_AD[14] A_AD[13] A_AD[12] A_AD[11] A_AD[10] A_AD[09] A_AD[08] A_AD[07] A_AD[06] A_AD[05] A_AD[04] A_AD[03] A_AD[02] A_AD[01] A_AD[00] A_CBE[3]# A_CBE[2]# A_CBE[1]# A_CBE[0]# A_DEVSEL# A_FRAME# A_GNT# A_IRDY# A_PAR A_REQ# A_SERR# A_STOP# A_TRDY# No. Y-29 Y-25 W-29 Y-26 V-27 W-25 V-28 W-27 U-28 V-26 U-29 U-25 T-29 U-26 R-27 T-27 N-27 N-29 M-25 M-28 M-26 M-29 L-25 L-28 L-29 K-27 K-29 K-25 J-29 J-26 J-28 J-25 V-25 R-28 P-29 L-26 P-27 R-26 AD-27 R-29 N-25 AD-29 P-28 P-26 P-25 74 Pin Designations Chapter 6 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 33. Name AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[09] AD[08] AD[07] AD[06] AD[05] AD[04] AD[03] AD[02] AD[01] AD[00] CBE[3]# CBE[2]# CBE[1]# CBE[0]# PCICLK DEVSEL# FRAME# WSC# IRDY# PAR SERR# STOP# TRDY# REQ[0]# AMD-761TM System Controller Pin Functional Grouping (2 of 3) PCI Bus No. Name AG-16 REQ[1]# AH-22 REQ[2]# AE-16 REQ[3]# AJ-23 REQ[4]# AF-17 REQ[5]# AH-23 REQ[6]# AE-17 GNT[0]# AG-23 GNT[1]# AE-18 GNT[2]# AH-24 GNT[3]# AF-19 GNT[4]# AG-24 GNT[5]# AJ-24 GNT[6]# AJ-25 SBREQ# AE-19 SBGNT# AH-25 RESET# AH-27 AE-22 AG-27 AF-23 AH-28 AE-23 AG-28 AF-24 AE-24 AF-27 AF-25 AF-28 AE-25 AF-29 AF-26 AE-26 AF-18 AF-20 AF-22 AG-29 F-28 AF-21 AG-25 AC-25 AE-20 AJ-27 AE-21 AH-26 AJ-26 AG-21 No. AH-21 AH-20 AH-19 AJ-19 AH-18 AH-17 AJ-22 AJ-21 AG-20 AJ-20 AG-18 AJ-18 AG-17 AE-27 AD-25 H-26 Name CLKFWDRST CONNECT PROCRDY SYSCLK SADDIN[02]# SADDIN[03]# SADDIN[04]# SADDIN[05]# SADDIN[06]# SADDIN[07]# SADDIN[08]# SADDIN[09]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[02]# SADDOUT[03]# SADDOUT[04]# SADDOUT[05]# SADDOUT[06]# SADDOUT[07]# SADDOUT[08]# SADDOUT[09]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCHECK[0]# SCHECK[1]# SCHECK[2]# SCHECK[3]# SCHECK[4]# SCHECK[5]# SCHECK[6]# SCHECK[7]# SDATA[00]# SDATA[01]# SDATA[02]# SDATA[03]# SDATA[04]# SDATA[05]# No. AF-15 AE-15 AJ-17 F-29 AJ-12 AJ-13 AG-14 AG-12 AG-13 AE-13 AE-14 AJ-14 AH-14 AH-12 AJ-16 AG-15 AJ-15 AH-15 R-1 T-1 T-4 P-2 P-3 M-3 P-1 N-3 R-3 R-5 N-2 M-1 L-1 N-1 AG-8 AE-11 AH-4 AF-5 AB-4 AD-1 T-3 W-3 AJ-9 AE-10 AJ-8 AH-9 AH-8 AJ-7 AMD Athlon System Bus Name No. Name SDATA[06]# AJ-6 SDATA[52]# SDATA[07]# AJ-5 SDATA[53]# SDATA[08]# AF-11 SDATA[54]# SDATA[09]# AJ-11 SDATA[55]# SDATA[10]# AE-12 SDATA[56]# SDATA[11]# AH-11 SDATA[57]# SDATA[12]# AG-10 SDATA[58]# SDATA[13]# AJ-10 SDATA[59]# SDATA[14]# AG-11 SDATA[60]# SDATA[15]# AF-9 SDATA[61]# SDATA[16]# AH-6 SDATA[62]# SDATA[17]# AG-6 SDATA[63]# SDATA[18]# AH-5 SDATAINCLK[0]# SDATA[19]# AG-4 SDATAINCLK[1]# SDATA[20]# AJ-3 SDATAINCLK[2]# SDATA[21]# AH-3 SDATAINCLK[3]# SDATA[22]# AG-3 SDATAINVALID# SDATA[23]# AG-2 SDATAOUTCLK[0]# SDATA[24]# AE-9 SDATAOUTCLK[1]# SDATA[25]# AF-8 SDATAOUTCLK[2]# SDATA[26]# AG-7 SDATAOUTCLK[3]# SDATA[27]# AE-8 SDATA[28]# AE-7 SDATA[29]# AF-6 SDATA[30]# AD-5 SDATA[31]# AE-4 SDATA[32]# AC-5 SDATA[33]# AC-4 SDATA[34]# AB-5 SDATA[35]# AA-5 SDATA[36]# Y-4 SDATA[37]# AA-3 SDATA[38]# AB-3 SDATA[39]# AA-1 SDATA[40]# AF-1 SDATA[41]# AE-3 SDATA[42]# AE-2 SDATA[43]# AE-1 SDATA[44]# AC-2 SDATA[45]# AC-1 SDATA[46]# Y-5 SDATA[47]# AB-2 SDATA[48]# W-5 SDATA[49]# U-2 SDATA[50]# V-5 SDATA[51]# W-4 No. U-5 U-1 U-4 T-5 AB-1 Y-3 Y-2 Y-1 W-2 V-3 W-1 U-3 AG-9 AE-6 AC-3 V-1 AF-14 AF-12 AF-2 AD-3 T-2 Chapter 6 Pin Designations 75 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 34. AMD-761TM System Controller Pin Functional Grouping (3 of 3) VDD Name VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_AGP VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI A_VDD VSS No. D-5 D-8 D-11 D-14 D-17 D-20 D-23 D-26 F-4 F-10 F-11 F-12 F-18 F-19 F-20 G-26 J-4 K-6 L-6 M-4 M-6 K-24 K-26 L-24 M-24 N-26 T-26 V-24 W-24 W-26 Y-24 AB-26 AD-18 AD-19 AD-20 AD-21 AD-22 AD-23 H-27 Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS No B-5 B-8 B-11 B-14 B-17 B-20 B-23 B-26 C-2 D-28 F-2 F-6 F-7 F-8 F-9 F-21 F-22 F-23 F-24 G-6 G-24 G-28 H-6 H-24 J-2 J-6 J-24 K-28 M-2 M-12 M-13 M-14 M-15 M-16 M-17 M-18 N-12 N-13 N-14 N-15 N-16 N-17 N-18 N-28 P-12 P-13 Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS No. P-14 P-15 P-16 P-17 P-18 R-2 R-12 R-13 R-14 R-15 R-16 R-17 R-18 T-12 T-13 T-14 T-15 T-16 T-17 T-18 T-28 U-12 U-13 U-14 U-15 U-16 U-17 U-18 V-2 V-12 V-13 V-14 V-15 V-16 V-17 V-18 W-28 AA-2 AA-6 AA-24 AB-6 AB-24 AB-28 AC-6 AC-24 AD-2 Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS No. AD-6 AD-7 AD-8 AD-9 AD-24 AE-28 AF-3 AG-1 AG-19 AG-22 AG-26 AH-7 AH-10 AH-13 AH-16 AJ-4 Miscellaneous Name No. S_CLKREF G-27 DCSTOP# G-25 K7_VCORE0 R-4 K7_VCORE1 V-4 K7_VCORE2 V-6 K7_VCORE3 W-6 K7_VCORE4 Y-6 K7_VCORE5 AA-4 K7_VCORE6 AD-4 K7_VCORE7 AD-10 K7_VCORE8 AD-11 K7_VCORE9 AD-12 K7_VCORE10 AF-7 K7_VCORE11 AF-10 K7_VCORE12 AF-13 K7_VCORE13 AF-16 K7_VCORE14 AG-5 P0_VREF AH-2 P0_CAL P-5 P0_CAL# N-4 SI_VSS AF-4 SI_VDD AE-5 AGP_VREF R-25 AGP_VREF4X T-25 AGP_CAL H-28 AGP_CAL# G-29 REF_5V AD-26 DDR_REF L-2 TEST# H-25 SPARE1 D-15 SPARE2 P-4 SPARE3 H-29 SPARE4 J-27 76 Pin Designations Chapter 6 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 7 Signal Descriptions Table 35 describes the terms used in the signal description table. The signals are organized within the following functional groups: * * * * * * * * Processor interface signals (page 78) PCI interface signals (page 80) DRAM interface signals (page 82) AGP/PCI signals (page 85) AGP-only signals (page 86) Initialization pinstrapping (page 88) Miscellaneous signals (page 87) Pin multiplexing options (page 92) Signal Descriptions Table Definitions Signal Types B I O STS TS Bidirectional Input Output Sustained three-state Three-state Table 35. Table 36 on page 78 contains a description of the AMD-761TM system controller signals. Chapter 7 Signal Descriptions 77 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal Signal Descriptions Type Description Processor Interface Signals CLKFWDRST O AMD AthlonTM System Bus Clock Forward Reset CLKFWDRST resets the source-synchronous clock circuitry for the processor. Forwarded clocks are driven continuously beginning three clocks after CLKFWDRST is negated. This signal is negated by RESET#. It changes on the rising edge of SYSCLK. AMD Athlon System Bus Connect CONNECT is an output from the AMD-761TM system controller and is used for power management and source-synchronous clock initialization at reset. This signal is negated by RESET#. It changes on the rising edge of SYSCLK. AMD Athlon System Bus Processor Ready PROCRDY is an input to the AMD-761 system controller and is used for power management and source-synchronous clock initialization at reset. This signal is sampled on the rising edge of SYSCLK. AMD Athlon System Bus Address/Command The SADDIN[14:2]# is a unidirectional system command bus to the processor. It is used to transfer probe and data movement commands into the processor. SADDIN[14:2]# are skew-aligned with the source-synchronous clock, SADDINCLK#. The AMD-761 system controller drives the SADDIN[14:2]# channel on each edge of SADDINCLK#. AMD Athlon System Bus System Address In Clock SADDINCLK# is the single-ended source-synchronous clock for the SADDIN[14:2]# bus, driven by the AMD-761 system controller. Each clock edge is used to transfer probe and data movement commands to the processor. This signal is driven inactive (negated) when the CLKFWDRST signal is asserted (true). When CLKFWDRST is negated, SADDINCLK# runs continuously after a three clock delay. AMD Athlon System Bus System Address Out The SADDOUT[14:2]# is a unidirectional system address interface from the processor to the AMD-761 system controller. The SADDOUT[14:2]# channel is used to transfer processor requests and probe responses to the system. This channel is skew-aligned with the source-synchronous clock, SADDOUTCLK#. The SADDOUT[14:2]# channel is sampled by the AMD-761 system controller on each edge of SADDOUTCLK#. The AMD-761 system controller samples commands driven by the processor on the SADDOUT[14:2]# channel and forwards them to the PCI bus, AGP bus, or DRAM, depending on the address range and AMD-761 configuration. AMD Athlon System Bus System Address Out Clock SADDOUTCLK# is a single-ended source synchronous clock for the SADDOUT[14:2]# channel driven by the processor. Each edge is used to transfer commands. This signal is driven inactive (negated) when the CLKFWDRST signal is asserted (true). When CLKFWDRST is negated, SADDOUTCLK# runs continuously after a three-clock delay. CONNECT O PROCRDY I SADDIN[14:2]# O SADDINCLK# O SADDOUT[14:2]# I SADDOUTCLK# I 78 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 36. Signal Signal Descriptions (Continued) Type Description AMD AthlonTM System Bus Data Bus Check Byte SCHECK[7:0]# transfer ECC check bits for data transferred on the SDATA[63:0]# bus. As Outputs: The AMD-761 system controller drives SCHECK[7:0]# with each valid data quadword. SCHECK[7:0]# are skew-aligned with the source-synchronous clocks, SDATAINCLK[3:0]#. As Inputs: The AMD-761 system controller samples SCHECK[7:0]# and transfers the data to the memory. The SCHECK[7:0]# is sampled by the AMD-761 system controller on each edge of SDATAOUTCLK[3:0]#. SCHECK[7:0]# are floated by RESET#. Check bits for write data are driven by the processor and check bits for read data are driven by the system controller. The AMD-761 system controller drives the previous data value between transfers to prevent floating inputs. AMD Athlon System Bus Processor Data Channel The SDATA[63:0]# transfer data between the processor and system. As Outputs: The AMD-761 system controller drives SDATA[63:0]# with each valid data quadword. SDATA[63:0]# are skew-aligned with the source-synchronous clocks, SDATAINCLK[3:0]#. As Inputs: The AMD-761 system controller samples SDATA[63:0]# and transfers the data to the memory. The SDATA[63:0]# is sampled by the AMD-761 system controller on each edge of SDATAOUTCLK[3:0]#. SDATA[63:0]# is floated out of RESET#. Write data is driven by the processor and read data is driven by the system controller. The AMD-761 system controller drives the previous data value between transfers to prevent floating inputs. AMD Athlon System Bus System Data In Clock SDATAINCLK[3:0]# is the single-ended source-synchronous clock driven by the AMD-761 system controller to transfer data on SDATA[63:0]# and check bits on SCHECK[7:0]#. Sixteen bits of data and two check bits are skew-aligned with each clock. Data is transferred on each clock edge. These signals are driven inactive (negated) when the CLKFWDRST signal is asserted (true). When CLKFWDRST is negated, SDATAINCLK[3:0]# run continuously after three clock delays. AMD Athlon System Bus System Data In Valid SDATAINVAL# is driven by the AMD-761 system controller and controls the flow of data into the processor. SDATAINVAL# can be used to introduce an arbitrary number of cycles between quadword pairs (128 bits). SDATAINVAL# is skew-aligned with the sourcesynchronous clock, SADDINCLK#. AMD Athlon System Bus System Address Out Clock SDATAOUTCLK[3:0]# is the single-ended source-synchronous clock driven by the processor and is used to transfer data and check bits on the SDATA[63:0]# and SCHECK[7:0]#. Sixteen bits of data and two check bits are skew-aligned with each clock. Data is transferred on each clock edge. These signals are driven inactive (negated) when the CLKFWDRST signal is asserted (true). When CLKFWDRST is negated, SDATAOUTCLK[3:0]# run continuously after three clock delays. SCHECK[7:0]# B SDATA[63:0]# B SDATAINCLK[3:0]# O SDATAINVAL# O SDATAOUTCLK[3:0]# I Chapter 7 Signal Descriptions 79 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal SYSCLK Signal Descriptions (Continued) Type I Description AMD AthlonTM System Bus System Clock SYSCLK is a single-ended input clock signal provided by the system clock generator to the phase locked loop (PLL) of the AMD-761 system controller. Frequencies of 66.67 MHz, 100.00 MHz, or 133.33 MHz are supported. PCI Interface Signals PCI Address/Data Bus This is the multiplexed address/data bus, sampled on the rising edge of PCICLK. The address is valid on AD[31:00] during the first clock when FRAME# is asserted. Write data is valid on AD[31:00] when IRDY# is asserted and read data is valid when TRDY# is asserted. Data transfers occur on AD[31:00] when both IRDY# and TRDY# are asserted. These pins are also used for initialization pinstrapping to configure various startup parameters of the AMD-761 system controller. The initialization pinstraps are configured with a weak pullup or pulldown and sampled by the AMD-761 system controller during system reset. Refer to Section 7.1 on page 88 for further details. PCI Command/Byte Enables During the address phase, these pins define the PCI command. During the data phase these pins are used as byte enables. These pins are also used for initialization pinstrapping to configure various startup parameters of the AMD-761 system controller. The initialization pinstraps are configured with a weak pullup or pulldown and sampled by the AMD-761 system controller during system reset. Refer to Section 7.1 on page 88 for further details. C/BE[1:0]# are also optionally used for connecting an external serial initialization packet (SIP) ROM for processor initialization. This feature is typically used only for test and debug modes. PCI Device Select The AMD-761 system controller asserts this pin when an external bus master drives a valid address within the AMD-761 system controller's memory region, as defined by the PCI Top of Memory register (Dev 0:F0:0x9C). The AMD-761 system controller responds only to memory cycles. This pin is sampled by the AMD-761 system controller when the CPU accesses a PCI target. PCI Cycle Frame The FRAME# pin is asserted by the AMD-761 system controller to indicate the beginning of a bus transaction. FRAME# is sampled by the AMD-761 PCI target controller when an external bus master is performing a transaction on the PCI bus. PCI Bus Grant As the PCI bus arbiter, the AMD-761 system controller asserts one of these device-specific bus grant signals off the rising clock edge to indicate to an initiator that it has been granted control of the PCI bus the next time the bus is idle. GNT[6:0]# signals are never floated. They are negated off the rising edge of the PCICLK input, indicating that no device has been granted the bus. One of the GNT[6:0]# signals is asserted off the rising edge of the clock, indicating the particular channel that is granted use of the bus. These pins are also optionally used in test modes as described in Table 38 on page 92, and in Chapter 3. AD[31:00] B TS C/BE[3:0]# B TS DEVSEL# B STS FRAME# B STS GNT[6:0]# O TS 80 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 36. Signal Signal Descriptions (Continued) Type Description PCI Initiator Ready The AMD-761TM system controller asserts this signal during PCI transactions to indicate that write data is valid or it is ready to receive read data. It is sampled by the AMD-761 system controller during memory transactions by external bus masters to DRAM. This pin is also optionally used in test modes as described in Table 38 on page 92, and in Chapter 3. PCI Bus Parity PAR is used to generate and check for even parity across the AD[31:0] and C/BE[3:0]# pins. The AMD-761 system controller generates but does not check parity. This pin is also optionally used in test modes as described in Table 38 on page 92, and in Chapter 3. PCI Clock PCICLK is a 33.33-MHz clock provided by the system clock generator. It is used by the AMD-761 system controller logic in the PCI clock domain. PCI Grant to Peripheral Bus Controller SBGNT# grants control of the PCI bus to the PCI-ISA/IDE bridge functions implemented in the AMD-766TM peripheral bus controller. SBGNT# is driven off the rising edge of PCICLK. RESET# forces SBGNT# inactive. SBGNT# is asserted in response to a SBREQ#. SBGNT# and GNT[6:0]# all grant control of the bus to an external device. Only one is asserted at any time. PCI Request from Peripheral Bus Controller The AMD-761 system controller samples SBREQ# to determine if the AMD-766 peripheral bus controller needs PCI bus access. This signal is sampled by the rising edge of every PCICLK. If asserted, the arbiter issues a SBGNT# when the bus is available. PCI Bus Request As the PCI bus arbiter, the AMD-761 system controller samples these device-specific bus request signals to determine if another agent requires control of the PCI bus. These signals are sampled by the rising edge of every PCICLK. If active, the arbiter issues the corresponding GNT[6:0]# when the bus is available. System Reset Asserting RESET# resets the AMD-761 system controller and sets all register bits to their default values (except memory controller registers as required for ACPI S3 support). Bidirectional signals are three-stated and outputs are driven inactive. RESET# is driven by the PCIRST# output of the AMD-766 peripheral bus controller. See "Pin States at Reset" on page 92. This signal may be asynchronous to SYSCLK and PCICLK. It is synchronized internally, therefore it must be active for a minimum of four PCICLK periods. PCI System Error SERR# is used by the AMD-761 system controller to transfer GART errors, ECC errors, or AGP A_SERR# pin assertion errors to error reporting logic on the AMD-766 peripheral bus controller. IRDY# B STS PAR B TS PCICLK I SBGNT# O TS SBREQ# I REQ[6:0]# I RESET# I SERR# O OD Chapter 7 Signal Descriptions 81 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal STOP# Signal Descriptions (Continued) Type B STS Description PCI Stop As a target, the STOP# signal is asserted by the AMD-761TM system controller PCI target logic to initiate a target disconnect, ending the current transfer. As a master, the AMD-761 system controller ends the current transfer when it samples the STOP# signal asserted. PCI Target Ready TRDY# is asserted by the AMD-761 system controller during accesses of DRAM by an external bus master when read data is valid or when the target logic is ready to receive write data. This signal is sampled by the AMD-761 PCI master logic when the AMD-761 system controller is accessing an external PCI target. This pin is also optionally used in test modes as described in Table 38 on page 92, and in Chapter 3. PCI Write Snoop Complete WSC# is asserted to indicate that all snoop activity on the processor bus on behalf of the last PCI-to-DRAM write transaction has completed. It indicates that an APIC interrupt message can be sent by the Southbridge. This signal is required only in configurations where an I/O APIC is installed. The WSC# pin is driven and sampled by the AMD-761 system controller on the rising edge of PCICLK. The AMD-761 system controller supports a bidirectional WSC# configuration by default for connection to Southbridges that drive a request on the WSC# pin as well as receive an acknowledge on the WSC# pin. On silicon revisions B4 and above, the AMD-761 system controller also supports a unidirectional WSC# mode for Southbridges that do not drive the WSC# pin. Refer to Chapter 2 on page 7 for details of WSC# operation. TRDY# B STS WSC# B TS Note: DDR DRAM Interface Signals DDR outputs are SSTL-2 compatible. DDR DIMM Chip Selects CS[7:0]# function as chip-select signals for the DDR DRAMs. These signals are negated by RESET#. The memory controller asserts or negates these signals relative to CLKOUT at the appropriate time in the memory access sequence. CS[7:0]# are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. DDR Data Masks/Data Strobes (for x4 DIMMs only) DM[8:0] provides data masks for each byte during DDR writes to x8 and x16 DIMMs only. For x4 DIMMs, these pins are used to provide the additional DQS pins required in x4 DIMM configurations. DM signals are not provided by x4 DIMMs. In the absence of the DM function, partial writes result in full-line read-modify-write cycles with all bytes being written active on the DIMM. These control signals are three-stated by RESET# and remain three-stated until driven by the AMD-761 system controller during writes or by the DDR DRAM during reads. During DDR writes to x8 and x16 DIMMs, the memory controller asserts or negates these signals relative to the DQS[8:0] clock signals (described below). For x4 DIMMs, these pins function as additional DQS strobe signals. See Chapter 2, "Functional Operation" starting on page 7 for more information. CS[7:0]# O DM[8:0] B 82 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 36. Signal Signal Descriptions (Continued) Type Description DDR Data Strobes DQS[8:0] are bidirectional data strobes between the memory devices and the memory controller that are used to capture data. The data strobes (DQS signals) are sourcesynchronous, which means that the DQS signals are driven by the device that is driving the data. The source-synchronous strobe scheme is also referred to as the clock-forwarded scheme. The AMD-761 system controller provides one DQS signal per byte of data for x8 and x16 DIMMs or one DQS signal per nibble of x4 DIMMs. During a x4 DIMM access, the DM pins provide the additional DQS strobe signals, which function the same as the DQS strobe signals. An access to a x4 DIMM requires 18 data strobes (including ECC), which are the DQS[8:0] and DM[8:0] pins combined. The AMD-761 system controller implements a DQS scheme on the DDR interface that is similar to the clock-forwarded scheme used on the AMD Athlon system bus interface. DDR Memory Address The multiplexed row and column address bits MAA[14:0] and MAB[14:0] connect to the system DDR SDRAMs. Two sets of memory addresses are provided to reduce signal loading for motherboard designs with more than one DIMM slot. In an effort to reduce switching noise on the DDR interface, the MAB bus is an inverted copy of the MAA bus, with the exception of the MA[10] bit that remains un-inverted on the MAB bus. The MAB bus is not inverted from the MAA bus during the DDR device initialization phase. The memory controller asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the memory access sequence. MAA[14:0] and MAB[14:0] are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. DDR Clock Enables CKEA and CKEB are clock enable signals for the DDR DRAMs and are used for power saving modes. They operate in parallel to drive greater loads than a single signal can support. These control signals are driven inactive (negated) by RESET# or when the DDR devices are placed in self refresh mode. The memory controller asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the memory access sequence. CKEA and CKEB are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. DDR Memory Data MDAT[63:0] connect to the DRAM data I/O. They are driven by the DDR DRAM during reads and are driven by the AMD-761 system controller during writes. During writes, the AMD-761 system controller provides the clock-forwarded DQS[8:0] strobes centered within the write data. The DQS strobes are used to capture the write data at the DDR DRAMs. (The DM pins provide additional strobes when accessing a x4 DIMM.) During reads, the DDR DRAMs source the DQS strobes aligned with MDAT and are used within the AMD-761 system controller to capture read data. (The DM pins are used to receive the DQS signals from the DDR DRAMs when accessing a x4 DIMM.) MDAT[63:0] are floated when neither the AMD-761 system controller nor the memory are driving the bus. DQS[8:0] B MAA[14:0] and MAB[14:0] O CKEA and CKEB O MDAT[63:0] B Chapter 7 Signal Descriptions 83 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal Signal Descriptions (Continued) Type Description DDR ECC MECC[7:0] carry error correction codes for the eight bytes of data on MDAT[63:0]. These signals are inputs to the AMD-761 system controller during DRAM read cycles and outputs during DRAM write cycles. During writes, the AMD-761 system controller provides the clock-forwarded DQS[8:0] strobes centered within the write data. The DQS strobes are used to capture the ECC write data at the DDR DRAMs. (The DM pins provide additional strobes when accessing a x4 DIMM.) During reads, the DDR DRAMs source the DQS strobes aligned with MECC and are used within the AMD-761 system controller to capture the ECC read data. (The DM pins are used to receive the DQS signals from the DDR DRAMs when accessing a x4 DIMM.) MECC[7:0] are floated when neither the AMD-761 system controller nor the memory are driving the bus. DDR Column Address Strobes CASA# and CASB# are column address strobe signals for the DDR DRAMs. They operate in parallel to drive greater loads than a single signal can support. The CASx signal is 1 bit of the 3-bit DDR DRAM command bus. These control signals are driven inactive (negated) by RESET#. The memory controller asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the memory access sequence. CASA and CASB are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. DDR Clock Outputs CLKOUT[5:0] and CLKOUT[5:0]# are differential clock pairs to the DDR DIMMs. The clock pairs can be individually disabled for unpopulated DIMM sockets. DDR Row Address Strobes RASA# and RASB# are row address strobe signals for the DDR DRAM. They operate in parallel to drive greater loads than a single signal can support. The RASx signal is 1 bit of the 3-bit DDR DRAM command bus. These control signals are driven inactive (negated) by RESET#. The memory controller asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the memory access sequence. RASA and RASB are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. DDR Memory Write Enables WEA# and WEB# are write enable signals for the DDR DRAM. They operate in parallel to drive greater loads than a single signal can support. The WEx signal is 1 bit of the 3-bit DDR DRAM command bus. These control signals are driven inactive (negated) by RESET#. The memory controller asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the memory access sequence. WEA and WEB are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See Chapter 2, "Functional Operation" starting on page 7 for more information. MECC[7:0] B CASA# and CASB# O CLKOUT[5:0] and CLKOUT[5:0]# O RASA# and RASB# O WEA# and WEB# O 84 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 36. Signal Signal Descriptions (Continued) Type Description AGP/PCI Signals B TS AGP/APCI Address/Data Bus These pins are the multiplexed address/data bus, sampled on the rising edge of AGPCLK. The address is valid on A_AD[31:00] during the first clock when FRAME# is asserted. Write data is valid on A_AD[31:00] when A_IRDY# is asserted and read data is valid when A_TRDY# is asserted. Data transfers occur on A_AD[31:00] when both A_IRDY# and A_TRDY# are asserted. AGP/APCI Command/Byte Enables During the address phase, these pins define the PCI command. During the data phase these pins are used as byte enables. AGP/APCI Clock AGPCLK receives a 66-MHz clock from the system clock generator. AGPCLK is used by the AMD-761TM system controller logic in the AGP clock domain. APCI Device Select The AMD-761 system controller asserts this pin when an external bus master drives a valid address within the memory region of the AMD-761 system controller. The AMD-761 system controller responds only to memory cycles. This pin is sampled by the AMD-761 system controller when the CPU accesses a PCI target. A_DEVSEL# is not used during AGP transfers. APCI Cycle Frame The A_FRAME# pin is asserted by the AMD-761 system controller to indicate the beginning of a bus transaction. A_FRAME# is sampled by the AMD-761 APCI target controller when an external bus master is performing a transaction on the PCI bus. A_FRAME# is not used during AGP transfers. AGP/APCI Bus Grant As the AGP bus arbiter, the AMD-761 system controller asserts A_GNT# in response to A_REQ# from the initiator (graphics controller) to indicate to the initiator that it has been granted control of the bus. At the same time, the system controller provides status information on status signals ST[2:0] to indicate to the initiator whether it is to supply data or receive data in response to a previously queued request. A_GNT# is asserted in response to an A_REQ#. A reset forces A_GNT# to be negated. AGP/APCI Initiator Ready The AMD-761 system controller asserts this signal during APCI transactions to indicate that write data is valid or it is ready to receive read data. It is sampled by the AMD-761 system controller during transactions by the AGP master. APCI Bus Parity PAR is used to generate and check for even parity across the AAD[31:00] and A_C/BE[3:0]# pins. The AMD-761 system controller generates but does not check parity. A_PAR# is not used during AGP transfers. AGP/APCI Bus Request As the bus arbiter, the AMD-761 system controller monitors A_REQ# to determine if the graphics controller requests access to the AGP bus. If A_REQ# is sampled asserted, the arbiter asserts A_GNT# as soon as the bus is available. A_AD[31:00] A_C/BE[3:0]# B TS I AGPCLK A_DEVSEL# B STS A_FRAME# B STS A_GNT# O TS A_IRDY# B STS A_PAR B TS A_REQ# I Chapter 7 Signal Descriptions 85 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal A_SERR# Signal Descriptions (Continued) Type I Description APCI System Error A_SERR# is not used during AGP transfers. An assertion on the A_SERR# pin during APCI transfers can be forwarded to the PCI SERR# pin when enabled in AMD-761 configuration registers. APCI Bus Stop The A_STOP# signal is asserted by the AMD-761TM system controller APCI target logic to initiate a disconnect by the AGP master. As a master, the AMD-761 system controller stops the current transfer when it samples the A_STOP# signal asserted. A_STOP# is not used during AGP transfers. AGP/APCI Target Ready The A_TRDY# signal is asserted by the AMD-761 system controller during accesses by an external bus master when read data is valid or when the target logic is ready to receive write data. This signal is sampled by the AMD-761 AGP master logic when the AMD-761 system controller is accessing an external APCI target. AGP-Only Signals A_STOP# B STS A_TRDY# B STS ADSTB[1:0] B STS B STS I STS AGP AD Bus Strobe These signals are driven by the agent that is providing the data, and are used to generate a timing strobe for 2X AGP transfers. ADSTB[0] is used for A_AD[15:00], and ADSTB[1] is used for A_AD[31:16]. AGP AD Bus Strobe (4X Timing) These signals are driven by the agent that is providing the data, and are used to generate a timing strobe for 4X AGP transfers. ADSTB[0]# is used for A_AD[15:00], and ADSTB[1]# is used for A_AD[31:16]. APG Pipelined Request This signal is asserted by the current master to indicate that a full-width request should be enqueued by the AMD-761 AGP target controller. The AMD-761 system controller enqueues a new request each edge of AGPCLK while the PIPE# signal is asserted. AGP Read Buffer Full This signal indicates that the AGP master's input buffer is full, and that it cannot accept more read data. When this signal is asserted by the AGP master, the AMD-761 system controller does not attempt to return previously requested low-priority read data. AGP Write Buffer Full This signal indicates that the AGP master cannot accept more fast writes from the AMD-761 system controller. When this signal is asserted by the AGP master, the AMD-761 system controller does not attempt to initiate fast writes. AGP Sideband Address Bus These pins provide an additional bus that can be used to pass commands (address and data) from the AGP master to the AMD-761 system controller. The sideband bus is driven by an external AGP master. AGP Sideband Strobes These strobes are driven by the AGP master to provide timing for the sideband address bus (SBA[7:0] pins). The SBSTB# pin provides the complement of SBSTB and is used only for AGP 4X timing mode. ADSTB[1:0]# PIPE# RBF# I WBF# I SBA[7:0] I SBSTB/SBSTB# I STS 86 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 36. Signal Signal Descriptions (Continued) Type Description AGP Status This bus is used to provide status from the AMD-761TM system controller to the AGP master. These signals are valid only when the A_GNT# signal is asserted (Low), and must be ignored by the AGP master at all other times. The status bits are encoded as follows: 000 = Indicates that previously requested low-priority read or flush data is being returned to the master. 001 = Indicates that previously requested high-priority read data is being returned to the master. 010 = Indicates that the master provides low-priority write data for a previous enqueued write command. 011 = Indicates that the master provides high-priority write data for a previous enqueued write command. 100 = Reserved 101 = Reserved 110 = Reserved 111 = Indicates that the master has been given permission to start a bus transaction. The master can enqueue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#. ST[2:0] are always an output from the core logic and an input to the master. Miscellaneous Signals Test Mode Enable The TEST# pin is used by AMD for internal chip testing. It is also used to enter NAND tree and three-state test modes for motherboard manufacturing test, as described in Chapter 3. DRAM Controller Stop This pin is used to support ACPI S1 and S3 power management modes. It is asserted by the AMD-766 peripheral bus controller to enter the S1 power state, and asserted in conjunction with RESET# to enter the S3 state. Refer to "Power Management" on page 24 for details of AMD-761 system controller power management modes. ST[2:0] O TEST# I DCSTOP# I VSS/VDD, I/O Pad and Voltage Reference, and Compensation Pins VSS VDD_CORE VDD_PCI VDD_AGP AVDD AGP_CAL and AGP_CAL# P0_CAL and P0_CAL# AGP_VREF VSS AMD-761 VDD pins, 2.5 Vdc. VDD for PCI I/O cells, 3.3 Vdc. This pin functions as VDD for AGP I/O cells, and can be 1.5 Vdc or 3.3 Vdc as determined by TYPEDET# pin on the motherboard. The motherboard drives this input to 1.5 Vdc when the TYPEDT# pin is asserted Low by an AGP card, or 3.3 Vdc when the TYPEDET# pin is High. Separately filtered 2.5 Vdc for analog PLL circuitry. Compensation pads for matching impedance of motherboard AGP traces. Compensation pads for matching impedance of motherboard AMD Athlon system bus traces. Voltage reference for 3.3 Vdc AGP I/O cells. Chapter 7 Signal Descriptions 87 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 36. Signal AGP_VREF4X REF_5V P0_VREF DDR_REF S_CLKREF CPU_VCORE Signal Descriptions (Continued) Type Description Voltage reference for 1.5 Vdc AGP I/O cells. Voltage reference to support 5 Vdc PCI signalling. AMD Athlon system bus I/O voltage reference. DDR I/O voltage reference. System clock reference voltage. Voltage for push-pull I/O pads. Connected to the AMD-761TM system controller VSS and VDD_CORE planes. These are intended only for signal integrity testing and should be connected to the motherboard VSS and VDD_CORE planes, respectively. SI_VSS and SI_VDD 7.1 Initialization Pinstrapping The AMD-761 system controller requires various strapping options to define the SIP stream returned to the AMD AthlonTM processor after reset, as well as to define specific AMD-761 system controller operating parameters. The pinstraps are set by 10K pullup or pulldown resistors attached externally to PCI bus pins, and they are sampled during reset. Unless otherwise defined, strapping options are enabled when pulled High, disabled when pulled Low. BIOS can read the value latched on most of these pinstraps in the Configuration Status register (Dev 0:F0:0x88). Table 37 on page 89 contains a description of the pinstrapping signals. 88 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 37. Signal Initialization Pinstrapping Type Description Initialization Pinstrapping ClkSpeed These pinstraps are used to define the clock speed of the AMD AthlonTM system bus, and are encoded as follows: 00: 100 MHz 01: 66 MHz 10: Reserved 11: 133 MHz PLL Reset This pin must be driven low when using the PLL bypass test mode. This pin is also optionally used in test modes as described in Chapter 3. A pullup resistor is required on this pinstrap for normal operation. SysClkThresh This pin functions as the AMD Athlon system bus threshold range select for the system clock input receiver. When Low, the system clock input senses thresholds between 0.6 V and 1.0 V. When High, the inputs sense thresholds between 1.0 V and 1.4 V. Reserved Three-State-Enable (For Test Only) When pulled High, this pin enables board test mode when TEST# is asserted. Refer to Chapter 3 for details of this test mode bit. Inclk_Delay_Enable When this pin is pulled High, forwarded clocks originating in the AMD-761TM system controller are delayed 1/4 SysClk period to place their edge in the nominal center of the associated data. Certain SIP parameters are also adjusted. When pulled Low, the forwarded clock edges are concurrent with the associated data transitions. NAND_TreeEnable (For Test Only) When this pin is pulled High, NAND tree test mode is enabled when TEST# is asserted. Refer to Chapter 3 for details of this test mode bit. CPU_ClkHist This field selects the amount of hysteresis applied to the SysDataOutClk[3:0]# and SysAddrOutClk# inputs for noise immunity. This field is encoded as follows: 00: No hysteresis 01: Low hysteresis (preferred setting) 10: Medium hysteresis 11: Maximum hysteresis TypeDet# This pin functions as the AGP card type detect, used by the AGP I/O cells for impedance compensation. The latched value of the TYPEDET# pin can also be read in the Configuration Status register (Dev 0:F0:0x88). 0: AGP card with 1.5-V referencing installed 1: AGP card with 3.3-V referencing installed AD[31:30] I AD[29] I AD[28] AD[27:26] AD[25] I I I AD[24] I AD[23] I AD[22:21] I AD[20] I Chapter 7 Signal Descriptions 89 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 37. Signal AD[19:16] AD[15] Initialization Pinstrapping (Continued) Type I I Reserved General-Purpose Status This bit can be used for any general-purpose communication to BIOS for motherboardspecific features. It is recommended that this bit be pulled down if not used. The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88). AGPClock_Mux[2:0] (For Test Only) This bit field selects input to APLL clock mux for PLL test mode. Refer to Chapter 3 for details of these bits. Length This bit field selects the CPU 0 physical AMD AthlonTM system bus length: 00: Short, non-slot A 01: Single Slot A or close 10: Far dual slot A 11: Farthest possible slot A See the AMD AthlonTM System Bus Design Guide, Rev. B, PID #22666, for details of the bus length assumptions used in the bus timing calculations. Bypass_PLLs (For Test Only) If this pin is pulled High, PLL bypass mode is enabled when TEST# is asserted. Refer to Chapter 3 for details of PLL bypass mode. OutClk_Delay_Enable When this pin is pulled High, forwarded clocks originating in the AMD Athlon are delayed to the nominal center of the associated data. This control is provided by adjusting SIP parameters. When pulled Low, the AMD Athlon forwarded clock edges are concurrent with the associated data transitions. For details refer to the SIP mapping description in the AMD AthlonTM System Bus Specification, order# 21902. SysClock_Mux[2:0] (For Test Only) This bit field selects input to SPLL clock mux for PLL test mode. Refer to Chapter 3 for details of these bits. CPU_Thresh This pin functions as the AMD Athlon system bus threshold range select for AMD Athlon system bus I/O cells. When Low, the AMD Athlon system bus inputs sense thresholds between 0.6 V and 1.0 V. When High, the inputs sense thresholds between 1.0 V and 1.4 V. CPU_Div These pins define the clock multiplier for the CPU, and are generated by the CPU. They are used internally to create the frequency ID (FID) value, which is used in the generation of SIP values sent to the AMD Athlon processor during initialization. Description AD[14:12] I AD[11:10] I AD[9] I AD[8] I AD[7:5] I AD[4] I AD[3:0] I 90 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 37. Signal C/BE[3]# C/BE[2]# C/BE[1]# Initialization Pinstrapping (Continued) Type I I I Description Reserved This pin must always have a pullup resistor installed for proper operation. Reserved This pin must always have a pullup resistor installed for proper operation. AGP4X Test Mode This pin should be pulled up when testing AGP in the 4X rate mode. This allows a 4X clock to be driven on the AGPCLK pin, and sets the appropriate internal clock dividers. SipRomEnable This pin enables an external serial ROM containing processor and system controller initialization parameters when pulled High. The initialization data is read from the external SIP ROM at power-on and transferred to the processor and system controller. When this pin is pulled Low, the SIP stream is generated internally and transferred to the processor and system controller. This feature is typically used only for debug and test modes. C/BE[0] I 7.2 Pin Multiplexing Some pin functions are multiplexed on PCI pins as described in Table 38 on page 92. Note that additional pin multiplexing is required for scan testing, and is described in Chapter 3. The pin multiplexing for scan mode does not affect normal operation. Pin multiplexing is defined for test modes only, and requires specific PCI bus signalling pins to be pulled Low during reset (RESET# asserted). Note that if these test functions are used on the motherboard in lab debugging, the normal PCI signal pullup resistors need replacing temporarily with pulldown resistors. This action should be done only for lab testing and not in a production environment. These signals include the following: n n IRDY# pin for the TEST_RESET# function PAR pin for PLL output test mode. These functions are described in detail in Chapter 3. Chapter 7 Signal Descriptions 91 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 38. Pin Multiplexing Options Primary Function PCI bus grant #6 PCI bus grant #5 PCI bus grant #3 PCI bus grant #2 PCI bus grant #1 PCI bus grant #0 PCI bus command/byte enable bit 1 Secondary Function APLL clock output for PLL test. Refer to Chapter 3 for details of this function. SPLL clock output for PLL test. Refer to Chapter 3 for details of this function. Output of the DDR DRAM interface NAND tree. Output of the PCI bus interface NAND tree. Output of the AGP interface NAND tree. Output of the AMD AthlonTM system bus interface NAND tree. SIP ROM data bit when using an external ROM to load processor interface initialization data. SIP ROM clock when using an external ROM to load processor interface initialization data. This feature is enabled via pinstrapping. When this pin is sampled High during reset, the external SIP ROM is enabled. Reset pin dedicated to PLL clock dividers. Refer to Chapter 3 for details of this function. Used only for PLL testing. Enables scan testing when TEST# is asserted. Not used in normal operation. Enables clock testing when TEST# is asserted. The values on pinstraps AGPClock_Mux[2:0] and SysClock_Mux[2:0] strapping pins select the clock mux inputs. Refer to Chapter 3 for details of PLL test mode. Primary/Secondary Pin Name GNT[6]#/AGPCLKOUT GNT[5]#/SYSCLKOUT GNT[3]#/DDR_NAND GNT[2]#/PCI_NAND GNT[1]#/AGP_NAND GNT[0]#/CPU_NAND CBE[1]#/ROM_SDA CBE[0]#/ROM_SCK PCI bus command/byte enable bit 0 IRDY#/TEST_RST# TRDY#/SCAN_EN# PCI bus IRDY# pin PCI bus TRDY# pin PAR/PLL_TEST# PCI bus PAR (parity) pin 7.3 Pin States at Reset The AMD-761 system controller default pin states are defined in Table 39 on page 93. These are listed for all output and bidirectional pins in the power-on reset state (reset) as well as the ACPI S1 and S3 power management states. Refer to "Power Management" on page 24 for details of the S1 and S3 modes. Note that most AMD-761 internal configuration registers are initialized to a known value when RESET# is asserted. To a c c o m m o d a t e t h e AC P I S 3 ( s u s p e n d t o R A M ) p owe r management state, the memory controller registers are not initialized at power-up and must be programmed by BIOS 92 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet following the first power-up. For further details refer to Chapter 2 on page 7 and the AMD-761TM System Controller Software/BIOS Design Guide, order# 24081. Table 39. CLKFWDRST CONNECT SADDIN[14:2]# SADDINCLK# SDATA[63:0]# SDATAINCLK[3:0]# SDATAINVAL# AD[31:00] C/BE[3:0]# DEVSEL# FRAME# GNT[6:0]# IRDY# PAR SBGNT# SERR# STOP# TRDY# WSC# CS[7:0]# DM[8:0] DQS[8:0] MAA[14:0] MAB[14:0] CKEA CKEB MDAT[63:0] MECC[7:0] CASA# CASB# CLKOUT[5:0] Reset Pin States RESET# State S1 State S3 State 1 1 1 1 1 1 1 Z Z Z Z Z Z Z Z Z Z Z Z 1 Z Z 0 0x7BFF 0 0 Z Z 1 1 Active 1 0 1 1 Park 1 1 Park Park Z Z 1 Z Park 1 Z Z Z Z 1 Z Z * * 0 0 Z Z * * * Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 0 Z Z Z Z Z * Unbuffered=Z, Registered=1 * Unbuffered=Z, Registered=1 * Unbuffered=Z, Registered=active * Unbuffered=Z, Registered=previous value * Unbuffered=Z, Registered=previous value Parked signals maintain their previous value. Comments Pin Name Chapter 7 Signal Descriptions 93 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 39. CLKOUT[5:0]# RASA# RASB# WEA# WEB# A_AD[31:00] A_C/BE[3:0]# A_DEVSEL# A_FRAME# A_GNT# A_IRDY# A_PAR A_STOP# A_TRDY# ADSTB[1:0] ADSTB[1:0]# SBSTB SBSTB# ST[2:0] Reset Pin States RESET# State S1 State S3 State Active 1 1 1 1 Z Z Z Z 1 Z Z Z Z Z Z Z Z 1 * * * * * Park Park Z Z 1 Z Park Z Z Z Z Z Z Park Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Input only Input only Comments * Unbuffered=Z, Registered=active * Unbuffered=Z, Registered=1 * Unbuffered=Z, Registered=1 * Unbuffered=Z, Registered=1 * Unbuffered=Z, Registered=1 Pin Name 94 Signal Descriptions Chapter 7 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet 8 Ordering Information AMD standard products are available in several packages and o p e ra t i n g ra n g e s . Th e o rd e r nu m b e r i s fo r m e d by a combination of the elements below. Contact your AMD representative for detailed ordering information. AMD-761 A C 1 Frontside Bus Speed 1 = 266 MHz 2 = 200 MHz Case Temperature C = Commercial Temperature Range Package Type A = Plastic Ball Grid Array Family/Core AMD-761 Chapter 8 Ordering Information 95 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 96 Ordering Information Chapter 8 Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Conventions, Abbreviations, and References This section contains information about the conventions and abbreviations used in this document and a list of related publications. Signals and Bits n n n n n Active-Low Signals--Signal names containing a pound sign, such as SFILL#, indicate active-Low signals. They are asserted in their Low-voltage state and negated in their High-voltage state. When used in this context, High and Low are written with an initial upper case letter. Signal Ranges--In a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, D[63:0]). Reserved Bits and Signals--Signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. These bits and signals are reserved by AMD for future implementations. When software reads registers with reserved bits, the reserved bits must be masked. When software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. Three-State--In timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. Invalid and Don't-Care--In timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. Data Terminology The following list defines data terminology: n Quantities * A word is two bytes (16 bits) * A doubleword is four bytes (32 bits) * A quadword is eight bytes (64 bits) * An AMD AthlonTM processor cache quadwords (64 bytes) line is eight Conventions, Abbreviations, and References 97 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 n Addressing--Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. Abbreviations--The following notation is used for bits and bytes: * Kilo (K, as in 4-Kbyte page) * Mega (M, as in 4 Mbits/sec) * Giga (G, as in 4 Gbytes of memory space) See Table 41 for more abbreviations. Little-Endian Convention--The byte with the address xx...xx00 is in the least-significant byte position (little end). In byte diagrams, bit positions are numbered from right to left--the little end is on the right and the big end is on the left. Data structure diagrams in memory show low addresses at the bottom and high addresses at the top. When data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. Because byte addresses increase from right to left, strings appear in reverse order when illustrated. Bit Ranges--In text, bit ranges are shown with a dash (for example, bits 9-1). When accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, AD[31:0]). Bit Values--Bits can either be set to 1 or cleared to 0. Hexadecimal and Binary Numbers--Unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. n n n n n Abbreviations and Acronyms Table 40 contains the definitions of abbreviations used in this document. Table 40. Abbreviations Abbreviation A F G Gbit Gbyte H Meaning Ampere Farad GigaGigabit Gigabyte Henry 98 Conventions, Abbreviations, and References Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 40. Abbreviation h K Kbyte M Mbit Mbyte MHz m ms mW Abbreviations (Continued) Meaning Hexadecimal KiloKilobyte MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond Ohm picopicoampere picofarad picohenry picosecond Second Volt Watt A F H s V n nA nF nH ns ohm p pA pF pH ps s V W Conventions, Abbreviations, and References 99 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 Table 41 contains the definitions of acronyms used in this document. Table 41. Acronyms Abbreviation AAT ACK ACPI AGP APCI API APIC BAR BIOS BIST BIU CS DDR DIMM DMA DRAM ECC EIDE EISA EPROM FID FIFO GART HSTL IACK IDE IMB ISA JEDEC JTAG LRU LSB Meaning AGP Address Translator Acknowledge Advanced Configuration and Power Interface Accelerated Graphics Port AGP Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Base Address Register Basic Input/Output System Built-In Self-Test Bus Interface Unit Chip Select Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Error Correcting Code Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory Frequency Integer Divisor First In, First Out Graphics Address Remapping Table High-Speed Transistor Logic Interrupt Acknowledge Integrated Device Electronics Interrupt Message Bus Industry Standard Architecture Joint Electron Device Engineering Council Joint Test Action Group Least-Recently Used Least Significant Bit 100 Conventions, Abbreviations, and References Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Table 41. Abbreviation LVTTL MA MCT MD MRL MRM MSB MTRR MWF MWI MUX NMI OD PBGA PA PCI PH PLL POS POST PPA PT PTE RAM ROM SBA SDRAM SIP SMbus SMC SPD SRAM SROM TLB Acronyms (Continued) Meaning Low Voltage Transistor Transistor Logic Memory Address Memory Controller Memory Data Memory Read Line Memory Read Multiple Most Significant Bit Memory Type and Range Registers Memory Write FIFO Memory Write-and-Invalidate Multiplexer Non-Maskable Interrupt Open Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Hit Phase Locked Loop Power-On Suspend Power-On Self-Test Physical Page Address Page Tables Page Table Entries Random Access Memory Read Only Memory Sideband Address Synchronous Direct Random Access Memory Serial Initialization Packet System Management Bus SDRAM Memory Controller Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Conventions, Abbreviations, and References 101 Preliminary Information AMD-761TM System Controller Data Sheet Table 41. Abbreviation TTL VAS VPA VGA 24088B--August 2001 Acronyms (Continued) Meaning Transistor Transistor Logic Virtual Address Space Virtual Page Address Video Graphics Adapter 102 Conventions, Abbreviations, and References Preliminary Information 24088B--August 2001 AMD-761TM System Controller Data Sheet Related Publications The following books discuss various aspects of computer architecture that may enhance your understanding of AMD products: AMD Publications AMD AthlonTM Processor Data Sheet, order# 21016 AMD-766TM Peripheral Bus Controller Data Sheet, order# 22548 Bus Architecture PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, Hillsboro, Oregon, 1998. AT Bus Design, Edward Solari, IEEE P996 Compatible, Annabooks, San Diego, CA, 1990. Accelerated Graphics Port Interface Specification, Revision 2.0, Intel Corporation, AGP Forum, 1998. x86 Architecture Programming the 80386, John Crawford and Patrick Gelsinger, Sybex, San Francisco, 1987. 80x86 Architecture & Programming, Rakesh Agarwal, Volumes I and II, Prentice-Hall, Englewood Cliffs, NJ, 1991. General References Websites Computer Architecture, John L. Hennessy and David A. Patterson, Morgan Kaufman Publishers, San Mateo, CA, 1990. Visit the AMD website for documentation of AMD products. www.amd.com Other websites of interest include the following: n n n JEDEC home page--www.jedec.org IEEE home page--www.computer.org AGP Forum--www.agpforum.org Conventions, Abbreviations, and References 103 Preliminary Information AMD-761TM System Controller Data Sheet 24088B--August 2001 104 Conventions, Abbreviations, and References |
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