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A8697 Wide Input Voltage 4.0 A Step Down Regulator
Features and Benefits
8 to 25 V input range Integrated DMOS switch Adjustable fixed off-time Adjustable output
Description
The A8697 is a constant off-time current mode step-down regulator with a wide input voltage range. Regulation voltage is set by external resistors, to output voltages as low as 0.8 V. The A8697 includes an integrated power DMOS switch to reduce the total solution footprint. It also features internal compensation, allowing users to design stable regulators with minimal design efforts. The off-time can be set with an external resistor, allowing flexibility in inductor selection. Additionally, the A8697 has a logic level enable pin which can shut the device down and put it into a low quiescent current mode for power sensitive applications.
Package: 8-Lead SOIC with exposed thermal pad (suffix LJ)
The A8697 is supplied in a low-profile 8-lead SOIC with exposed pad (package LJ). Applications include: Applications with 8 to 25 V input Consumer electronics, networking equipment 12 V lighter-powered applications (portable DVD, etc.) Point of Sale (POS) applications
Approximate Scale 1:1
Typical Application
VIN +12 V
CBOOT 0.01 F
Efficiency versus Load Current
90 80 70 VOUT = 2.5 V
+
CIN 47 F 25 V
BOOT
VIN VOUT 1.06 V/ 4.0 A
VOUT = 1.8 V VOUT = 1.06 V
Efficiency (%)
60 50 40 30 20 10 0 0 1 2 3 4
ENB A8697 TSET RTSET 51.1 k GND
Ratings: L: CDRH104R-3R8 COUT: EEUFM1V151 CIN: EEVFC1H470P
LX
L 3.8 H D1 R1 2k
VBIAS
+
COUT 150 F 56 m
FB R2 6.14 k
Load Current (A)
Circuit for 12 V step down to 1.06 V at 4 A
A8697-DS, Rev. 2
Efficiency curve for circuit at left
A8697
Wide Input Voltage 4.0 A Step Down Regulator
Absolute Maximum Ratings
Characteristic VIN Supply Voltage VBIAS Input Voltage Switching Voltage ENB Input Voltage Operating Ambient Temperature Range Junction Temperature Storage Temperature Symbol VIN VBIAS VS VENB TA TJ(max) TS Range E Conditions Min. - -0.3 -1 -0.3 -40 - -55 Typ. - - - - - - - Max. 25 7 - 7 85 150 150 Units V V V V C C C
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150C.
Package Thermal Characteristics*
Package LJ RJA (C/W) 35 PCB 4-layer
* Additional information is available on the Allegro website.
Ordering Information Use the following complete part numbers when ordering:
Part Numbera A8697ELJTR-T A8697ELJ-T
aLeadframe bContact Allegro
Packingb 13 in. reel, 3000 pieces/reel 98 pieces/tube
Description LJ package, SOIC surface mount with exposed thermal pad
plating 100% matte tin. for additional packing options.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Functional Block Diagram
BOOT Boot Charge
VIN
VIN
+
VIN
LX L1 D1 ESR COUT
VOUT
ENB C
Switch Disable
Switch PWM Control
TSET I_Peak
+
-
I_Demand Error
COMP GND
+
VBB UVLO TSD
Soft Start Ramp Generation
-
Clamp
-
FB
Bias Supply
VBIAS
0.8 V
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
ELECTRICAL CHARACTERISTICS1,2 at TA = 25C, VIN = 8 to 25 V (unless noted otherwise)
Characteristics Symbol Test Conditions VENB = LOW, VIN = 12 V, VBIAS = 3.2 V, VFB = 1.5 V (not switching) VIN Quiescent Current IVIN(Q) VENB = LOW, VIN = 12 V, VBIAS < 3 V, VFB = 1.5 V VENB = HIGH VBIAS Input Current Buck Switch On Resistance Fixed Off-Time Proportion Feedback Voltage Output Voltage Regulation Feedback Input Bias Current Soft Start Time Buck Switch Current Limit ENB Open Circuit Voltage ENB Input Voltage Threshold ENB Input Current VIN Undervoltage Threshold VIN Undervoltage Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis
1Negative 2Specifications
Min. - - - - - -15 0.784 -3 -400 5
Typ. 1.0 4.1 - 3.8 180 - 0.8 - -100 10 6.2 2.7 - - - 6.9 - 165 15
Max. - - 100 5 - 15 0.816 3 100 15 7.2 - 7 1.0 -1 7.2 1.1 - -
Units mA mA A mA m % V % nA ms A A V V A V V C C
IBIAS RDS(on) VFB VOUT IFB tss ICL VOC VENB(0) IENB(0) VUVLO VUVLO(hys) TJTSD TJTSD(hys)
VBIAS = VOUT TA = 25C, IOUT = 3 A Based on calculated value IOUT = 0 mA to 3 A
VFB > 0.4 V VFB < 0.4 V Output disabled LOW level input (Logic 0), output enabled VENB = 0 V VIN rising VIN falling Temperature increasing Recovery = TJTSD - TJTSD(hys)
4.8 - 2.0 - -10 6.6 0.7 - -
current is defined as coming out of (sourcing) the specified device pin. over the junction temperature range of 0C to 125C are assured by design and characterization.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Performance Characteristics
Start-up Power Off
EN; 5.00 V/div.
EN; 5.00 V/div. VOUT; 1.00 V/div.
VOUT; 1.00 V/div.
IOUT; 2.00 A/div. IOUT; 2.00 A/div.
t
t = 5.00 ms/div.
t
t = 5.00 ms/div.
Output Ripple with Electrolytic Capacitor
IOUT = 4 A IOUT; 1.00 A/div.
Switching
IOUT = 4 A
VSW; 10.0 V/div. VOUTAC; 100 mV/div. IOUT; 1.00 A/div.
t
t = 2.00 s/div.
t
t = 2.00 s/div.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Load Transient, Step Up
IOUT = 0.8 to 1.6 A
Load Transient, Step Down
IOUT = 1.6 to 0.8 A
VOUTAC; 200 mV/div.
VOUTAC; 200 mV/div.
IOUT; 500 mA/div. IOUT; 500 mA/div.
t
t = 100 s/div.
t
t = 100 s/div.
Short Circuit
1.2 1.0 0.8
VOUT Error (%)
Load Regulation
0.6 0.4 0.2 0 -0.2 -0.4
VOUT; 1.00 V/div.
IOUT; 2.00 A/div.
t
t = 100 s/div.
0
1
2
3
4
5
Load Current (A)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Functional Description
The A8697 is a fixed off-time, current-mode-controlled buck switching regulator. The regulator requires an external clamping diode, inductor, and filter capacitor, and operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. The value of a resistor between the TSET pin and ground determines the fixed off-time (see graph in the tOFF section). VOUT. The output voltage is adjustable from 0.8 to 20 V, based on the combination of the value of the external resistor divider and the internal 0.8 V 2% reference. The voltage can be calculated with the following formula: VOUT = VFB x (1 + R1/R2) (1) Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. Internally, the ramp is set to 10 ms nominal rise time. During soft start, current limit is 3.5 A minimum. The following conditions are required to trigger a soft start: * VIN > 6 V * ENB pin input falling edge * Reset of a TSD (thermal shut down) event VBIAS. To improve overall system efficiency, the regulator output, VOUT, is connected to the VBIAS input to supply the operating bias current during normal operating conditions. During startup the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and 5 V. If the output voltage is less than 3.3 V, then the A8697 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, VIN. VBIAS can also be supplied with an external voltage source. No power-up sequencing is required for normal operation. ON/OFF Control. The ENB pin is externally pulled to ground to enable the device and begin the soft start sequence. When the ENB is open circuited, the switcher is disabled and the output decays to 0 V. Protection. The buck switch will be disabled under one or more of the following fault conditions: * VIN < 6 V * ENB pin = open circuit * TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. tOFF. The value of a resistor between the TSET pin and ground determines the fixed off-time. The formula to calculate tOFF (s) is: 1-0.03 VBIAS (2) , tOFF = RSET 10.2 x 109 where RTSET (k) is the value of the resistor. Results are shown in the following graph:
Off-Time Setting versus Resistor Value
200 180 160 140
RTSET (k)
120 100 80 60 40 20 0 1 2 3 4 5
VBIAS = 5 V VBIAS = 3.3 V
6
7
8
9
10
11 12 13 14 15
16
tOFF (s)
tON. From the volt-second balance of the inductor, the turn-on time, ton , can be calculated approximately by the equation:
tON =
(VOUT + Vf + IOUT RL) tOFF VIN - IOUT RDS(on) - IOUT RL - VOUT
(3)
where Vf is the voltage drop across the external Schottky diode, RL is the winding resistance of the inductor, and RDS(on) is the on-resistance of the switching MOSFET.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
The switching frequency is calculated as follows:
to the minimum on-time of the switcher. (4) The extension of the off-time is based on the value of the TSET multiplier and the FB voltage, as shown in the following table:
VFB (V) < 0.16 < 0.32 < 0.5 > 0.5 TSET Multiplier 8 x tOFF 4 x tOFF 2 x tOFF tOFF
1 fSW = tON + tOFF
Shorted Load. If the voltage on the FB pin falls below 0.4 V, the regulator will invoke a 1.5 A typical overcurrent limit to handle the shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due
Component Selection
L1. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by: IRIPPLE = VL(OFF) x tOFF / L VL(OFF) = VOUT + Vf + IL(AV) x RL Example: Given VOUT = 1.06 V, Vf = 0.3 V, VIN = 12 V, ILOAD = 4.0 A, power inductor with L = 3.8 H and RL = 0.05 Rdc at 55C, tOFF = 5.0 s, and RDS(on) = 0.2 . Substituting into equation 6: VL(OFF) = 1.06 V + 0.3 V+ 4 A x 0.05 = 1.56 V Substituting into equation 5: IRIPPLE = 1.56 V x 5 s / 3.8 H = 2.05 A The switching frequency, fSW, can then be estimated by: fSW = 1 / ( tON + tOFF ) tON = IRIPPLE x L / VL(ON) VL(ON) = VIN - IL(AV) x RDS(on) - IL(AV) x RL- VOUT Substituting into equation 9: VL(ON) = 12 V - 4 A x 0.2 - 4 A x 0.05 - 1.06 V = 9.94 V (7) (8) (9) (5) (6) Substituting into equation 8: tON = 2.05 A x 3.8 H / 9.94 V = 0.785 s Substituting into equation 7: fSW = 1 / (5 s + 0.785 s) = 173 kHz Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. Please refer to the Maximum Load Current graph for the maximum load recommended. D1. The Schottky catch diode should be rated to handle 1.2 times the maximum load current. The voltage rating should be higher than the maximum input voltage expected during all operating conditions. The duty cycle for high input voltages can be very close to 100%. COUT. The main consideration in selecting an output capacitor is voltage ripple on the output. For electrolytic output capacitors, a low-ESR type is recommended. The peak-to-peak output voltage ripple is simply IRIPPLE x ESR. Note that increasing the inductor value can decrease the ripple current. The ESR should be in the range from 50 to 500 m.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
RTSET Selection. Correct selection of RTSET values will ensure that minimum on-time of the switcher is not violated and prevent the switcher from cycle skipping. For a given VIN to VOUT ratio, the RTSET value must be greater than or equal to the value defined by the curve in the plot below. Note. The curve represents the minimum RTSET value. When calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating conditions the resistance on the TSET pin is allowed to go below the minimum value. FB Resistor Selection. The impedance of the FB network should be kept low to improve noise immunity. Large value resistors can pick up noise generated by the inductor, which can affect voltage regulation of the switcher.
13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5
Violation of Minimum On-Time
ET
VIN / VOUT
8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0
um im in M
e lu Va
R of
TS
Safe Operating Area
67.5
65.0
70.0
50.0
55.0
60.0
52.5
45.0
57.5
47.5
40.0
42.5
37.5
35.0
32.5
62.5
30.0
25.0
27.5
20.0
22.5
17.5
15.0
12.5
Maximum Load Current
Using Allegro A8698 Evaluation Board*
6 5 4
10.0
RTSET (k )
3 2 1 0 0 1 2 3 4 5
*To test maximum load current, the A8697 IC was mounted on an A8698 Evaluation Board (see next page), and a thermocouple attached to the IC case to measure TC. The assembly was placed in an environmental chamber in still air. The initial air temperature in the chamber temperature was 60C (TA), and during the test, IOUT was adjusted until TC = 115C.
VOUT (V)
Load Current (A)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Application Circuit
Evaluation Board for the A8697
Silkscreen Layer
Bottom Layer
J1 8 to 24 Vdc C1.2 J2 GND C1.3 C1.1
C3 C2 J4 GND VIN C4.1 L1 C4.2 J3 3.3 V / 3.0 A C4.3 VOUT
BOOT R4 ENB TSET R3 EN GND PAD
A8697
LX VBIAS FB D1
R2 R1 R5
Top and Silkscreen Layers
P1
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Wide Input Voltage 4.0 A Step Down Regulator
Evaluation Board Bill of Materials
Designator Quantity C1.1 C1.2, C1.3 C2 C3 C4.2 C4.1 C4.3 L1 D1 0 2 1 1 0 0 1 1 1 Description Ceramic chip, 22 F, 25 V, 20%, X5R Aluminum electrolytic capacitor, 25 V / 47 F Ceramic capacitor, X7R, 10%, 0.1 F / 50 V Ceramic capacitor, X7R, 10%, 0.01 F / 50 V Special polymer capacitor, 120 F / 6.3 V, 15 m Ceramic capacitor, 47 F / 6.3 V, 20%, X5R Aluminum electrolytic capacitor, 35 V / 150 F, 56 m Inductor, 3.8 H, 13 m, 6 A, 20% Schottky diode, 20 V / 4.0 A Chip resistor, 1/16 W, 1% 2 k at VOUT = 1.06 V R1 1 2.55 k at VOUT = 1.8 V 6.34 k at VOUT = 3.3 V 10.5 k at VOUT = 5.0 V Chip resistor,1/16W, 1% R2 R3 R4 R5 J1, J2, J3, J4 P1 EN U1 1 1 1 1 4 1 1 1 6.14 k at VOUT = 1.06 V 2 k at VOUT = 1.8, 3.3, or 5.0 V Chip resistor, 51.1 k, 1/16 W, 1% Chip resistor, 10 k, 1/16 W, 1% Chip resistor, 0 , 1/16 W, 1% Header, 2-pin, 100 mil spacing Test point, Red, 1 mm Test point, Black, 1 mm Wide Input Voltage Step Down Regulator Std. Std. Std. Sullins Farnell Farnell Allegro 0603 0603 0603 0.100 in. x 2 0.038 in. 0.038 in. ESOIC8 Std. Std. Std. PTC36SAAN 240-345 240-333 A8697 Std. 0603 Std. Manufacturer Panasonic Rubycon Murata Kemet Panasonic Panasonic Panasonic Sumida Diodes, Inc. Std. Footprint 1210 8 mm x 12 mm 0603 0603 7.3 mm x 4.3 mm x 3.1 mm 1210 8 mm x 10.2 mm 10.3 mm x 10.5 mm x 4 mm SMA 0603 Part Number ECJ4YB1E226M EEVFC1H470P GRM188R71H104KA93D C0603C103K5RACTU EEFUD0J121R ECJ4YB0J476M EEFM1V151 CDRH104R-3R8 SL42-9C Std.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8697
Package LJ 8-Pin SOIC
Wide Input Voltage 4.0 A Step Down Regulator
6.20 .244 5.80 .228 0.25 [.010] M B M 8 5.00 .197 4.80 .189 A B 8 0 0.25 .010 0.17 .007
B
4.00 .157 3.80 .150 2.41 .095 NOM
A
1.27 .050 0.40 .016
3.30 .130 NOM 8X 0.10 [.004] C 8X 0.51 .020 0.31 .012
1
2 0.25 .010 SEATING PLANE 1.75 .069 1.35 .053 C SEATING PLANE GAUGE PLANE
0.25 [.010] M C A B 1.27 .050
0.25 .010 0.10 .004
0.65 .026 MAX
1.27 .050 NOM
1.75 .069 NOM
2X 0.20 .008 MIN
2.41 .095 NOM C
5.60 .220 NOM
All dimensions reference, not for tooling use (reference JEDEC MS-012 AA) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1 3.30 .130 NOM
2 6X 0.20 .008 MIN
Pin-out Diagram
Terminal List Table
Number 1 2 3 4 5 6 7 8 - Name BOOT ENB TSET GND FB VBIAS LX VIN Pad Description Gate drive boost node On/off control; logic input Off-time setting Ground Feedback for adjustable regulator Bias supply input Buck switching node Supply input Exposed pad for enhanced thermal dissipation
BOOT ENB TSET GND
1 2 3 4 Pad
8 7 6 5
VIN LX VBIAS FB
(Top View)
The products described herein are manufactured under one or more patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties that may result from its use. Copyright (c) 2006 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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