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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16702
256/263-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The PD16702 is a TFT-LCD gate driver equipped with 256/263-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also drive the XGA/SXGA, and SXGA+ panel.
FEATURES
* CMOS level input (3.3 V/2.5 V) * 256/263 outputs * High-output voltage (VDD2 to VEE2 = amplitude: 40 V MAX.) * Capable of All-on outputting (/AO)
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16702N-xxx
Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14680EJ1V0DS00 (1st edition) Date Published September 2001 NS CP (K) Printed in Japan
The mark
shows major revised points.
(c)
2000
PD16702
1. BLOCK DIAGRAM
R,/L LS1
Note
MODE
LS1
Note
CLK
LS1
Note
STVR
LS1
Note
SR1 SR2 SR3
263-bit shift register
SR261 SR262 SR263
LS1
Note
STVL
OE1
LS1
Note
OE2
LS1
Note
OE3
LS1Note
/AO
LS1Note
LS2 VEE2
Note
LS2
Note
LS2
Note
LS2Note LS2Note LS2Note
O1
O2
O3
O261
O262
O263
Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2 to VEE2). Remark /xxx indicates active low signal.
2
Data Sheet S14680EJ1V0DS
PD16702
2. PIN CONFIGURATION (Top of copper foil surface, Face-up)
PD16702N-xxx: TCP (TAB package)
O1 O2 VDD2 VEE2 VEE1 VSS STVR R,/L CLK /AO OE1 OE2 OE3 STVL VDD1 MODE VSS VEE1 VEE2 VDD2
Copper foil Surface
O261 O262 O263
Remark This figure does not specify the TCP package.
Data Sheet S14680EJ1V0DS
3
PD16702
3. PIN FUNCTIONS
Pin Symbol O1 to O263 Pin Name Driver output I/O Description
Output These pins output scan signals that drive the vertical direction (gate lines) of a TFTLCD. The output signals change in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 to VEE2. Input I/O R,/L = H (right shift): STVR O1 O263 STVL R,/L = L (left shift): STVL O263 O1 STVR This is the input of the internal shift register. The start pulse is read at the rising edge of shift clock CLK, and scan signals are output from the driver output pins. The input level is a VDD1 to VSS (logic level). When in MODE = H, the start pulse is output at the falling edge of the 263rd clock of shift clock CLK, and is cleared at the falling edge of the 264th clock. The output level is VDD1 to VSS (logic level). This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input. When this pin goes high level, the driver output is fixed to VEE2 level. The shift register is not cleared. CLK is asynchronous in the clock. Note that the output terminal which can be controlled by the enable signal changes refers to 4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL. When this pin goes low level, the driver output is fixed to VDD2 level. The shift register is not cleared. This pin has priority over OE1 to OE3. This pin is pulled up to VDD1 power supply inside PD16702. CLK is asynchronous in the clock. MODE = VDD1 or open: 263 outputs MODE = VSS: 256 outputs (Outputs pins O129 to O135 are invalid in 256-output mode.) Input level is VDD1 to VSS (logic level) This pin is pulled up to VDD1 power supply inside PD16702. 2.3 to 3.6 V 15 to 25 V The driver output: high level Connect this pin to the ground of the system. -15 to -5 V
R,/L STVR, STVL
Shift direction select input Start pulse input/output
CLK OE1, OE2, OE3 /AO
Shift clock input Output enable input
Input Input
All-on control
Input
MODE
Selection of Number of outputs
Input
VDD1 VDD2 VSS VEE1
Logic power supply Driver positive power supply Logic ground Negative Power supply for internal operation Driver negative power supply
- - - -
VEE2
-
The driver output: low level (VEE2 to VEE1 < 6.0 V)
Cautions 1. To prevent latch-up, turn on power to VDD1, VEE1/2, VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period. 2. Insert a capacitor of about 0.1 F between each power line, as shown below, to secure noise margin such as VIH and VIL.
VDD2 VDD1 0.1 F VSS 0.1 F VEE 0.1 F
4
Data Sheet S14680EJ1V0DS
PD16702
4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL
Switching is possible for 263/256 with PD16702 by the MODE pin. And, the output terminal which can be controlled by the enable signal changes as follows along with this function.
263 Output TCP 263 Output Mode (MODE = H) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) O127 (OE1) O128 (OE2) O129 (OE3) O130 (OE1) O131 (OE2) O132 (OE3) O133 (OE1) O134 (OE2) O135 (OE3) O136 (OE1) O137 (OE2) O259 (OE1) O260 (OE2) O261 (OE3) O262 (OE1) O263 (OE2) 256 Output Mode (MODE = L) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) O127 (OE1) O128 (OE2) VX = VEE2 VX = VEE2 VX = VEE2 VX = VEE2 VX = VEE2 VX = VEE2 VX = VEE2 O136 (OE3) O137 (OE1) O259 (OE3) O260 (OE1) O261 (OE2) O262 (OE3) O263 (OE1)
256 Output TCP 263 Output Mode (MODE = H) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) O127 (OE1) O128 (OE2) 256 Output Mode (MODE = L) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) O127 (OE1) O128 (OE2)
O136 (OE1) O137 (OE2) O259 (OE1) O260 (OE2) O261 (OE3) O262 (OE1) O263 (OE2)
O136 (OE3) O137 (OE1) O259 (OE3) O260 (OE1) O261 (OE2) O262 (OE3) O263 (OE1)
Remark VX is power-supply voltage of output pin O1 to O263.
Data Sheet S14680EJ1V0DS
5
PD16702
5. TIMING CHART (R,/L = H, /AO = H, MODE = H)
1 CLK 2 3 262 263 264 265
266
OE1
OE2
OE3
STVR (STVL)
O1 (O263)
O2 (O262)
O3 (O261)
O262 (O2)
O263 (O1)
STVL (STVR)
O1 of next stage (O263 of next stage)
O2 of next stage (O262 of next stage)
6
Data Sheet S14680EJ1V0DS
PD16702
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Power Supply Voltage Internal Operation Negative Supply Voltage Driver Negative Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature VDD1 VDD2 VDD2 to VEE1, VEE2 VEE1 VEE2 VI TA Tstg Symbol Rating -0.5 to +7.0 -0.5 to +28 -0.5 to +42 -16 to + 0.5 VEE1 - 0.3 to VEE1 + 7.0 -0.5 to VDD1 + 0.5 -20 to +75 -55 to +125 Unit V V V V V V C C
Caution
Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = -20 to +75C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Internal Operation Negative Supply Voltage Power Supply Voltage VDD1 VDD2 VEE1 VDD2 to VEE1 VEE2 to VEE1 Clock Frequency fCLK Symbol MIN. 2.3 15 -15 20 0 TYP. 3.3 23 -10 33 MAX. 3.6 25 -5.0 40 6.0 100 Unit V V V V V kHz
Data Sheet S14680EJ1V0DS
7
PD16702
Electrical Characteristics (TA = -20 to +75C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage LCD Driver Output ON Resistance Pull-up Resistance Input Leak Current Static Current Dissipation Symbol VIH VIL VOH VOL RON RPU IIL IDD1 Condition CLK, STVR (STVL), R,/L, OE1 to OE3 STVR (STVL), IOH = -40 A STVR (STVL), IOL = +40 A VOUT = VEE2 + 1.0 V, or VDD2 - 1.0 V VDD1 = 3.3 V, /AO, MODE VI = 0 V or 3.6 V, except for /AO, MODE VDD1, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IDD2 VDD2, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IEE VEE1, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load -1100 -550
Note
MIN. 0.8 VDD1 VSS VDD1 - 0.4 VSS
TYP.
MAX. VDD1 0.2 VDD1 VDD1 VSS + 0.4 1.0
Unit V V V V k k
15
35
80 1.0
A A
550
Note
1000
10
Note
100
A
A
Remark STV: STVR (STVL)
Note The TYP. values refer to VDD1 = 3.3 V, TA = 25C.
8
Data Sheet S14680EJ1V0DS
PD16702
Switching Characteristics (TA = -20 to +75C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter Cascade Output Delay Time Symbol tPHL1 tPLH1 Driver Output Delay Time tPHL2 tPLH2 tPHL3 tPLH3 Output Rise Time Output Fall Time Input Capacitance tTLH tTHL CI TA = 25C CL = 300 pF CL = 300 pF, OEn On Condition CL = 20 pF, CLK STVL (STVR) CL = 300 pF, CLK On MIN. TYP. MAX. 800 800 800 800 800 800 350 350 15 Unit ns ns ns ns ns ns ns ns pF
Timing Requirements (TA = -20 to +75C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter Clock Pulse High Width Clock Pulse Low Width Enable Pulse Width Data Setup Time Data Hold Time Symbol PWCLK(H) PWCLK(L) PWOE tSETUP tHOLD STVR (STVL) CLK CLK STVR (STVL) Condition MIN. 500 500 1000 200 200 TYP. MAX. Unit ns ns ns ns ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. Caution Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90% of the rated values).
Data Sheet S14680EJ1V0DS
9
PD16702
Switching Characteristics Waveform (R,/L= H, MODE = H) Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
tf
tr
90%
10%
PWOE
tPHL3
tPLH3
tPLH1
tPHL1
50%
4
5
6
7
260
261
262
263
PWCLK(L)
3
PWCLK(H)
tPHL2
2
90%
90%
tSETUP tHOLD
tPLH2
1
50%
50%
10%
10% tTLH
tTHL
50%
50%
10
Data Sheet S14680EJ1V0DS
O1 to O263 STVR STVL O1 O262 CLK O263 OE O2 * * *
90%
10%
PD16702
7. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16702. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16702N-xxx: TCP (TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C, heating for 2 to 3 seconds : pressure 100g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm2: time 3 to 5 sec. Real bonding 165 to 180C: pressure 25 to 45 kg/cm2: time 30 to 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
Data Sheet S14680EJ1V0DS
11
PD16702
[MEMO]
12
Data Sheet S14680EJ1V0DS
PD16702
[MEMO]
Data Sheet S14680EJ1V0DS
13
PD16702
[MEMO]
14
Data Sheet S14680EJ1V0DS
PD16702
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14680EJ1V0DS
15
PD16702
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E)
* The information in this document is current as of September, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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