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PIC12F635/PIC16F636/639 Data Sheet
8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
*8-bit, 8-pin Devices Protected by Microchip's Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41232B-page ii
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers With nanoWatt Technology
High-Performance RISC CPU:
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Peripheral Features:
* 6/12 I/O pins with individual direction control: - High-current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups/ pull-downs - Ultra Low-Power Wake-up * Analog comparator module with: - Up to two analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally accessible * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected * KEELOQ(R) compatible hardware Cryptographic module * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1% - Software selectable frequency range of 8 MHz to 31 kHz - Software tunable - Two-Speed Start-up mode - Crystal fail detect for critical applications * Clock mode switching for low power operation * Power-saving Sleep mode * Wide operating voltage range (2.0V-5.5V) * Industrial and Extended Temperature range * Power-on Reset (POR) * Wake-up Reset (WUR) * Independent weak pull-up/pull-down resistors * Programmable Low-Voltage Detect (PLVD) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Detect (BOD) with software control option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with pull-up/input pin * Programmable code protection (program and data independent) * High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM Retention: > 40 years
Low Frequency Analog Front-End Features (PIC16F639 only):
* Three input pins for 125 kHz LF input signals * High input detection sensitivity (3 mVPP, typical) * Demodulated data, Carrier clock or RSSI output selection * Input carrier frequency: 125 kHz, typical * Input modulation frequency: 4 kHz, maximum * 8 internal configuration registers * Bidirectional transponder communication (LF talk back) * Programmable antenna tuning capacitance (up to 63 pF, 1 pF/step) * Low standby current: 5 A (with 3 channels enabled), typical * Low operating current: 15 A (with 3 channels enabled), typical * Serial Peripheral Interface (SPITM) with internal MCU and external devices * Supports Battery Back-up mode and batteryless operation with external circuits
Low Power Features:
* Standby Current: - 1 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 1
PIC12F635/PIC16F636/639
Program Memory Device Flash (words) PIC12F635 PIC16F636 PIC16F639 1024 2048 2048 SRAM (bytes) 64 128 128 EEPROM (bytes) 128 256 256 6 12 12 1 2 2 Data Memory I/O Comparators Low Frequency Analog Front-End N N Y
Pin Diagrams
8-Pin PDIP, SOIC, DFN-S
VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT
14-Pin PDIP, SOIC, TSSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3 1 2 3 4 5 6 7 VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2
PIC12F635 PIC16F636
14 13 12 11 10 9 8
20-Pin SSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO VDDT(3) LCZ LCY VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT VSST(4) LCCOM LCX
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively. 2: Additional information on I/O ports may be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). 3: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in this document unless otherwise stated. 4: VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated as VSS in this document unless otherwise stated.
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Preliminary
PIC16F639
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Clock Sources ............................................................................................................................................................................ 29 4.0 I/O Ports ..................................................................................................................................................................................... 39 5.0 Timer0 Module ........................................................................................................................................................................... 53 6.0 Timer1 Module with Gate Control............................................................................................................................................... 56 7.0 Comparator Module.................................................................................................................................................................... 61 8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 71 9.0 Data EEPROM Memory ............................................................................................................................................................. 73 10.0 KeeLoq Compatible Cryptographic Module................................................................................................................................ 77 11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 79 12.0 Special Features of the CPU.................................................................................................................................................... 111 13.0 Instruction Set Summary .......................................................................................................................................................... 131 14.0 Development Support............................................................................................................................................................... 141 15.0 Electrical Specifications............................................................................................................................................................ 147 16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 173 17.0 Packaging Information.............................................................................................................................................................. 175 On-Line Support 185 Systems Information and Upgrade Hot Line ..................................................................................................................................... 185 Reader Response ............................................................................................................................................................................. 186 Appendix A: Data Sheet Revision History......................................................................................................................................... 187 Appendix B: Product Identification System ....................................................................................................................................... 193 Worldwide Sales and Service ........................................................................................................................................................... 194
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:
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(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 3
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 4
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC12F635/PIC16F636/639 devices. Additional information may be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F635/PIC16F636/639 devices are covered by this data sheet. Figure 1-1 shows a block diagram of the PIC12F635/PIC16F636/639 devices. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC12F635 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 1K x 14 Program Memory Data Bus 8 GPIO GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT GP3/MCLR/VPP GP4/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN
8-level Stack (13-bit)
RAM 64 bytes File Registers RAM Addr 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg Status reg 8 3
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect Programmable Low-Voltage Detect Wake-up Reset
MUX
ALU 8 W reg
T1G MCLR VDD T1CKI Timer0 T0CKI Timer1 VSS
Cryptographic Module
1 Analog Comparator and Reference
EEDAT 128 bytes Data EEPROM EEADDR
C1IN- C1IN+ C1OUT
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 5
PIC12F635/PIC16F636/639
FIGURE 1-2: PIC16F636 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 2K x 14 Program Memory Data Bus 8 PORTA RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK 8-level Stack (13-bit) RAM 128 bytes File Registers RAM Addr 9 RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr PORTC RC0/C2IN+ RC1/C2INRC2 RC3 RC4/C2OUT RC5 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect Programmable Low-Voltage Detect Wake-up Reset 3 MUX
FSR reg Status reg 8
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
ALU 8 W reg
T1CKI
T1G
MCLR VDD Timer0 T0CKI
VSS Timer1
Cryptographic Module
2 Analog Comparators and Reference
EEDAT 256 bytes Data EEPROM EEADDR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
DS41232B-page 6
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 1-3: PIC16F639 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 2K x 14 Program Memory Data Bus 8 PORTA RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RAM 8-level Stack (13-bit) RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN
128 bytes
File Registers RAM Addr (1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr PORTC RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT RC3/LFDATA/RSSI/CCLK/SDIO RC4/C2OUT RC5 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect Programmable Low-voltage Detect Wake-up Reset 3 MUX
FSR reg Status reg 8
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
ALU 8 W reg VDDT VSST LCCOM
125 kHz Analog Front-End (AFE)
T1CKI
T1G
LCX LCY LCZ
MCLR VDD Timer0 T0CKI
VSS Timer1
KEELOQ Module
2 Analog Comparators and Reference
EEDAT 256 bytes DATA EEPROM EEADDR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 7
PIC12F635/PIC16F636/639
TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS
Function VDD GP5 T1CKI OSC1 CLKIN GP4/T1G/OSC2/CLKOUT GP4 T1G OSC2 CLKOUT GP3/MCLR/VPP GP3 MCLR VPP GP2/T0CKI/INT/C1OUT GP2 Input Type D TTL ST XTAL ST TTL ST -- -- TTL ST HV ST Output Type -- Description Power supply for microcontroller. Name VDD GP5/T1CKI/OSC1/CLKIN
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up/pull-down. -- -- -- Timer1 clock. XTAL connection. TOSC reference clock.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up/pull-down. -- XTAL -- -- -- Timer1 gate. XTAL connection. General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage.
CMOS TOSC/4 reference clock.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- -- External clock for Timer0. External interrupt.
T0CKI INT C1OUT GP1/C1IN-/ICSPCLK GP1
ST ST -- TTL
CMOS Comparator 1 output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- -- -- Comparator 1 input - negative. Serial programming clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input - positive. Ultra Low-Power Wake-up input. Ground reference for microcontroller.
C1INICSPCLK GP0/C1IN+/ICSPDAT/ULPWU GP0
AN ST TTL
C1IN+ ICSPDAT ULPWU VSS VSS Legend: AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN D
-- -- --
CMOS Serial programming data I/O.
CMOS = CMOS compatible input or output D = Direct ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS
Function VDD RA5 T1CKI OSC1 CLKIN RA4/T1G/OSC2/CLKOUT RA4 T1G OSC2 CLKOUT RA3/MCLR/VPP RA3 MCLR VPP RC5 RC4/C2OUT RC3 RC2 RC1/C2INRC0/C2IN+ RA2/T0CKI/INT/C1OUT RC5 RC4 C2OUT RC3 RC2 RC1 C2INRC0 C2IN+ RA2 T0CKI INT C1OUT RA1/C1IN-/VREF/ICSPCLK RA1 C1INICSPCLK RA0/C1IN+/ICSPDAT/ULPWU RA0 Input Type D TTL ST XTAL ST TTL ST -- -- TTL ST HV TTL TTL -- TTL TTL TTL AN TTL AN ST ST ST -- TTL AN ST TTL Output Type -- Description Power supply for microcontroller. Name VDD RA5/T1CKI/OSC1/CLKIN
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- -- -- Timer1 clock. XTAL connection. TOSC reference clock.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- XTAL -- -- -- Timer1 gate. XTAL connection. General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage.
CMOS TOSC/4 reference clock.
CMOS General purpose I/O. CMOS General purpose I/O. CMOS Comparator 2 output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. -- -- Comparator 1 input - negative. Comparator 1 input - positive. CMOS General purpose I/O. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- -- External clock for Timer0. External interrupt.
CMOS Comparator 1 output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. -- -- -- Comparator 1 input - negative. Serial programming clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input - positive. Ultra Low-Power Wake-up input. Ground reference for microcontroller.
C1IN+ ICSPDAT ULPWU VSS VSS Legend: AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN D
-- -- --
CMOS Serial programming data I/O.
CMOS = CMOS compatible input or output D = Direct ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 9
PIC12F635/PIC16F636/639
TABLE 1-3:
Name VDD RA5/T1CKI/OSC1/CLKIN
PIC16F639 PINOUT DESCRIPTIONS
Function VDD RA5 T1CKI OSC1 CLKIN Input Type D TTL ST XTAL ST TTL ST -- -- TTL ST HV TTL TTL -- TTL -- -- -- TTL D AN AN AN AN D TTL TTL -- TTL AN TTL TTL AN ST ST ST -- TTL AN ST TTL Output Type -- CMOS -- -- -- CMOS -- XTAL CMOS -- -- -- CMOS CMOS CMOS CMOS CMOS Current -- CMOS -- -- -- -- -- -- CMOS -- OD CMOS -- -- CMOS -- CMOS -- -- CMOS CMOS -- -- -- Description Power supply for microcontroller General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 clock XTAL connection TOSC/4 reference clock General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 gate XTAL connection TOSC reference clock General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage General purpose I/O General purpose I/O Comparator2 output General purpose I/O Digital output representation of analog input signal to LC pins. Received signal strength indicator. Analog current that is proportional to input amplitude. Carrier clock output Input/Output for SPI communication Power supply for Analog Front-End. In this document, VDDT is treated the same as VDD, unless otherwise stated. 125 kHz analog Z channel input 125 kHz analog Y channel input 125 kHz analog X channel input Common reference for analog inputs Ground reference for Analog Front-End. In this document, VSST is treated the same as VSS, unless otherwise stated. General purpose I/O Digital clock input for SPI communication
Output with internal pull-up resistor for AFE error signal General purpose I/O Comparator1 input - negative Chip select input for SPI communication with internal pull-up resistor General purpose I/O Comparator1 input - positive
RA4/T1G/OSC2/CLKOUT
RA4 T1G OSC2 CLKOUT
RA3/MCLR/VPP
RA3 MCLR VPP
RC5 RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO
RC5 RC4 C2OUT RC3 LFDATA RSSI CCLK SDIO
VDDT LCZ LCY LCX LCCOM VSST RC2/SCLK/ALERT
VDDT LCZ LCY LCX LCCOM VSST RC2 SCLK ALERT
RC1/C2IN-/CS
RC1 C2INCS
RC0/C2IN+ RA2/T0CKI/INT/C1OUT
RC0 C2IN+ RA2 T0CKI INT C1OUT
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. External clock for Timer0 External Interrupt Comparator1 output General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Comparator1 input - negative Serial Programming Clock General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator1 input - positive Serial Programming Data IO Ultra Low-Power Wake-up input Ground reference for microcontroller D = Direct OD = Direct
RA1/C1IN-/VREF/ICSPCLK
RA1 C1INICSPCLK
RA0/C1IN+/ICSPDAT/ULPWU
RA0
C1IN+ ICSPDAT ULPWU VSS Legend: VSS AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN D CMOS ST XTAL
-- CMOS -- --
= CMOS compatible input or output = Schmitt Trigger input with CMOS levels = Crystal
DS41232B-page 10
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-1: PROGRAM MEMORY MAP AND STACK OF THE PIC12F635
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 13
The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
Stack Level 8 Reset Vector 0000h
2.2
Data Memory Organization
Interrupt Vector
0004h 0005h
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, register locations 40h through 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h7Fh in Bank 0. All other RAM is unimplemented and returns `0' when read. RP0 (STATUS<5>) is the bank select bit.
On-chip Program Memory 03FFh 0400h Access 0-3FFh 1FFFh
FIGURE 2-2: PROGRAM MEMORY MAP AND STACK OF THE PIC16F636/639
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1
TABLE 2-1:
RP0 0 1 0 1
BANK SELECTION
RP1 0 0 1 1 Bank 0 1 2 3
13
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h 0005h
On-chip Program Memory
07FFh 0800h Access 0-7FFh 1FFFh
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 11
PIC12F635/PIC16F636/639
2.2.1 GENERAL PURPOSE REGISTER
The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select Register, FSR (see Section 2.4 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS
File Address Indirect addr.(1) TMR0 PCL STATUS FSR GPIO 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h LVDCON WPUDA IOCA WDA VRCON EEDAT EEADR EECON1 EECON2(1) Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISIO File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h CRCON CRDAT0(2) CRDAT1(2) CRDAT2 CRDAT3
(2) (2)
File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
Accesses 00h-0Bh
Accesses 80h-8Bh
PCLATH INTCON PIR1 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PCON OSCCON OSCTUNE
WDTCON CMCON0 CMCON1
General Purpose Register 64 Bytes Bank 0
3Fh 40h EFh F0h FFh 16Fh 170h 17Fh 1EFh 1F0h 1FFh
7Fh
Accesses 70h-7Fh Bank 1
Accesses 70h-7Fh Bank 2
Accesses Bank 0 Bank 3
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register. 2: CRDAT<3:0> are KEELOQ(R) hardware peripheral related registers and require the execution of the "KEELOQ(R) Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 13
PIC12F635/PIC16F636/639
FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h 86h TRISC 87h 88h 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch 8Dh PCON 8Eh OSCCON OSCTUNE 8Fh 90h 91h 92h 93h LVDCON WPUDA IOCA WDA VRCON EEDAT EEADR EECON1 EECON2(1) 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h CRCON CRDAT0(2) CRDAT1(2) CRDAT2
(2)
File Address Indirect addr.(1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h 06h PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H T1CON 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register 96 Bytes 7Fh Bank 0
Accesses 00h-0Bh
File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
Accesses 80h-8Bh
File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
CRDAT3(2)
WDTCON CMCON0 CMCON1
General Purpose Register 32 Bytes
Accesses 70h-7Fh Bank 1
BFh C0h EFh F0h FFh
Accesses 70h-7Fh Bank 2
16Fh 170h 17Fh
Accesses Bank 0 Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register. 2: CRDAT<3:0> are KEELOQ hardware peripheral related registers and require the execution of the "KEELOQ(R) Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
DS41232B-page 14
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-2:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- WDTCON CMCON0 CMCON1 -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP -- RP1 -- RP0 GP5 TO GP4 PD GP3 Z GP2 DC GP1 C GP0 Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIF -- PEIE LVDIF -- T0IE CRIF Write Buffer for upper 5 bits of Program Counter INTE -- RAIE C1IF T0IF OSFIF INTF -- RAIF(2) TMR1IF xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --xx xx00 --uu uu00 -- -- -- -- -- -- -- -- Name
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOD/ WUR Value on all other Resets(1)
---0 0000 ---0 0000 0000 0000 0000 0000 000- 00-0 000- 00-0 -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- C1OUT -- -- -- -- C1INV -- CIS -- CM2 -- CM1 T1GSS CM0 TMR1CS
TMR1ON 0000 0000 uuuu uuuu -- -- -- -- -- -- -- -- -- -- -- -- -- --
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 -0-0 0000 -0-0 0000 -- -- -- -- -- -- -- -- -- -- CMSYNC ---- --10 ---- --10
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 15
PIC12F635/PIC16F636/639
TABLE 2-3:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 9Bh 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: INDF OPTION_REG PCL STATUS FSR TRISIO -- -- -- -- PCLATH INTCON PIE1 -- PCON OSCCON OSCTUNE -- -- -- LVDCON WPUDA(2) IOCA WDA(2) -- VRCON EEDAT EEADR EECON1 EECON2 -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- INTEDG RP1 -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC TRISIO1 PS0 C Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer TRISIO5 TRISIO4 TRISIO3 TRISIO2 Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIE -- -- -- -- PEIE LVDIE -- IRCF2 -- -- T0IE CRIE Write Buffer for upper 5 bits of Program Counter INTE -- RAIE C1IE WUR OSTS TUN3 T0IF OSFIE -- HTS TUN2 INTF -- POR LTS TUN1 xxxx xxxx xxxx xxxx 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu TRISIO0 --11 1111 --11 1111 -- -- -- -- -- -- -- -- Name
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOD/ WUR Value on all other Resets(1)
---0 0000 ---0 0000
RAIF(3) 0000 0000 0000 0000 TMR1IE 000- 00-0 000- 00-0 -- -- BOD SCS TUN0
Unimplemented ULPWUE SBODEN IRCF1 -- IRCF0 TUN4
--01 q-qq --0u u-uu -110 q000 -110 x000 ---0 0000 ---u uuuu -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented -- -- -- -- VREN -- -- -- -- -- IRVST IOCA5 WDA5 VRR LVDEN IOCA4 WDA4 -- -- -- IOCA3 -- VR3 LVDL2 IOCA2 WDA2 VR2 LVDL1 IOCA1 WDA1 VR1 LVDL0 IOCA0 WDA0 VR0 WPUDA5 WPUDA4
--00 -000 --00 -000
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 --00 0000 --00 0000 --11 -111 --11 -111 -- --
Unimplemented
0-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 -- -- -- -- WRERR WREN WR RD ---- x000 ---- q000 ---- ---- ---- ----- -- -- -- EEPROM Control Register 2 (not a physical register) Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set again if the mismatch exists.
DS41232B-page 16
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-4:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: INDF TMR0 PCL STATUS FSR PORTA -- PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- WDTCON CMCON1 -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP -- -- RP1 -- -- RP0 RA5 RC5 TO RA4 RC4 PD RA3 RC3 Z RA2 RC2 DC RA1 RC1 C RA0 RC0 Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented -- GIE EEIF -- PEIE LVDIF -- T0IE CRIF Write Buffer for upper 5 bits of Program Counter INTE C2IF RAIE C1IF T0IF OSFIF INTF -- RAIF(2) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuxx --xx xx00 --uu uu00 -- -- -- -- -- -- Name
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOD/ WUR Value on all other Resets(1)
--xx xx00 --uu uu00
---0 0000 ---0 0000 0000 0000 0000 0000 -- --
TMR1IF 0000 00-0 0000 00-0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- C1OUT -- -- C2INV -- C1INV -- CIS -- CM2 -- CM1 T1GSS CM0
TMR1CS TMR1ON 0000 0000 uuuu uuuu -- -- -- -- -- -- -- -- -- -- -- -- -- --
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- C2SYNC ---- --10 ---- --10
CMCON0 C2OUT
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 17
PIC12F635/PIC16F636/639
TABLE 2-5:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h INDF OPTION_REG PCL STATUS FSR TRISA -- TRISC -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- -- INTEDG RP1 -- -- T0CS RP0 TRISA5 TRISC5 T0SE TO TRISA4 TRISC4 PSA PD TRISA3 TRISC3 PS2 Z TRISA2 TRISC2 PS1 DC TRISA1 TRISC1 PS0 C Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented -- GIE EEIE -- OSCCON OSCTUNE -- -- -- LVDCON WPUDA(2) IOCA WDA(2) -- VRCON -- -- -- -- PEIE LVDIE -- IRCF2 -- -- T0IE CRIE Write Buffer for upper 5 bits of Program Counter INTE C2IE RAIE C1IE WUR OSTS TUN3 T0IF OSFIE -- HTS TUN2 INTF -- POR LTS TUN1 RAIF(3) xxxx xxxx xxxx xxxx 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu TRISA0 --11 1111 --11 1111 -- -- -- -- -- -- TRISC0 --11 1111 --11 1111 Name
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOD/ WUR Value on all other Resets(1)
8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 9Bh 99h 8Eh PCON
---0 0000 ---0 0000 0000 0000 0000 0000 -- --
TMR1IE 0000 00-0 0000 00-0 BOD SCS TUN0
Unimplemented ULPWUE SBODEN IRCF1 -- IRCF0 TUN4
--01 q-qq --0u u-uu -110 q000 -110 x000 ---0 0000 ---u uuuu -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented -- -- -- -- VREN -- -- -- -- -- IRVST IOCA5 WDA5 VRR LVDEN IOCA4 WDA4 -- -- -- IOCA3 -- VR3 LVDL2 IOCA2 WDA2 VR2 LVDL1 IOCA1 WDA1 VR1 EEDAT1 WR LVDL0 IOCA0 WDA0 VR0 WPUDA5 WPUDA4
--00 -000 --00 -000
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 --00 0000 --00 0000 --11 -111 --11 -111 -- --
Unimplemented EEDAT7 EEDAT6 EEDAT5 -- -- -- EEDAT4 EEDAT3 EEDAT2 -- WRERR WREN
0-0- 0000 0-0- 0000
9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON2 9Eh 9Fh Legend: Note 1: 2: 3: -- --
EEDAT0 0000 0000 0000 0000 RD ---- x000 ---- q000 ---- ---- ---- ----- -- -- --
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EEPROM Control Register 2 (not a physical register) Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
DS41232B-page 18
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-6:
Addr Bank 2 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h Legend: Note 1:
2:
PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOD/ WUR Value on all other Resets(1)
Name
-- -- -- -- CRCON CRDAT1(2)
Unimplemented Unimplemented Unimplemented Unimplemented GO/DONE ENC/DEC -- -- -- -- CRREG1
-- -- -- --
-- -- -- --
CRREG0 00-- --00 00-- --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- --
CRDAT0(2) Cryptographic Data Register 0 Cryptographic Data Register 1 CRDAT2(2) Cryptographic Data Register 2 CRDAT3(2) Cryptographic Data Register 3 -- -- Unimplemented Unimplemented
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
CRDAT<3:0> are KEELOQ(R) hardware peripheral related registers and require the execution of the "KEELOQ Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 19
PIC12F635/PIC16F636/639
2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Status register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see Section 13.0 "Instruction Set Summary". Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS - STATUS REGISTER (ADDRESS: 03h OR 83h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes. TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS41232B-page 20
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
2.2.2.2 Option Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting the PSA bit to `1' (OPTION_REG<3>). See Section 5.4 "Prescaler". The Option register is a readable and writable register which contains various control bits to configure: * * * * TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-up/pull-downs on PORTA
REGISTER 2-2:
OPTION_REG - OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RAPU: PORTA Pull-up/Pull-down Enable bit 1 = PORTA pull-ups/pull-downs are disabled 0 = PORTA pull-ups/pull-downs are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 21
PIC12F635/PIC16F636/639
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
REGISTER 2-3:
INTCON - INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE(1) R/W-0 T0IF
(2)
R/W-0 INTF
R/W-0 RAIF(3) bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt RAIE: PORTA Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur RAIF: PORTA Change Interrupt Flag bit(3) 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state Note 1: IOCA register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing the T0IF bit. 3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41232B-page 22
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
PIE1 -- PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 LVDIE R/W-0 CRIE R/W-0 C2IE(1) R/W-0 C1IE R/W-0 OSFIE U-0 -- R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the LVD interrupt 0 = Disables the LVD interrupt CRIE: Cryptographic Interrupt Enable bit 1 = Enables the cryptographic interrupt 0 = Disables the cryptographic interrupt C2IE: Comparator 2 Interrupt Enable bit(1) 1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt C1IE: Comparator 1 Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt Unimplemented: Read as `0' TMR1IE: Timer1 Interrupt Enable bit 1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt Note 1: PIC16F636/639 only. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 23
PIC12F635/PIC16F636/639
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
PIR1 - PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 LVDIF R/W-0 CRIF R/W-0 C2IF(1) R/W-0 C1IF R/W-0 OSFIF U-0 -- R/W-0 TMR1IF bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = The supply voltage has crossed selected LVD voltage (must be cleared in software) 0 = The supply voltage has not crossed selected LVD voltage CRIF: Cryptographic Interrupt Flag bit 1 = The Cryptographic module has completed an operation (must be cleared in software) 0 = The Cryptographic module has not completed an operation or is Idle C2IF: Comparator 2 Interrupt Flag bit(1) 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed INTOSC (must be cleared in software) 0 = System clock operating Unimplemented: Read as `0' TMR1IF: Timer1 Interrupt Flag bit 1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 has not rolled over Note 1: PIC16F636/639 only. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
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2.2.2.6 PCON Register
The Power Control (PCON) register (see Table 12-3) contains flag bits to differentiate between a: * * * * * Power-on Reset (POR) Wake-up Reset (WUR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD. The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON - POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- R/W-0 R/W-1
(1)
R/W-x WUR
U-0 --
R/W-0 POR
R/W-x BOD bit 0
ULPWUE SBODEN
bit 7-6 bit 5
Unimplemented: Read as `0' ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled SBODEN: Software BOD Enable bit(1) 1 = BOD enabled 0 = BOD disabled WUR: Wake-up Reset Status bit 1 = No Wake-up Reset occurred 0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs) Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect Status bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) Note 1: BODEN<1:0> = 01 in the Configuration Word register for SBODEN to control the Brown-out Detect module. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3
bit 2 bit 1
bit 0
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2.3 PCL and PCLATH
2.3.1 COMPUTED GOTO
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
2.3.2
STACK
FIGURE 2-5:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU Result
PCH 12 PC 5
The PIC12F635/PIC16F636/639 family has an 8level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions.
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode<10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
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2.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (STATUS<7>), as shown in Figure 2-6.
EXAMPLE 2-1:
MOVLW MOVWF CLRF INCF BTFSS GOTO
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;INC POINTER ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639
Indirect Addressing 0 IRP 7 File Select Register 0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Bank 1 Bank 2 Bank 3
1FFh
Note: For memory map detail, see Figure 2-2.
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NOTES:
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3.0
3.1
CLOCK SOURCES
Overview
The PIC12F635/PIC16F636/639 can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on RA4. LP - Low gain crystal or Ceramic Resonator Oscillator mode. XT - Medium gain crystal or Ceramic Resonator Oscillator mode. HS - High gain crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on RA4. RCIO - External Resistor-Capacitor (RC) with I/O on RA4. INTOSC - Internal oscillator with FOSC/4 output on RA4 and I/O on RA5. INTOSCIO - Internal oscillator with I/O on RA4 and RA5.
The PIC12F635/PIC16F636/639 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications, while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC12F635/PIC16F636/639 clock sources. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the internal oscillator.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 12.0 "Special Features of the CPU"). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator. The LFINTOSC is a low-frequency uncalibrated oscillator.
FIGURE 3-1:
PIC12F635/PIC16F636/639 CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word) SCS (OSCCON<0>)
External Oscillator OSC2 Sleep OSC1 IRCF<2:0> (OSCCON<6:4>) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz LFINTOSC(2) 31 kHz 31 kHz 011 010 001 000 MUX 1 MHz HFINTOSC 8 MHz
(1)
LP, XT, HS, RC, RCIO, EC MUX
System Clock (CPU and Peripherals)
111 110
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) Note 1: 2: HFINTOSC = High-Frequency Calibrated Internal Oscillator. LFINTOSC = Low-Frequency Internal Oscillator is not calibrated.
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3.2 Clock Source Modes 3.3
3.3.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock source modes can be classified as external or internal. External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC mode) circuits. Internal clock sources are contained internally within PIC12F635/PIC16F636/639. The device has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 "Clock Switching").
If the PIC12F635/PIC16F636/639 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from the OSC1 pin following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC12F635/ PIC16F636/639. When switching between clock sources, a delay is required to allow the new clock to stabilize. Table 3-1 shows oscillator delay examples. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Startup mode can be selected (see Section 3.6 "Two-Speed Clock Start-up Mode").
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch To LFINTOSC HFINTOSC EC, RC EC, RC LP, XT, HS HFINTOSC Frequency 31 kHz 125 kHz-8 MHz DC - 20 MHz DC - 20 MHz 31 kHz-20 MHz 125 kHz-8 MHz 1024 Clock Cycles (OST) 1 s (approx.) Oscillator Delay 5 s-10 s (approx.) CPU Start-up
Switch From Sleep/POR Sleep/POR LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz)
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3.3.2 EC MODE FIGURE 3-3:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the RA5 pin is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC12F635/PIC16F636/639 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
C1 Quartz Crystal OSC2 RS(1) C2 RF(2)
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC12F635/PIC16F636/639
OSC1
To Internal Logic Sleep
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M).
FIGURE 3-2:
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC12F635/PIC16F636/639
Clock from Ext. System RA4
I/O (OSC2)
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
3.3.3
LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is better suited to drive resonators with a medium drive level specification, for example, lowfrequency AT-cut quartz crystal resonators. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is better suited for resonators that require a high drive setting, for example, high-frequency AT-cut quartz crystal resonators or ceramic resonators. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
FIGURE 3-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC12F635/PIC16F636/639
OSC1
C1 RP(3) OSC2 RS(1) C2 Ceramic Resonator RF(2)
To Internal Logic Sleep
Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation (typical value 1 M).
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3.3.4 EXTERNAL RC MODES
3.4
Internal Clock Modes
The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes, RC and RCIO. In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKOUT pin outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the RC mode connections.
The PIC12F635/PIC16F636/639 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted 12% via software using the OSCTUNE register (Register 3-1). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
2.
FIGURE 3-5:
VDD REXT
RC MODE
The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits.
Internal Clock
OSC1 CEXT VSS FOSC/4
The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 3.5 "Clock Switching").
3.4.1
PIC12F635/PIC16F636/639 OSC2/CLKOUT
LFINTOSC AND LFINTOSCIO MODES
Recommended values: 3 k REXT 100 k CEXT > 20 pF
In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of PORTA (RA4). Figure 3-6 shows the RCIO mode connections.
The LFINTOSC and LFINTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection (FOSC) bits in the Configuration Word register (Register 12-1). In LFINTOSC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKOUT pin outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In LFINTOSCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.
FIGURE 3-6:
VDD REXT
RCIO MODE
OSC1 CEXT VSS RA4
Internal Clock
3.4.2
HFINTOSC
PIC12F635/PIC16F636/639 I/O (OSC2)
Recommended values: 3 k REXT 100 k CEXT > 20 pF
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately 12% via software using the OSCTUNE register (Register 3-1). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF 000) as the system clock source (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF 000). The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.
The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal threshold voltage. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency or for low CEXT values. The user also needs to take into account variation due to tolerance of external RC components used.
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3.4.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The OSCTUNE register has a tuning range of approximately 12%. The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. Due to process variation, the monotonicity and frequency step cannot be specified. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 3-1:
OSCTUNE - OSCILLATOR TUNING REGISTER (ADDRESS: 90h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
bit 7-5 bit 4-0
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency Legend: R = Readable bit - n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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3.4.3 LFINTOSC 3.4.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 "Frequency Select Bits (IRCF)"). The LFINTOSC is also the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock source (SCS = 1), or when any of the following are enabled: * * * * Two-Speed Start-up (IESO = 1 and IRCF = 000) Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10 s delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. IRCF bits are modified. If the new clock is shut down, a 10 s clock startup delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. HTS/LTS bits are updated as required. Clock switch is complete.
The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.
3.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz Note: Following any Reset, the IRCF bits are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Note: Care must be taken to ensure a valid voltage or frequency selection is chosen. See voltage vs. frequency diagrams (Figure 15-2, Figure 15-3 and Figure 15-4) for more detail.
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PIC12F635/PIC16F636/639
3.5 Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit. When the PIC12F635/PIC16F636/639 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 "Oscillator Startup Timer (OST)"). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.
3.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals. When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (Register 12-1). When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.
3.6.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO = 1 (CONFIG<10>) Internal/External Switchover bit. * SCS = 0. * FOSC configured for LP, XT or HS mode. * Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after PWRT has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then TwoSpeed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
3.5.2
OSCILLATOR START-UP TIME-OUT STATUS BIT
The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
3.6.2
TWO-SPEED START-UP SEQUENCE
The Two-Speed Start-up sequence is listed below.
3.6
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.
1. 2.
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits (OSCCON<6:4>). OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
3.6.3
CHECKING EXTERNAL/INTERNAL CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F635/PIC16F636/639 is running from the external clock source, as defined by the FOSC bits in the Configuration Word register (Register 12-1) or the internal oscillator.
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FIGURE 3-7: TWO-SPEED START-UP
Q1 INTOSC TOST T OSC1 0 1 1022 1023 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC2 Program Counter PC PC + 1 PC + 2
System Clock
3.7
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.
The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit. The FSCM sample clock is generated by dividing the LFINTOSC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram. On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the sample clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled, as reflected by the IRCF.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Primary Clock
S
Q
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
C
Q
Clock Failure Detected
Note 1: Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled. 2: Primary clocks with a frequency of ~488 Hz will be considered failed by FSCM. A slow starting oscillator can cause an FCSM interrupt.
The FSCM function is enabled by setting the FCMEN bit in the Configuration Word register (Register 12-1). It is applicable to all external clock options (LP, XT, HS, EC, RC or I/O modes). In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1<2>) and generate an oscillator fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
3.7.1 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F635/ PIC16F636/639 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-9:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
3.7.2
RESET OR WAKE-UP FROM SLEEP
Note:
The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events. For LP, XT or HS mode, the external oscillator may require a start-up time considerably longer than the FSCM sample clock time or a false clock failure may be detected (see Figure 3-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 37
PIC12F635/PIC16F636/639
REGISTER 3-2: OSCCON - OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 -- bit 7 bit 7 bit 6-4 Unimplemented: Read as `0' IRCF<2:0>: Nominal Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC) HTS: HFINTOSC (High Frequency - 8 MHz to 125 kHz) Status bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC (Low Frequency - 31 kHz) Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. Legend: R = Readable bit - n = Value at POR R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1 OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
bit 3
bit 2
bit 1
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TABLE 3-2:
Address 0Ch 8Ch 8Fh 90h 2007h(1) Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 EEIF EEIE -- -- CPD Bit 6 LVDIF LVDIE IRCF2 -- CP Bit 5 CRIF CRIE IRCF1 -- Bit 4 C2IF C2IE IRCF0 TUN4 Bit 3 C1IF C1IE OSTS TUN3 WDTE Bit 2 OSFIF OSFIE HTS TUN2 FOSC2 Bit 1 -- -- LTS TUN1 FOSC1 Bit 0 Value on: POR, BOD, WUR Value on all other Resets
PIR1 PIE1 OSCCON OSCTUNE CONFIG
TMR1IF 0000 00-0 0000 00-0 TMR1IE 0000 00-0 0000 00-0 SCS TUN0 FOSC0 -110 x000 -110 x000 ---0 0000 ---u uuuu -- --
MCLRE PWRTE
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by oscillators. See Register 12-1 for operation of all Configuration Word register bits.
DS41232B-page 38
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.0 I/O PORTS
4.2 Additional Pin Functions
There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/ pull-down option. RA0 has an Ultra Low-Power Wakeup option. The next three sections describe these functions.
4.2.1
WEAK PULL-UP/PULL-DOWN
4.1
PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 4-1 shows how to initialize PORTA. Reading the PORTA register (Register 4-3) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. RA3 reads `0' when MCLRE = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
Each of the PORTA pins, except RA3, has an internal weak pull-up and pull-down. The WDA bits select either a pull-up or pull-down for an individual port bit. Individual control bits can turn on the pull-up or pulldown. These pull-ups/pull-downs are automatically turned off when the port pin is configured as an output, as an alternate function or on a Power-on Reset, setting the RAPU bit (OPTION_REG<7>). A weak pullup on RA3 is enabled when configured as MCLR in the Configuration Word register and disabled when high voltage is detected, to reduce current consumption through RA3, while in Programming mode. Note: PORTA = GPIO TRISA = TRISIO
EXAMPLE 4-1:
BCF BCF CLRF MOVLW MOVWF BSF BCF MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 PORTA 07h CMCON0 STATUS,RP0 STATUS,RP1 0Ch TRISA STATUS,RP0 STATUS,RP1
INITIALIZING PORTA
;Bank 0 ; ;Init PORTA ;Set RA<2:0> to ;digital I/O ;Bank 1 ; ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs ;Bank 0 ;
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 39
PIC12F635/PIC16F636/639
REGISTER 4-1: WDA - WEAK PULL-UP/PULL-DOWN REGISTER (ADDRESS: 97h)
U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as `0' WDA<5:4>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected Unimplemented: Read as `0' WDA<2:0>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected Note 1: The weak pull-up/pull-down device is enabled only when the global RAPU bit is enabled, the pin is in Input mode (TRIS = 1), the individual WDA bit is enabled (WDA = 1) and the pin is not configured as an analog input or clock function. 2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in Programming mode. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 WDA5 R/W-1 WDA4 U-0 -- R/W-1 WDA2 R/W-1 WDA1 R/W-1 WDA0 bit 0
bit 3 bit 2-0
REGISTER 4-2:
WPUDA - WEAK PULL-UP/PULL-DOWN DIRECTION REGISTER (ADDRESS: 95h)
U-0 -- bit 7 U-0 -- R/W-1 WPUDA5(3) R/W-1 WPUDA4(3) U-0 -- R/W-1 R/W-1 R/W-1 bit 0 WPUDA2 WPUDA1 WPUDA0
bit 7-6 bit 5-4
Unimplemented: Read as `0' WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits(3) 1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled Unimplemented: Read as `0' WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits 1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled Note 1: The weak pull-up/pull-down direction device is enabled only when the global RAPU bit is enabled, the pin is in Input mode (TRIS = 1), the individual WPUDA bit is enabled (WPUDA = 1) and the pin is not configured as an analog input or clock function. 2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in Programming mode. 3: WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads as `1'. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as `1'. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2-0
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Preliminary
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PIC12F635/PIC16F636/639
REGISTER 4-3: PORTA - PORTA REGISTER (ADDRESS: 05h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as `0' RA<5:0>: PORTA I/O pins 1 = Port pin is > VIH 0 = Port pin is < VIL Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x RA5 R/W-x RA4 R-x RA3 R/W-x RA2 R/W-0 RA1 R/W-0 RA0 bit 0
REGISTER 4-4:
TRISA - PORTA TRI-STATE REGISTER (ADDRESS: 85h)
U-0 -- bit 7 U-0 -- R/W-1 R/W-1 R-1 TRISA3(1) R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0 TRISA5(2) TRISA4(2)
bit 7-6: bit 5-0:
Unimplemented: Read as `0' TRISA<5:0>: PORTA Tri-State Control bits(1,2) 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: TRISA<3> always reads `1'. 2: TRISA<5:4> always reads `1' in XT, HS and LP Oscillator modes. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 41
PIC12F635/PIC16F636/639
4.2.2 INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The `mismatch' outputs of the last read are OR'd together to set the PORTA Change Interrupt Flag bit (RAIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTA. This will end the mismatch condition, then Clear the flag bit RAIF. A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOD Reset. After these Resets, the RAIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
REGISTER 4-5:
IOCA - INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
U-0 -- bit 7 U-0 -- R/W-0 IOCA5(2) R/W-0 IOCA4(2) R/W-0 IOCA3(3) R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
bit 7-6 bit 5-0
Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-change PORTA Control bits(2,3) 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads `0' in XT, HS and LP Oscillator modes. 3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DS41232B-page 42
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.3 ULTRA LOW-POWER WAKE-UP EXAMPLE 4-2:
BCF BCF BSF MOVLW MOVWF BSF BCF BCF CALL BSF BSF BSF MOVLW MOVWF SLEEP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on RA0. To use this feature, the RA0 pin is configured to output `1' to charge the capacitor, interrupt-on-change for RA0 is enabled and RA0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on RA0 drops below VIL, an interrupt will be generated which will cause the device to wake-up. Depending on the state of the GIE bit (INTCON<7>), the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.2 "Interrupt-on-change" and Section 12.9.3 "PORTA Interrupt" for more information. This feature provides a low power technique for periodically waking up the device from Sleep. The timeout is dependent on the discharge time of the RC circuit on RA0. See Example 4-2 for initializing the Ultra Low Power Wake-up module. The series resistor provides overcurrent protection for the RA0 pin and can allow for software calibration of the timeout (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879).
ULTRA LOW-POWER WAKE-UP INITIALIZATION
;Bank 0 ; ;Set RA0 data latch ;Turn off ; comparators ;Bank 1 ; ;Output high to ; charge capacitor ;Enable ULP Wake-up ;Select RA0 IOC ;RA0 to input ;Enable interrupt ; and clear flag ;Wait for IOC
STATUS,RP0 STATUS,RP1 PORTA,0 H'7' CMCON0 STATUS,RP0 STATUS,RP1 TRISA,0 CapDelay PCON,ULPWUE IOCA,0 TRISA,0 B'10001000' INTCON
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 43
PIC12F635/PIC16F636/639
4.2.4 PIN DESCRIPTIONS AND DIAGRAMS 4.2.4.1 RA0/C1IN+/ICSPDAT/ULPWU
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator, refer to the appropriate section in this data sheet. Figure 4-2 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input to the comparator In-Circuit Serial ProgrammingTM data an analog input for the Ultra Low-Power Wake-up
FIGURE 4-1:
BLOCK DIAGRAM OF RA0
Analog Input Mode(1)
Data Bus WR WPUDA RD WPUDA
VDD D Q Weak CK Q RAPU Weak
D WR WDA RD WDA D WR PORTA
Q
CK Q VDD
Q I/O pin
CK Q - + D Q IULP 0 1 VSS ULPWUE
VSS VT
WR TRISA RD TRISA RD PORTA
CK Q
Analog Input Mode(1)
D WR IOCA RD IOCA
Q Q D EN Q3
CK Q
Interrupt-onChange
Q
D EN
RD PORTA
Note
1:
Comparator mode determines Analog Input mode.
DS41232B-page 44
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.4.2 RA1/C1IN-/VREF/ICSPCLK 4.2.4.3 RA2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator * In-Circuit Serial Programming clock Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * a general purpose I/O the clock input for TMR0 an external edge-triggered interrupt a digital output from the comparator
FIGURE 4-2:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA D WR PORTA Q Q D Q
BLOCK DIAGRAM OF RA1
Analog Input Mode(1) VDD
FIGURE 4-3:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA VDD D Q Q Q D Q
BLOCK DIAGRAM OF RA2
CK Q RAPU
VDD Weak CK Q RAPU Weak Weak
Weak
CK Q
VSS
CK Q
VSS
C1OUT Enable C1OUT 1 0
VDD
CK Q I/O pin D Q
WR PORTA
CK
I/O pin
WR TRISA RD TRISA RD PORTA
D CK Q Analog Input Mode(1) VSS WR TRISA RD TRISA RD PORTA Q D EN Q3 WR IOCA RD IOCA D CK CK
Q Q VSS
D WR IOCA RD IOCA
Q
CK Q
Q Q Q EN Q3 D
Q
D EN
Q
D EN
Interrupt-onchange RD PORTA To Comparator
Interrupt-onchange
RD PORTA
To TMR0 Note 1: Comparator mode determines Analog Input mode. To INT
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 45
PIC12F635/PIC16F636/639
4.2.4.4 RA3/MCLR/VPP
Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset with weak pull-up * a high-voltage detect for Program mode entry
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
VDD MCLRE Program Mode Weak
HV Detect Reset MCLRE
Data Bus Input pin MCLRE VSS D WR IOCA RD IOCA Q D EN CK Q Q Q EN Q3 D
RD TRISA RD PORTA
VSS
RD PORTA
Interrupt-onchange
WURE Sleep
DS41232B-page 46
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.4.5 RA4/T1G/OSC2/CLKOUT 4.2.4.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 gate input a crystal/resonator connection a clock output Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input
FIGURE 4-5:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA Q
BLOCK DIAGRAM OF RA4
FIGURE 4-6:
Data Bus
BLOCK DIAGRAM OF RA5
D
Q
CLK(1) Modes
D
Q
VDD Weak WR WPUDA RD WPUDA D VSS WR WDA RD WDA VDD D WR PORTA I/O pin D VSS WR TRISA RD TRISA RD PORTA D Q CK Q Q CK Q Q Q CK Q
CLK(1) Modes
VDD Weak
CK Q RAPU
RAPU Weak
Weak
CK Q Oscillator Circuit OSC1 CLKOUT Enable D Q Q CLKOUT Enable D Q Q INTOSC/ RC/EC(2) CLKOUT Enable XTAL Fosc/4 1 0
CK Q
VSS
Oscillator Circuit OSC2 VDD
WR PORTA
CK
I/O pin
VSS INTOSC Mode
(2)
WR TRISA RD TRISA RD PORTA
CK
D WR IOCA RD IOCA CK
Q Q Q EN Q D EN Q3 D
WR IOCA RD IOCA
CK
Q Q
D EN Q3
Q
D EN
Interrupt-onchange
Interrupt-onchange
RD PORTA RD PORTA T1G To Timer1 Note 1: 2: Oscillator modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. With CLKOUT option. Note T1G To Timer1 1: 2: Oscillator modes are XT, HS, LP and LPTMR1. When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 47
PIC12F635/PIC16F636/639
TABLE 4-1:
Add r Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- GIE Bit 6 -- PEIE Bit 5 RA5 T0IE Bit 4 RA4 INTE Bit 3 RA3 RAIE Bit 2 RA2 T0IF Bit 1 RA1 INTF Bit 0 RA0 RAIF Value on: POR, BOD, WUR Value on all other Resets
05h PORTA 0Bh/ INTCON 8Bh 0Eh TMR1L 0Fh TMR1H 10h T1CON 1Ah CMCON1 19h CMCON0 85h TRISA 95h WPUDA 96h IOCA 97h WDA Legend:
--xx xx00 --uu uu00 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- INTEDG -- -- -- -- -- C2INV T0CS TRISA5 IOCA5 WDA5 -- C1INV T0SE TRISA4 IOCA4 WDA4 -- CIS PSA TRISA3 -- IOCA3 -- -- CM2 PS2 TRISA2 IOCA2 WDA2 T1GSS CM1 PS1 TRISA1 IOCA1 WDA1
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu C2SYNC ---- --10 ---- --10 CM0 PS0 0000 0000 0000 0000 1111 1111 1111 1111 C2OUT C1OUT -- -- -- --
81h OPTION_REG RAPU
TRISA0 --11 1111 --11 1111 IOCA0 WDA0 --00 0000 --00 0000 --11 -111 --11 -111
WPUDA5 WPUDA4
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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Preliminary
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PIC12F635/PIC16F636/639
4.3 PORTC
FIGURE 4-7:
Data Bus
PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to comparator. For specific information about individual functions, refer to the appropriate section in this data sheet. Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
BLOCK DIAGRAM OF RC0 AND RC1
D WR PORTC CK
Q Q
VDD
I/O pin D WR TRISC RD TRISC RD PORTC To Comparators CK Q Q Analog Input Mode VSS
EXAMPLE 4-3:
BCF BCF CLRF MOVLW MOVWF BSF BCF MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 PORTC 07h CMCON0 STATUS,RP0 STATUS,RP1 0Ch TRISC STATUS,RP0 STATUS,RP1
INITIALIZING PORTC
;Bank 0 ; ;Init PORTC ;Set RC<4,1:0> to ;digital I/O ;Bank 1 ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 ;
4.3.3
RC2
4.3.1
RC0/C2IN+
The RC2 pin is configurable to function as a general purpose I/O.
The RC0 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator
4.3.4
RC3
The RC3 pin is configurable to function as a general purpose I/O.
4.3.5
RC5
4.3.2
RC1/C2IN-
The RC1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator
The RC5 pin is configurable to function as a general purpose I/O.
FIGURE 4-8:
BLOCK DIAGRAM OF RC2, RC3 AND RC5
Data Bus VDD
D WR PORTC CK
Q Q
I/O pin D WR TRISC RD TRISC RD PORTC CK Q Q VSS
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 49
PIC12F635/PIC16F636/639
4.3.6 RC4/C2OUT
The RC4 pin is configurable to function as one of the following: * a general purpose I/O * a digital output from the comparator
FIGURE 4-9:
C2OUT Enable C2OUT
BLOCK DIAGRAM OF RC4
Data Bus VDD
D WR PORTC
Q 1 0
CK Q
I/O pin
D WR TRISC RD TRISC RD PORTC
Q VSS
CK Q
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PIC12F635/PIC16F636/639
REGISTER 4-6: PORTC - PORTC REGISTER (ADDRESS: 07h)
U-0 -- bit 7 bit 7-6: bit 5-0: Unimplemented: Read as `0' RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-0 RC1 R/W-0 RC0 bit 0
REGISTER 4-7:
TRISC - PORTC TRI-STATE REGISTER (ADDRESS: 87h)
U-0 -- bit 7 U-0 -- R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
bit 7-6: bit 5-0:
Unimplemented: Read as `0' TRISC<5:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TABLE 4-2:
Address 07h 19h 87h Legend: Name PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 -- C2OUT -- Bit 6 -- C1OUT -- Bit 5 RC5 C2INV Bit 4 RC4 C1INV Bit 3 RC3 CIS Bit 2 RC2 CM2 Bit 1 RC1 CM1 Bit 0 RC0 CM0 Value on: POR, BOD, WUR Value on all other Resets
--xx xx00 --uu uu00 0000 0000 0000 0000
CMCON0 TRISC
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
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NOTES:
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PIC12F635/PIC16F636/639
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note: Counter mode has specific external clock requirements. Additional information on these requirements is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the "PICmicro(R) MidRange MCU Family Reference Manual" (DS33023).
5.2
Timer0 Interrupt
5.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep.
FIGURE 5-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 SYNC/2 Cycles 0 0 TMR0 8
T0CKI pin T0SE T0CS
8-bit Prescaler 1 8
Set Flag bit T0IF on Overflow PSA
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler LFINTOSC Watchdog Timer WDTPS<3:0> Note 1:
1 WDT Time-out 0
16 PSA
T0SE, T0CS, PSA, PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.
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5.3 Using Timer0 with an External Clock
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
REGISTER 5-1:
OPTION_REG - OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual values in the WPUDA register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/T0CKI/INT/C1OUT pin 0 = Interrupt on falling edge of RA2/T0CKI/INT/C1OUT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA2/T0CKI/INT/C1OUT pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI/INT/C1OUT pin 0 = Increment on low-to-high transition on RA2/T0CKI/INT/C1OUT pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate(1) 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F635/PIC16F636/639. See Section 12.11 "Watchdog Timer (WDT)" for more information. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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5.4 Prescaler
EXAMPLE 5-1:
BCF STATUS,RP0 BCF STATUS,RP1 CLRWDT CLRF TMR0 BSF BCF MOVLW MOVWF CLRWDT MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 b'00101111' OPTION_REG
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as "prescaler" throughout this data sheet. The prescaler assignment is controlled in software by the control bit, PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
CHANGING PRESCALER (TIMER0 WDT)
;Bank 0 ; ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ; ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ;Bank 0 ;
b'00101xxx' OPTION_REG STATUS,RP0 STATUS,RP1
5.4.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 5-1 and Example 5-2) must be executed when changing the prescaler assignment from Timer0 to WDT.
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 5-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
CLRWDT BSF BCF MOVLW
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler ;Bank 1 ; ;Select TMR0, ;prescale, and ;clock source ; ;Bank 0 ;
STATUS,RP0 STATUS,RP1 b'xxxx0xxx'
MOVWF BCF BCF
OPTION_REG STATUS,RP0 STATUS,RP1
TABLE 5-1:
Address 01h 81h 85h Legend:
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD, WUR Value on all other Resets
TMR0 OPTION_REG TRISA
Timer0 Module Register GIE RAPU -- PEIE INTEDG -- T0IE T0CS INTE T0SE RAIE PSA T0IF PS2 INTF PS1 RAIF PS0
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111
0Bh/8Bh INTCON
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
-- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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Preliminary
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NOTES:
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PIC12F635/PIC16F636/639
6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
The PIC12F635/PIC16F636/639 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input: - Selectable gate source: T1G or C2 output (T1GSS) - Selectable gate polarity (T1GINV) * Optional LP oscillator * * * * * * *
FIGURE 6-1:
TIMER1 ON THE PIC12F635/PIC16F636/639 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE
(1)
T1GINV
Set Flag bit TMR1IF on Overflow
To C2 Comparator Module TMR1 Clock 0 1
(3)
TMR1 TMR1H Oscillator
TMR1L
Synchronized Clock Input
OSC1/T1CKI FOSC/4 Internal Clock
T1SYNC 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS 1 C2OUT(2) 0 T1GSS Sleep Input Synchronize det
OSC2/T1G INTOSC No CLKOUT T1OSCEN
Note 1: 2: 3:
Timer1 increments on the rising edge. C2OUT for PIC16F636/639, C1OUT for PIC12F635. ST Buffer is low-power type when using LP oscillator, or high-speed type when using T1CKI.
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Preliminary
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6.1 Timer1 Modes of Operation 6.3 Timer1 Prescaler
Timer1 can operate in one of three modes: * 16-bit timer with prescaler * 16-bit synchronous counter * 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter and Timer modules, the counter/timer clock can be gated by the Timer1 gate, which can be selected as either the T1G pin or the Comparator 2 output. If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. Timer1 has four prescaler options, allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of Comparator 2. This allows the device to directly time external events using T1G or analog events using Comparator 2. See CMCON1 (Register 7-2) for selecting the Timer1 gate source. This feature can simplify the software for many other applications. Note: TMR1GE bit (T1CON<6>) must be set to use either T1G or C2OUT as the Timer1 gate source. See Register 7-2 for more information on selecting the Timer1 gate source.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit (PIE1<0>) * PEIE bit (INTCON<6>) * GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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REGISTER 6-1: T1CON - TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 T1GINV bit 7 bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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Preliminary
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6.5 Timer1 Operation in Asynchronous Counter Mode 6.6 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 31 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. Table 3-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as `0' and TRISA5 and TRISA4 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
6.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
6.7
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * Timer1 must be on (T1CON<0>) * TMR1IE bit (PIE1<0>) must be set * PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow. If the GIE bit is clear, execution will continue with the next instruction.
TABLE 6-1:
Addr 0Bh/ 8Bh 0Ch 0Eh 0Fh 10h 1Ah 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON CMCON 1 PIE1
REGISTERS ASSOCIATED WITH TIMER1
Bit 7 GIE EEIF Bit 6 PEIE LVDIF Bit 5 T0IE CRIF Bit 4 INTE C2IF Bit 3 RAIE C1IF Bit 2 T0IF OSFIF Bit 1 INTF -- Bit 0 RAIF Value on POR, BOD, WUR Value on all other Resets
0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- EEIE -- LVDIE -- CRIE -- C2IE -- C1IE -- OSFIE T1GSS --
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu C2SYNC ---- --10 ---- --10 TMR1IE 0000 00-0 0000 00-0
Legend:
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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7.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0, RA1, RC0 and RC1, while the outputs are multiplexed to pins RA2 and RC4. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparators. The CMCON0 register (Register 7-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 7-4. Note: The PIC12F635 has only 1 comparator. The comparator on the PIC12F635 behaves like comparator 2 of the PIC16F636/639.
REGISTER 7-1:
CMCON0 - COMPARATOR CONTROL 0 REGISTER (ADDRESS: 19h)
R-0 C2OUT bit 7
(1)
R-0 C1OUT
(2)
R/W-0 C2INV
(1)
R/W-0 C1INV
(2)
R/W-0 CIS
R/W-0 CM2
R/W-0 CM1
R/W-0 CM0 bit 0
bit 7
C2OUT: Comparator 2 Output bit(1) When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit(2) When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit(1) 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit(2) 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1 VIN- connects to RA0 C2 VIN- connects to RC0 0 = C1 VIN- connects to RA1 C2 VIN- connects to RC1 When CM<2:0> = 001: 1 = C1 VIN- connects to RA0 0 = C1 VIN- connects to RA1 CM<2:0>: Comparator Mode bits Figure 7-4 shows the Comparator modes and CM<2:0> bit settings. Note 1: PIC16F636/639 only. Reads as `0' for PIC12F635. 2: PIC12F635 bit names are COUT and CINV. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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Preliminary
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7.1 Comparator Operation
FIGURE 7-1:
VIN+ VIN-
SINGLE COMPARATOR
+ -
A single comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-1 represent the uncertainty due to input offsets and response time. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON0 (19h) register.
Output
VINVIN- VIN+ VIN+
Output Output
The polarity of the comparator output can be inverted by setting the CxINV bits (CMCON0<5:4>). Clearing CxINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 7-1.
7.2
Analog Input Connection Considerations
TABLE 7-1:
OUTPUT STATE VS. INPUT CONDITIONS
CINV 0 0 1 1 CxOUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+
A simplified circuit for an analog input is shown in Figure 7-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Note 1: When reading the Port register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as analog inputs according to the input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
FIGURE 7-2:
ANALOG INPUT MODEL
VDD Rs < 10 k AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
Vss Legend: CPIN VT ILEAKAGE RIC RS VA = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage
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7.3 Comparator Configuration
There are eight modes of operation for the comparators. The CMCON0 register is used to select these modes. Figure 7-3 and Figure 7-4 show the eight possible modes. The TRISA and TRISC registers control the data direction of the comparator output pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 15.0 "Electrical Specifications". Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 7-3:
CM<2:0> = 000
COMPARATOR I/O OPERATING MODES FOR PIC12F635
Comparator Off (Lowest Power)(1) CM<2:0> = 111
Comparator Reset (POR Default Value - Low Power)
GP1/CINGP0/CIN+
A A Off (Read as `0')
GP1/CINGP0/CIN+
D D Off (Read as `0')
GP2/C1OUT D
GP2/C1OUT D
Comparator without Output CM<2:0> = 010
Comparator w/o Output and with Internal Reference CM<2:0> = 100
GP1/CINGP0/CIN+
A A C1OUT
GP1/CINGP0/CIN+
A D C1OUT
GP2/C1OUT D
GP2/C1OUT D From CVREF Module
Comparator with Output and Internal Reference CM<2:0> = 011
Multiplexed Input with Internal Reference and Output CM<2:0> = 101
GP1/CINGP0/CIN+
A D C1OUT
GP1/CINGP0/CIN+
A A CIS = 0 CIS = 1 C1OUT
GP2/C1OUT D From CVREF Module
GP2/C1OUT D From CVREF Module
Comparator with Output CM<2:0> = 001
Multiplexed Input with Internal Reference CM<2:0> = 110
GP1/CINGP0/CIN+
A A C1OUT
GP1/CINGP0/CIN+
A A CIS = 0 CIS = 1 C1OUT
GP2/C1OUT D
GP2/C1OUT D From CVREF Module
Legend: A = Analog Input, ports always read `0' D = Digital Input Note 1:
CIS = Comparator Input Switch (CMCON0<3>)
Lowest power statement assures valid digital stats on GPO, GP1 and GP2.
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Preliminary
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FIGURE 7-4: COMPARATOR I/O OPERATING MODES FOR PIC16F636/639
Comparators Off (Lowest Power)(1) CM<2:0> = 111
RA1 C1 Off (Read as `0') RA0
D D
Comparator Reset (POR Default Value) CM<2:0> = 000
RA1 RA0
A A
VINVIN+
VINVIN+ C1 Off (Read as `0')
RC1 RC0
A A
VINVIN+ C2 Off (Read as `0')
RC1 RC0
D D
VINVIN+ C2 Off (Read as `0')
Two Independent Comparators CM<2:0> = 100
RA1 RA0
A A
Four Inputs Multiplexed to Two Comparators CM<2:0> = 010
RA1
A A
VINVIN+ C1 C1OUT
RA0 RC1
CIS = 0 CIS = 1
VINVIN+ VINVIN+ C2 C2OUT C1 C1OUT
A A
RC1 RC0
A A
VINVIN+ C2 C2OUT
RC0
CIS = 0 CIS = 1
From CVREF Module
Two Common Reference Comparators CM<2:0> = 011
RA1 RA0
A D
Two Common Reference Comparators with Outputs CM<2:0> = 110
RA1
A
VINVIN+ C1 C1OUT
VINVIN+ C1 C1OUT
RA2/C1OUT D
RC1 RC0
A A
VINVIN+ C2 C2OUT
RC1 RC0 RC4/C2OUT
A A
VINVIN+ C2 C2OUT
One Independent Comparator CM<2:0> = 101
RA1 RA0
D D
Three Inputs Multiplexed to Two Comparators CM<2:0> = 001
Off (Read as `0') RA1 RA0
A A
VINVIN+ C1
CIS = 0 CIS = 1
VINVIN+ VINVIN+ C2 C2OUT C1 C1OUT
RC1 RC0
A A
VINVIN+ C2 C2OUT
RC1 RC0
A A
Legend: A = Analog Input, ports always read `0' D = Digital Input
CIS = Comparator Input Switch (CMCON0<3>)
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PIC12F635/PIC16F636/639
FIGURE 7-5: PIC12F635 COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins C1SYNC To TMR1 0 To C1OUT pin 1 Q EN D TMR1 Clock Source(1)
C1INV
To Data Bus
Q
D EN
RD CMCON
Set C2IF bit
Q
D EN CL Reset RD CMCON
Note 1:
Comparator 1 output is latched on falling edge of T1 clock source.
FIGURE 7-6:
PIC16F636/639 COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins
C1INV
To C1OUT pin To Data Bus Q EN RD CMCON D
Set C1IF bit
Q
D EN CL NRESET RD CMCON
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Preliminary
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PIC12F635/PIC16F636/639
FIGURE 7-7: PIC16F636/639 COMPARATOR C2 OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins C2SYNC To TMR1 0 To C2OUT pin 1 Q EN D TMR1 Clock Source(1)
C2INV
To Data Bus
Q
D EN
RD CMCON
Set C2IF bit
Q
D EN CL Reset RD CMCON
Note 1:
Comparator 2 output is latched on falling edge of T1 clock source.
REGISTER 7-2:
CMCON1 - COMPARATOR CONTROL 1 REGISTER (ADDRESS: 1Ah)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC(1) bit 0
bit 7-2: bit 1
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G pin (RA4 must be configured as digital input) 0 = Timer1 gate source is Comparator 2 output C2SYNC: Comparator 2 Synchronize bit(2) 1 = C2 output synchronized with falling edge of Timer1 clock 0 = C2 output not synchronized with Timer1 clock Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown C2SYNC is C1SYNC in PIC12F635.
bit 0
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7.4 Comparator Outputs
The comparator outputs are read through the CMCON0 register. These bits are read-only. The comparator outputs may also be directly output to the RA2 and RC4 I/O pins. When enabled, multiplexers in the output path of the RA2 and RC4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 7-5 and Figure 7-6 show the output block diagrams for Comparator 1 and 2. The TRIS bits will still function as an output enable/ disable for the RA2 and RC4 pins while in this mode. The polarity of the comparator outputs can be changed using the C1INV and C2INV bits (CMCON0<5:4>). Timer1 gate source can be configured to use the T1G pin or Comparator 2 output as selected by the T1GSS bit (CMCON1<1>). This feature can be used to time the duration or interval of analog events. The output of Comparator 2 can also be synchronized with Timer1 by setting the C2SYNC bit (CMCON1<0>). When enabled, the output of Comparator 2 is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, Comparator 2 is latched after the prescaler. To prevent a race condition, the Comparator 2 output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See Figure 7-6, Comparator C2 Output Block Diagram and Figure 5-1, Timer1 on the PIC12F635/ PIC16F636/639 Block Diagram for more information. It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. The CxIE bits (PIE1<4:3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CxIF bits will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. Clear flag bits CxIF.
A mismatch condition will continue to set flag bits CxIF. Reading CMCON0 will end the mismatch condition and allow flag bits CxIF to be cleared. Note: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR1<4:3>) interrupt flags may not get set.
7.5
Comparator Interrupts
The comparator interrupt flags are set whenever there is a change in the output value of its respective comparator. Software will need to maintain information about the status of the output bits, as read from CMCON0<7:6>, to determine the actual change that has occurred. The CxIF bits (PIR1<4:3>) are the Comparator Interrupt Flags. These bits must be reset in software by clearing them to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated.
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Preliminary
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7.6 Comparator Reference
EQUATION 7-1:
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32) The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register (Register 7-3) controls the voltage reference module shown in Figure 7-8.
7.6.2 7.6.1 CONFIGURING THE VOLTAGE REFERENCE
VOLTAGE REFERENCE ACCURACY/ERROR
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. The following equation determines the output voltages:
The voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 15.0 "Electrical Specifications".
FIGURE 7-8:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR
VR<3:0>
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7.7 Comparator Response Time
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 15-7). While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h) and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected.
7.9
Effects of a Reset
7.8
Operation During Sleep
The comparators and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in Sleep mode, turn off the comparator, CM<2:0> = 111 and voltage reference, VRCON<7> = 0.
A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its OFF state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.
REGISTER 7-3:
VRCON - VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0 VREN bit 7 U-0 -- R/W-0 VRR R/W-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
bit 7
VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF Value Selection bits 0 VR<3:0> 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6 bit 5
bit 4 bit 3-0
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NOTES:
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8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE
8.1 Voltage Trip Points
The PIC12F635/PIC16F636/639 device supports eight internal PLVD trip points. See Register 8-1 for available PLVD trip point voltages.
The Programmable Low-Voltage Detect module is an interrupt driven supply level detection. The voltage detection monitors the internal power supply.
REGISTER 8-1:
LVDCON - LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 94h)
U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN U-0 -- R/W-1 LVDL2 R/W-0 LVDL1 R/W-0 LVDL0 bit 0
bit 7-6 bit 5
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Status Flag bit 1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt should not be enabled LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables PLVD, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD, powers down PLVD and supporting circuitry Unimplemented: Read as `0' LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values) 111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V 000 = 1.9V(1) Note 1: Not tested and below minimum VDD. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3 bit 2-0
TABLE 8-1:
Address 94h 0Bh/8Bh 0Ch 8Ch Legend: Note 1: Name
REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
Bit 7 -- GIE EEIF EEIE Bit 6 -- PEIE LVDIF LVDIE Bit 5 IRVST T0IE CRIF CRIE Bit 4 LVDEN INTE C2IF C2IE(1) Bit 3 -- RAIE C1IF C1IE Bit 2 LVDL2 T0IF OSFIF OSFIE Bit 1 LVDL1 INTF -- -- Bit 0 LVDL0 RAIF Value on POR, BOD, WUR Value on all other Resets
LVDCON INTCON PIR1 PIE1
--00 -000 --00 -000 0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0 TMR1IE 0000 00-0 0000 00-0
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the comparator or comparator voltage reference module. PIC16F636/639 only.
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NOTES:
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PIC12F635/PIC16F636/639
9.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: * * * * EECON1 EECON2 (not a physically implemented register) EEDAT EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to A/C specifications in Section 15.0 "Electrical Specifications" for exact limits. When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access the data EEPROM data and will read zeroes. Additional information on the data EEPROM is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC16F636/639 has 256 bytes of data EEPROM and the PIC12F635 has 64 bytes.
REGISTER 9-1:
EEDAT - EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0 EEDAT7 bit 7 R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 EEDAT2 R/W-0 EEDAT1 R/W-0 EEDAT0 bit 0
bit 7-0
EEDATn: Byte Value to Write to or Read From Data EEPROM bits
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 9-2:
EEADR - EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 bit 7 R/W-0 R/W-0 EEADR5 R/W-0 EEADR4 R/W-0 EEADR3 R/W-0 EEADR2 R/W-0 EEADR1 R/W-0 EEADR0 bit 0 EEADR7(1) EEADR6
bit 7-0
EEADR: Specifies 1 of 256 Locations for EEPROM Read/Write Operation bits Note 1: PIC16F636/639 only. Read as `0' on PIC12F635. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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9.1 EECON1 AND EECON2 Registers
EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as `0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized. Interrupt flag, EEIF bit (PIR1<7>), is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1).
REGISTER 9-3:
EECON1 - EEPROM CONTROL 1 REGISTER (ADDRESS: 9Ch)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-4 bit 3
Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD detect) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1
bit 0
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9.2 Reading the EEPROM Data Memory
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR1<7>) must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 9-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).
9.4
Write Verify
EXAMPLE 9-1:
BSF BCF MOVLW MOVWF BSF MOVF
DATA EEPROM READ
;Bank 1 ; ; ;Address to read ;EE Read ;Move data to W
STATUS,RP0 STATUS,RP1 CONFIG_ADDR EEADR EECON1,RD EEDAT,W
Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9-3) to the desired value to be written.
EXAMPLE 9-3:
BSF BCF MOVF BSF XORWF BTFSS GOTO :
WRITE VERIFY
;Bank 1 ; ;EEDAT not changed ;from previous write ;YES, Read the ;value written ;Is data the same ;No, handle error ;Yes, continue
STATUS,RP0 STATUS,RP1 EEDAT,W EECON1,RD EEDAT,W STATUS,Z WRITE_ERR
9.3
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 9-2.
9.4.1 EXAMPLE 9-2:
BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
USING THE DATA EEPROM
DATA EEPROM WRITE
;Bank 1 ; ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTS
STATUS,RP0 STATUS,RP1 EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
Required Sequence
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). The maximum endurance for any EEPROM cell is specified as D120. D124 specifies a maximum number of writes to any EEPROM location before a refresh is required of infrequently changing memory locations.
9.4.2
EEPROM ENDURANCE
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
As an example, hypothetically, a data EEPROM is 64 bytes long and has an endurance of 1M writes. It also has a refresh parameter of 10M writes. If every memory location in the cell were written the maximum number of times, the data EEPROM would fail after 64M write cycles. If every memory location, save 1, were written the maximum number of times, the data EEPROM would fail after 63M write cycles, but the one remaining location could fail after 10M cycles. If proper refreshes occurred, then the lone memory location would have to be refreshed 6 times for the data to remain correct.
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9.5 Protection Against Spurious Write 9.6
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * Brown-out * Power glitch * Software malfunction
Data EEPROM Operation During Code Protection
Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 12-1) to `0'. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to `0' will also help prevent data memory code protection from becoming breached.
TABLE 9-1:
Address 0Bh/8Bh 0Ch 8Ch 9Ah 9Bh 9Ch 9Dh Legend: Note 1: Name INTCON PIR1 PIE1 EEDAT EEADR
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 GIE EEIF EEIE EEDAT7 -- Bit 6 PEIE LVDIF LVDIE Bit 5 T0IE CRIF CRIE Bit 4 INTE C2IF(1) C2IE(1) Bit 3 RAIE C1IF C1IE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF -- -- Bit 0 RAIF Value on POR, BOD, WUR Value on all other Resets
0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0 TMR1IE 0000 00-0 0000 00-0
EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 -- -- -- WRERR WREN WR RD ---- x000 ---- q000 ---- ---- ---- ----
EEADR7(1) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EECON1
EECON2 EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the data EEPROM module. PIC16F636/639 only.
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10.0 KEELOQ(R) COMPATIBLE CRYPTOGRAPHIC MODULE
To obtain information regarding the implementation of the KEELOQ module, Microchip Technology requires the execution of the "KEELOQ(R) Encoder License Agreement". The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ. Further information may be obtained by contacting your local Microchip Sales Representative.
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11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)
11.2 Modulation Circuit
The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components. The modulation transistor and the internal tuning capacitors are connected between the LC input pin and LCCOM pin. Each LC input has its own modulation transistor. When the modulation transistor turns on, its low Turn-on Resistance (RM) clamps the induced LC antenna voltage. The coil voltage is minimized when the modulation transistor turns-on and maximized when the modulation transistor turns-off. The modulation transistor's low Turn-on Resistance (RM) results in a high modulation depth. The LF talk-back is achieved by turning on and off the modulation transistor. The modulation data comes from the microcontroller section via the digital SPI interface as "Clamp On", "Clamp Off" commands. Only those inputs that are enabled will execute the clamp command. A basic block diagram of the modulation circuit is shown in Figure 11-1 and Figure 11-2. The modulation FET is also shorted momentarily after Soft Reset and Inactivity timer time-out.
The PIC16F639 device consists of the PIC16F636 device and low frequency (LF) Analog Front-End (AFE), with the AFE section containing three analoginput channels for signal detection and LF talk-back. This section describes the Analog Front-End (AFE) in detail. The PIC16F639 device can detect a 125 kHz input signal as low as 1 mVpp and transmit data by using internal LF talk-back modulation or via an external transmitter. The PIC16F639 can also be used for various bidirectional communication applications. Figure 11-3 and Figure 11-4 show application examples of the device. Each analog input channel has internal tuning capacitance, sensitivity control circuits, an input signal strength limiter and an LF talk-back modulation transistor. An Automatic Gain Control (AGC) loop is used for all three input channel gains. The output of each channel is OR'd and fed into a demodulator. The digital output is passed to the LFDATA pin. Figure 11-1 shows the block diagram of the AFE and Figure 11-2 shows the LC input path. There are a total of eight Configuration registers. Six of them are used for AFE operation options, one for column parity bits and one for status indication of AFE operation. Each register has 9 bits including one row parity bit. These registers are readable and writable by SPI (Serial Protocol Interface) commands except for the Status register, which is read-only.
11.3
Tuning Capacitor
Each channel has internal tuning capacitors for external antenna tuning. The capacitor values are programmed by the Configuration registers up to 63 pF, 1 pF per step. Note: The user can control the tuning capacitor by programming the AFE Configuration registers.
11.1
RF Limiter 11.4 Variable Attenuator
The variable attenuator is used to attenuate, via AGC control, the input signal voltage to avoid saturating the amplifiers and demodulators. Note: The variable attenuator function is accomplished by the device itself. The user cannot control its function.
The RF Limiter limits LC pin input voltage by de-Q'ing the attached LC resonant circuit. The absolute voltage limit is defined by the silicon process's maximum allowed input voltage (see Section 15.0 "Electrical Specifications"). The limiter begins de-Q'ing the external LC antenna when the input voltage exceeds VDE_Q, progressively de-Q'ing harder to reduce the antenna input voltage. The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal.
11.5
Sensitivity Control
The sensitivity of each channel can be reduced by the channel's Configuration register sensitivity setting. This is used to desensitize the channel from optimum. Note: The user can desensitize the channel sensitivity by programming the AFE Configuration registers.
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11.6 AGC Control 11.10 Demodulator
The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal. The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 "Variable Attenuator"). The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal. Note: The AGC control function is accomplished by the device itself. The user cannot control its function.
11.11 Data Slicer
The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The reference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are OR'd together and sent to the output enable filter.
11.7
Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provides a maximum two-stage gain of 40 dB. Note: The user cannot control the gain of these two amplifiers.
11.12 Output Enable Filter
The Output Enable Filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 11.15 "Configurable Output Enable Filter").
11.8
Auto Channel Selection 11.13 RSSI (Received Signal Strength Indicator)
The RSSI provides a current which is proportional to the input signal amplitude (see Section 11.31.3 "Received Signal Strength Indicator (RSSI) Output").
The Auto Channel Selection feature is enabled if the Auto Channel Select bit AUTOCHSEL<8> in Configuration Register 5 (Register 11-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (TSTAB). If the output is high, it allows this channel to pass data, otherwise it is blocked. The status of this operation is monitored by AFE Status Register 7 bits <8:6> (Register 11-8). These bits indicate the current status of the channel selection activity, and automatically updates for every Soft Reset period. The auto channel selection function resets after each Soft Reset (or after Inactivity timer time-out). Therefore, the blocked channels are reenabled after Soft Reset. This feature can make the output signal cleaner by blocking any channel that was not high at the end of TAGC. This function works only for demodulated data output, and is not applied for carrier clock or RSSI output.
11.14 Analog Front-End Timers
The AFE has an internal 32 kHz RC oscillator. The oscillator is used in several timers: * Inactivity timer * Alarm timer * Pulse Width timer * Period timer * AGC settling timer
11.14.1
RC OSCILLATOR
The RC oscillator is low power, 32 kHz 10% over temperature and voltage variations.
11.9
Carrier Clock Detector
The Detector senses the input carrier cycles. The output of the Detector switches digitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in the AFE Configuration Register 1 (Register 11-2).
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11.14.2 INACTIVITY TIMER
The timer is reset when the: * CS pin is low (any SPI command). * Output enable filter is disabled. * LFDATA pin is enabled (signal passed output enable filter). The timer starts when: * Receiving a LF signal. The timer causes a low output on the ALERT pin when: * Output enable filter is enabled and modulated input signal is present for TALARM, but does not pass the output enable filter requirement. Note: The Alarm timer is disabled if the output enable filter is disabled. The Inactivity Timer is used to automatically return the AFE to Standby mode, if there is no input signal. The time-out period is approximately 16 ms (TINACT), based on the 32 kHz internal clock. The purpose of the Inactivity Timer is to minimize AFE current draw by automatically returning the AFE to the lower current Standby mode, if there is no input signal for approximately 16 ms. The timer is reset when: * An amplitude change in LF input signal, either high-to-low or low-to-high * CS pin is low (any SPITM command) * Timer-related Soft Reset The timer starts when: * AFE receives any LF signal The timer causes an AFE Soft Reset when: * A previously received LF signal does not change either high-to-low or low-to-high for TINACT The Soft Reset returns the AFE to Standby mode where most of the analog circuits, such as the AGC, demodulator and RC oscillator, are powered down. This returns the AFE to the lower Standby Current mode.
11.14.4
PULSE WIDTH TIMER
The Pulse Width Timer is used to verify that the received output enable sequence meets both the minimum TOEH and minimum TOEL requirements.
11.14.5
PERIOD TIMER
The Period Timer is used to verify that the received output enable sequence meets the maximum TOET requirement.
11.14.3
ALARM TIMER
11.14.6
AGC SETTLING TIMER (TAGC)
The Alarm Timer is used to notify the MCU that the AFE is receiving LF signal that does not pass the output enable filter requirement. The time-out period is approximately 32 ms (TALARM) in the presence of continuing noise. The Alarm Timer time-out occurs if there is an input signal for longer than 32 ms that does not meet the output enable filter requirements. The Alarm Timer time-out causes: a) b) The ALERT pin to go low. The ALARM bit to set in the AFE Status Configuration 7 register (Register 11-8).
This timer is used to keep the output enable filter in Reset while the AGC settles on the input signal. The time-out period is approximately 3.5 ms. At end of this time (TAGC), the input should remain high (TPAGC), otherwise the counting is aborted and a Soft Reset is issued. See Figure 11-6 for details. Note 1: The AFE needs continuous and uninterrupted high input signal during AGC settling time (TAGC). Any absence of signal during this time may reset the timer and a new input signal is needed for AGC settling time, or may result in improper AGC gain settings which will produce invalid output. 2: The rest of the AFE section wakes up if any of these input channels receive the AGC settling time correctly. AFE Status Register 7 bits <4:2> (Register 11-8) indicate which input channels have waken up the AFE first. Valid input signal on multiple input pins can cause more than one channel's indicator bit to be set.
The MCU is informed of the Alarm timer time-out by monitoring the ALERT pin. If the Alarm timer time-out occurs, the MCU can take appropriate actions such as lowering channel sensitivity or disabling channels. If the noise source is ignored, the AFE can return to a lower standby current draw state.
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FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM - ANALOG FRONT-END
LCX
AGC Detector RF Lim Tune X Mod Sensitivity Control X
/ 64 WAKEX
A
/ 64 LCCOM WAKEY LCY AGC Detector RF Lim Tune Y Mod Sensitivity Control Y A WAKEZ
LCCOM / 64 Detector RF Lim Tune Z Mod Sensitivity Control Z Watchdog A
LCZ
AGC
Modulation Depth LCCOM To Sensitivity X To Sensitivity Y To Sensitivity Z AGC Preserve To Modulation Transistors To Tuning Cap X To Tuning Cap Y To Tuning Cap Z 32 kHZ Oscillator AGC Timer
B
Output Enable Filter
Command Decoder/Controller
Configuration Registers
VSST
VDDT
RSSI
SCLK/ALERT
CS
LFDATA/RSSI/ CCLK/SDIO
MCU
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FIGURE 11-2:
AGC
FGA1 Capacitor Tuning Carrier Detector LFDATA Output Enable Filter / 64 - /1 OR /4 DETX DETY DETZ A CLKDIV C + Sens. Control Var Atten
LCX/ LCY/ LCZ
FGA2
RF Limiter
MOD FET
(c) 2005 Microchip Technology Inc.
00 01 10 RSSI GEN 11 DATOUT WAKEX WAKEY WAKEZ 32 kHz Clock/AGC Timer AGCSIG LFDATA RSSI C
LC INPUT PATH
> 4 VPP
LCCOM
0.1V
-
1
0
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Preliminary
0.4V
Decode A Y Z Full-Wave Rectifier X Low-Pass Filter Peak Detector AGC Feedback Amplifier REF GEN MOD Depth Control Data Slicer - + Demodulator
Configuration
Registers + AGCACT
Legend:
FGA = Fixed Gain Amplifier
FWR = Full-wave Rectifier
CHX CHY CHZ Auto Channel Selector X Y Z AUTOCHSEL
ACT
LPF = Low-pass Filter
PD = Peak Detector
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FIGURE 11-3:
BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE
d Encrypte Codes se Respon F) (UH
LED
LED
UHF Receiver Microcontroller (MCU)
mand LF Com z) 5 kH (12
UHF Transmitter Ant. X PIC16F639 Ant. Y MCU (PIC16F636) + Ant. Z 3 Input Analog Front-End
LF Transmitter/ Receiver
LF Talk-Back (125 kHz)
Base Station
Transponder
FIGURE 11-4:
PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE
315 MHz
+3V VDD S0 S1 S2 1 2 3 4 20 19 18 S5 17 VSS +3V S3 S4 +3V
PIC16F639
RF Circuitry (UHF TX)
Data RFEN LFDATA/RSSI/CCLK/SDIO
5 6 7 8 9 10
16 15 14 13 12 11
LED CS SCLK/ALERT VSST LCCOM LCZ
+3V VDDT LCX LCY air-core coil
ferrite-core coil
ferrite-core coil
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11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output and wake the microcontroller only after receiving a specific sequence of pulses on the LC input pins. Therefore, it prevents the AFE from waking up the microcontroller due to noise or unwanted input signals. The circuit compares the timing of the demodulated header waveform with a pre-defined value, and enables the demodulated LFDATA output when a match occurs. The output enable filter consists of a high (TOEH) and low duration (TOEL) of a pulse immediately after the AGC settling gap time. The selection of high and low times further implies a max period time. The output enable high and low times are determined by SPI interface programming. Figure 11-5 and Figure 11-6 show the output enable filter waveforms. There should be no missing cycles during TOEH. Missing cycles may result in failing the output enable condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence TSTAB (TAGC + TPAGC) Data Packet TGAP t TOEH t TOEL Start bit LFDATA output is enabled on this rising edge
Demodulator Output
AFE Wake-up
and AGC Stabilization
AGC Gap Pulse
t TOET
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FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)
LFDATA Output
Start bit
3.5 ms
LF Coil Input
Low Current Standby Mode
TAGC (AGC settling time)
TPAGC TGAP (need Gap "high") Pulse
t TOEL t TOEH t TOET
t TE
TSTAB (AFE Stabilization)
Filter starts
Filter is passed and LFDATA is enabled
Legend:
TAGC = AGC stabilization time TE = Time element of pulse TGAP = AGC stabilization gap TOEH = Minimum output enable filter high time TOEL = Minimum output enable filter low time TOET = Maximum output enable filter period TPAGC = High time after TAGC TSTAB = TAGC + TPAGC
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TABLE 11-1:
OEH <1:0> 01 01 01 01 10 10 10 10 11 11 11 11 00 Note 1:
TYPICAL OUTPUT ENABLE FILTER TIMING
TOEH (ms) 1 1 1 1 2 2 2 2 4 4 4 4 TOEL (ms) 1 1 2 4 1 1 2 4 1 1 2 4 Filter Disabled TOET (ms) 3 3 4 6 4 4 5 8 6 6 8 10
OEL <1:0> 00 01 10 11 00 01 10 11 00 01 10 11
XX
If the filter resets due to a long high (TOEH > TOET), the high-pulse timer will not begin timing again until after a gap of TE and another low-to-high transition occurs on the demodulator output. Disabling the output enable filter disables the TOEH and TOEL requirement and the AFE passes all received LF data. See Figure 11-10, Figure 11-11 and Figure 11-12 for examples. When viewed from an application perspective, from the pin input, the actual output enable filter timing must factor in the analog delays in the input path (such as demodulator charge and discharge times). * TOEH - TDR + TDF * TOEL + TDR - TDF The output enable filter starts immediately after TGAP, the gap after AGC stabilization period.
11.16 Input Sensitivity Control
The AFE is designed to have typical input sensitivity of 3 mVPP. This means any input signal with amplitude greater than 3 mVPP can be detected. The AFE's internal AGC loop regulates the detecting signal amplitude when the input level is greater than approximately 20 mVPP. This signal amplitude is called "AGC-active level". The AGC loop regulates the input voltage so that the input signal amplitude range will be kept within the linear range of the detection circuits without saturation. The AGC Active Status bit (AGCACT<5>) in the AFE Status Register 7 (Register 11-8) is set if the AGC loop regulates the input voltage. Table 11-2 shows the input sensitivity comparison when the AGCSIG option is used. When AGCSIG option bit is set, the demodulated output is available only when the AGC loop is active (see Table 11-1). The AFE has also input sensitivity reduction options per each channel. The Configuration Register 3 (Register 11-4), Configuration Register 4 (Register 11-5) and Configuration Register 5 (Register 11-6) have the option to reduce the channel gains from 0 dB to approximately -30 dB.
Typical at room temperature and VDD = 3.0V, 32 kHz oscillator.
TOEH is measured from the rising edge of the demodulator output to the first falling edge. The pulse width must fall within TOEH t TOET. TOEL is measured from the falling edge of the demodulator output to the rising edge of the next pulse. The pulse width must fall within TOEL t TOET. TOET is measured from rising edge to the next rising edge (i.e., the sum of TOEH and TOEL). The pulse width must be t TOET. If the Configuration Register 0 (Register 11-1), OEL<8:7> is set to `00', then TOEH must not exceed TOET and TOEL must not exceed TINACT. The filter will reset, requiring a complete new successive high and low period to enable LFDATA, under the following conditions. * The received high is not greater than the configured minimum TOEH value. * During TOEH, a loss of signal > 56 s. A loss of signal < 56 s may or may not cause a filter Reset. * The received low is not greater than the configured minimum TOEL value. * The received sequence exceeds the maximum TOET value: - TOEH + TOEL > TOET - or TOEH > TOET - or TOEL > TOET * A Soft Reset SPI command is received.
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TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)
Description Disabled - the AFE passes signal of any amplitude level it is capable of detecting (demodulated data and carrier clock). Enabled - No output until AGC Status = 1 (i.e., VPEAK 20 mVPP) (demodulated data and carrier clock). * Provides the best signal to noise ratio. Input Sensitivity (Typical) 3.0 mVPP 20 mVPP AGCSIG<7> (Config. Register 5) 0 1
11.17 Input Channels (Enable/Disable)
Each channel can be individually enabled or disabled by programming bits in Configuration Register 0<3:1> (Register 11-1). The purpose of having an option to disable a particular channel is to minimize current draw by powering down as much circuitry as possible, if the channel is not needed for operation. The exact circuits disabled when an input is disabled are amplifiers, detector, full-wave rectifier, data slicer, and modulation FET. However, the RF input limiter remains active to protect the silicon from excessive antenna input voltages.
11.19 AGC Preserve
The AGC preserve feature allows the AFE to preserve the AGC value during the AGC settling time (TAGC) and apply the value to the data slicing circuit for the following data streams instead of using a new tracking value. This feature is useful to demodulate the input signal correctly when the input has random amplitude variations at a given time period. This feature is enabled when the AFE receives an AGC Preserve On command and disabled if it receives an AGC Preserve Off command. Once the AGC Preserve On command is received, the AFE acquires a new AGC value during each AGC settling time and preserves the value until a Soft Reset or an AGC Preserve Off command is issued. Therefore, it does not need to issue another AGC Preserve On command. An AGC Preserve Off command is needed to disable the AGC preserve feature (see Section 11.32.2.5 "AGC Preserve On Command" and Section 11.32.2.6 "AGC Preserve Off Command" for AGC Preserve commands).
11.18 AGC Amplifier
The circuit automatically amplifies input signal voltage levels to an acceptable level for the data slicer. Fast attack and slow release by nature, the AGC tracks the carrier signal level and not the modulated data bits. The AGC inherently tracks the strongest of the three antenna input signals. The AGC requires an AGC stabilization time (TAGC). The AGC will attempt to regulate a channel's peak signal voltage into the data slicer to a desired regulated AGC voltage - reducing the input path's gain as the signal level attempts to increase above regulated AGC voltage, and allowing full amplification on signal levels below the regulated AGC voltage. The AGC has two modes of operation: 1. During the AGC settling time (TAGC), the AGC time constant is fast, allowing a reasonably short acquisition time of the continuous input signal. After TAGC, the AGC switches to a slower time constant for data slicing.
2.
Also, the AGC is frozen when the input signal envelope is low. The AGC tracks only high envelope levels.
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11.20 Soft Reset
The AFE issues a Soft Reset in the following events: a) b) c) d) After Power-on Reset (POR), After Inactivity timer time-out, If an "Abort" occurs, After receiving SPI Soft Reset command.
TABLE 11-3:
SETTING FOR MINIMUM MODULATION DEPTH REQUIREMENT
Modulation Depth
MODMIN Bits (Config. Register 5) Bit 6 0 0 1 1 Bit 5 0 1 0 1
The "Abort" occurs if there is no positive signal detected at the end of the AGC stabilization period (TAGC). The Soft Reset initializes internal circuits and brings the AFE into a low current Standby mode operation. The internal circuits that are initialized by the Soft Reset include: * * * * Output Enable Filter AGC circuits Demodulator 32 kHz Internal Oscillator
50% (default) 75% 25% 12%
The Soft Reset has no effect on the Configuration register setup, except for some of the AFE Status Register 7 bits. (Register 11-8). The circuit initialization takes one internal clock cycle (1/32 kHz = 31.25 s). During the initialization, the modulation transistors between each input and LCCOM pins are turned-on to discharge any internal/ external parasitic charges. The modulation transistors are turned-off immediately after the initialization time. The Soft Reset is executed in Active mode only. It is not valid in Standby mode.
11.21 Minimum Modulation Depth Requirement for Input Signal
The AFE demodulates the modulated input signal if the modulation depth of the input signal is greater than the minimum requirement that is programmed in the AFE Configuration Register 5 (Register 11-6). Figure 11-7 shows the definition of the modulation depth and examples. MODMIN<6:5> of the Configuration Register 5 offer four options. They are 75%, 50%, 25% and 12%, with a default setting of 50%. The purpose of this feature is to enhance the demodulation integrity of the input signal. The 12% setting is the best choice for the input signal with weak modulation depth, which is typically observed near the high-voltage base station antenna and also at fardistance from the base station antenna. It gives the best demodulation sensitivity, but is very susceptible to noise spikes that can result in a bit detection error. The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings.
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FIGURE 11-7:
MODULATION DEPTH EXAMPLES (a) Modulation Depth Definition Amplitude Modulation Depth (%) = t B A A-B A X 100%
(b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting Amplitude 7 mVPP 10 mVPP Coil Input Strength Modulation Depth (%) = t 10 - 7 X 100% = 30% 10
Input signal with modulation depth = 30%
Demodulated LFDATA Output when MODMIN Setting = 25% t (LFDATA output = toggled) Amplitude Demodulated LFDATA Output if MODMIN Setting = 50% (LFDATA output = not toggled) 0 t
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11.22 Low Current Sleep Mode
The Sleep command from the microcontroller, via an SPI Interface command, places the AFE into an ultra Low-current mode. All circuits including the RF Limiter, except the minimum circuitry required to retain register memory and SPI capability, will be powered down to minimize the AFE current draw. Power-on Reset or any SPI command, other than Sleep command, is required to wake the AFE from Sleep.
11.25 Error Detection of AFE Configuration Register Data
The AFE's Configuration registers are volatile memory. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect. To ensure the data integrity, the AFE has an error detection mechanism using row and column parity bits of the Configuration register memory map. The bit 0 of each register is a row parity bit which is calculated over the eight configuration bits (from bit 1 to bit 8). The Column Parity Register (Configuration Register 6) holds column parity bits; each bit is calculated over the respective columns (Configuration registers 0 to 5) of the Configuration bits. The Status register is not included for the column parity bit calculation. Parity is to be odd. The parity bit set or cleared makes an odd number of set bits. The user needs to calculate the row and column parity bits using the contents of the registers and program them. During operation, the AFE continuously calculates the row and column parity bits of the configuration memory map. If a parity error occurs, the AFE lowers the SCLK/ALERT pin (interrupting the microcontroller section) indicating the configuration memory has been corrupted or unloaded and needs to be reprogrammed. At an initial condition after a Power-On-Reset, the values of the registers are all clear (default condition). Therefore, the AFE will issue the parity bit error by lowering the SCLK/ALERT pin. If user reprograms the registers with correct parity bits, the SCLK/ALERT pin will be toggled to logic high level immediately. The parity bit errors do not change or affect the AFE's functional operation. Table 11-4 shows an example of the register values and corresponding parity bits.
11.23 Low Current Standby Mode
The AFE is in Standby mode when no LF signal is present on the antenna inputs but the AFE is powered and ready to receive any incoming signals.
11.24 Low Current Operating Mode
The AFE is in Low-current Operating mode when a LF signal is present on an LF antenna input and internal circuitry is switching with the received data.
TABLE 11-4:
AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 8 1 0 0 0 0 1 1 Bit 7 0 0 0 0 0 0 1 Bit 6 1 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 1 Bit 4 1 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 1 Bit 2 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 0 1 Bit 0 (Row Parity) 0 1 1 1 1 0 1
Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Configuration Register 5 Configuration Register 6 (Column Parity Register)
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11.26 Factory Calibration
Microchip calibrates the AFE to reduce the device-todevice variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation.
11.28 Battery Back-up and Batteryless Operation
The device supports both battery back-up and batteryless operation by the addition of external components, allowing the device to be partially or completely powered from the field. Figure 11-8 shows an example of the external circuit for the battery back-up. Note: Voltage on LCCOM combined with coil input voltage must not exceed the maximum LC input voltage.
11.27 De-Q'ing of Antenna Circuit
When the transponder is close to the base station, the transponder coil may develop coil voltage higher than VDE_Q. This condition is called "near field". The AFE detects the strong near field signal through the AGC control, and de-Q'ing the antenna circuit to reduce the input signal amplitude.
FIGURE 11-8:
LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE
VBAT
VDD RLIM DBLOCK DLIM CPOOL DFLAT1 LX Air Coil LY CY CX LCY LCX
LCZ
LZ
CZ LCCOM
DFLAT2 RCOM CCOM
Legend:
CCOM = LCCOM charging capacitor. CPOOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device. DBLOCK = Battery protection from reverse charge. Schottky for low forward bias drop. DFLAT = Field rectifier diodes. DLIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields. RCOM = Ccom discharge path. RLIM = Current limiting resistor, required for air coil in strong fields.
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11.29 Demodulator
The demodulator recovers the modulation data from the received signal, containing carrier plus data, by appropriate envelope detection. The demodulator has a fast rise (charge) time (TDR) and a fall time (TDF) appropriate to an envelope of input signal (see Section 15.0 "Electrical Specifications" for TDR and TDF specifications). The demodulator contains the full-wave rectifier, low-pass filter, peak detector and data slicer.
FIGURE 11-9:
DEMODULATOR CHARGE AND DISCHARGE
Signal into LC input pins
Full-wave Rectifier output
Data Slicer output (demodulator output) TDR TDF
11.30 Power-On Reset
This circuit remains in a Reset state until a sufficient supply voltage is applied to the AFE. The Reset releases when the supply is sufficient for correct AFE operation, nominally VPOR of AFE. The Configuration registers are all cleared on a Poweron Reset. As the Configuration registers are protected by odd row and column parity, the ALERT pin will be pulled down - indicating to the microcontroller section that the AFE configuration memory is cleared and requires loading.
For a clean data output or to save operating power, the input channels can be individually enabled or disabled. If more than one channel is enabled, the output is the sum of each output of all enabled channels. There will be no valid output if all three channels are disabled. When the demodulated output is selected, the output is available in two different conditions depending on how the options of Configuration Register 0 (Register 11-1) are set: Output Enable Filter is disabled or enabled. Related Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT <8:7>: - bit 8 bit 7 0 0 1 0 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
11.31 LFDATA Output Selection
The LFDATA output can be configured to pass the Demodulator output, Received Signal Strength Indicator (RSSI) output, or Carrier Clock. See Configuration Register 1 (Register 11-2) for more details.
11.31.1
DEMODULATOR OUTPUT
* Configuration Register 0 (Register 11-1): all bits
The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output.
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Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization time (TAGC). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled.
FIGURE 11-10:
INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE FILTER IS DISABLED
Input Signal
LFDATA Output
Case II. When Output Enable Filter is enabled: Demodulated output is available only if the incoming signal meets the enable filter timing criteria that is defined in the Configuration Register 0 (Register 11-1). If the criteria is met, the output is available after the low timing (TOEL) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of demodulated output when the Output Enable Filter is enabled.
FIGURE 11-11:
INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS)
Input Signal
LFDATA Output
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FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS)
Input Signal
No LFDATA Output
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11.31.2 CARRIER CLOCK OUTPUT
When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (TAGC) is completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT<7> of Configuration Register 2 (Register 11-3). The carrier clock output is available immediately after the AGC settling time. The Output Enable Filter, AGCSIG, and MODMIN options are applicable for the carrier clock output in the same way as the demodulated output. The input channel can be individually enabled or disabled for the output. If more than one channel is enabled, the output is the sum of each output of all enabled channels. Therefore, the carrier clock output waveform is not as precise as when only one channel is enabled. It is recommended to enable one channel only if a precise output waveform is desired. There will be no valid output if all three channels are disabled. See Figure 11-13 for carrier clock output examples. Related Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT <8:7>: bit 8 bit 7 0 0 1 1 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
* Configuration Register 2 (Register 11-3), CLKDIV<7>: 0: Carrier Clock/1 1: Carrier Clock/4 * Configuration Register 0 (Register 11-1): all bits are affected * Configuration Register 5 (Register 11-6)
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FIGURE 11-13:
CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION
Carrier Clock Output
Carrier Input
(B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION
Carrier Clock Output
Carrier Input
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11.31.3 RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT FIGURE 11-14:
RSSI OUTPUT PATH An analog current is available at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE's Configuration register. The analog current is linearly proportional to the input signal strength (see Figure 11-15). All timers in the circuit, such as inactivity timer, alarm timer, and AGC settling time, are disabled during the RSSI mode. Therefore, the RSSI output is not affected by the AGC settling time, and available immediately when the RSSI option is selected. The AFE enters Active mode immediately when the RSSI output is selected. The MCU I/O pin (RC3) connected to the LFDATA pin, must be set to high-impedance state during the RSSI Output mode. When the AFE receives an SPI command during the RSSI output, the RSSI mode is temporary disabled until the SPI interface communication is completed. It returns to the RSSI mode again after the SPI interface communication is completed. The AFE holds the RSSI mode until another output type is selected (CS low turns off the RSSI signal). To obtain the RSSI output for a particular input channel, or to save operating power, the input channel can be individually enabled or disabled. If more than one channel is enabled, the RSSI output is from the strongest signal channel. There will be no valid output if all three channels are disabled. Related AFE Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT<8:7>: bit 8 0 0 1 1 bit 7 0: Demodulated Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
RSSI Output Current Generator Current Output VDD Off if RSSI active
RC3/LFDATA/RSSI/CCLK Pin RSSIFET
RSSI Pull-down MOSFET (controlled by Config. 2, bit 8)
* Configuration Register 2 (Register 11-3), RSSIFET<8>: 0: Pull-Down MOSFET off 1: Pull-Down MOSFET on. Note: The pull-down MOSFET option is valid only when the RSSI output is selected. The MOSFET is not controllable by users when Demodulated or Carrier Clock output option is selected.
* Configuration Register 0 (Register 11-1): all bits are affected.
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FIGURE 11-15:
90 80 70
RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE
RSSI Output Current (uA)
60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10
Input Voltage (VPP)
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11.31.3.1 ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL
11.32 AFE Configuration
11.32.1 SPI COMMUNICATION
The AFE's RSSI output is an analog current. It needs an external analog-to-digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device or by firmware utilizing MCU's internal comparator along with a few external resistors and a capacitor. For slope ADC implementations, the external capacitor at the LFDATA pad needs to be discharged before data sampling. For this purpose, the internal pulldown MOSFET on the LFDATA pad can be utilized. The MOSFET can be turned on or off with bit RSSIFET<8> of the Configuration Register 2 (Register 11-3). When it is turned on, the internal MOSFET provides a discharge path for the external capacitor. This MOSFET option is valid only if RSSI output is selected and not controllable by users for demodulated or carrier clock output options. See separate application notes for various external ADC implementation methods for this device.
The AFE SPI interface communication is used to read or write the AFE's Configuration registers and to send command only messages. For the SPI interface, the device has three pads; CS, SCLK/ALERT, and LFDATA/RSSI/CCLK/SDIO. Figure 11-15, Figure 1114, Figure 11-16 and Figure 11-17 shows examples of the SPI communication sequences. When the device powers up, these pins will be highimpedance inputs until firmware modifies them appropriately. The AFE pins connected to the MCU pins will be as follows. CS * Pin is permanently an input with an internal pull-up. SCLK/ALERT * Pin is an open collector output when CS is high. An internal pull-up resistor exists internal to the AFE to ensure no spurious SPI communication between powering and the MCU configuring its pins. This pin becomes the SPI clock input when CS is low. LFDATA/RSSI/CCLK/SDIO * Pin is a digital output (LFDATA) so long as CS is high. During SPI communication, the pin is the SPI data input (SDI) unless performing a register Read, where it will be the SPI data output (SDO).
FIGURE 11-16:
POWER-UP SEQUENCE
MCU pin is input. CS pulled high by internal pull-up Driving CS high MCU pin output
CS
SCLK/ALERT
LFDATA/RSSI/ CCLK/SDIO
MCU pin is input.
LFDATA (output)
by internal pull-up ALERT (open collector output)
MCU pin is input. SCLK pulled high
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FIGURE 11-17: SPI WRITE SEQUENCE
TCSH 2 CS TCSSC Driven low by MCU TSCCS TCS1 Driven low by MCU 7 6 MCU pin to Input
SCLK/ ALERT ALERT (output)
SCLK (input)
MSb 1/FSCLK
LSb
ALERT (output)
1 MCU pin still Input
LFDATA/RSSI/ CCLK/SDIO LFDATA (output)
SDI (input) 3
MCU pin to Output
MCU pin to Input
TSU
THD
5
LFDATA (output)
MCU SPI Write Details: 1. 2. Drive the AFE's open collector ALERT output low. * to ensure no false clocks occur when CS drops Drop CS. * AFE SCLK/ALERT becomes SCLK input * LFDATA/RSSI/CCLK/SDIO becomes SDI input Change LFDATA/RSSI/CCLK/SDIO connected pin to output. * driving SPI data Clock in 16-bit SPI Write sequence - command, address, data and parity bit. * command, address, data and parity bit Change LFDATA/RSSI/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Write. Change SCLK/ALERT back to input.
3. 4. 5. 6. 7.
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Driven low by MCU
4 16 Clocks for Write Command, Address and Data THI TLO
TCS0
PIC12F635/PIC16F636/639
FIGURE 11-18: SPI READ SEQUENCE
TCSH 2 6 MCU pin to Input 7 9
TCSH
TCSSC
4
16 Clocks for Read Command, Address and Dummy Data THI TLO
TSCCS TCS1
TCS0
TCSSC
8 16 Clocks for Read Result
10 TCSSC TCS1
MCU pin to Input
CS
TCS0 Driven low by MCU
Driven low by MCU
SCLK/ALERT ALERT (output)
SCLK (input)
MSb 1/FSCLK
LSb ALERT (output)
SCLK (input)
Driven low by MCU TDO
Driven low by MCU
ALERT (output)
1 MCU pin still Input
TSU THD MCU pin to Output MCU pin to Input 3 5 LFDATA (output)
LFDATA/RSSI/ CCLK/SDIO LFDATA (output)
SDI (input)
SDO (output)
LFDATA (output)
MCU SPI Read Details: 1. 2. Drive the AFE's open collector ALERT output low. * To ensure no false clocks occur when CS drops. Drop CS * AFE SCLK/ALERT becomes SCLK input. * LFDATA/RSSI/CCLK/SDIO becomes SDI input. Change LFDATA/RSSI/CCLK/SDIO connected pin to output. * Driving SPI data. Clock in 16-bit SPI Read sequence. * Command, address and dummy data. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Read entry of command and address. The TCSH is considered as one clock. Therefore, the Configuration register data appears at 6th clock after TCSH. 7. Drop CS. * AFE SCLK/ALERT becomes SCLK input. * LFDATA/RSSI/CCLK/SDIO becomes SDO output. Clock out 16-bit SPI Read result. * First seven bits clocked-out are dummy bits. * Next eight bits are the Configuration register data. * The last bit is the Configuration register row parity bit. Raise CS to complete the SPI Read. Change SCLK/ALERT back to input.
8.
3. 4. 5. 6.
9. 10.
Note:
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11.32.2 COMMAND DECODER/ CONTROLLER
The circuit executes 8 SPI commands from the MCU. The command structure is: Command (3 bits) + Configuration Address (4 bits) + Data Byte and Row Parity Bit received by the AFE Most Significant bit first. Table 11-5 shows the available SPI commands. The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK. There must be multiples of 16 clocks (SCLK) while CS is low or commands will abort.
TABLE 11-5:
SPI COMMANDS (AFE)
Data Row Parity X X X X X X P P P P P P P X P P P P P P P X Description
Command Address
Command only - Address and Data are "Don't Care", but need to be clocked in regardless. 000 001 010 011 100 101 110 XXXX XXXX XXXX XXXX XXXX XXXX 0000 0001 0010 0011 0100 0101 0110 0111 111 0000 0001 0010 0011 0100 0101 0110 0111 Note: XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity AFE Status Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity Not Used Clamp on - enable modulation circuit Clamp off - disable modulation circuit Enter Sleep mode (any other command wakes the AFE) AGC Preserve On - to temporarily preserve the current AGC level AGC Preserve Off - AGC again tracks strongest input signal Soft Reset - resets various circuit blocks General - options that may change during normal operation LCX antenna tuning and LFDATA output format LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 AFE status - parity error, which input is active, etc. General - options that may change during normal operation LCX antenna tuning and LFDATA output format LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 Register is readable, but not writable
Read Command - Data will be read from the specified register address.
Write Command - Data will be written to the specified register address.
`P' denotes the row parity bit (odd parity) for the respective data byte.
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FIGURE 11-19:
CS 1 SCLK MSb SDIO bit 2 bit 0 bit 3 bit 0 bit 7 bit 0 Data Byte Row Parity Bit LSb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DETAILED SPI INTERFACE TIMING (AFE)
Command
Address
11.32.2.1
Clamp On Command
11.32.2.5
AGC Preserve On Command
This command results in activating (turning on) the modulation transistors of all enabled channels; channels enabled in Configuration Register 0 (Register 11-1).
11.32.2.2
Clamp Off Command
This command results in de-activating (turning off) the modulation transistors of all channels.
This command results in preserving the AGC level during each AGC settling time and apply the value to the data slicing circuit for the following data stream. The preserved AGC value is reset by a Soft Reset, and a new AGC value is acquired and preserved when it starts a new AGC settling time. This feature is disabled by an AGC Preserve Off command (see Section 11.19 "AGC Preserve").
11.32.2.3
Sleep Command
This command places the AFE in Sleep mode - minimizing current draw by disabling all but the essential circuitry. Any other command wakes the AFE (example: Clamp Off command).
11.32.2.6
AGC Preserve Off Command
This command disables the AGC preserve feature and returns the AFE to the normal AGC tracking mode, fast tracking during AGC settling time and slow tracking after that (see Section 11.19 "AGC Preserve").
11.32.2.4
Soft Reset Command
The AFE issues a Soft Reset when it receives an external Soft Reset command. The external Soft Reset command is typically used to end a SPI communication sequence or to initialize the AFE for the next signal detection sequence, etc. See Section 11.20 "Soft Reset" for more details on Soft Reset. If a Soft Reset command is sent during a "Clamp-on" condition, the AFE still keeps the "Clamp-on" condition after the Soft Reset execution. The Soft Reset is executed in Active mode only, not in Standby mode. The SPI Soft Reset command is ignored if the AFE is not in Active mode.
11.32.3
CONFIGURATION REGISTERS
The AFE includes 8 Configuration registers, including a column parity register and AFE Status register. All registers are readable and writable via SPI, except Status register, which is readable only. Bit 0 of each register is a row parity bit (except for the AFE Status Register 7) that makes the register contents an odd number.
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TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY
Bit 8 OEH DATOUT RSSIFET CLKDIV Unimplemented Channel X Sensitivity Control AGCSIG MODMIN MODMIN Column Parity Bits Active Channel Indicators AGCACT Wake-up Channel Indicators ALARM Bit 7 Bit 6 OEL Bit 5 Bit 4 ALRTIND Bit 3 LCZEN Bit 2 LCYEN Bit 1 LCXEN Bit 0 R0PAR R1PAR R2PAR R3PAR R4PAR R5PAR R6PAR PEI Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Column Parity Register 6 AFE Status Register 7
Channel X Tuning Capacitor Channel Y Tuning Capacitor Channel Z Tuning Capacitor Channel Y Sensitivity Control Channel Z Sensitivity Control
Configuration Register 5 AUTOCHSEL
REGISTER 11-1:
R/W-0 OEH1 bit 8 bit 8-7
CONFIGURATION REGISTER 0 (ADDRESS: 0000)
R/W-0 OEH0 R/W-0 OEL1 R/W-0 OEL0 R/W-0 ALRTIND R/W-0 LCZEN R/W-0 LCYEN R/W-0 LCXEN R/W-0 R0PAR bit 0
OEH<1:0>: Output Enable Filter High Time (TOEH) bit 00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA) 01 = 1 ms 10 = 2 ms 11 = 4 ms OEL<1:0>: Output Enable Filter Low Time (TOEL) bit 00 = 1 ms 01 = 1 ms 10 = 2 ms 11 = 4 ms ALRTIND: ALERT bit, output triggered by: 1 = Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 "Alarm Timer") 0 = Parity error LCZEN: LCZ Enable bit 1 = Disabled 0 = Enabled LCYEN: LCY Enable bit 1 = Disabled 0 = Enabled LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled R0PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 11-2:
R/W-0 DATOUT1 bit 8 bit 8-7 DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier Clock output 10 = RSSI output 11 = RSSI output LCXTUN<5:0>: LCX Tuning Capacitance bit 000000 =+0 pF (Default) : 111111 =+63 pF R1PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CONFIGURATION REGISTER 1 (ADDRESS: 0001)
R/W-0 DATOUT0 R/W-0 LCXTUN5 R/W-0 LCXTUN4 R/W-0 LCXTUN3 R/W-0 LCXTUN2 R/W-0 LCXTUN1 R/W-0 LCXTUN0 R/W-0 R1PAR bit 0
bit 6-1
bit 0
REGISTER 11-3:
R/W-0 RSSIFET bit 8 bit 8
CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0 CLKDIV R/W-0 LCYTUN5 R/W-0 LCYTUN4 R/W-0 LCYTUN3 R/W-0 LCYTUN2 R/W-0 LCYTUN1 R/W-0 LCYTUN0 R/W-0 R2PAR bit 0
RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only) 1 = Pull-down RSSI MOSFET on 0 = Pull-down RSSI MOSFET off CLKDIV: Carrier Clock Divide-by bit 1 = Carrier Clock/4 0 = Carrier Clock/1 LCYTUN<5:0>: LCY Tuning Capacitance bit 000000 =+0 pF (Default) : 111111 =+63 pF R2PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 7
bit 6-1
bit 0
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REGISTER 11-4:
U-0 -- bit 8 bit 8-7 bit 6-1 Unimplemented: Read as `0' LCZTUN<5:0>: LCZ Tuning Capacitance bit 000000 =+0 pF (Default) : 111111 =+63 pF R3PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CONFIGURATION REGISTER 3 (ADDRESS: 0011)
U-0 -- R/W-0 LCZTUN5 R/W-0 LCZTUN4 R/W-0 LCZTUN3 R/W-0 LCZTUN2 R/W-0 LCZTUN1 R/W-0 LCZTUN0 R/W-0 R3PAR bit 0
bit 0
REGISTER 11-5:
R/W-0 LCXSEN3 bit 8 bit 8-5
CONFIGURATION REGISTER 4 (ADDRESS: 0100)
R/W-0 LCXSEN2 R/W-0 LCXSEN1 R/W-0 LCXSEN0 R/W-0 LCYSEN3 R/W-0 LCYSEN2 R/W-0 LCYSEN1 R/W-0 LCYSEN0 R/W-0 R4PAR bit 0
LCXSEN<3:0>(1): Typical LCX Sensitivity Reduction bit 0000 = -0 dB (Default) 0001 = -2 dB 0010 = -4 dB 0011 = -6 dB 0100 = -8 dB 0101 = -10 dB 0110 = -12 dB 0111 = -14 dB 1000 = -16 dB 1001 = -18 dB 1010 = -20 dB 1011 = -22 dB 1100 = -24 dB 1101 = -26 dB 1110 = -28 dB 1111 = -30 dB LCYSEN<3:0>(1): Typical LCY Sensitivity Reduction bit 0000 = -0 dB (Default) : 1111 = -30 dB R4PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Assured monotonic increment (or decrement) by design.
bit 4-1
bit 0
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REGISTER 11-6:
R/W-0 AUTOCHSEL bit 8 bit 8
CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0 AGCSIG R/W-0 MODMIN1 R/W-0 MODMIN0 R/W-0 LCZSEN3 R/W-0 LCZSEN2 R/W-0 LCZSEN1 R/W-0 LCZSEN0 R/W-0 R5PAR bit 0
AUTOCHSEL: Auto Channel Select bit 1 = Enabled - AFE selects channel(s) that has demodulator output "high" at the end of TSTAB; or otherwise, blocks the channel(s). 0 = Disabled - AFE follows channel enable/disable bits defined in Register 0 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active 1 = Enabled - No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set when the AGC begins regulating. 0 = Disabled - the AFE passes signal of any level it is capable of detecting MODMIN<1:0>: Minimum Modulation Depth bit 00 = 50% 01 = 75% 10 = 25% 11 = 12% LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit 0000 = -0dB (Default) : 1111 = -30dB R5PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Assured monotonic increment (or decrement) by design.
bit 7
bit 6-5
bit 4-1
bit 0
REGISTER 11-7:
R/W-0 COLPAR7 bit 8 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0 COLPAR6 R/W-0 COLPAR5 R/W-0 COLPAR4 R/W-0 COLPAR3 R/W-0 COLPAR2 R/W-0 COLPAR1 R/W-0 COLPAR0 R/W-0 R6PAR bit 0
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the config register row parity bits contain an odd number of set bits. COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in config registers 0 through 5 contain an odd number of set bits. COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in config registers 0 through 5 contain an odd number of set bits. COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in config registers 0 through 5 contain an odd number of set bits. COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in config registers 0 through 5 contain an odd number of set bits. COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in config registers 0 through 5 contain an odd number of set bits. COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in config registers 0 through 5 contain an odd number of set bits. COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in config registers 0 through 5 contain an odd number of set bits. R6PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 11-8:
R-0 CHZACT bit 8 bit 8 CHZACT: Channel Z Active(1) bit (cleared via Soft Reset) 1 = Channel Z is passing data after TAGC 0 = Channel Z is not passing data after TAGC CHYACT: Channel Y Active(1) bit (cleared via Soft Reset) 1 = Channel Y is passing data after TAGC 0 = Channel Y is not passing data after TAGC CHXACT: Channel X Active(1) bit (cleared via Soft Reset) 1 = Channel X is passing data after TAGC 0 = Channel X is not passing data after TAGC AGCACT: AGC Active Status bit (real time, cleared via Soft Reset) 1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range. 0 = AGC is inactive (Input signal is weak) WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset) 1 = Channel Z caused a AFE wake-up (passed /64 clock counter) 0 = Channel Z did not cause a AFE wake-up WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset) 1 = Channel Y caused a AFE wake-up (passed /64 clock counter) 0 = Channel Y did not cause a AFE wake-up WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset) 1 = Channel X caused a AFE wake-up (passed /64 clock counter) 0 = Channel X did not cause a AFE wake-up ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read "Status Register command") 1 = The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the Configuration register 0 0 = The Alarm timer is not timed out PEI: Parity Error Indicator bit - indicates whether a Configuration register parity error has occurred (real time) 1 = A parity error has occurred and caused the ALERT output to go low 0 = A parity error has not occurred Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
AFE STATUS REGISTER 7 (ADDRESS: 0111)
R-0 CHYACT R-0 CHXACT R-0 AGCACT R-0 WAKEZ R-0 WAKEY R-0 WAKEX R-0 ALARM R-0 PEI bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
See Table 11-7 for the bit conditions of the AFE Status register after various SPI commands and the AFE Power-on Reset.
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TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS)
Bit 8 Condition CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM POR Read Command (STATUS Register only) Sleep Command Soft Reset Executed(1) 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 0 u u PEI 1 u u u Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Legend: u = unchanged Note 1: See Section 11.20 "Soft Reset" and Section 11.32.2.4 "Soft Reset Command" for the condition of Soft Reset execution.
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12.0 SPECIAL FEATURES OF THE CPU
The PIC12F635/PIC16F636/639 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Powerup Timer to provide at least a nominal 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An Interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 12-1).
The PIC12F635/PIC16F636/639 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Wake-up Reset (WUR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) * Interrupts * Watchdog Timer (WDT) * Oscillator selection * Sleep * Code protection * ID Locations * In-Circuit Serial Programming
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12.1 Configuration Word Bits
Note: The Configuration Word bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
REGISTER 12-1:
U-1 -- bit 13 bit 13 bit 12 R/P-1 R/P-1
CONFIG - CONFIGURATION WORD (ADDRESS: 2007h)
R/P-1 IESO R/P-1 R/P-1 R/P-1 CPD R/P-1 CP R/P-1 R/P-1
(1)
R/P-1 WDTE
R/P-1 FOSC2
R/P-1 F0SC1
R/P-1 F0SC0 bit 0
WURE FCMEN
BODEN1 BODEN0
MCLRE PWRTE
Unimplemented: Read as `1' WURE: Wake-up Reset Enable bit 1 = Standard wake-up and continue enabled 0 = Wake-up and Reset enabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled IESO: Internal-External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled BODEN<1:0>: Brown-out Detect Enable bits 11 = BOD enabled and SBODEN bit disabled 10 = BOD enabled while running and disabled in Sleep. SBODEN bit disabled. 01 = SBODEN in Register 2-6 controls BOD function 00 = BOD and SBODEN disabled CPD: Code Protection Data bit 1 = Data memory is not protected 0 = Data memory is external read protected CP: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is external read and write-protected MCLRE: MCLR Pin Function Select bit 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is alternate function, MCLR function is internally disabled PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled using SWDTEN in Register 12-2 FOSC<2:0>: Oscillator Selection bits 000 = LP oscillator: Low power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT 001 = XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT 010 = HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT 011 = EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN 110 = EXTRCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN 111 = EXTRC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN Note 1: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Enabling Brown-out Detect does not automatically enable the Power-up Timer (PWRT).
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
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PIC12F635/PIC16F636/639
12.2 Reset
The PIC12F635/PIC16F636/639 differentiates between various kinds of Reset: a) b) c) d) e) f) g) Power-on Reset (POR) Wake-up Reset (WUR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Detect (BOD) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-3. These bits are used in software to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Detect
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Sleep WURE Wake-up Interrupt
External Reset MCLR/VPP pin WDT Module VDD Rise Detect VDD Brown-out(1) Detect BODEN BODEN<0> SBODEN <1> Power-on Reset Sleep WDT Time-out Reset
RA3 Change
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register 12-1).
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 113
PIC12F635/PIC16F636/639
12.3 Power-on Reset 12.5 MCLR
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 "Electrical Specifications" for details. If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches VBOD (see Section 12.6 "Brown-out Detect (BOD)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach VSS for a minimum of 100 s. PIC12F635/PIC16F636/639 has a noise filter in the MCLR Reset path. The filter will ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. See Figure 12-2 for the recommended MCLR circuit. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
FIGURE 12-2:
VDD R1 1 k (or greater)
RECOMMENDED MCLR CIRCUIT
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the Application Note AN607, "Power-up Trouble Shooting" (DS00607).
PIC12F635/PIC16F636/639
MCLR C1 0.1 F (optional, not critical)
12.4
Wake-up Reset (WUR)
The PIC12F635/PIC16F636/639 has a modified wakeup from Sleep mechanism. When waking from Sleep, the WUR function resets the device and releases Reset when VDD reaches an acceptable level. If the WURE bit is enabled (`0') in the Configuration Word register, the device will Wake-up Reset from Sleep through one of the following events: 1. On any event that causes a wake-up event. The peripheral must be enabled to generate an interrupt or wake-up, GIE state is ignored. When WURE is enabled, RA3 will always generate an interrupt-on-change signal during Sleep.
2.
The WUR, POR and BOD bits in the PCON register and the TO and PD bits in the Status register can be used to determine the cause of device Reset. To allow WUR upon RA3 change: 1. 2. 3. 4. 5. Enable the WUR function, WURE Configuration Bit = 0. Enable RA3 as an input, MCLRE Configuration Bit = 0. Read PORTA to establish the current state of RA3. Execute SLEEP instruction. When RA3 changes state, the device will wakeup and then reset. The WUR bit in PCON will be cleared to `0'.
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PIC12F635/PIC16F636/639
12.6 Brown-out Detect (BOD)
The BODEN0 and BODEN1 bits in the Configuration Word register select one of four BOD modes. Two modes have been added to allow software or hardware control of the BOD enable. When BODEN<1:0> = 01, the SBODEN bit (PCON<4>) enables/disables the BOD allowing it to be controlled in software. By selecting BODEN<1:0>, the BOD is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBODEN bit is disabled. See Register 12-1 for the Configuration Word definition. If VDD falls below VBOD for greater than parameter (TBOD) (see Section 15.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOD for less than parameter (TBOD). On any Reset (Power-on, Brown-out Detect, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOD (see Figure 12-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional nominal 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register.
If VDD drops below VBOD while the Power-up Timer is running, the chip will go back into a Brown-out Detect and the Power-up Timer will be re-initialized. Once VDD rises above VBOD, the Power-up Timer will execute a 64 ms Reset.
FIGURE 12-3:
BROWN-OUT DETECT SITUATIONS
VDD VBOD
Internal Reset VDD
64 ms(1)
VBOD < 64 ms
Internal Reset
64 ms(1)
VDD
VBOD
Internal Reset Note 1:
64 ms(1) Nominal 64 ms delay only if PWRTE bit is programmed to `0'.
(c) 2005 Microchip Technology Inc.
Preliminary
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PIC12F635/PIC16F636/639
12.7 Time-out Sequence 12.8 Power Control (PCON) Register
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The device can execute code from the INTOSC, while OST is active, by enabling Two-Speed Start-up or Fail-Safe Clock Monitor (See Section 3.6.2 "Two-Speed Start-up Sequence" and Section 3.7 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F635/PIC16F636/ 639 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. The Power Control register, PCON (address 8Eh), has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOD = 0, indicating that a Brown-out has occurred. The BOD Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BODEN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 4.2.3 "Ultra LowPower Wake-up" and Section 12.6 "Brown-out Detect (BOD)".
TABLE 12-1:
Oscillator Configuration XT, HS, LP RC, EC, INTOSC
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Brown-out Detect PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
TABLE 12-2:
Address 03h 8Eh Legend: Note 1: Name
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT DETECT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RP0 Bit 4 TO Bit 3 PD WUR Bit 2 Z -- Bit 1 DC POR Bit 0 C BOD Value on POR, BOD, WUR 0001 1xxx --01 q-qq Value on all other Resets(1) 000q quuu --0u u-uu
STATUS PCON
ULPWUE SBODEN
u = unchanged, x = unknown, -- = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOD. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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PIC12F635/PIC16F636/639
TABLE 12-3:
POR 0 u u u u u u u x 0 u u u u u 0
PCON BITS AND THEIR SIGNIFICANCE
WUR x u u u u u 0 u TO 1 1 0 0 u 1 1 1 PD 1 1 u 0 u 0 0 1 Power-on Reset Brown-out Detect WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Wake-up Reset during Sleep Brown-out Detect during Sleep Condition
BOD
Legend: u = unchanged, x = unknown
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Preliminary
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PIC12F635/PIC16F636/639
FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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TABLE 12-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset Wake-up Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xx00 --xx xx00 ---0 0000 0000 0000 0000 00-0 xxxx xxxx xxxx xxxx 0000 0000 ---0 1000 0000 0000 ---- --10 1111 1111 --11 1111 --11 1111 0000 00-0 --01 q-qq -110 x000 ---0 0000 --11 -111 --00 0000 --11 -111 0-0- 0000 0000 0000 0000 0000 ---- x000 ---- ---xxxx xxxx -000 -----00 -000 00-- --00 MCLR Reset WDT Reset Brown-out Detect(1) Wake-up Reset uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu
(4)
Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uu00 --uu uu00 ---u uuuu uuuu uuuu(2) uuuu uu-u(2) uuuu uuuu uuuu uuuu -uuu uuuu ---u uuuu uuuu uuuu ---- --uu uuuu uuuu --uu 1uuu --uu 1uuu uuuu uu-u --0u u-uu -uuu uuuu ---u uuuu uuuu uuuu --uu uuuu uuuu uuuu u-u- uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- ---uuuu uuuu -uuu -----uu -uuu uu-- --uu
W INDF TMR0 PCL STATUS FSR PORTA PORTC
(6)
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 07h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 18h 19h 1Ah 81h 85h
(6)
uuuu uuuu --00 0000 --00 0000 ---0 0000 0000 0000 0000 00-0 uuuu uuuu uuuu uuuu uuuu uuuu ---0 1000 0000 0000 ---- --10 1111 1111 --11 1111 --11 1111 0000 00-0 --0u u-uu
(1,5)
PCLATH INTCON PIR1 TMR1L TMR1H T1CON WDTCON CMCON0 CMCON1 OPTION_REG TRISA TRISC PIE1 PCON OSCCON OSCTUNE WPUDA IOCA WDA VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 LVDCON CRCON Legend: Note 1: 2: 3: 4: 5: 6:
87h 8Ch 8Eh 8Fh 90h 95h 96h 97h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 94h 110h
-110 x000 ---u uuuu --11 -111 --00 0000 --11 -111 0-0- 0000 0000 0000 0000 0000 ---- q000 ---- ---uuuu uuuu -000 -----00 -000 00-- --00
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F636/639 only.
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Preliminary
DS41232B-page 119
PIC12F635/PIC16F636/639
TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from Sleep Wake-up Reset Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) 000h Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu 0001 1xxx PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu --01 --0x
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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PIC12F635/PIC16F636/639
12.9 Interrupts
The PIC12F635/PIC16F636/639 has 8 sources of interrupt: * * * * * * * External Interrupt RA2/INT Timer0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, comparators or data EEPROM modules, refer to the respective peripheral section.
The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTA Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: * * * * EEPROM Data Write Interrupt 2 Comparator Interrupts Timer1 Overflow Interrupt Fail-Safe Clock Monitor Interrupt
12.9.1
RA2/INT INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 12.12 "Power-Down Mode (Sleep)" for details on Sleep and Figure 12-10 for timing of wake-up from Sleep through RA2/INT interrupt. Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h.
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Preliminary
DS41232B-page 121
PIC12F635/PIC16F636/639
12.9.2 TMR0 INTERRUPT 12.9.3 PORTA INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 "Timer0 Module" for operation of the Timer0 module. An input change on PORTA change sets the RAIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the RAIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOCA register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 LVDIF LVDIE TMR1IF TMR1IE C1IF C1IE C2IF(1) (1) C2IE EEIF EEIE OSFIF OSFIE CRIF CRIE T0IF T0IE INTF INTE RAIF RAIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
Note 1:
PIC16F636/639 only.
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PIC12F635/PIC16F636/639
FIGURE 12-8:
Q1 OSC1 CLKOUT(3) INT pin
(1) (4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(1) (5)
INTF Flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
Interrupt Latency(2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 15.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6:
Address 0Bh, 8Bh 0Ch 8Ch Legend: Note 1: Name
SUMMARY OF INTERRUPT REGISTERS
Bit 7 GIE EEIF EEIE Bit 6 PEIE LVDIF LVDIE Bit 5 T0IE CRIF CRIE Bit 4 INTE C2IF(1) C2IE(1) Bit 3 RAIE C1IF C1IE Bit 2 T0IF OSFIF OSFIE Bit 1 INTF -- -- Bit 0 RAIF Value on POR, BOD, WUR Value on all other Resets
INTCON PIR1 PIE1
0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0 TMR1IE 0000 00-0 0000 00-0
x = unknown, u = unchanged, -- = unimplemented, read as `0', q = value depends upon condition. Shaded cells are not used by the interrupt module. PIC16F636/639 only.
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Preliminary
DS41232B-page 123
PIC12F635/PIC16F636/639
12.10 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F635/PIC16F636/639 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example 12-1 can be used to: * * * * * Store the W register. Store the Status register. Execute the ISR code. Restore the Status (and Bank Select Bit register). Restore the W register. Note: The PIC12F635/PIC16F636/639 normally does not require saving the PCLATH. However, if computed GOTO's are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 12-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into Status register ;Swap W_TEMP ;Swap W_TEMP into W
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PIC12F635/PIC16F636/639
12.11 Watchdog Timer (WDT)
The PIC12F635/PIC16F636/639 WDT is code and functionally compatible with other PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 12-7. A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC by 32 to 65536, giving the WDT a nominal range of 1 ms to 268s.
12.11.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit (WDTCON<0>) has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC16F family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
12.11.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC12F635/PIC16F636/639 microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 12-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1)
16-bit WDT Prescaler
1
8 PSA 31 kHz LFINTOSC Clock
PS<2:0> To TMR0 0 1 PSA
WDTPS<3:0>
WDTE from Configuration Word Register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 "Prescaler" for more information.
TABLE 12-7:
WDTE = 0
WDT STATUS
Conditions WDT
CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, HFINTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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Preliminary
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REGISTER 12-2: WDTCON - WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16394 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved SWDTEN: Software Enable/Disable for Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 R/W-0 bit 0 WDTPS0 SWDTEN(1)
bit 0
TABLE 12-8:
Address 18h 81h 2007h
(1)
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 -- RAPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS MCLRE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN T0SE PWRTE PSA WDTE PS2 FOSC2 PS1 FOSC1 PS0 FOSC0
WDTCON OPTION_REG CONFIG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits.
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12.12 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). 6. External Interrupt from INT pin. Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level. Note 1: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. 2: The Analog Front-End (AFE) section in the PIC16F639 device is independent of the microcontroller's power-down mode (Sleep). See Section 11.32.2.3 "Sleep Command" for AFE's Sleep mode.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. Note: If WUR is enabled (WURE = 0 in Configuration Word), then the Wake-up Reset module will force a device Reset.
12.12.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
12.12.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTA change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. Special event trigger (Timer1 in Asynchronous mode using an external clock). EEPROM write operation completion. Comparator output changes state. Interrupt-on-change.
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FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Inst(PC) = Sleep Inst(PC - 1) Processor in Sleep Interrupt Latency(3)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.13 Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
12.14 ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
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12.15 In-Circuit Serial Programming
The PIC12F635/PIC16F636/639 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: * Power * Ground * Programming Voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information. RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204). A typical In-Circuit Serial Programming connection is shown in Figure 12-11.
12.16 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB(R) ICD 2 development with a 14-pin device is not practical. A special 20-pin PIC16F636 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. Use of the ICD device requires the purchase of a special header. On the top of the header is an MPLAB ICD 2 connector. On the bottom of the header is a 14-pin socket that plugs into the user's target via the 14-pin stand-off connector. When the ICD pin on the PIC16F636 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger:
TABLE 12-9:
Resource I/O pins Stack
DEBUGGER RESOURCES
Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh
Program Memory
For more information, see the "MPLAB(R) ICD 2 InCircuit Debugger User's Guide" (DS51331), available on Microchip's web site (www.microchip.com).
FIGURE 12-12:
20-Pin PDIP
20-PIN ICD PINOUT
FIGURE 12-11:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
In-Circuit Debug Device
NC ICDMCLR/VPP VDD RA5 RA4 RA3 RC5 RC4 RC3 ICD
1 2 20 19
PIC16F636-ICD
External Connector Signals +5V 0V VPP CLK Data I/O
3 4 5 6 7 8 9 10
18 17 16 15 14 13 12 11
*
PIC16F636 VDD VSS MCLR/VPP/RA3 RA1 RA0
ICDCLK ICDDATA VSS RA0 RA1 RA2 RC0 RC1 RC2 ENPORT
*
*
*
To Normal Connections *Isolation devices (as required).
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NOTES:
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13.0 INSTRUCTION SET SUMMARY
The PIC12F635/PIC16F636/639 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16FXXX instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended result of clearing the condition that set the GPIF flag.
TABLE 13-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 13-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
13.1
Read-Modify-Write Operations
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
k = 11-bit immediate value
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TABLE 13-2:
Mnemonic, Operands
PIC12F635/PIC16F636/639 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
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13.2
ADDLW Syntax: Operands: Operation: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) Operation: Status Affected: Description: The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
Status Affected: C, DC, Z
ADDWF Syntax: Operands: Operation: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
Status Affected: C, DC, Z
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0', the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSS Syntax: Operands: Operation: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
Status Affected: None
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Call subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits, TO and PD, are set.
Status Affected: None Description: Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `0', the result is stored back in register `f'.
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DECFSZ Syntax: Operands: Operation: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
Status Affected: None Description:
Status Affected: None Description:
GOTO Syntax: Operands: Operation:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: None Description:
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff
MOVWF
f
0 f 127
The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' = 0, destination is W register. If d = 1, the destination is file register `f' itself. d = 1 is useful to test a file register, since status flag Z is affected. 1 1
MOVF FSR, 0 W = value in FSR register Z =1
Move data from W register to register `f'. 1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Before Instruction
Words: Cycles: Example:
After Instruction
OPTION = W =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None
00 0000 0xx0 0000
MOVLW k
NOP
0 k 255
The eight-bit literal `k' is loaded into the W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A W = 0x5A
No operation. 1 1
NOP
Words: Cycles: Example:
After Instruction
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RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] None TOS PC, 1 GIE
00 0000 0000 1001
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
RETFIE
Status Affected: None Encoding: Description: Return from interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting the Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
Words: Cycles: Example:
After Interrupt
PC = GIE = TOS 1
RETLW Syntax: Operands: Operation:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC
11 01xx kkkk kkkk
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
RLF
f,d
Status Affected: None Encoding: Description: The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2
CALL TABLE ;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
Words: Cycles: Example:
The contents of register `f' are rotated one bit to the left through the CARRY flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C
TABLE
Before Instruction
= = = = = 1110 0110 0 1110 0110 1100 1100 1
After Instruction
REG1 W C
Before Instruction
W W = = 0x07 value of k8
After Instruction
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RRF Syntax: Operands: Operation: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below The contents of register `f' are rotated one bit to the right through the CARRY flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
Status Affected: C
Status Affected: C, DC, Z
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The Power-down Status bit, PD, is cleared. Time-out Status bit, TO, is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
Status Affected: Description:
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
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XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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14.0 DEVELOPMENT SUPPORT
14.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) - PICDEM MSC - microID(R) - CAN - PowerSmart(R) - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
14.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
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14.3 MPLAB C17 and MPLAB C18 C Compilers 14.6 MPLAB ASM30 Assembler, Linker and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
14.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
14.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
14.5
MPLAB C30 C Compiler
14.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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14.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 14.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode.
14.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS-232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
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14.14 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
14.17 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers.
14.15 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
14.18 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
14.19 PICDEM 4 8/14/18-Pin Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for HBridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide.
14.16 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
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14.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external onboard Flash memory. A generous prototype area is available for user hardware expansion.
14.24 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
14.25 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits.
14.21 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
14.22 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
14.23 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User's Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.
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15.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS/VSST pin ............................................................................................................ 300 mA Maximum current into VDD/VDDT pin ............................................................................................................... 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO >VDD) ....................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTC (combined) .......................................................................... 200 mA Maximum current sourced PORTA and PORTC (combined) .......................................................................... 200 mA Maximum LC Input Voltage (LCX, LCY, LCZ)(2) loaded, with device ............................................................ 10.0 VPP Maximum LC Input Voltage (LCX, LCY, LCZ)(2) unloaded, without device ................................................. 700.0 VPP Maximum Input Current (rms) into device per LC Channel(2) ........................................................................... 10 mA Human Body ESD rating ........................................................................................................................ 4000 (min.) V Machine Model ESD rating ...................................................................................................................... 400 (min.) V Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL). Power dissipation for AFE section is calculated as follows: PDIS = VDD x IACT = 3.6V x 16 A = 57.6 W Specification applies to the PIC16F639 only.
2:
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a `low' level to the MCLR pin, rather than pulling this pin directly to VSS.
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FIGURE 15-1: PIC12F635/PIC16F636 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20
FIGURE 15-2:
PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5
VDD (Volts)
4.0 3.6 3.0 2.5 2.0 0 4 10 Frequency (MHz) 20
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D001 D001C D001D D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal
Sym VDD
Characteristic Supply Voltage
2.0 3.0 4.5 1.5* --
-- -- -- -- VSS
5.5 5.5 5.5 -- --
V V V V V
FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 12.3 "Power-on Reset" for details.
D004
SVDD
VDD Rise Rate to ensure 0.05* internal Power-on Reset signal Brown-out Detect --
--
--
V/ms See Section 12.3 "Power-on Reset" for details. V
D005
VBOD
2.1
--
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
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15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Sym IDD Device Characteristics Supply Current
(1,2)
DC CHARACTERISTICS Param No. D010
Min -- -- --
Typ 9 18 35 110 190 330 220 370 600 70 140 260 180 320 580 TBD TBD TBD 340 500 800 180 320 580 2.1 2.4
Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units VDD A A A A A A A A A A A A A A A A A mA A A A A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz HFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32.768 kHz LP Oscillator mode
D011
-- -- --
D012
-- -- --
D013
-- -- --
D014
-- -- --
D015
-- -- --
D016
-- -- --
D017
-- -- --
D018
-- --
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Sym IPD Device Characteristics Power-down Base Current(4) Min -- -- -- D021 IWDT -- -- -- D022A IBOD D022B ILVD -- -- -- -- -- D023 ICMP -- -- -- D024 IVREF -- -- -- D025 IT1OSC -- -- -- Typ 0.99 1.2 2.9 0.3 1.8 8.4 58 109 TBD TBD TBD 3.3 6.1 11.5 58 85 138 4.0 4.6 6.0 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD nA nA nA A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 T1OSC Current(3) CVREF Current(3) Comparator Current(3) PLVD Current BOD Current(3) Note WDT, BOD, Comparators, VREF and T1OSC disabled WDT Current(3) DC CHARACTERISTICS Param No. D020
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 151
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Sym IDD Device Characteristics Supply Current(1,2) Min -- -- -- D011E -- -- -- D012E -- -- -- D013E -- -- -- D014E -- -- -- D015E -- -- -- D016E -- -- -- D017E -- -- -- D018E -- -- Typ 9 18 35 110 190 330 220 370 600 70 140 260 180 320 580 TBD TBD TBD 340 500 800 180 320 580 2.1 2.4 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A A A A A A A A A A mA A A A A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz IHFINTOSC FOSC = 31 kHz LFINTOSC FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32.768 kHz LP Oscillator mode
DC CHARACTERISTICS Param No. D010E
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232B-page 152
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Sym IPD Device Characteristics Power-down Base Current(4) Min -- -- -- D021 IWDT -- -- -- D022A D022B IBOD ILVD -- -- -- -- -- D023 ICMP -- -- -- D024 IVREF -- -- -- D025 IT1OSC -- -- -- Typ 0.0009 0.0012 0.0029 0.3 1.8 8.4 58 109 TBD TBD TBD 3.3 6.1 11.5 58 85 138 4.0 4.6 6.0 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 T1OSC Current(3) CVREF Current(3) Comparator Current(3) PLVD Current BOD Current(3) WDT Current(3) Note WDT, BOD, Comparators, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 153
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1)
D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B IIL D060 D060A D060B D061 D063 D070 IPUR VOL D080 D083
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V Otherwise Entire range
Input High Voltage I/O ports: with TTL buffer 2.0 (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- -- -- 50* -- -- -- -- -- -- -- 0.1 0.1 0.1 0.1 0.1 250 VDD VDD VDD VDD VDD VDD VDD 1 1 1 5 5 400* V V V V V V V A A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 5.0V, VPIN = VSS (Note 1) (Note 1) 4.5V VDD 5.5V Otherwise Entire range
with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2) I/O ports Analog inputs VREF MCLR(3) OSC1 PORTA Weak Pull-up Current Output Low Voltage I/O ports OSC2/CLKOUT (RC mode)
-- --
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.)
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 "Using the Data EEPROM" for additional information.
DS41232B-page 154
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VOH
Characteristic Output High Voltage I/O ports OSC2/CLKOUT (RC mode)
D090 D092 D100 IULP
VDD - 0.7 VDD - 0.7 --
-- -- 200
-- -- --
V V nA
IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
Ultra Low-power Wake-up Current Capacitive Loading Specs on Output Pins
D100
COSC2 OSC2 pin
--
--
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101 D120 D121
CIO ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W E/W V -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage
D120A ED
D122 D123 D124
TDEW TRETD TREF
Erase/Write cycle time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D131 D132 D133 D134
EP VPR VPEW TPEW TRETD
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
E/W E/W V V ms
-40C TA +85C +85C TA +125C VMIN = Minimum operating voltage
D130A ED
Year Provided no other specifications are violated
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 "Using the Data EEPROM" for additional information.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 155
PIC12F635/PIC16F636/639
15.5 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min 2.0 2.0 1.5* -- Typ Max Units -- -- -- VSS 3.6 3.6 -- -- V V V V Conditions FOSC 10 MHz Analog Front-End VDD voltage. Treated as VDD in this document. Device in Sleep mode See Section 12.3 "Power-on Reset" for details. Analog Front-End POR voltage.
DC CHARACTERISTICS Param No. D001 D001A D002 D003
Sym VDD VDDT VDR VPOR
Characteristic Supply Voltage Supply Voltage (AFE) RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Start Voltage (AFE) to ensure internal Poweron Reset signal
D003A
VPORT
--
--
1.8
V
D004
SVDD
VDD Rise Rate to ensure 0.05* internal Power-on Reset signal Brown-out Detect Turn-on Resistance or Modulation Transistor Digital Input Pull-Up Resistor CS, SCLK Analog Input Leakage Current LCX, LCY, LCZ LCCOM -- -- 50
--
--
V/ms See Section 12.3 "Power-on Reset" for details. V Ohm VDD = 3.0V
D005 D006 D007
VBOD RM RPU
2.1 -- 200
-- 100 300
kOhm VDD = 3.6V
D008
IAIL
-- --
-- --
1 1
A A
VDD = 3.6V, VSS VIN VDD, tested at Sleep mode
*
These parameters are characterized but not tested.
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS41232B-page 156
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.6 DC Characteristics: PIC16F639-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Supply Voltage 2.0V VDD 3.6V Conditions Sym Device Characteristics
(1,2,3)
DC CHARACTERISTICS
Param No. D010
Min
Typ
Max
Units VDD Note FOSC = 32.768 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz HFINTOSC mode FOSC = 4 MHz EXTRC mode WDT, BOD, Comparators, VREF and T1OSC disabled (excludes AFE) WDT Current(3) BOD Current(3) PLVD Current Comparator Current(3) CVREF Current(3) T1OSC Current(3) A A A A A A A A A A A A A A A A nA nA A A A A A A A A A A A
IDD
Supply Current
-- --
9 18 110 190 220 370 70 140 180 320 TBD TBD 340 500 180 320 0.99 1.2 0.3 1.8 58 TBD TBD 3.3 6.1 58 85 4.0 4.6
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0
D011
-- --
D012
-- --
D013
-- --
D014
-- --
D015
-- --
D016
-- --
D017 Power-down Base Current(4)
-- --
D020
IPD
-- --
D021
IWDT IBOD ILVD ICMP IVREF IT1OSC IACT Active Current of AFE only (receiving signal) 1 LC Input Channel Signal 3 LC Input Channel Signals Standby Current of AFE only (not receiving signal) 1 LC Input Channel Enabled 2 LC Input Channels Enabled 3 LC Input Channels Enabled Sleep Current of AFE only
-- --
D022A D022B
-- -- --
D023
-- --
D024
-- --
D025
-- --
D026
-- --
10 --
-- 16
A A
3.6 3.6
CS = VDD; Input = Continuous Wave (CW); Amplitude = 300 mVPP. All channels enabled. CS = VDD; ALERT = VDD
D027
ISTDBY
-- -- -- --
3 4 5 0.2
5 6 7 1
A A A
3.6 3.6 3.6 3.6 CS = VDD; ALERT = VDD
D028 Legend: Note 1: 2:
ISLEEP
3:
4:
TBD = To Be Determined Data in `Typ' column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 157
PIC12F635/PIC16F636/639
15.7 DC Characteristics: PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Supply Voltage 2.0V VDD 3.6V Conditions Sym Device Characteristics
(1,2)
DC CHARACTERISTICS
Param No. D010E
Min
Typ
Max
Units VDD Note A A A A A A A A A A A A A A A A nA nA A A A A A A A A A A A
IDD
Supply Current
-- --
9 18 110 190 220 370 70 140 180 320 TBD TBD 340 500 180 320 0.99 1.2 0.3 1.8 58 TBD TBD 3.3 6.1 58 85 4.0 4.6
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 CS = VDD; Input = Continuous Wave (CW); Amplitude = 300 mVPP. All channels enabled. CS = VDD; ALERT = VDD T1OSC Current(3) CVREF Current(3) Comparator Current(3) BOD Current(3) PLVD Current WDT, BOD, Comparators, VREF and T1OSC disabled (excludes AFE) WDT Current(3)
D011E
-- --
D012E
-- --
D013E
-- --
D014E
-- --
D015E
-- --
D016E
-- --
D017E Power-down Base Current(4)
-- --
D020
IPD IWDT IBOD ILVD ICMP IVREF IT1OSC IACT
-- --
D021
-- --
D022A D022B
-- -- --
D023
-- --
D024
-- --
D025
-- --
D026
Active Current of AFE only (receiving signal) 1 LC Input Channel Signal 3 LC Input Channel Signals Standby Current of AFE only (not receiving signal) 1 LC Input Channel Enabled 2 LC Input Channels Enabled 3 LC Input Channels Enabled Sleep Current of AFE only
-- --
10 --
-- 16
A A
3.6 3.6
D027
ISTDBY
-- -- -- --
3 4 5 0.2
5 6 7 1
A A A
3.6 3.6 3.6 3.6 CS = VDD; ALERT = VDD
D028 Legend: Note
ISLEEP 1: 2: 3:
4:
TBD = To Be Determined Data in `Typ' column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232B-page 158
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.8 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Supply Voltage 2.0V VDD 3.6V Characteristic Input Low Voltage I/O ports: D030 D030A D031 D032 D033 D033A D034 VIH with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1) Digital Input Low Voltage Input High Voltage I/O ports: D040 D040A D041 D042 D043 D043A D043B with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Digital Input High Voltage D044 IIL D060 D060A D060B D061 D063 SCLK, CS, SDIO for Analog Front-End (AFE) Input Leakage Current(2) I/O ports Analog inputs VREF MCLR(3) OSC1 Digital Input Leakage Current(2) D064 D064A D070 IPUR VOL D080 D083 SDI for Analog Front-End (AFE) SCLK, CS for Analog Front-End (AFE) PORTA Weak Pull-up Current Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) Digital Output Low Voltage D084 * 1: 2: 3: 4: ALERT, LFDATA/SDIO for Analog Front-End (AFE) -- -- VSS + 0.4 V -- -- -- -- 0.6 0.6 V V IOL = 8.5 mA, VDD = 3.6V (Ind.) IOL = 1.6 mA, VDD = 3.6V (Ind.) IOL = 1.2 mA, VDD = 3.6V (Ext.) Analog Front-End section IOL = 1.0 mA, VDD = 2.0V -- -- 50* -- -- 250 1 1 400* A A A -- -- -- -- -- 0.1 0.1 0.1 0.1 0.1 1 1 1 5 5 A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 3.6V, Analog Front-End section VSS VPIN VDD VPIN VDD VDD = 3.6V, VPIN = VSS 0.7 VDD -- VDD V with TTL buffer (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD V V V V V V Analog Front-End section (Note 1) (Note 1) with TTL buffer VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD 0.3 VDD V V V V V V Analog Front-End section Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Sym VIL
Note
These parameters are characterized but not tested. Data in `Typ' column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.4.1 "Using the Data EEPROM" for additional information
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 159
PIC12F635/PIC16F636/639
15.8 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Supply Voltage 2.0V VDD 3.6V Characteristic Output High Voltage I/O ports OSC2/CLKOUT (RC mode) Digital Output High Voltage D093 LFDATA/SDIO for Analog Front-End (AFE) Capacitive Loading Specs on Output Pins D100 D101 D102 COSC2 CIO IULP OSC2 pin All I/O pins Ultra Low-power Wake-up Current Data EEPROM Memory D120 D120A D121 D122 D123 D124 ED ED VDRW TDEW TRETD TREF Byte Endurance Byte Endurance VDD for Read/Write Erase/Write cycle time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory D130 D130A D131 D132 D133 D134 EP ED VPR VPEW TPEW TRETD * 1: 2: 3: 4: Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention 10K 1K VMIN 4.5 -- 40 100K 10K -- -- 2 -- -- -- 5.5 5.5 2.5 -- E/W E/W V V ms Year Provided no other specifications are violated -40C TA +85C +85C TA +125C VMIN = Minimum operating voltage 100K 10K VMIN -- 40 1M 1M 100K -- 5 -- 10M -- -- 5.5 6 -- -- E/W E/W V ms Year E/W Provided no other specifications are violated -40C TA +85C -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage -- -- -- -- -- 200 15* 50* -- pF pF nA In XT, HS and LP modes when external clock is used to drive OSC1 VDD - 0.5 -- -- V VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -3.0 mA, VDD = 3.6V (Ind.) IOH = -1.3 mA, VDD = 3.6V (Ind.) IOH = -1.0 mA, VDD = 3.6V (Ext.) Analog Front-End (AFE) section IOH = -400 A, VDD = 2.0V Min Typ Max Units Conditions DC CHARACTERISTICS
Param No.
Sym VOH
D090 D092
Note
These parameters are characterized but not tested. Data in `Typ' column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.4.1 "Using the Data EEPROM" for additional information
DS41232B-page 160
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.9 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCLK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 15-3:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
pin VSS Legend: RL = 464
CL
pin VSS
CL
CL = 50 pF for all pins 15 pF for OSC2 output
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 161
PIC12F635/PIC16F636/639
15.10 AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended)
FIGURE 15-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 15-1:
Param No. Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min DC DC DC DC Oscillator Frequency(1) 5 -- DC 0.1 1 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- 125 -- -- -- TCY -- -- -- -- -- -- Max 37 4 20 20 37 -- 4 4 20 -- -- -- -- 200 -- -- 10,000 1,000 DC -- -- -- 50* 25* 15* Units kHz Conditions LP Oscillator mode
MHz XT Oscillator mode MHz HS Oscillator mode MHz EC Oscillator mode kHz LP Oscillator mode MHz HFINTOSC Oscillator mode MHz RC Oscillator mode MHz XT Oscillator mode MHz HS Oscillator mode s ns ns ns s ns ns ns ns ns s ns ns ns ns ns LP Oscillator mode HS Oscillator mode EC Oscillator mode XT Oscillator mode LP Oscillator mode INTOSC Oscillator mode RC Oscillator mode XT Oscillator mode HS Oscillator mode TCY = 4/FOSC LP oscillator, TOSC L/H duty cycle HS oscillator, TOSC L/H duty cycle XT oscillator, TOSC L/H duty cycle LP oscillator XT oscillator HS oscillator
1
TOSC
External CLKIN Period(1)
27 50 50 250
Oscillator Period
(1)
27 -- 250 250 50
2 3
TCY TosL, TosH
Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low
200 2* 20* 100* -- -- --
4
TosR, TosF
External CLKIN Rise External CLKIN Fall
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices.
DS41232B-page 162
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 15-2:
Param No. F10 Sym FOSC
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic Internal Calibrated INTOSC Frequency(1) HFINTOSC Freq Min Tolerance 1% 2% 5% -- -- -- Typ 8.00 8.00 8.00 Max TBD TBD TBD Units Conditions
MHz VDD and Temperature (TBD) MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.) s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
F14
TIOSCST Oscillator Wake-up from Sleep Start-up Time*
-- -- --
-- -- --
TBD TBD TBD
TBD TBD TBD
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 15-5:
CLKOUT AND I/O TIMING
Q4 Q1 Q2 11 22 23 13 14 19 18 12 16 Q3
OSC1 10 CLKOUT
I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 163
PIC12F635/PIC16F636/639
TABLE 15-3:
Param No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT Rise Time CLKOUT Fall Time CLKOUT to Port Out Valid Port In Valid before CLKOUT Port In Hold after CLKOUT OSC1 (Q1 cycle) to Port Out Valid OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) Port Input Valid to OSC1 (I/O in setup time) Port Output Rise Time Port Output Fall Time INT pin High or Low Time PORTA Change INT High or Low Time Min -- -- -- -- -- TOSC + 200 ns 0 -- -- 100 0 -- -- 25 TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 10 -- -- Max 200 200 100 100 20 -- -- 150* 300 -- -- 40 40 -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
Sym TOSH2CKL TOSH2CKH TCKR TCKF TCKL2IOV TIOV2CKH TCKH2IOI TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF TINP TRBP
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
FIGURE 15-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins 32 30
31 34
DS41232B-page 164
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(c) 2005 Microchip Technology Inc.
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FIGURE 15-7: BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD VBOD (Device in Brown-out Detect) (Device not in Brown-out Detect)
35
Reset (due to BOD)
64 ms Time-out(1)
Note 1:
64 ms delay only if PWRTE bit in Configuration Word register is programmed to `0'.
TABLE 15-4:
Param No. 30 31 32 33* 34 35 36
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT DETECT REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Detect Voltage Brown-out Detect Pulse Width Min 2 11 10 10 -- 28* TBD -- 2.025 100* Typ -- 18 17 17 1024 TOSC 64 TBD -- -- -- Max -- 24 25 30 -- 132* TBD 2.0 2.175 -- Units s ms ms ms -- ms ms s V s VDD VBOD (D005) Conditions VDD = 5.0V, -40C to +85C Extended temperature VDD = 5.0V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5.0V, -40C to +85C Extended Temperature
Sym TMCL TWDT TOST TPWRT TIOZ VBOD TBOD
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 165
PIC12F635/PIC16F636/639
FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 48
TMR0 or TMR1
TABLE 15-5:
Param No. 40* 41* 42* Sym TT0H TT0L TT0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC 2 TOSC* Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4,..., 256) Conditions
45*
TT1H
T1CKI High Time
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
47*
TT1P
T1CKI Input Period
Synchronous
Asynchronous 48 49 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
-- -- --
-- 200* 7 TOSC*
ns kHz --
TCKEZTMR1 Delay from External Clock Edge to Timer increment *
These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41232B-page 166
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 15-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Sym VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Min -- 0 +55* -- -- Typ 5.0 -- -- 150 -- Max 10 VDD - 1.5 -- 400* 10* Units mV V db ns s Comments
TMC2COV Comparator Mode Change to Output Valid * Note 1:
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V.
TABLE 15-7:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Sym. Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) * Note 1: Min -- -- -- -- -- -- Typ VDD/24* VDD/32 -- -- 2K* -- Max -- -- 1/4* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low range (VRR = 1) High range (VRR = 0) Low range (VRR = 1) High range (VRR = 0)
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111`.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 167
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial -40C TAMB +125C for extended LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic LC Input Sensitivity 1 3.0 6 mVPP Min Typ Max Units Conditions VDD = 3.0V Output enable filter disabled AGCSIG = 0; MODMIN = 00 (50% modulation depth setting) Input = Continuous Wave (CW) Output = Logic level transition from low-tohigh at sensitivity level for CW input. VDD = 3.0V, Force IIN = 5 A VDD = 2.0V, VIN = 8 VDC VDD = 3.0V No sensitivity reduction selected Max reduction selected Monotonic increment in attenuation value from setting = 0000 to 1111 by design VDD = 3.0V 63 38 13 0 -- 44.1 75 50 25 12 0 63 87 62 37 24 -- 81.9 % % % % pF pF VDD = 3.0V, Config. Reg. 1, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 1, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design VDD = 3.0V, Config. Reg. 2, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 2, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design Characterized at bench. Input data rate, characterized at bench.
Param No.
Sym. VSENSE
VDE_Q RFLM SADJ
Coil de-Q'ing Voltage RF Limiter (RFLM) must be active RF Limiter Turn-on Resistance (LCX, LCY, LCZ) Sensitivity Reduction
3 --
-- --
5 700
V Ohm
-- --
0 -30
-- --
dB dB
VIN_MOD
Minimum Modulation Depth 75% 12% 50% 12% 25% 12% 12% 12% LCX Tuning Capacitor
CTUNX
CTUNY
LCY Tuning Capacitor -- 44.1 0 63 -- 81.9 pF pF
FCARRIER Carrier frequency FMOD * Note 1: 2: Input modulation frequency
-- --
125 --
-- 4
kHz kHz
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
DS41232B-page 168
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial -40C TAMB +125C for extended LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic LCZ Tuning Capacitor -- 44.1 0 63 -- 81.9 pF pF Min Typ Max Units Conditions VDD = 3.0V, Config. Reg. 3, bits<6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 3, bits<6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design Characterized at bench test VDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80% VDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80% VDD = 3.0V Time is measured from 10% to 90% of amplitude VDD = 3.0V Time is measured from 10% to 90% of amplitude Time required for AGC stabilization Equivalent to two Internal clock cycle (FOSC) AGC stabilization time
Param No.
Sym. CTUNZ
C_Q TDR
Q of Trimming Capacitors Demodulator Charge Time (delay time of demodulated output to rise)
50* --
-- 50
-- --
pF s
TDF
Demodulator Discharge Time (delay time of demodulated output to fall)
--
50
--
s
TLFDATAR Rise time of LFDATA
--
0.5
--
s
TLFDATAF Fall time of LFDATA
--
0.5
--
s
TAGC TPAGC TSTAB
AGC stabilization time High time after AGC settling time AGC stabilization time plus high time (after AGC settling time) (TAGC + TPAGC) Gap time after AGC settling time Time from exiting Sleep or POR to being ready to receive signal Minimum time AGC level must be held after receiving AGC Preserve command Internal RC oscillator frequency (10%) Inactivity timer time-out Alarm timer time-out LC Pin Input Impedance LCX, LCY, LCZ
-- -- 4
3.5* 62.5 --
-- -- --
ms s ms
TGAP TRDY TPRES
200 -- 5*
-- -- --
-- 50* --
s ms ms
Typically 1 TE
AGC level must not change more than 10% during TPRES. Internal clock trimmed at 32 kHz during test 512 cycles of RC oscillator @ FOSC 1024 cycles of RC oscillator @ FOSC
FOSC TINACT TALARM RLC * Note 1: 2:
28.8 14.4 28.8 --
32 16 32 1*
35.2 17.6 35.2 --
kHz ms ms
MOhm Device in Standby mode
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 169
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial -40C TAMB +125C for extended LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic Time element of pulse Minimum output enable filter high time OEH (Bits Config0<7:6>) 01 = 1 ms 10 = 2 ms 11 = 4 ms 00 = Filter Disabled Minimum output enable filter low time OEL (Bits Config0<5:4>) 00 = 1 ms 01 = 1 ms 10 = 2 ms 11 = 4 ms Maximum output enable filter period OEH 01 01 01 01 10 10 10 10 11 11 11 11 00 IRSSI OEL 00 01 10 11 00 01 10 11 00 01 10 11 XX TOEH 1 ms 1 ms 1 ms 1 ms 2 ms 2 ms 2 ms 2 ms 4 ms 4 ms 4 ms 4 ms TOEL 1 ms 1 ms 2 ms 4 ms 1 ms 1 ms 2 ms 4 ms 1 ms 1 ms 2 ms 4 ms Min 200 Typ -- Max -- Units s RC oscillator = FOSC Viewed from the pin input: (Note 1) 32 (~1ms) 64 (~2ms) 128 (~ms) -- -- -- -- -- -- -- -- -- clock count Conditions
Param No.
Sym. TE TOEH
TOEL
32 (~1ms) 32 (~1ms) 64 (~2ms) 128 (~4ms)
-- -- -- --
-- -- -- --
clock count
RC oscillator = FOSC Viewed from the pin input: (Note 2)
TOET
RC oscillator = FOSC
= = = = = = = = = = = =
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- 100
96 (~3ms) 96 (~3ms) 128 (~4ms) 192 (~6ms) 128 (~4ms) 128 (~4ms) 160 (~5ms) 250 (~8ms) 192 (~6ms) 192 (~6ms) 256 (~8ms) 320 (~10ms) -- --
clock count
= Filter Disabled
LFDATA output appears as long as input signal level is greater than VSENSE. A VDD = 3.0V, VIN = 0 to 4 VPP Linearly increases with input signal amplitude. Tested at VIN = 40 mVPP, 400 mVPP, and 4 VPP VIN = 40 mVPP VIN = 400 mVPP VIN = 4 VPP
RSSI current output
-- -- -- IRSSILR * Note 1: 2: RSSI current linearity --
1 10 100 TBD
-- -- -- --
A A A --
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
DS41232B-page 170
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.12 SPI Timing: Analog Front-End (AFE) for PIC16F639
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial -40C TAMB +125C for extended LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic SCLK Frequency CS fall to first SCLK edge setup time SDI setup time SDI hold time SCLK high time SCLK low time SDO setup time SCLK last edge to CS rise setup time CS high time CS rise to SCLK edge setup time SCLK edge to CS fall setup time Rise time of SPI data (SPI Read command) Fall time of SPI data (SPI Read command) Min -- 100 30 50 150 150 -- 100 500 50 50 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- 10 10 Max 3 -- -- -- -- -- 150 -- -- -- -- -- -- Units MHz ns ns ns ns ns ns ns ns ns ns ns ns SCLK edge when CS is high VDD = 3.0V. Time is measured from 10% to 90% of amplitude VDD = 3.0V. Time is measured from 90% to 10% of amplitude Conditions
Param
Sym FSCLK Tcssc TSU THD THI TLO TDO TSCCS TCSH TCS1 TCS0 TSPIR TSPIF
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF 2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
*
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 171
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 172
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs and Tables are not available at this time.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 173
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 174
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
17.0
17.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP XXXXXXXX XXXXXNNN YYWW Example 12F635/P 017 0510
8-Lead SOIC XXXXXXXX XXXXYYWW NNN
Example 12F635 /SN0510 017
8-Lead DFN-S XXXXXX XXXXXX YYWW NNN
Example PIC12F 635/MF 0510 017
14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example PIC16F636-I/P 0510017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 175
PIC12F635/PIC16F636/639
17.1 Package Marking Information (Continued)
14-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16F636 -I/SL 0510017
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
F636/ST 0510 017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F639 -I/SS 0510017
DS41232B-page 176
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
17.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
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Preliminary
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PIC12F635/PIC16F636/639
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
DS41232B-page 178
Preliminary
(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) - Saw Singulated
(c) 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 179
PIC12F635/PIC16F636/639
14-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP)
E1
D
2 n 1
E A A2
c eB A1 B1 B p
L
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 5 10 15 Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
14-Lead Plastic Small Outline (SL) - Narrow, 150 mil Body (SOIC)
E E1
p
D
2 B n 1 h 45 c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
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14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body (TSSOP)
E E1 p
D
2 n B 1
A c
L A1 A2
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5
MAX
MIN
.033 .002 .246 .169 .193 .020 0 .004 .007 0 0
.043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10
MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
20-Lead Plastic Shrink Small Outline (SS) - 209 mil Body, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
f L A1
Number of Pins Pitch Overall Height A .079 Molded Package Thickness A2 .065 .073 Standoff A1 .002 Overall Width E .291 .323 Molded Package Width E1 .197 .220 Overall Length D .272 .289 Foot Length L .022 .037 c Lead Thickness .004 .010 f Foot Angle 0 8 Lead Width B .009 .015 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150
Drawing No. C04-072
Units Dimension Limits n p
MIN
INCHES NOM 20 .026 .069 .307 .209 .283 .030 4 -
MAX
MIN
MILLIMETERS* NOM 20 0.65 1.65 1.75 0.05 7.40 7.80 5.00 5.30 .295 7.20 0.55 0.75 0.09 0 4 0.22 -
MAX
2.00 1.85 8.20 5.60 7.50 0.95 0.25 8 0.38
Revised 11/03/03
(c) 2005 Microchip Technology Inc.
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NOTES:
DS41232B-page 184
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com In addition, there is a Development Systems Information Line which lists the latest versions of Microchip's development systems software products. This line also provides information on how customers can receive currently available upgrade kits. The Development numbers are: Systems Information Line
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
1-800-755-2345 - United States and most of Canada 1-480-792-7302 - Other International Locations
(c) 2005 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41232B FAX: (______) _________ - _________
Device: PIC12F635/PIC16F636/639 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41232B-page 186
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
Revision B
Added PIC16F639 to the data sheet.
(c) 2005 Microchip Technology Inc.
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NOTES:
DS41232B-page 188
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
INDEX
A
Absolute Maximum Ratings .............................................. 147 AC Characteristics Analog Front-End (AFE) for PIC16F639 ................... 168 Industrial and Extended ............................................ 162 Load Conditions ........................................................ 161 AGC Settling ....................................................................... 81 Analog Front-End Configuration Registers Summary Table ................................................ 105 Analog Front-End (AFE) ..................................................... 79 A/D Data Conversion of RSSI Signal........................ 100 AFE Status Register Bit Condition ............................ 110 AGC ................................................................ 80, 81, 88 AGC Preserve............................................................. 88 Battery Back-up and Batteryless Operation................ 92 Block Diagrams Bidirectional PKE System Application Example...................................................... 84 Functional ........................................................... 82 LC Input Path ...................................................... 83 Output Enable Filter Timing ................................ 85 Output Enable Filter Timing (Detailed) ............... 86 Carrier Clock Detector ................................................ 80 Carrier Clock Output ................................................... 96 Examples ............................................................ 97 Command Decoder/Controller .................................. 103 Configuration Registers ............................................ 104 Data Slicer .................................................................. 80 Demodulator ......................................................... 80, 93 De-Q'ing of Antenna Circuit ........................................ 92 Error Detection............................................................ 91 Factory Calibration...................................................... 92 Fixed Gain Amplifiers.................................................. 80 Input Sensitivity Control .............................................. 87 LF Field Powering/Battery Back-up Examples ............................................................ 92 LFDATA Output Selection........................................... 93 Case I ................................................................. 94 Case II ................................................................ 94 Low Current Modes Operating ............................................................ 91 Sleep................................................................... 91 Standby............................................................... 91 Modulation Circuit ....................................................... 79 Modulation Depth........................................................ 89 Examples ............................................................ 90 Output Enable Filter .................................................... 80 Configurable Smart ............................................. 85 Output Enable Filter Timing (Table)............................ 87 Power-on Reset .......................................................... 93 RF Limiter ................................................................... 79 RSSI...................................................................... 80, 98 Output Path Diagram .......................................... 98 Power-up Sequence Diagram........................... 100 SPI Read Sequence Diagram........................... 102 SPI Write Sequence Diagram ........................... 101 RSSI Output Current vs. Input Signal Level Example .............................................................. 99 Sensitivity Control ....................................................... 79 Soft Reset ................................................................... 89 SPI Interface Timing Diagram................................... 104 Timers ................................................................... 80, 81 Alarm .................................................................. 81 Auto Channel Selection ...................................... 80 Inactivity ............................................................. 81 Period ................................................................. 81 Preamble Counters............................................. 81 Pulse Width ........................................................ 81 RC Oscillator ...................................................... 80 Tuning Capacitor ........................................................ 79 Variable Attenuator..................................................... 79 Analog Input Connection Considerations ........................... 62 Assembler MPASM Assembler .................................................. 141
B
Block Diagrams Analog Input Model..................................................... 62 Ceramic Resonator Operation.................................... 31 Clock Source .............................................................. 29 Comparator C1 Output ............................................... 65 Comparator C2 Output ............................................... 66 Comparator I/O Operating Modes for PIC12F635 ...... 63 Comparator I/O Operating Modes for PIC16F636/639 .................................................. 64 Comparator Voltage Reference (CVREF).................... 68 External Clock Mode .................................................. 31 Fail-Safe Clock Monitor (FSCM)................................. 36 Functional (AFE)......................................................... 82 In-Circuit Serial Programming Connection ............... 129 Interrupt Logic........................................................... 122 On-Chip Reset Circuit............................................... 113 PIC12F635 Device ....................................................... 5 PIC16F636 Device ....................................................... 6 PIC16F639 Device ....................................................... 7 Quartz Crystal Operation............................................ 31 RA0 Pin ...................................................................... 44 RA1 Pin ...................................................................... 45 RA2 Pin ...................................................................... 45 RA3 Pin ...................................................................... 46 RA4 Pin ...................................................................... 47 RA5 Pin ...................................................................... 47 RC Mode .................................................................... 32 RC0 and RC1 Pins ..................................................... 49 RC2, RC3 and RC5 Pins ............................................ 49 RC4 Pin ...................................................................... 50 RCIO Mode................................................................. 32 Recommended MCLR Circuit................................... 114 Timer1 ........................................................................ 57 TMR0/WDT Prescaler ................................................ 53 Watchdog Timer (WDT)............................................ 125 Brown-out Detect (BOD)................................................... 115 Associated Registers................................................ 116 Specifications ........................................................... 165
C
C Compilers MPLAB C17.............................................................. 142 MPLAB C18.............................................................. 142 MPLAB C30.............................................................. 142 CLKOUT and I/O Timing Requirements ........................... 164 Clock Sources..................................................................... 29 Associated Registers.................................................. 38 External Clock Modes................................................. 30 Internal Clock Modes.................................................. 32 Modes......................................................................... 30
(c) 2005 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
Oscillator Configuration............................................... 29 Clock Switching................................................................... 35 Fail-Safe Clock Monitor............................................... 36 Two-Speed Clock Start-up .......................................... 35 Code Examples Assigning Prescaler to Timer0 .................................... 55 Assigning Prescaler to WDT ....................................... 55 Data EEPROM Read .................................................. 75 Data EEPROM Write .................................................. 75 Indirect Addressing ..................................................... 27 Initializing PORTA ....................................................... 39 Initializing PORTC....................................................... 49 Saving Status and W Registers in RAM ................... 124 Ultra Low-Power Wake-up Initialization ...................... 43 Write Verify ................................................................. 75 Code Protection ................................................................ 128 Comparator Voltage Reference (CVREF) ............................ 68 Accuracy/Error ............................................................ 68 Configuring.................................................................. 68 Specifications ............................................................ 167 Comparators ....................................................................... 61 C2OUT as T1 Gate ............................................... 58, 67 Configurations ............................................................. 63 Effects of a Reset........................................................ 69 Interrupts ..................................................................... 67 Operation .................................................................... 62 Operation During Sleep .............................................. 69 Outputs ....................................................................... 67 Response Time ........................................................... 69 Specifications ............................................................ 167 Synchronizing C2OUT w/ Timer1 ............................... 67 Computed GOTO ................................................................ 26 Configuration Bits.............................................................. 112 CPU Features ................................................................... 111 Customer Change Notification Service ............................. 185 Customer Notification Service........................................... 185 Customer Support ............................................................. 185 Device Overview................................................................... 5
E
EECON1 (EEPROM Control 1) Register ............................ 74 EECON2 (EEPROM Control 2) Register ............................ 74 EEPROM Data Memory Reading ...................................................................... 75 Write Verify ................................................................. 75 Writing ........................................................................ 75 Electrical Specifications .................................................... 147 Errata .................................................................................... 3 Evaluation and Programming Tools.................................. 145 External Clock Timing Requirements ............................... 162
F
Fail-Safe Clock Monitor ...................................................... 36 Fail-Safe Condition Clearing....................................... 37 Reset and Wake-up from Sleep.................................. 37 Firmware Instructions ....................................................... 131
G
General Purpose Register (GPR) File ................................ 12
I
ID Locations...................................................................... 128 In-Circuit Debugger........................................................... 129 In-Circuit Serial Programming (ICSP)............................... 129 Indirect Addressing, INDF and FSR Registers ................... 27 Instruction Format............................................................. 131 Instruction Set................................................................... 131 ADDLW..................................................................... 133 ADDWF..................................................................... 133 ANDLW..................................................................... 133 ANDWF..................................................................... 133 BCF .......................................................................... 133 BSF........................................................................... 133 BTFSC ...................................................................... 133 BTFSS ...................................................................... 133 CALL......................................................................... 134 CLRF ........................................................................ 134 CLRW ....................................................................... 134 CLRWDT .................................................................. 134 COMF ....................................................................... 134 DECF ........................................................................ 134 DECFSZ ................................................................... 135 GOTO ....................................................................... 135 INCF ......................................................................... 135 INCFSZ..................................................................... 135 IORLW ...................................................................... 135 IORWF...................................................................... 135 MOVF ....................................................................... 136 MOVLW .................................................................... 136 MOVWF .................................................................... 136 NOP .......................................................................... 136 RETFIE ..................................................................... 137 RETLW ..................................................................... 137 RETURN................................................................... 137 RLF ........................................................................... 137 RRF .......................................................................... 138 SLEEP ...................................................................... 138 SUBLW ..................................................................... 138 SUBWF..................................................................... 138 SWAPF ..................................................................... 138 XORLW .................................................................... 138 XORWF .................................................................... 139 Summary Table ........................................................ 132
D
Data EEPROM Memory Associated Registers .................................................. 76 Code Protection .................................................... 73, 76 Endurance................................................................... 75 Protection Against Spurious Write .............................. 76 Using ........................................................................... 75 Data Memory....................................................................... 11 DC and AC Characteristics Graphs and Tables........................... 173 DC Characteristics Extended (PIC12F635/PIC16F636) .......................... 152 Extended (PIC16F639) ............................................. 158 Industrial (PIC12F635/PIC16F636)........................... 150 Industrial (PIC16F639) .............................................. 157 Industrial/Extended (PIC12F635/PIC16F636) .. 149, 154 Industrial/Extended (PIC16F639)...................... 156, 159 Demonstration Boards PICDEM 1 ................................................................. 144 PICDEM 17 ............................................................... 145 PICDEM 18R ............................................................ 145 PICDEM 2 Plus ......................................................... 144 PICDEM 3 ................................................................. 144 PICDEM 4 ................................................................. 144 PICDEM LIN ............................................................. 145 PICDEM USB............................................................ 145 PICDEM.net Internet/Ethernet .................................. 144 Development Support ....................................................... 141
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(c) 2005 Microchip Technology Inc.
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Internal Oscillator Block INTOSC Specifications ............................................. 163 Internet Address................................................................ 185 Interrupts ........................................................................... 121 Associated Registers ................................................ 123 Comparators ............................................................... 67 Context Saving.......................................................... 124 Data EEPROM Memory Write .................................... 74 Interrupt-on-change .................................................... 42 PORTA Interrupt-on-change ..................................... 122 RA2/INT .................................................................... 121 TMR0 ........................................................................ 122 INTOSC Specifications ..................................................... 163 RA1/C1IN-/Vref/ICSPCLK Pin .................................... 45 RA2/T0CKI/INT/C1OUT Pin ....................................... 45 RA3/MCLR/VPP PIN .................................................... 46 RA4/T1G/OSC2/CLKOUT Pin .................................... 47 RA5/T1CKI/OSC1/CLKIN Pin..................................... 47 PORTC ............................................................................... 49 Associated Registers.................................................. 51 RC0/C2IN+ Pin ........................................................... 49 RC2 Pin ...................................................................... 49 RC3 Pin ...................................................................... 49 RC4/C2OUT Pin ......................................................... 50 Power Control (PCON) Register....................................... 116 Power-Down Mode (Sleep)............................................... 127 Power-on Reset ................................................................ 114 Power-up Timer (PWRT) Specifications ........................................................... 165 Precision Internal Oscillator Parameters .......................... 163 Prescaler Shared WDT/Timer0................................................... 55 Switching Prescaler Assignment ................................ 55 PRO MATE II Universal Device Programmer ................... 143 Product Identification ........................................................ 193 Program Memory ................................................................ 11 Program Memory Map and Stack PIC12F635 ................................................................. 11 PIC16F636/639 .......................................................... 11 Programmable Low-Voltage Detect (PLVD) Module .......... 71 Programming, Device Instructions.................................... 131
K
KEELOQ ............................................................................... 77
L
Load Conditions ................................................................ 161
M
MCLR ................................................................................ 114 Internal ...................................................................... 114 Memory Organization.......................................................... 11 Data ............................................................................ 11 Data EEPROM Memory.............................................. 73 Program ...................................................................... 11 Microchip Internet Web Site .............................................. 185 MPLAB ASM30 Assembler, Linker, Librarian ................... 142 MPLAB ICD 2 In-Circuit Debugger ................................... 143 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................................... 143 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ................................................... 143 MPLAB Integrated Development Environment Software .. 141 MPLAB PM3 Device Programmer .................................... 143 MPLINK Object Linker/MPLIB Object Librarian ................ 142
R
Reader Response............................................................. 186 Read-Modify-Write Operations ......................................... 131 Registers Analog Front-End (AFE) AFE Status Register 7 ...................................... 109 Column Parity Register 6.................................. 108 Configuration Register 0................................... 105 Configuration Register 1................................... 106 Configuration Register 2................................... 106 Configuration Register 3................................... 107 Configuration Register 4................................... 107 Configuration Register 5................................... 108 CMCON0 (Comparator Control 0) .............................. 61 CMCON1 (Comparator Control 1) .............................. 66 CONFIG (Configuration Word) ................................. 112 EEADR (EEPROM Address) ...................................... 73 EECON1 (EEPROM Control 1) .................................. 74 EEDAT (EEPROM Data) ............................................ 73 INTCON (Interrupt Control) ........................................ 22 IOCA (Interrupt-on-change PORTA) .......................... 42 LVDCON (Low-Voltage Detect Control) ..................... 71 OPTION_REG (Option) ........................................ 21, 54 OSCCON (Oscillator Control)..................................... 38 OSCTUNE (Oscillator Tuning).................................... 33 PCON (Power Control) ............................................... 25 PIE1 (Peripheral Interrupt Enable 1) .......................... 23 PIR1 (Peripheral Interrupt Request 1) ........................ 24 PORTA ....................................................................... 41 PORTC ....................................................................... 51 Reset Values ............................................................ 119 Reset Values (Special Registers)............................. 120 Status ......................................................................... 20 T1CON (Timer1 Control) ............................................ 59 TRISA (PORTA Tri-State) .......................................... 41 TRISC (PORTC Tri-State) .......................................... 51 VRCON (Voltage Reference Control) ......................... 69
O
Opcode Field Descriptions ................................................ 131 Oscillator Start-up Timer (OST) .......................................... 30 Specifications............................................................ 165
P
Packaging ......................................................................... 175 Details ....................................................................... 177 Marking ..................................................................... 175 PCL and PCLATH ............................................................... 26 Computed GOTO........................................................ 26 Stack ........................................................................... 26 PICkit 1 Flash Starter Kit................................................... 145 PICSTART Plus Development Programmer ..................... 144 Pin Diagrams ........................................................................ 2 Pinout Descriptions PIC12F635.................................................................... 8 PIC16F636.................................................................... 9 PIC16F639.................................................................. 10 PORTA................................................................................ 39 Additional Pin Functions ............................................. 39 Interrupt-on-change ............................................ 42 Ultra Low-Power Wake-up ............................ 39, 43 Weak Pull-down .................................................. 39 Weak Pull-up ...................................................... 39 Associated Registers .................................................. 48 Pin Descriptions and Diagrams................................... 44 RA0/C1IN+/ICSPDAT/ULPWU Pin ............................. 44
(c) 2005 Microchip Technology Inc.
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WDA (Weak Pull-up/Pull-down PORTA)..................... 40 WDTCON (Watchdog Timer Control)........................ 126 WPUDA (Weak Pull-up/Pull-down Direction PORTA). 40 Reset................................................................................. 113 Revision History ................................................................ 187 Timing Parameter Symbology .......................................... 161 TRISA ................................................................................. 39 Two-Speed Clock Start-up Mode........................................ 35
U
Ultra Low-Power Wake-up.................................. 9, 10, 39, 43
S
Software Simulator (MPLAB SIM)..................................... 142 Software Simulator (MPLAB SIM30)................................. 142 Special Function Registers (SFR)....................................... 12 Maps PIC12F635.......................................................... 13 PIC16F636/639................................................... 14 Summary PIC12F635, Bank 0............................................. 15 PIC12F635, Bank 1............................................. 16 PIC12F635/PIC16F636/639, Bank 2 .................. 19 PIC16F636/639, Bank 0...................................... 17 PIC16F636/639, Bank 1...................................... 18 SPI Timing Analog Front-End (AFE) for PIC16F639 ................... 171 Status Register IRP Bit ......................................................................... 20 RP Bits ........................................................................ 20
V
Voltage Reference. See Comparator Voltage Reference (CVREF).
W
Wake-up from Sleep ......................................................... 127 Wake-up Reset (WUR) ..................................................... 114 Wake-up using Interrupts.................................................. 127 Watchdog Timer (WDT).................................................... 125 Associated Registers ................................................ 126 Control ...................................................................... 125 Oscillator................................................................... 125 Specifications ........................................................... 165 WWW Address ................................................................. 185 WWW, On-Line Support ....................................................... 3
T
Time-out Sequence........................................................... 116 Timer0 ................................................................................. 53 Associated Registers .................................................. 55 Interrupt....................................................................... 53 Operation .................................................................... 53 T0CKI .......................................................................... 54 Using with External Clock ........................................... 54 Timer0 and Timer1 External Clock Requirements ................................... 166 Timer1 ................................................................................. 57 Associated Registers .................................................. 60 Asynchronous Counter Mode ..................................... 60 Reading and Writing ........................................... 60 Interrupt....................................................................... 58 Modes of Operations................................................... 58 Operation During Sleep .............................................. 60 Oscillator ..................................................................... 60 Prescaler ..................................................................... 58 Timer1 Gate Inverting Gate ..................................................... 58 Selecting Source........................................... 58, 67 Synchronizing C2OUT w/ Timer1 ....................... 67 TMR1H Register ......................................................... 57 TMR1L Register .......................................................... 57 Timing Diagrams Brown-out Detect (BOD) ........................................... 165 Brown-out Detect Situations ..................................... 115 CLKOUT and I/O....................................................... 163 External Clock ........................................................... 162 Fail-Safe Clock Monitor (FSCM) ................................. 37 INT Pin Interrupt........................................................ 123 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ................................................ 164 Single Comparator ...................................................... 62 Time-out Sequence on Power-up (Delayed MCLR) . 118 Time-out Sequence on Power-up (MCLR with VDD). 118 Timer0 and Timer1 External Clock ........................... 166 Timer1 Incrementing Edge.......................................... 58 Two-Speed Start-up .................................................... 36 Wake-up from Sleep through Interrupt...................... 128
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(c) 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC12F635: Standard VDD range PIC12F635T: (Tape and Reel) PIC16F636: Standard VDD range PIC16F636T: (Tape and Reel) PIC16F639: Standard VDD range PIC16F639T: (Tape and Reel) PIC12F635-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC12F635-I/S = Industrial Temp., SOIC package, 20 MHz
Temperature Range
I E
= =
-40C to +85C -40C to +125C
Package
MF P SN SL SS ST
= = = = = =
DFN-S (6x5 mm, 8-pin) PDIP (300 mil) SOIC (Gull wing, 150 mil body, 8-pin) SOIC (Gull wing, 150 mil body, 14-pin) SSOP (209 mil, 20-pin) TSSOP (4.4 mm, 14-pin)
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
(c) 2005 Microchip Technology Inc.
Preliminary
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http:\\support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205
ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459
EUROPE
Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/20/04
DS41232B-page 194
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Price & Availability of PIC12F635EMF

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