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64Mx64 bits Unbuffered DDR SDRAM DIMM HYMD564646B(L)8J-D43/J DESCRIPTION Hynix HYMD564646B(L)8J-D43/J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 64M x 64 high-speed memory arrays. Hynix HYMD564646B(L)8J-D43/J series consists of eight 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD564646B(L)8J-D43/J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD564646B(L)8J-D43/J series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD564646B(L)8J-D43/J series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES * * * 512MB (64M x 64) Unbuffered DDR DIMM based on 64M x 8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) 2.6V +/- 0.1V VDD and VDDQ Power supply for DDR400, 2.5V +/- 0.2V VDD and VDDQ for DDR333 supported All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 166/200MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock * * * * * * * * * Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 3 for DDR400, 2.5 for DDR333 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms * * * ORDERING INFORMATION Part No. HYMD564646B(L)8J-D43 HYMD564646B(L)8J-J Power Supply VDD=2.6V,VDDQ=2.6V VDD=2.5V,VDDQ=2.5V Clock Frequency 200MHz (*DDR400 3-3-3) Interface SSTL_2 Form Factor 184pin Unbuffered DIMM 5.25 x 1.25 x 0.15 inch 166MHz (*DDR333) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/May 2004 1 HYMD564646B(L)8J-D43/J PIN DESCRIPTION Pin CK0,/CK0,CK1,/CK1,CK2,/CK2 CS0 CKE0 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0* CB1* VDD DQS8* A0 CB2* VSS CB3* BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Name VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1* VDDQ BA2* DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 key VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Name VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0 /CK0 VSS DM8* A10 CB6* VDDQ CB7* Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name /RAS DQ45 VDDQ /CS0 /CS1* DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD * These are not used on this module but may be used for other module in 184pin DIMM family Rev. 0.1/May 2004 2 HYMD564646B(L)8J-D43/J FUNCTIONAL BLOCK DIAGRAM /C S 0 DQS0 D M 0 /D Q S 9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 /C S DQS DQS4 D M 4 /D Q S 1 3 D Q 32 D Q 33 D Q 34 D Q 35 D Q 36 D Q 37 D Q 38 D Q 39 DM I/O 0 I/O 1 I/O 2 /C S DQS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS1 D M 1 /D Q S 1 0 DQ8 DQ9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15 DM I/O 0 I/O 1 I/O 2 /C S DQS DQS5 D M 5 /D Q S 1 4 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 D Q 47 DM I/O 0 I/O 1 I/O 2 /C S DQS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DQS2 D M 2 /D Q S 1 1 DQS6 D M 6 /D Q S 1 5 DM I/O 0 I/O 1 I/O 2 /C S DQS D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23 DQS3 D M 3 /D Q S 1 2 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 S e ria l P D SCL I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 D Q 48 D Q 49 D Q 50 D Q 51 D Q 52 D Q 53 D Q 54 D Q 55 DM I/O 0 I/O 1 I/O 2 /C S DQS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS7 D M 7 /D Q S 1 6 DM I/O 0 I/O 1 I/O 2 /C S DQS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63 VDD SPD SPD D O -D 8 D O -D 8 D O -D 8 S tra p :s e e N o te 4 DM I/O 0 I/O 1 I/O 2 /C S DQS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 *C lo c k W irin g SDA W P V D D /V D D Q VREF C lo c k In p u t SDRAMs A0 A1 A2 VSS V D D ID N o te s : *C K 0 , /C K 0 *C K 1 , /C K 1 *C K 2 , /C K 2 2 SDRAMs 3 SDRAMs 3 SDRAMs SA0 SA1 SA2 *W ire p e r C lo c k L o a d in g T a b le /W irin g D ia g ra m s B A 0 -B A 1 A 0 -A 1 3 /R A S /C A S CKE0 /W E B A 0 -B A 1 : S D R A M s D 0 -D 7 A 0 -A 1 3 : S D R A M s D 0 -D 7 /R A S : S D R A M s D 0 -D 7 /C A S : S D R A M s D 0 -D 7 C K E : S D R A M s D 0 -D 7 /W E : S D R A M s D 0 -D 7 1 . D Q -to -I/O w irin g is s h o w n a s re c o m m e n d e d b u t m ay be changed. 2 . D Q /D Q S /D M /C K E /S re la tio n s h ip s m u s t b e m a in ta in e d a s s h o w n . 3 . D Q , D Q S , D M /D Q S re s is to rs : 2 2 O h m s + - 5 % . 4 . V D D ID s tra p c o n n e c tio n s (fo r m e m o ry d e v ic e V D D , V D D Q ): S T R A P O U T (O P E N ) : V D D = V D D Q S T R A P IN (V S S ) : V D D V D D Q 5 . B A x , A x , R A S , C A S , W E re s is to rs : 5 .1 O h m s + - 5 % Rev. 0.1/May 2004 3 HYMD564646B(L)8J-D43/J ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on Inputs relative to VSS Voltage on I/O Pins relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature / Time TA TSTG VIN VIO VDD VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1.0 x # of Components 260 / 10 Rating o o Unit C C V V V V mA W o C / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Power Supply Voltage Power Supply Voltage Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage VDD VDD VDDQ VDDQ VIH VIL VTT VREF Symbol Min 2.3 2.5 2.3 2.5 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ Typ. 2.5 2.6 2.5 2.6 VREF 0.5*VDDQ Max 2.7 2.7 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ Unit V V V V V V V V 3 2 4 1 1,4 Note Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. 4. For DDR400, VDD=2.6V +/- 0.1V, VDDQ=2.6V+/-0.1V Rev. 0.1/May 2004 4 HYMD564646B(L)8J-D43/J AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF Rev. 0.1/May 2004 5 HYMD564646B(L)8J-D43/J CAPACITANCE (TA=25oC, f=100MHz ) Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0 CS0 CK0, /CK0, CK1, /CK1, CK2,/CK2 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 Pin Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIO1 Min 58 58 58 58 25 7 7 Max 72 72 72 72 40 12 12 Unit pF pF pF pF pF pF pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 0.1/May 2004 6 HYMD564646B(L)8J-D43/J DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Input Leakage Current Add, CMD, /CS, /CKE CK, /CK Symbol ILI ILO VOH VOL Min. -16 -12 -5 VTT + 0.76 - Max 16 12 5 VTT - 0.76 Unit uA uA V V Note 1 2 IOH = -15.2mA IOL = +15.2mA Output Leakage Current Output High Voltage Output Low Voltage Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V 3. These values are device characteristics. Rev. 0.1/May 2004 7 HYMD564646B(L)8J-D43/J DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition One bank; Active - Precharge ; tRC=tRC(min); tCK= tCK(min) ; DQ,DM and DQS inputs changing twice per clock cycle ; address and control inputs changing once per clock cycle One bank ; Active - Read - Precharge ; Burst Length = 2 ; tRC=tRC(min); tCK= tCK(min) ; address and control inputs changing once per clock cycle All banks idle ; Power down mode ; CKE= Low, tCK= tCK(min) /CS = High, All banks idle ; tCK= tCK(min) ; CKE = High ; address and control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM One bank active ; Power down mode ; CKE= Low, tCK= tCK(min) /CS= HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS(max); tCK = t CK (max); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2 ; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK= tCK (min); IOUT = 0mA Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (min); DQ, DM, and DQS inputs changing twice per clock cycle tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE =< 0.2V; External clock on; tCK = tCK(min) Normal Low Power 4320 Speed -D43 -J Unit Note Operating Current IDD0 1200 1120 mA Operating Current Precharge Power Down Standby Current Idle Standby Current Active Power Down Standby Current Active Standby Current IDD1 1600 1440 mA IDD2P 80 mA IDD2F 280 mA IDD3P 96 mA IDD3N 400 360 mA Operating Current IDD4R 2240 2000 Operating Current IDD4W 2240 2000 mA Auto Refresh Current Self Refresh Current Operating Current Four Bank Operation IDD5 2400 40 20 2240 mA mA 3680 mA IDD6 IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition Rev. 0.1/May 2004 8 HYMD564646B(L)8J-D43/J AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Bin Sort : J(DDR333@CL=2.5), D43(DDR400@CL=3) -D43 Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time CL = 3 CL = 2.5 Symbol Min tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL tCK tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tHZ tLZ tIS tIH tIS tIH 0.6 0.6 0.7 0.7 55 70 40 tRCD or tRAS(min) -J Unit Note Max 70K 10 12 0.55 0.55 0.7 0.55 0.4 0.5 tAC (Max) tAC (Max) - Min 60 72 42 tRCD or tRAS(min) Max 70K 12 0.55 0.55 0.7 0.6 0.45 0.55 0.7 0.7 ns ns ns ns ns ns CK ns ns CK CK ns ns CK CK ns ns ns ns ns ns ns ns ns ns ns ns 1, 10 1,9 10 17 17 2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6 15 16 15 10 1 15 15 2 (tWR/tCK) + (tRP/tCK) 18 12 1 18 15 1 (tWR/tCK) + (tRP/tCK) System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew 5 6 0.45 0.45 -0.7 -0.55 tHP -tQHS min (tCL,tCH) - 6 0.45 0.45 -0.7 -0.6 tHP -tQHS min (tCL,tCH) -0.7 -0.7 0.75 0.75 0.8 0.8 DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Data-out high-impedance window from CK, /CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Rev. 0.1/May 2004 9 HYMD564646B(L)8J-D43/J AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -D43 Parameter Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In DQS falling edge to CK setup time DQS falling edge hold time from CK Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit self refresh to Any Executable Command Average Periodic Refresh Interval Note : 1. 2. 3. 4. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. For command/address input slew rate >=1.0V/ns For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 5. 6. Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0 Symbol Min tIPW tDQSH tDQSL tDQSS tDSS tDSH tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI 2.2 0.35 0.35 0.72 0.2 0.2 0.4 0.4 1.75 0.9 0.4 0 0.25 0.4 2 200 1.1 0.6 0.6 7.8 Max 1.28 Min 2.2 0.35 0.35 0.75 0.2 0.2 0.45 0.45 1.75 0.9 0.4 0 0.25 0.4 2 200 1.1 0.6 0.6 7.8 Max 1.25 ns CK CK CK CK CK ns ns ns CK CK CK CK CK CK CK us 8 6,7,11, ~13 6 6 - continued -J Unit Note Bin Sort : J(DDR333@CL=2.5), D43(DDR400@CL=3) CK, /CK slew rates are >=1.0V/ns, ie, >=2.0V/ns differential. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 7. Rev. 0.1/May 2004 10 HYMD564646B(L)8J-D43/J 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 9. 10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150 12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50 13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0.25 +/- 0.5 Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. Rev. 0.1/May 2004 11 HYMD564646B(L)8J-D43/J SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X /CS L L H L L L /RAS L L X H L H /CAS L L X H H L /WE L L X H H H CA RA L H L H H L X X ADDR A10/ AP OP code OP code X BA Note 1,2 1,2 1 V V 1 1 1,3 1 1,4 1,5 1 1 1 1 H X L H L L CA V X V H H H H L X X H L H L L L L H L H L H L H L L H L L X H X H X H X V X H H L L X H X H X H X V L L H H X H X H X H X V X X 1 1 Entry Precharge Power Down Mode Exit H L X 1 1 1 1 L H Active Power Down Mode Entry Exit H L L H X 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. DM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.1/May 2004 12 HYMD564646B(L)8J-D43/J PACKAGE DIMENSIONS 133.35 5.25 Front 131.35 5.171 128.95 5.077 (2X)4.00 0.157 10.0 0.394 31.75 1.250 Back 3.18 0.125MAX 17.80 0.700 (2) 0 2.5 0.098 2.30 0.91 Side (Front) 1.27+/-0.10 0.050+/-0.004 Rev. 0.1/May 2004 13 SERIAL PRESENCE DETECT SPD SPECIFICATION (64Mx64 Unbuffered DDR DIMM) Rev. 0.1/May 2004 14 HYMD564646B(L)8J-D43/J SERIAL PRESENCE DETECT Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 41 42 43 44 45 62 63 Function Description Number of Bytes written into serial memory at module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of physical banks on DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) DDR SDRAM cycle time at CAS Latency=2.5(tCK)@DDR333, 3(tCK)@DDR400 DDR SDRAM access time from clock at CL=2.5 (tAC), 3(tCK)@DDR400 Module configuration type Refresh rate and type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address(tCCD) Burst lengths supported Number of banks on each DDR SDRAM CAS latency supported CS latency WE latency DDR SDRAM module attributes DDR SDRAM device attributes : General DDR SDRAM cycle time at CL=2.0(tCK), 2.5(tCK) DDR SDRAM access time from clock at CL=2.0(tAC), 2.5(tAC) DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK) DDR SDRAM access time from clock at CL=1.5(tAC), 2.0(tAC) Minimum row precharge time(tRP) Minimum row activate to row active delay(tRRD) Minimum RAS to CAS delay(tRCD) Minimum active to precharge time(tRAS) Module row density Command and address signal input setup time(tIS) Command and address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) Minimum active / auto-refresh time ( tRC) Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) SPD Revision code Checksum for Bytes 0~62 0.6ns 0.6ns 0.4ns 0.4ns Undefined 55ns 70ns 10ns 0.4ns 0.50ns 60ns 72ns 12ns 0.45ns 0.55ns Undefined Initial release A7h 37h 46h 28h 28h 50h 00h 00h 41h 2, 2.5, 3 0 1 Differential Clock Input +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 6ns +/-0.7ns 7.5ns +/-0.75ns 15ns 10ns 15ns 40ns 512MB 0.75ns 0.75ns 0.45ns 0.45ns 60h 60h 40h 40h 00h 3Ch 48h 30h 2Dh 55h 7.5ns +/-0.7ns 18ns 12ns 18ns 42ns 60h 70h 75h 75h 3Ch 28h 3Ch 28h 80h 75h 75h 45h 45h 5.0ns +/-0.7ns Non-ECC 7.8us & Self refresh x8 N/A 1 CLK 2,4,8 4 Banks 2, 2.5 1Ch 01h 02h 20h C0h 75h 70h 00h 00h 48h 30h 48h 2Ah 2 2 2 2 Bin Sort : J(DDR333@CL=2.5), D43(DDR400@CL=3) Function Supported -D43 128 Bytes 256 Bytes DDR SDRAM 13 11 1Bank 64 Bits SSTL 2.5V 6.0ns 50h 70h 00h 82h 08h 00h 01h 0Eh 04h 0Ch -J Hexa Value -D43 80h 08h 07h 0Dh 0Bh 01h 40h 00h 04h 60h 2 2 1 1 -J Note 36~40 Reserved for VCSDRAM 46~61 Superset information(Reserved for IDD values, Tcase, etc.) Rev. 0.1/May 2004 15 HYMD564646B(L)8J-D43/J SERIAL PRESENCE DETECT Byte # 64 65~71 Function Description Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code Bin Sort : J(DDR333@CL=2.5), D43(DDR400@CL=3) Function Supported -D43 Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M D 5 6 4 Blank 6 4 6(8K refresh,4Bank) B 8 J `-' D 4 3 Undefined Undefined J Blank Blank 44h 34h 33h 00h 00h 3 3 4 5 5 -J Hexa Value -D43 ADh 00h 0*h 1*h 2*h 3*h 4*h 5*h 48h 59h 4Dh 44h 35h 36h 34h 20h 36h 34h 36h 42h 38h 4Ah 2Dh 4Ah 20h 20h -J Note - continued - Hynix JEDEC ID 72 Manufacturing location 6 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~127 Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Refresh, # of Bank.) Manufacture part number(Component Generation) Manufacture part number(Component configuration) Manufacture part number(Module Type) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) 128~255 Open for customer use Note : 1. The bank address is excluded 2. These value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number system 5. These bytes undefined and coded as `00h' 6. Refer to Hynix web site Byte 85~87, Low power part Byte # 85 86 87 Function Description Manufacture part number(Low power part) Manufacture part number(Component configuration) Manufacture part number(Module Type) Function Supported -D43 L 8 J -J Hexa Value -D43 4Ch 38h 4Ah -J Note Rev. 0.1/May 2004 16 |
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