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this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 19720 rev : c amendment /0 issue date: august 1995 amd bios development guide
? 1995 advanced micro devices, inc . all rights reserved . advanced micro devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. this publication neither states nor implies any representations or warranties of any kind, includ- ing but not limited to any implied warranty of merchantability or fitness for a particular purpose. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any conse- quences resulting from the use of the information included herein. trademarks amd, the amd logo, and am486 are registered trademarks, and am5 k 86 and k86 are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
amd bios development guide iii contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 recommended documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 standard am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 am486plus microprocessor vs. enhanced am486 microprocessor . . . . . . . . . 2 enhanced am486 microprocessor vs. am5 x 86 microprocessor . . . . . . . . . . . . 2 3 cpu identification algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 standard am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 enhanced am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 am5 x 86 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 cpuid instruction for the enhanced am486 and am5 x 86 microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 7 test registers 4 and 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 tr4 definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 tag (bits 31C11 for 8-kbyte cache, or bits 31C12 for 16-kbyte cache) 15 stn (bits 30C29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 st3 (bits 27C26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 st2 (bits 25C24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 st1 (bits 23C22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 st0 (bits 21C20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 cache size bit (bit 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 valid (bit 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 lru (bits 9C7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 valid (bits 6C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 tr5 definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ext (bit 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
iv amd bios development guide set state (bits 18C17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 index (8-kbyte cache = bits 10C4; 16-kbyte cache = bits 11C4) . . . 17 entry (bits 3C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 control (bits 1C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 using tr4 and tr5 for cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 example 1: reading the cache (write-back mode only) . . . . . . . . . . 18 example 2: writing the cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 example 3: flushing the cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 smm support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 standard am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 enhanced am486 and am5 x 86 microprocessors . . . . . . . . . . . . . . . . . . . . . . 20 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 exceptions and interrupts within smm . . . . . . . . . . . . . . . . . . . . . . . . 21 system management mode revision . . . . . . . . . . . . . . . . . . . . . . . . . 21 auto halt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 auto halt power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 relocatable smi handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 i/o trap restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 state save information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 sreset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 standard am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 enhanced am486 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 am5 x 86 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
amd bios guide v tables table 1-1. reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 3-1. summary of cpu ids for the standard am486 microprocessor . . . . . . . 3 table 3-2. summary of cpu ids for enhanced am486 microprocessors . . . . . . . . . 5 table 3-3. summary of cpu ids for the am5 x 86 microprocessors . . . . . . . . . . . . . 7 table 5-1. cache mode selection using wb/wt . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6-1. clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7-1. test register 4 (tr4) bit definitions for 8-kbyte cache . . . . . . . . . . . . 14 table 7-2. test register 4 (tr4) bit definitions for 16-kbyte cache . . . . . . . . . . . 14 table 7-3. test register 5 (tr5) bit definitions for 8-kbyte cache . . . . . . . . . . . . 15 table 7-4. test register 5 (tr5) bit definitions for 16-kbyte cache . . . . . . . . . . . 15 table 8-1. smm initial cpu register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8-2. segment register initial states in smm . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8-3. smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8-4. i/o trap word configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8-5. enhanced am486 and am5 x 86 microprocessor state save map . . . . . 24
amd bios guide vii figures figure 3-1. standard am486 microprocessor identification procedure . . . . . . . . . . . . . 4 figure 3-2. enhanced am486 microprocessor identification procedure. . . . . . . . . . . . . 6 figure 3-3. am5 x 86 microprocessor identification procedure . . . . . . . . . . . . . . . . . . . . 8 figure 4-1. cpuid instruction pseudo-code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5-1. cache size detection code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5-2. cache size determination flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8-1. auto halt restart implementation pseudo-code . . . . . . . . . . . . . . . . . . . . 22 figure 8-2. relocatable smi handler implementation pseudo-code . . . . . . . . . . . . . . 23 figure 8-3. i/o trap restart implementation pseudo-code . . . . . . . . . . . . . . . . . . . . . 24
amd bios development guide introduction 1 1 introduction purpose the purpose of this document is to identify bios modifications required to support standard am486 ? microprocessors, enhanced am486 micropro- cessors, and am5 x 86? microprocessors. there may be more than one way to implement the functionality detailed in this document; this informa- tion provides implementation examples. audience the reader should have a detailed familiarity with x86 architecture and programming requirements, the enhanced am486 microprocessor, and the am5 x 86 microprocessor. the data provided in this document is designed to assist third party vendors to prepare bios to support the enhanced am486 processor and am5 x 86 processor families. recommended documentation table 1-1 lists additional reference documentation for writing software for amd microprocessors. table 1-1. reference documentation document title document # am486 microprocessor software users manual 18497a standard am486dx2 microprocessor data sheet 19200d standard am486dx4 microprocessor data sheet 19160d enhanced am486 microprocessor family data sheet 19225b am5 x 86 microprocessor family data sheet 19751b
2 general amd bios development guide 2 general standard am486 microprocessor at reset, the standard am486dx4-100 processor places a value of 043xh in the dx register. this value is different from that used by the i486dx4-100 cpu. use the detection algorithm presented in figure 3-1 on page 4 to assure proper detection of amd microprocessors. am486plus microprocessor vs. enhanced am486 microprocessor early documentation released under non-disclosure agreements referred to an am486plus microprocessor. the am486plus designation was an internal code name. the released product is named the enhanced am486 microprocessor. use the detection algorithm presented in figure 3-2 on page 6 to assure proper detection of enhanced amd microprocessors. enhanced am486 microprocessor vs. am5 x 86 microprocessor the enhanced am486 and am5 x 86 microprocessors can be easily differ- entiated by evaluating clock speed. am5 x 86 processors operate at clock speeds of 133 mhz and greater. enhanced am486 microprocessors operate at clock speeds of 120 mhz or less.
amd bios development guide cpu identification algorithms 3 3 cpu identification algorithms the following sections describe the cpu identification algorithms for the various microprocessors. standard am486 microprocessor table 3-1 summarizes the cpu ids found in the dx register after reset for the standard am486 microprocessor.. table 3-1. summary of cpu ids for the standard am486 microprocessor amd cpu type cpu id in dx at reset standard am486dx 041xh standard am486dx2 043xh standard am486dx4 043xh
4 cpu identification algorithms amd bios development guide figure 3-1. standard am486 microprocessor identification procedure no no yes start cpu identification yes no proceed to enhanced am486 cpu flowchart, figure 3-2 save value in the dx register in variable dx_at_reset yes dx_at_reset = 043xh? no cpu speed = 100 mhz? yes finish of cpu identification perform speed loop test to determine cpu speed dx_at_reset = 041xh? standard am486dx cpu identified standard am486dx2 cpu identified standard am486dx4 cpu identified non-amd part identified eflags.21 writable?
amd bios development guide cpu identification algorithms 5 enhanced am486 microprocessor table 3-2 summarizes the cpu ids found in the dx register after reset for the enhanced am486 microprocessors. table 3-2. summary of cpu ids for enhanced am486 microprocessors amd cpu type cpu id in dx at reset comments enhanced am486dx2 cpu 043xh write through cache 047xh write-back cache enhanced am486dx4 cpu 048xh write-through cache 049xh write-back cache
6 cpu identification algorithms amd bios development guide figure 3-2. enhanced am486 microprocessor identification procedure enhanced am486dx4 cpu wt cache identified enhanced am486dx2 cpu wb cache identified enhanced am486dx2 cpu wt cache identified error in cpu identification process no start cpu identification eflags.21 writable? yes no proceed to standard am486 cpu flow chart, figure 3-1 save value in the dx register in variable dx_at_reset execute cpuid instructions with eax = 0h id string = authenticamd no yes yes dx_at_reset = 043xh? dx_at_reset = 047xh? yes no yes dx_at_reset = 048xh? no no yes dx_at_reset = 049xh? finish at cpu identification enhanced am486dx4 cpu wb cache identified cpu vendor other than amd has been found yes no proceed to am5 x 86 cpu flow chart, figure 3-3 speed 3 133 mhz
amd bios development guide cpu identification algorithms 7 am5 x 86 microprocessor table 3-3summarizes the cpu ids found in the dx register after reset for the am5 x 86 microprocessors. table 3-3. summary of cpu ids for the am5 x 86 microprocessors amd cpu type cpu id in dx at reset comments am5 x 86 cpu at 133 mhz or 160 mhz 04exh write-through cache 04fxh write-back cache am5 x 86 cpu at 150 mhz 048xh write-through cache 049xh write-back cache
8 cpu identification algorithms amd bios development guide figure 3-3. am5 x 86 microprocessor identification procedure am5 x 86-133/160 cpu wt cache identified error in cpu identification process start cpu identification eflags.21 writable? yes no proceed to standard am486 cpu flow chart, figure 3-1 save value in the dx register in variable dx_at_reset execute cpuid instructions with eax = 0h id string = authenticamd no yes yes dx_at_reset = 04exh? no no yes dx_at_reset = 04fxh? finish at cpu identification am5 x 86-133/160 cpu wb cache identified cpu vendor other than amd has been found proceed to enhanced am486 cpu flow chart, figure 3-2 speed 3 133 mhz yes no am5 x 86-150 cpu wb cache identified am5 x 86-150 cpu wt cache identified no yes dx_at_reset = 048xh? dx_at_reset = 049xh? yes no
amd bios development guide cpuid instruction for the enhanced am486 and am5 x 86 microprocessors 9 4 cpuid instruction for the enhanced am486 and am5 x 86 microprocessors enhanced am486 and am5 x 86 microprocessors support the cpuid instruction. to utilize the cpuid instruction, a pseudo-code algorithm is provided in figure 4-1 to aid code development. figure 4-1. cpuid instruction pseudo-code begin { if eflags.21 is writable then { if vendor string report desired { load eax with 0h execute cpuid instruction (opcode = 0fh a2h) if result: ebx = auth edx = enti ecx = camd part is amd. } else part is non-amd. if part description is desired { load eax with 1 execute cpuid instruction (opcode = 0fh a2h) result: eax[3C0] = stepping id (contact amd for specifics) eax[7C4] = model am486dx2-wt -> 3 am486dx2-wb -> 7 am486dx4-wt -> 8 am486dx4-wb -> 9 am5 x 86-wt (150 mhz) -> 8 am5 x 86-wb (150 mhz) -> 9 am5 x 86-wt (133 and 160 mhz) -> e am5 x 86-wb (133 and 160 mhz) -> f eax[11C8] = family am486 cpu -> 4 am5 x 86 cpu -> 4 eax[15C12] = 0000
10 cpuid instruction for the enhanced am486 and am5 x 86 microprocessors amd bios development guide eax[31C16] = reserved ebx = 00000000h ecx = 00000000h edx = 00000001h (bit 0==1 indicates fpu present) } } else cpuid is not supported }end note: the standard am486 microprocessor does not support the cpuid instruction.
amd bios development guide cache 11 5cache the enhanced am486 and am5 x 86 processors support both write-back and write-through cache modes. to select between the different cache modes, set the wb/wt pin on the microprocessor to the proper logic state at reset (see table 5-1). the processor responds with the proper cpu id in the dx register after reset so that the bios can detect the selected cache operating mode. the cpuid instruction also reports the proper con- figuration. figure 5-1 shows a code example that can be used to test the cache size. figure 5-2 is a flow diagram that illustrates how this code detects the cache size. if the ext bit in tr5 = 0, bit 11 in the tag field in tr4 will behave as follows: ? for 8-kbyte cache, the bit is read/write. ? for 16-kbyte cache, the bit is read only and always zero during a cache look-up. the bit is read/write otherwise. figure 5-1. cache size detection code example disable_cache mov ebx,00000002h ;perform cache read with ext==0 mov tr5,ebx mov eax,tr4 ;read tr4 to get valid tag bits xor eax,00000800h ;toggle bit 11 of tr4 mov tr4,eax ;write new value to tr4 mov ebx,00000001h ;perform cache write with new tr4 mov tr5,ebx push eax mov ebx,00000002h ;cache read with ext==0 mov tr5,ebx mov eax,tr4 ;read tr4 for valid tag bits pop ebx and bh,00001000b ;mask for bit 11 and ah,00001000b ;mask for bit 11 table 5-1. cache mode selection using wb/wt wb/wt input at reset cache mode selected v ss or floating write-through v cc write-back
12 cache amd bios development guide cmp ah,bh jne 16k_cache jmp 8k_cache 16k_cache: ;16-kbyte cache is detected 8k_cache: ;8-kbyte cache is detected figure 5-2. cache size determination flowchart start cache size determination disable cache set ext bit in tr5 equal to 0 tr4 bit 11 writable on cache look-up? yes no cpu contains 16-kbyte cache cpu contains 8-kbyte cache return
amd bios development guide clock mode selection 13 6 clock mode selection the enhanced am486 and am5 x 86 processors sample the clkmul input signal at reset to determine the design operating frequency. if clkmul is high or floating, the cpu uses 3x clock mode. if clkmul is low, the enhanced am486 cpu uses a 2x clock mode; the am5 x 86 cpu uses a 4x clock mode (see table 6-1). an internal pull-up connects clkmul to v cc . the processor responds with the proper cpu id in the dx register after reset so that the bios can detect the selected clock mode. the cpuid instruction also reports the clock mode configuration. note: the enhanced am486 microprocessor and the am5 x 86 micropro- cessor do not support a 2.5 times clock multiplier. do not connect the breq signal to the clkmul input signal. table 6-1. clock mode selection clkmul input state at reset clock mode selected v ss enhanced am486 cpu = 2x am5 x 86 cpu = 4x v cc or floating 3x
14 test registers 4 and 5 amd bios development guide 7 test registers 4 and 5 the cache test registers for the enhanced am486 and am5 x 86 micro- processors are the same test registers (tr3, tr4, and tr5) provided in earlier am486 microprocessors. tr3 is the cache test data register. tr4, the cache test status register, and tr5, the cache test control register, oper- ate together with tr3. if wb/wt meets the necessary setup timing and is sampled low on the falling edge of reset, the processor is placed in write-through cache mode and the test register function is identical to the earlier am486 micro- processors. if wb/wt meets the necessary setup timing and is sampled high on the falling edge of reset, the processor is placed in write-back cache mode and tr4 and tr5 are modified to support the added write- back cache functionality. the following tables show the individual bit functions of these registers. note: bit 11 of tr4 can be used to identify internal cache size. see fig- ures 5 and 6 for additional information. table 7-1. test register 4 (tr4) bit definitions for 8-kbyte cache bit 31 30C 29 28 27C 26 25C 24 23C 22 21C 20 19C16 15C11 10 9C7 6C3 2C0 ext=0 tag valid lru valid (rd) na ext=1 na stn resv. st3 st2 st1 st0 reserved na valid lru valid (rd) na table 7-2. test register 4 (tr4) bit definitions for 16-kbyte cache bit 31 30C 29 28 27C 26 25C 24 23C 22 21C 20 19C16 15C 12 11 10 9C7 6C3 2C0 ext=0 tag 0 valid lru valid (rd) na ext=1 na stn resv. st3 st2 st1 st0 reserved na na valid lru valid (rd) na
amd bios development guide test registers 4 and 5 15 note: tr3 has the same functions in both write-through and write-back cache modes. these functions are identical to the tr3 register functions provided by earlier am486 microprocessors. tr4 definition this section includes a detailed description of the bit fields defined for tr4. tag (bits 31C11 for 8-kbyte cache, or bits 31C12 for 16- kbyte cache) read/write, always available in write-through mode. available only when ext=0 in tr5 in write-back mode. for a cache write, this is the tag that specifies the address in memory. on a cache look-up, this is tag for the selected entry in the cache. stn (bits 30C29) read only, available only in write-back mode when ext=1 in tr5. stn returns the status of the set (st3, st2, st1, or st0) specified by the tr5 set state field (bits 18C17) during cache look-ups. returned values are: 00 = invalid 01 = exclusive 10 = modified 11 = shared table 7-3. test register 5 (tr5) bit definitions for 8-kbyte cache cache type 31C20 19 18C17 16 15C11 10C4 3C2 1C0 wb not used ext set state resv. not used index entry control wt not used index entry control table 7-4. test register 5 (tr5) bit definitions for 16-kbyte cache cache type 31C20 19 18C17 16 15C12 11C4 3C2 1C0 wb not used ext set state resv. not used index entry control wt not used index entry control
16 test registers 4 and 5 amd bios development guide st3 (bits 27C26) read only, available only in write-back mode when ext=1 in tr5. st3 returns the status of set 3 during cache look-ups. returned values are: 00 = invalid 01 = exclusive 10 = modified 11 = shared st2 (bits 25C24) read only, available only in write-back mode when ext=1 in tr5. st2 returns the status of set 2 during cache look-ups. returned values are: 00 = invalid 01 = exclusive 10 = modified 11 = shared st1 (bits 23C22) read only, available only in write-back mode when ext=1 in tr5. st1 returns the status of set 1 during cache look-ups. returned values are: 00 = invalid 01 = exclusive 10 = modified 11 = shared st0 (bits 21C20) read only, available only in write-back mode when ext=1 in tr5. st0 returns the status of set 0 during cache look-ups. returned values are: 00 = invalid 01 = exclusive 10 = modified 11 = shared cache size bit (bit 11) read/write for 8-kbyte cache if ext=0. read only for 16-kbyte cache if ext=0 during a cache look-up (the bit is read/write at all other times). the bit can be used to determine cache size. see figures 5 and 6 for more infor- mation. valid (bit 10) read/write, independent of the ext bit in tr5. this is the valid bit for the accessed entry. on a cache look-up, valid is a copy of one of the bits reported in bits 6C3. on a cache write in write-through mode, valid becomes the new valid bit for the selected entry and set. in write-back mode, writing to the valid bit has no effect and is ignored; the set state bit locations in tr5 are used to set the valid bit for the selected entry and set.
amd bios development guide test registers 4 and 5 17 lru (bits 9C7) read only, independent of the ext bit in tr5. on a cache look-up, these are the three lru bits of the accessed set. on a cache write, these bits are ignored; the lru bits in the cache are updated by the pseudo-lru cache replacement algorithm. write operations to these locations have no effect on the device. valid (bits 6C3) read only, independent of the ext bit in tr5. on a cache look-up, these are the four valid bits of the accessed set. in write-back mode, these valid bits are set if a cache set is in the exclusive, modified, or shared state. write operations to these locations have no effect on the device. tr5 definition this section includes a detailed description of the bit fields in the tr4. ext (bit 19) read/write, available only in write-back mode. ext, or extension, deter- mines which bit fields are defined for tr4: the address tag field, or the stn and st3Cst0 status bit fields. in write-through mode, the ext bit is not accessible. the following describes the two states of ext: ext = 0, bits 31C11 of tr4 contain the tag address ext = 1, bits 30C29 of tr4 contain stn, bits 27C20 contain st3Cst0 set state (bits 18C17) read/write, available only in write-back mode. the set state field is used to change the mesi state of the set specified by the index and entry bits. the state is set by writing one of the following combinations to this field: 00 = invalid 01 = exclusive 10 = modified 11 = shared index (8-kbyte cache = bits 10C4; 16-kbyte cache = bits 11C4) read/write, independent of write-through or write-back mode. index selects one of the 128 sets. entry (bits 3C2) read/write, independent of write-through or write-back mode. entry selects between one of the four entries in the set addressed by the set select during a cache read or write. during cache fill buffer writes or cache read buffer reads, the value in the entry field selects one of the four double- words in a cache line.
18 test registers 4 and 5 amd bios development guide control (bits 1C0) read/write, independent of write-through or write-back mode. the control bits determine which operation to be performed. the following is a defini- tion of the control operations: 00 = write to cache fill buffer, or read from cache read buffer. 01 = perform cache write. 10 = perform cache read. 11 = flush the cache (mark all entries invalid). using tr4 and tr5 for cache testing the following sections provide examples of testing the cache using tr4 and tr5. example 1: reading the cache (write-back mode only) 1. disable caching by setting the cd bit in the cr0 register. 2. in tr5, load 0 into the ext field (bit 19), the required index into the index field (bits 10C4), the required entry value into the entry field (bits 3C2), and 10 into the control field (bits 1C0). loading the values into tr5 triggers the cache read. the cache read loads the tr4 register with the tag for the read entry, and the lru and valid bits for the entire set that was read. the cache read loads 128 data bits into the cache read buffer. the entire buffer can be read by placing each of the four binary combinations in the entry field and setting the control field in tr5 to 00 (binary). read each doubleword from the cache read buffer through tr3. 3. reading the set state fields in tr4 during write-back mode is accom- plished by setting the ext field in tr5 to 1 and re-reading tr4. example 2: writing the cache 1. disable the cache by setting the cd bit in the cr0 register. 2. in tr5, load 0 into the ext field (bit 19), the required entry value into the entry field (bits 3C2), and 00 into the control field (bits 1C0). 3. load the tr3 register with the data to write to the cache fill buffer. the cache fill buffer write is triggered by loading tr3. 4. repeat steps 2 and 3 for the remaining three doublewords in the cache fill buffer. 5. in tr4, load the required values into tag field (bits 31C11) and the valid field (bit 10). in write-back mode, the valid bit is ignored since the set state field in tr5 is used in place of the tr4 valid bit. the other bits in tr4 (9C0) have no effect on the cache write.
amd bios development guide test registers 4 and 5 19 6. in tr5, load 0 into the ext field (bit 19), the required value into the set state field (bits 18C17) (write-back mode only), the required index into the index field (bits 10C4), the required entry value into the entry field (bits 3C2), and 01 into the control field (bits 1C0). loading the values into tr5 triggers the cache write. in write-through mode, the set state field is ignored, and the valid bit (bit 10) in tr4 is used instead to define the state of the specified set. example 3: flushing the cache the cache flush mechanism functions the same way both in write-back and write-through modes. load 11 into the control field (bits 1C0) of tr5. all other fields are ignored, except for ext in write-back mode. the cache flush is triggered by loading the value into tr5. all of the lru bits, valid bits, and set state bits are cleared.
20 smm support amd bios development guide 8 smm support standard am486 microprocessor the standard am486 microprocessor does not provide smm support. enhanced am486 and am5 x 86 microprocessors when an smi signal is recognized on an instruction execution boundary, the processor waits for all stores to complete. the processor then saves its register state to smram and begins to execute the smm handler. the following is a summary of the key features in the smm environment: ? real mode style addressing ? 4-gbyte limit checking ? if flag is cleared; intr is not recognized ? nmi is disabled ? tf flag in eflags is cleared; single step traces are disabled ? dr7 is cleared; debug traps are disabled ? the rsm instruction restores the state of the cpu prior to entering smm ? default 16-bit opcode, register, and stack use cpu registers tables 8-1 and 8-2 highlight the default register values when entering smm. table 8-1. smm initial cpu register settings register smm initial state general purpose registers unmodified eflags 00000002h cr0 bits 0, 2, 3, and 31 cleared (pe, em, ts, and pg); remainder is unmodified dr6 undefined dr7 bit 12 retains its value at the time the pro- cessor entered smm mode gdtr, ldtr, idtr, tssr unmodified eip 00008000h
amd bios development guide smm support 21 exceptions and interrupts within smm this feature is compatible with the industry standard 2-pin smm (see doc- uments # 19225 and 19751). system management mode revision the smm revision identifier specifies the version of smm and the exten- sions that are available on the processor. table 8-3 defines the bits associ- ated with this register. a 1 present in either the i/o trap extension or the smm base relocation indicates that this feature is available for use. table 8-2. segment register initial states in smm segment register selector base attributes limit cs 3000h 30000h 16-bit, expand up 4 gbytes ds 0000h 00000000h 16-bit, expand up 4 gbytes es 0000h 00000000h 16-bit, expand up 4 gbytes fs 0000h 00000000h 16-bit, expand up 4 gbytes gs 0000h 00000000h 16-bit, expand up 4 gbytes ss 0000h 00000000h 16-bit, expand up 4 gbytes table 8-3. smm revision identifier 31C18 17 16 15C0 reserved i/o trap extension smm base relocation smm revision level 0 1 1 0000h
22 smm support amd bios development guide auto halt restart the auto halt restart slot at register offset 7f02h in smram indicates to the smm handler that the smi interrupted the cpu during a halt state. bit position 0 of 7f02h will be set to a one in this condition. figure 8-1 shows the pseudo-code required to implement this feature in the bios. figure 8-1. auto halt restart implementation pseudo-code begin { if eflags.21 is writable then ;should be done during id process { if hlt instruction needs to be restarted then { if smi during halt state then ;bit 0 of offset 7f02h = 1 set hlt restart slot to 00ffh ;offset 7f00h in state save map } } else smm features are not supported } end auto halt power down this feature is described in documents # 19225 and 19751. relocatable smi handler the address space used as smram can be modified by changing the smbase register before exiting an smi handler routine. smbase can be changed to any 32-kbyte aligned value. values that are not 32-kbyte aligned will cause the cpu to enter the shutdown state when executing the rsm instruction. smbase is set to the default value of 30000h on reset, but is not changed an smm handler. all subsequent smi requests will ini- tiate a state save at the new smbase. the smbase slot in the smm state save area indicates and changes the smi vector location and the smram save area. when bit 17 of the smm revision identifier is set, then this feature exists and the smram base and consequently the jump vector are as indicated by the smm base slot. fig- ure 8-2 shows the pseudo-code required to implement this feature in the bios.
amd bios development guide smm support 23 figure 8-2. relocatable smi handler implementation pseudo-code begin { if eflags.21 is writable then { if smi handler is to be relocated then { set smbase slot to required value;offset fef8h in state map resume } else { smi handler execution to begin at relocation area. resume } } else smm is not supported } end i/o trap restart the i/o instruction restart slot gives the smm handler the option of caus- ing the rsm instruction to automatically re-execute an interrupted i/o instruction. when the rsm instruction is executed and the i/o instruction restart slot contains the value 0ffh, the cpu automatically re-executes the i/o instruction that the smi signal trapped. the cpu automatically initial- izes the i/o instruction restart slot to 00h during smm entry. the i/o instruction restart slot should be written only when a valid i/o instruction has occurred; this can be checked via the i/o trap configuration word bit 1 (offset 0ff04h in the state save map). the bit definitions for the i/o trap word are in table 8-4. if the i/o instruction restart slot is set on an invalid i/o instruction the processor operation is unpredictable. if the system executes back-to-back smi requests, the second smm han- dler must not set the i/o instruction restart slot. the second smi signal will not have the i/o trap word set. figure 8-3 shows the pseudo-code required to implement this feature in the bios. table 8-4. i/o trap word configuration 31 C 16 15 C 21 0 i/o address reserved valid i/o instruction read/write
24 smm support amd bios development guide figure 8-3. i/o trap restart implementation pseudo-code begin { if eflags.21 is writable then { if i/o instruction needs to be restarted then { if valid i/o instruction then set i/o restart slot to 00ffh;offset 7f00h in state save map } } else smm features are not supported } end state save information when the smi signal is recognized, enhanced am486 and am5 x 86 micro- processors will save the cpu state to the state save area specified in table 8-5. if the smi has been relocated, then the state dump will begin at cs base + [8000h + 7fffh]. the default cs base is 3000h. table 8-5. enhanced am486 and am5 x 86 microprocessor state save map cpu registers address cr0 fffch cr3 fff8h eflags fff4h eip fff0h edi ffech esi ffe8h ebp ffe4h esp ffe0h ebx ffdch edx ffd8h ecx ffd4h eax ffd0h dr6 (ffffcff3h) ffcch dr7 ffc8h tr ffc4h
amd bios development guide smm support 25 ldtr ffc0h gs ffbch fs ffb8h ds ffb4h ss ffb0h cs ffach es ffa8h tss atr ffa4h tss base ffa0h tss limit ff9ch idt atr ff98h idt base ff94h idt limit ff90h gdt atr ff8ch gdt base ff88h gdt limit ff84h ldt atr ff80h ldt base ff7ch ldt limit ff78h gs atr ff74h gs base ff70h gs limit ff6ch fs atr ff68h fs base ff64h fs limit ff60h ds atr ff5ch ds base ff58h ds limit ff54h ss atr ff50h ss base ff4ch ss limit ff48h cs atr ff44h table 8-5. enhanced am486 and am5 x 86 microprocessor state save map (continued) cpu registers address
26 smm support amd bios development guide cs base ff40h cs limit ff3ch es atr ff38h es base ff34h es limit ff30h no ff2ch no ff28h eip_prev ff10h no ff0ch no ff08h io trap word ff04h halt auto rstrt/io rstrt ff00h smm rev id 20030000h fefch state dump base fef8h cr2 fef4h dr0 fef0h dr1 feech dr2 fee8h dr3 fee4h table 8-5. enhanced am486 and am5 x 86 microprocessor state save map (continued) cpu registers address
amd bios development guide sreset 27 9 sreset standard am486 microprocessor the standard am486 microprocessor does not provide support for sreset. enhanced am486 microprocessor this feature is described in document # 19225. am5 x 86 microprocessor the feature is described in document # 19751.

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