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topswitch-gx forward design methodology application note AN-30 introduction the single-ended forward converter topology is often the best solution for ac-dc applications that require higher powers and higher output currents than are practical from flyback converters. the forward converter extends the power capability of topswitch-gx to greater than 200 w for high current outputs. the feature set of topswitch-gx offers the following advantages in single-ended forward designs: built-in soft-start built-in under-voltage lockout built-in adjustable current limit programmable duty cycle reduction to limit duty cycle excursion at high line and transient load conditions higher efficiency (typically >70%) very good light-load efficiency voltage mode control for simpler loop designs with magnetic amplifier post-regulators built-in remote on-off low component count improved emi scope this application note is for engineers designing an ac-dc power supply using topswitch-gx in a single-ended forward converter. it addresses single input voltage 230 vac or doubled 115 vac input, but does not address universal input (85 v to 265 v) designs. the document highlights design parameters that are fundamental to the use of topswitch-gx in a single- ended forward converter. it offers a procedure to compute transformer turns, output inductance and other design parameters. this procedure enables designers to build an operational prototype in the shortest possible time. refinement of the prototype hardware after bench evaluation will lead to a final design. the design methodology presented here is sufficiently general to cover a variety of single-ended forward designs, including power supplies for personal computers. it provides for multiple outputs with coupled inductors, independent multiple outputs, and outputs with both linear or magnetic amplifier post regulators. december 2002 u1 dl sf c ac input v o + + r a non-doubled doubled clamp diode snubber output inductor output capacitor r c c vs r d r b under-voltage lockout sense pi-2817-121201 feedback circuit control control topswitch-gx primary clamp circuit tl431 with frequency compensation v db v db + + v z + 2c in 2c in bias voltage figure 1. typical configuration of topswitch-gx in a single-ended forward converter.
AN-30 2 b 12/02 this document does not address the design of magnetic amplifiers nor linear regulators. it determines design parameters for the transformer and the inductors, but does not give construction details for those magnetic components. such details are deferred to other application notes and component suppliers. references [1] through [6] are good sources of information for the design of transformers and inductors. software for design of magnetic amplifiers is available from [5]. reference [1] is also an excellent resource for other important topics in power electronics. design methodology overview the methodology assumes the reader knows the theory of operation of the forward converter and the fundamentals of power supply design. it is a companion to the pi expert software for forward converter design (available from the power integrations web site). designers are advised to check power integrations?web site at www.powerint.com for the latest application information. this presentation uses a typical combination of output options for illustration of the methodology (see figure 2). this document + + pi-2818-121201 optional lc post filter dc stacked or conventional mag amp control mag amp linear post regulator optional lc post filter n p n b choose connection output return input voltage from v aux , v main , v mainma or v ind any output voltage less than input voltage n aux n ind l ind i load i load l mainma l main v auxref n main i aux v aux i main i ind i mainma v mainma v ind + v main + figure 2. general output options for the forward converter described in the methodology.
AN-30 3 b 12/02 gives the basic expressions illustrating the methodology. the pi expert software uses more complex versions of these expressions containing additional parameters to account for non-ideal effects. thus, results from the software may not exactly match the computations from expressions in this document. this document assumes a non-doubled input configuration. pi expert includes modified expressions for both doubler and non-doubler input configurations. to simplify the expressions, all outputs are assumed to operate in continuous conduction mode, consistent with the worst case design at maximum load. at lower load conditions it is possible for individual outputs to operate in discontinuous conduction mode. the methodology begins with an explanation of the general converter topology. it then presents the design flow, showing the major tasks in a high level flowchart. after a review of the nomenclature and definitions of variables, it discusses the details of the design procedure. rationale, assumptions and expressions are given to help the designer enter parameters and interpret results. a complete list of variables used in the expressions follows in appendix a. appendix b offers a procedure for hardware verification. a worked example is presented in appendix c. general converter topology figure 1 shows a typical single-ended forward converter using topswitch-gx . detail is focused on the primary side of the transformer because the circuits on the secondary are conventional and covered in other literature. resistors r a and r b set the under-voltage lockout threshold. resistor network r a , r b , r c , and r d with capacitor c vs adjusts the maximum duty ratio as a function of the input voltage. this methodology gives the procedure to determine proper values for the resistors and the capacitor. another key element in the use of topswitch-gx is the primary clamp (c cp , d1, vr1, vr2 and vr3 in figure 10) which resets the transformer flux and limits the maximum drain voltage. this methodology assumes use of this zener-capacitor clamp circuit. guidance for selection of components for this particular clamp is included in this application note. the topic of clamp circuits is deferred to a separate application note. designers may choose to use their own clamp circuits with the restriction that resonant clamps, (for example, lcd clamps?nductor/capacitor/diode) and reset windings are not recommended . the internal current sense of topswitch-gx does not allow the high reset current of a resonant clamp to be excluded from the sensed drain current. this methodology uses an ordinary optically isolated feedback circuit that is common in voltage mode systems with a two-pole response. the frequency compensation will in general require two zeros and two poles to obtain the phase margin desired for most applications. while the design of the feedback circuit is a separate topic beyond the scope of this application note, the general topology of the circuit is discussed. output options salient features of the output circuits are illustrated in figure 2. multiple secondary windings of the transformer may be configured in many different ways to give several options for regulated and unregulated output voltages. all applications will have only one main output. this is the voltage that is regulated directly by topswitch-gx through the optically isolated feedback circuit. in general, any number of auxiliary outputs may be derived from other secondary windings and regulated indirectly by means of a coupled inductor that they share with the main output. the secondary windings for the auxiliary outputs may be configured in two different ways. the conventional configuration connects one side of the auxiliary winding to the main output return. this connection is used when the auxiliary output is the opposite polarity of the main output. an alternative configuration, sometimes known as the dc stacked connection, has one side of the auxiliary winding referenced to the main output instead of the output return. it has the advantage of better regulation of the auxiliary output voltage than the non-stacked arrangement, but is limited to outputs that are greater in magnitude and of the same polarity as the main output voltage. any number of unregulated output voltages may be derived from circuits that do not share an inductor with any other outputs. they are related to the main output only through separate secondary windings on the transformer. their inductors are independent of the others. these outputs typically are referenced to the output return, but alternatively they may be referenced to any potential that the isolation of the transformer will tolerate. multiple tightly regulated voltages may be obtained with either linear or switching post regulators. these external regulators may be added to any output, including the main output. they are simply additional loads on those output voltages. a particularly useful type of switching post regulator is the magnetic amplifier, which uses a saturating magnetic element as an independently controlled switching device. while a magnetic amplifier can in theory be operated from any output, this methodology restricts the connection to the main output only. since it is not possible to treat every combination of output
AN-30 4 b 12/02 options in this presentation, the methodology will be restricted to those that are typical for power supplies in personal computers. therefore, this methodology allows the following options: one main output ? maximum of one auxiliary output that may be dc stacked to the main output or referenced to output return ? maximum of one independent output ? maximum of one magnetic amplifier post regulator that operates from the secondary winding for the main output any number of linear post regulators that may operate from any output design flow figure 3 is an abbreviated flowchart of the major tasks in the design methodology. the important decision blocks involve the selection of the proper topswitch-gx device for the application, and the designer? satisfaction with the overall design. all designs begin with the definition of requirements. the next section discusses the parameters a designer needs to know before the design can start. parameters for the forward converter are dominated by the output specifications. the designer will have to choose a topology that is appropriate for the application. an application that calls for only one output is simplest, while a requirement for several outputs with complex loading needs careful consideration. it may be necessary to go through several designs to select the most satisfactory configuration. knowledge of system requirements and selection of the output topology allow the designer to compute the magnetic parameters. these are turns ratios for the transformer and the coupled inductor (if the design has an auxiliary output), plus values of inductance for independent outputs and the output inductor for the magnetic amplifier (also called mag amp). the output inductor for the mag amp is different from the inductive switching element (sometimes called a saturable reactor, saturable core, or saturable choke), that is not addressed in this note. the peak primary current can be computed from the turns ratios established for the transformer along with the ripple current in the output inductors. this allows selection of the appropriate topswitch-gx . it must have sufficient current limit to handle the maximum steady-state load and must have enough additional margin to accommodate peak loads and transients. another consideration in the selection of the topswitch-gx is power dissipation in the device. a device that can handle the steady-state and peak primary currents does not guarantee ability to meet thermal limitations ?this is an independent consideration. get system requirements select output topology choose design parameters yes estimate peak primary current select topswitch-gx from current and power guidelines are parameters within topswitch-gx boundaries? design transformer compute operational parameters determine control and clamp components evaluate prototype on bench topswitch-gx selection ok? determine component stress compute output inductance design satisfactory? performance satisfactory? check assumptions adjust design parameters design complete no no no no start yes pi-2819-121301 yes yes figure 3. flowchart showing major tasks in the design of forward converters with topswitch-gx.
AN-30 5 b 12/02 the efficiency of the power system is an important consideration in every design. the designer should have a goal for the efficiency of the system at the start of the design, based on reasonable allowances for power lost in the specific areas of the power supply. the efficiency goal should take into account losses in the transformer, inductors, output rectifiers, and clamp circuits. most high power designs have some form of power factor correction (pfc). the type of pfc will affect the efficiency. for example, the voltage drop on a passive pfc (a large inductor in series with the ac line input) will reduce the minimum input voltage at the converter, and will also reduce system efficiency. total system efficiency should consider losses in the ac input circuit, including the emi filter, that are not part of this design methodology. only a bench evaluation can determine the actual efficiency of the power supply. if the efficiency is not satisfactory, the designer must revise the values of component parameters or change the output topology for a repeat design. if the requirements call for a holdup time, the designer must determine the amount of bulk input capacitance that is required to achieve the specified holdup time from the designated input voltage. it is often necessary to adjust parameters by iteration to meet the objectives of the design. pi expert performs the calculations to allow the designer to see the interactions of the variables immediately. after the values of the major power components are determined, the designer needs to check voltage and current stress to select components with the proper ratings. then the designer can choose values for small signal components that set voltage detection thresholds and other control parameters. the final step is an evaluation of a prototype on the bench. this is the only way to confirm that the design is satisfactory, and to get necessary information to adjust the parameters if a redesign is necessary. definition of variables table 1 gives a set of system parameters that should be known at the start of the design. the list is general, so all the parameters will not necessarily be relevant to all applications. some values will be given by the system specification, while others are the designer? choice. the notation in this document uses descriptive subscripts to keep track of variables. quantities that refer to the main output are designated with the subscript main . variables associated with an auxiliary output are identified by the subscript aux , and those related to an independent output have the subscript ind . these conventions are used to identify voltages, currents, and components. when there is more than one output in a category, the individual members are distinguished by numbers appended to the subscript, as in ind1 , ind2 and ind3 for three independent outputs. quantities related to the magnetic amplifier have ma appended to the subscript, as in mainma referring to the magnetic amplifier on the secondary winding for the main output. this notation has the generality necessary to expand the allowable output options. turns ratios on magnetic components are designated by lower case n with appropriate subscripts, while actual numbers of turns are distinguished by upper case n with identifying subscripts. there are a few other variables and notations that need definition. figure 4 shows a section of output circuitry that identifies some important electrical quantities. each output of a forward converter has two diodes. one is designated the forward diode and the other is the catch diode. associated quantities have f or c appended to their respective subscripts. name description total system efficiency f l ac mains frequency f s topswitch-gx switching frequency i aux current from auxiliary output i ind current from independent output i main current from main output i mainma current from magnetic amplifier t h holdup time v acmax maximum ac input voltage v acmin minimum ac input voltage v acnom nominal ac input voltage v acuv ac under-voltage threshold v aux auxiliary output voltage v auxref auxiliary output reference voltage v dropout lowest dc bus voltage for regulation v dsop maximum drain-to-source voltage v holdup dc bus voltage at start of t h v ind independent output voltage v main main output voltage v mainma magnetic amplifier output voltage t able 1. system parameters needed to start a design.
AN-30 6 b 12/02 voltage drops on diodes have subscripts with the prefix d for the conduction drop and piv for the reverse blocking voltage. the only exception to this convention is for drain-to-source voltages, which will be obvious from context. figure 4 also shows series resistances that the designer can include to get better predictions of performance. detailed design procedure this methodology guides the designer through a procedure that determines parameters for prototype hardware. after bench evaluation, the designer refines the parameters to meet all requirements. the design can start with knowledge of only the most basic system requirements. for example, the forward voltage drops on diodes and the resistances of transformer windings are seldom known very accurately at the beginning of a new design. results of the design with default values will guide the designer to select particular components with known parameters. figure 5 gives an expanded flowchart that includes the detailed steps which follow. step 1. establish system requirements. determine the parameters in table 1. these should be available from a system specification of the power supply? application. the software will compute and display the maximum and minimum dc bus voltages to the converter from the ac inputs. the need to know maximum and minimum voltages is obvious. the optional nominal input voltage v acnom helps determine the turns ratios of the transformer. the goal is to set the unregulated output voltages at their nominal values when the input is at its nominal value. the designer may choose any value between v acmax and v acmin to be the nominal value. the peak dc bus voltage (non-doubled) is (1) while the dc bus voltage at the valley of the ripple at the minimum steady state ac input is (2) where p o is the total output power, t c is the conduction time of the bridge rectifier, dc is the efficiency exclusive of losses in the ac input circuit, and c in is the capacitance at the input to the converter. use 3 ms for t c and use the total system efficiency for dc if no better estimates are available. a good initial value for c in is 1 f per watt multiplied by p o . the designer should carefully choose the value of t c when using passive pfc input (a large inductor in the ac line), since this approach significantly increases the diode conduction time. also, the voltage waveform will deviate from a sinusoid, causing some error in the prediction of equations (1) and (2). remember to use the input voltage to linear regulators, not the regulated output voltage, to compute the total output power. the dissipation in the linear regulator is part of the load on the converter. the nominal dc bus voltage is defined to be (3) this is simply the midpoint between the peak and valley of the ripple voltage on the input capacitor (non-doubled). step 2. set ripple current in the output inductors. choose the ripple current factor k ? i . figure 6 shows how it is related to the average output current. k ? i is a useful parameter for design because it directly influences the size of the output inductor. it also affects the peak primary current and the rms current in the output capacitors. pi-2820-121301 + + + v main v dmainc v dmainf l main n p r p r lmain r smain n main forward diode catch diode figure 4. output circuit with parameter definitions. vv max acmax = 2 vv p f t c min acmin o l c dc in = ? ? ? ? ? ? ? ? 2 2 1 2 2 vvv p f t c nom acnom acnom o l c dc in =+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 1 2 2
AN-30 7 b 12/02 1. establish system requirements (specifications & output topology) 15. calculate component values for external dc max reduction 2. set inductor current ripple review requirements check assumptions adjust design parameters construct hardware prototype evaluate thoroughly on bench determine limits of operation operation within topswitch-gx guidelines? operation within topswitch-gx guidelines? 14. inductor size satisfactory? is performance satisfactory? 16. calculate resistor values for optional external uvlo circuit 17. choose components for clamp circuit design complete 18. choose components for feedback circuit pi-2831-020502 3. calculate transformer turns ratios 4. estimate primary current 5. choose topswitch-gx 6. design transformer no no yes yes no no 7. check peak primary current 8. determine input capacitance 9. calculate stress on rectifiers 10. calculate rms ripple current in output capacitors 11. calculate parameters for coupled inductor 12. calculate inductance for independent outputs 13. calculate output inductance for magnetic amplifier yes yes figure 5. expanded flow chart showing detailed steps in forward design methodology.
AN-30 8 b 12/02 the ripple current in the inductor depends on the converter? operating point. in general, k ? i will change with the duty ratio according to the relationship (4) where k ? i0 is the limit as the duty ratio approaches zero. the expression that relates k ? i0 to the inductance l for a given generic output is (5) where v d(output)c is the voltage on the catch diode when it is conducting. k ? i will be between 0.15 and 0.3 for most practical designs. the k ? i corresponding to the highest input voltage is used for calculations. all dependent quantities should then be computed for the designer? inspection. since the duty ratio at the highest input voltage will usually be very small, k ? i0 is usually a very good approximation to the worst case k ? i . if any outputs have nonzero minimum load, use the minimum load as a guide for the upper limit on k ? i . the best regulation across multiple outputs at minimum load is obtained when (6) where i minimum and i maximum are the respective minimum and maximum average output currents. the common k ? i at full load allows calculation of the inductance. the designer has the option to change any value of any inductor to suit particular requirements. the change in inductance will change the k ? i for that particular inductor. for coupled inductors, k ? i indicates the ripple component of the total ampere turns, not ripple current on any individual winding. step 3. calculate turns ratios for the transformer. turns ratios on the transformer are computed with respect to the main output winding. the primary-to-main turns ratio is fixed by the input and output voltages and the maximum duty ratio, which is limited by the maximum drain-to-source voltage that is set by the designer. the maximum duty ratio to guarantee reset of the transformer is (7) pi-2821-121401 t ? i k ? i = ? i i o dt s i o (1-d) t s t s = 1 f s i figure 6. inductor current showing definition of k ? i . kk d ii ?? = ? () 0 1 k vv li f i output d output c output s ? 0 = + () k i i i minimum maximum ? ? ? ? ? ? ? 2 d v v max reset dropout dsop _ . ? 1074
AN-30 9 b 12/02 from d max in equation (8). in equation (10), l mainlk is the leakage inductance of the secondary winding of the main output, i mainsec is the winding current required to turn off the catch diode of the main output, and f s is the switching frequency. note that in the dc stacked connection for the auxiliary output, the winding for the main output carries the current of the main output plus the current of the stacked auxiliary outputs. next, compute the duty ratio d nom that corresponds to the nominal input voltage. (11) this allows a better estimate of the turns ratio that will produce the desired independent output voltage. (12) finally, compute the turns ratio for the bias winding so that the bias voltage is greater than eight volts. this value is the control pin voltage, 5.8 v, plus the 2.2 v saturation voltage of the optocoupler? phototransistor at v dropout . the turns ratio for the bias winding is then (13) where v dropout is the minimum dc bus voltage for regulation and v db is the voltage drop on the rectifier for the bias voltage. check that the breakdown voltage on the phototransistor of the optocoupler is higher than the bias voltage at the highest transient input voltage. step 4. calculate the primary current. find the peak and rms values for the primary current. this is a preliminary estimate from the system parameters. it allows the designer to assess the suitability of his application for topswitch-gx as early as possible. figure 7 shows typical primary current waveforms for forward converters with and without a magnetic amplifier post regulator. figure 7(a) is without a magnetic amplifier, whereas figure 7(b) shows the effect of one magnetic amplifier post regulator. topswitch-gx determines the duty ratio d to regulate the main output, whereas the post regulator sets d ma independently by its own local feedback to regulate the output voltage from the magnetic amplifier. n vv vv d d vv p dropout ds main dmainc max max main dmainf = ? + () ? ? ? ? ? ? ? ++ 1 n vvd vv p dropout ds max main dmain = ? () + d vv v n vv nom main dmainc nom p dmainf dmainc = + ? + n vv v vv aux aux dauxc auxref main dmainc = + ? + d mainlk mainsec main max s li v df = nn v v bp db dropout + ? ? ? ? ? ? 8 volts n vvd v d vvdv d ind ind dindf nom dindc nom main dmainf nom dmainc nom = ++ ? () ++ ? () 1 1 where v dropout is the dc bus voltage at the end of the holdup time and v dsop is the maximum drain-to-source voltage on the topswitch-gx during operation. the minimum recommended value for v dropout is 130 v, while v dsop is usually less than the breakdown voltage of 700 v by a comfortable safety margin. a safety margin of 15% is typical, giving 600 v for v dsop . the maximum duty ratio for the converter occurs at v dropout . this must be reduced as a function of line voltage from the dc max of topswitch-gx by external circuitry in step 15. the recommended maximum duty ratio d max for the forward converter application depends on the operating input voltage range. for a 3:1 operating range (v max :v dropout ) 70% is typical. as the operating range reduces so does the value of d max . for a 2:1 operating range a value of 50% would be selected. first, compute the turns ratios for the primary and the auxiliary winding. the turns ratio on the primary of the transformer is (8a) where v ds is the average drain-to-source voltage during the on-time of topswitch-gx : when v dmainf and v dmainc are the same value v dmain , this equation simplifies to: (8b) the turns ratio for the auxiliary winding is (9) equation (8) is valid for systems where the leakage inductance of the transformer is negligible. this is a reasonable assumption because the leakage inductance must be minimized for low power dissipation and proper operation of the clamp circuit. leakage inductance reduces the effective duty ratio on the secondary circuits by delaying the turn-off of the catch diodes. the effect can be significant in designs with very high output currents. to compute the turns ratio for the primary winding when leakage inductance is a consideration, subtract the constant (10)
AN-30 10 b 12/02 the computation is simply the reflection of peak currents in the secondary circuits by the ideal turns ratios of the transformer. using the principle that the sum of the ampere turns for an ideal transformer is zero, the instantaneous primary current for a transformer with w secondary windings is just (14) where i j is the current in the secondary winding with turns ratio n j . thus, for a transformer with three secondary windings, the primary current would be the sum i 1 n 1 +i 2 n 2 +i 3 n 3 divided by the turns ratio of the primary. note that since all turns ratios are defined with respect to the main output winding, the turns ratio of the main output winding is 1. equation (14) may also be used with the actual number of primary turns n p substituted for the turns ratio n p , and the actual secondary turns n j substituted for the turns ratios n j . this estimate does not include the effect of magnetizing current in the transformer, which will be determined after the transformer is designed. the magnetization current will raise the peak value of this estimate by typically less than 10% worst case. the computation in pi expert includes the ripple current in the output inductors to find the peak primary current. ripple current is ignored to calculate the rms value. the resulting error in the rms current is less than 1% for practical values of inductance and current. the rms current is computed at the duty ratio that corresponds to v acmin because worst case steady- state resistive losses occur at that operating point. step 5. choose the appropriate topswitch-gx device. select a topswitch-gx according to the requirements for peak primary current and acceptable power dissipation. for operation of the converter in continuous conduction mode it is recommended to operate the device at no more than 80% of its current limit for ordinary thermal design. to reduce device dissipation it is possible to use a topswitch-gx device that has a lower r ds(on) when the current limit is adjusted accordingly. lowering i limit externally (using a programming resistor to the x pin), takes advantage of the lower r ds(on) of the larger device while maintaining the same level of overload protection. the external current limit reduction factor is (15) where 0.4 k i 1.0, and is set by the value of a resistor connected between the x pin and source pin. refer to the topswitch-gx data sheet for details. with external current limit reduction, the actual (external) current limit is (16) pi-2822-121401 t s = 1 i p i p i pp i pp dt s (1-d) t s (a) (b) dt s d ma t s (1-d)t s 0 0 t t f s t s = 1 f s figure 7. typical primary current waveforms for a converter without magnetic amplifier (a) and with a mag amp (b). k i = external current limit data sheet current limit iik xlimit limit i = i n in p p jj j w = = 1 1
AN-30 11 b 12/02 remember to check the maximum and minimum tolerance on i limit from the data sheet for the selected device. allow margin to guarantee that the peak primary current i pp is less than the minimum value of i xlimit at high temperature. with minimum device i limit , check that (17) adjust the system specifications if the peak current is too high for the largest device. while some specifications are fixed, others are adjustable at the discretion of the designer. raising the minimum input voltage will give lower peak current. step 6. design the transformer. the transformer design can be either completed in-house or delegated to a qualified supplier of custom magnetics. an outside supplier needs to know the turns ratios and the recommended restrictions on flux density to start a design. even if the ultimate design will be done outside, it is beneficial to do a rough design in-house. a proposed design with actual numbers of turns on each winding will reduce the time required to obtain a satisfactory transformer. the maximum recommended flux density for this application is (18) and the recommended maximum change in flux density per switching period (ac flux density) is (19) the constraint on b m sets the minimum number of turns for a particular core, while the limit on b peak restricts the maximum transient duty ratio. although peak flux density under steady- state conditions can be calculated, the designer should allow sufficient margin to avoid saturation under transient conditions. to start the design, select a core that is likely to meet the size and efficiency requirements of the application. since the voltages and turns ratios are determined, all that remains is to find the actual number of turns and the size of wire for each winding. compute the minimum turns for the main output. (20) where a e is the effective area of the core. units in the above expression are volts, tesla, meter 2 and hertz. round n main upward to the next integer value. compute the turns for the other power windings. (21) round n p downward to the next integer. round n aux and n ind to the nearest integer. compute the turns for the bias winding. (22) round n b upward to the nearest integer value. designers should use copper foil instead of wire for windings of few turns that carry high current. it is very important to the success of the design to minimize leakage inductance. compute an estimate of the peak magnetizing current. the primary inductance in henries is (23) where 0 is the permeability of free space, a e is the effective area, l e is the effective path length in the core and l g is the length of the air gap (see zero gap transformer section). the dimensionless relative permeability r is given by (24) units in the above two expressions are the si basic units with the exception of inductance coefficient a l , which has the conventional units of nh/turn 2 . with no gap, the primary inductance in henries is simply (25) now the peak magnetizing current is given by (26) units in the above expression are amperes, volts, henries and hertz. the magnetizing current should be less than 10% of the primary current for reasonable power dissipation in the clamp circuit. nnn pp main = nnn aux aux main = nnn ind ind main = l an p ep e r g = + 0 2 l l r le e a a = l 400 lan pnogap lp ? = ? 29 10 iik pp limit i = 096 1 . for iik pp xlimit i < 086 1 . for b peak 03 3000 .( ) tesla gauss i vd lf mp min max ps = b m 02 2000 .( ) tesla gauss nn v v bp db dropout = + ? ? ? ? ? ? 8 volts n vv baf main main dmainf mes +
AN-30 12 b 12/02 estimate the power lost in the core from the manufacturer? data on the core material, operating frequency and b m . copper losses may be estimated from the resistance and rms current in each winding. if the estimates indicate excessive loss, repeat the design with a larger core. zero gap transformers for highest efficiency in this application with the simple zener clamp circuit, it is recommended that the transformer core have no air gap. while an air gap reduces the remnant flux density and stabilizes the primary inductance, it increases the stored energy that must be processed by the clamp circuit. with the use of a suitable reset scheme, transformer saturation is not a problem in the absence of an air gap. using this methodology and the recommended clamp scheme, the design restricts peak flux density and the clamp circuit produces negative magnetizing current during reset. the negative magnetizing current during reset prevents flux build-up in the transformer during successive switching periods. even with no intentional gap in the transformer core, mechanical imperfections will always give a finite effective gap (when calculating with pi expert a value of 0.02 mm is used). if an air gap is desired for other reasons, it should be as small as possible. step 7. check primary current. use the actual number of turns from the design of the transformer to compute the peak and rms current on the primary. primary current was estimated in step 4 with an ideal turns ratio before the transformer was designed. add the peak of the magnetizing current to obtain actual peak of the primary current under steady-state conditions. designers should be aware that the primary current observed on prototype hardware may be lower than predicted because the circuit that resets the flux in the transformer allows a negative average magnetizing current, as mentioned previously in step 6 in the section on zero gap transformers. the design, however, must allow for conditions when the magnetizing current adds to the reflected secondary currents. step 8. determine the input capacitance for holdup time. the holdup time must be specified at a minimum voltage v holdup . this is often, but not always v min . for maximum flexibility, this methodology allows the designer to determine the value of input capacitance required to obtain a given holdup time from an arbitrary input voltage. if a dc voltage is specified to mark the beginning of the holdup time, the minimum required input capacitance is (27) where p o is the total output power that corresponds to the efficiency at the dc bus, dc and t h is the holdup time. if an ac voltage v acholdup is specified to mark the beginning of the holdup time, the minimum required input capacitance (no doubler) is (28) where t c is the conduction time of the ac input rectifiers and f l is the frequency of the ac power line. again, note that t c will increase significantly if the design has passive pfc. the efficiency dc excludes losses in the ac input circuit and emi filter. no power is dissipated in the ac input circuit during the holdup time because the ac input is disconnected. the lower system efficiency that includes the ac input losses would give a value of c in that is larger than required. compare the value from equation (27) or (28) with the estimate for c in in step 1. adjust c in in step 1 and repeat the calculations until the computed value is approximately the same as in step 1. step 9. calculate stress on rectifiers. pi expert calculates voltage and current stress on rectifiers for guidance in selection of appropriate components. the recommended derating factor for peak inverse voltage is 80%. derating for the currents is generally not necessary. thus, the recommended voltage rating for the input bridge rectifier is (29) current ratings for rectifiers are average values, not rms. the current rating for the bridge rectifier is computed from (30) where v ll is the average dc bus voltage at the lowest steady- state line voltage (no doubler). (31) c pt vv in oh dc holdup dropout ? () 2 22 vv pivac acmax = 125 2 . i p v davbr o dc ll = c p tt f vv in o dc hc l acholdup dropout ? () + ? ? ? ? ? ? ? ? ? ? ? 2 2 1 2 22 vvv p f t c ll acmin acmin o l c dc in =+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 1 2 2
AN-30 13 b 12/02 output. the computation is based on k ? i , which considers the total ampere turns of the coupled inductor, not just the current in one winding. the inductance of the winding for the main output, valid for only the dc stacked configuration, is (34) pi expert gives the designer the turns ratio, the total ampere turns, and the peak energy stored in the inductor. the designer has the option to change these parameters by adjustment of the k ? i for each inductor. these quantities assist the designer to obtain an appropriate inductor of either his own design or one from a qualified supplier. bench evaluation of the prototype will determine if fine adjustment of the turns is necessary in the final configuration. step 12. calculate inductance for independent outputs. calculation of the inductance for independent outputs is straightforward and similar to the computation of the parameters for the coupled inductor. design of the component is simplified because there is no turns ratio associated with an inductor that has only one winding. pi expert computes the inductance and the peak stored energy. this information is useful for selection of magnetic cores from catalogs. step 13. calculate output inductance for the magnetic amplifier. pi expert computes the output inductor for a magnetic amplifier post regulator in the same way as for an independent output. it does not address the magnetic switching element. step 14. adjust output inductors if necessary. the designer may modify the k ? i of any inductor to accommodate special requirements. if the value or the estimated physical size of the computed inductor is not satisfactory, adjust the individual k ? i to achieve the desired result. step 15. calculate component values for external reduction of dc max . the maximum duty ratio (dc max ) of topswitch-gx must be restricted to avoid saturation of the transformer during transient loading. a network of four resistors and a capacitor (r a , r b , r c , v z , r d and c vs in figure 1 and figure 1 of appendix b) determines a variable upper limit on the duty ratio. adjustment of the maximum duty ratio with input voltage allows enough deviation beyond the steady-state operating point to respond to transients while maintaining enough time in every switching cycle for the transformer to reset. i ki rms i output = ? 23 n n n n lmain laux main aux = calculations of the peak inverse voltage on the output rectifiers use v max , v dsop , and the output voltages with the turns on the transformer windings. calculations of worst case average current in the catch diodes are with the duty ratio that corresponds to the maximum input voltage. a very good approximation to the average rectifier current is then just the output current. current in the forward diodes is computed with d max . note that with dc stacked outputs, the rectifiers on the main output must conduct the sum of the currents of the main and auxiliary outputs. in general, the stress will be different for the forward diode and the catch diode on the same output. designers will have to consider the one with the greater stress when choosing components that contain both diodes in the same package. step 10. calculate rms ripple currents in output capacitors. currents in the output capacitors are computed at the maximum loads. in continuous conduction mode, the rms ripple current is given by (32) where k ? i is for the particular output under consideration. this expression is reliable for independent outputs and for a main output with no coupled inductors. for converters with auxiliary outputs, equation (32) is only an estimate. ripple currents in the individual windings of coupled inductors depend on magnetic coupling coefficients, parasitic voltage drops, and other quantities in the circuit that are difficult to predict. therefore, designers must evaluate prototype hardware on the bench to confirm that the assumptions of the design are valid for a particular application. step 11. calculate parameters for the coupled inductor. the coupled inductor allows the auxiliary outputs to have better regulation than independent outputs, with the penalty of increased complexity of the inductor. pi expert allows two options for the topology of the auxiliary output. the auxiliary output may be referenced to the main output voltage for the best regulation or to output return when necessary. the reference must be at output return to obtain a negative auxiliary output with a positive main output. turns ratios for the coupled inductor are the same as the ratios for the transformer. the turns ratio of a coupled inductor for a converter that has one auxiliary output is, in terms of the actual number of turns, (33) inductance is computed for the winding that is on the main l vv ki i n n f main main dmainc i main aux laux lmain s = + ++ ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1
AN-30 14 b 12/02 the resistor network also sets the threshold for line under- voltage lockout. protection from over-voltage is generally not a concern for this topology since it uses a zener clamp to provide a hard limit on the drain-to-source voltage. the resistors are matched to the capacitor to form an integrator with an appropriate time constant to give a cycle-by-cycle duty ratio limit. the integration of the voltage on the bias winding gives the external duty ratio limit a desirable relationship to the flux in the transformer. the circuit adjusts the duty ratio limit to set an upper bound on the volt-second product, and to balance the volt-second product during topswitch-gx on and off times. the dynamic nature of the circuit allows greater freedom and precision in the design without interference from the line over-voltage threshold limit. figure 1 shows the locations of resistors r a , r b , r c and r d with capacitor c vs . several important quantities related to their values are illustrated in figure 8. the broken vertical lines in figure 8 mark the boundaries of the dc bus voltage for minimum and maximum operating voltages, the line under- voltage lockout threshold, and the lowest input voltage that will guarantee regulation of the output. the broken horizontal line shows the maximum guaranteed duty cycle of topswitch-gx . a value of 74% is recommended for design. the lowest curve is the duty ratio d that corresponds to steady- state operation at a given input voltage. the straight line with negative slope is the maximum duty ratio d reset that will still guarantee reset of the transformer for a given v dsop . the converter must always operate with d less than d reset to avoid saturation of the transformer. the curved line between the d and d reset lines is the external duty ratio limit d xmax that is set by the resistors. the designer must choose the components to set the curve of d xmax at a desired position between the boundaries of d reset and d for a given set of specified voltages. pi-expert prompts the user to enter several parameters that are important to the computation of the resistor values. some parameters are from the topswitch-gx data sheet while others are design choices. the software suggests default and typical values. the designer can enter maximum and minimum values to check worst case situations. the components are calculated to satisfy the constraints of four parameters: d xdo (external duty ratio limit at v dropout ), d xhl (external duty ratio limit at v max ), v uvlo (input voltage where the topswitch-gx starts switching), and the maximum transient input voltage v ov that is greater than v max . pi-2823-121701 d ll_actual d xmax d ll_reset d reset d hl_reset d hl_actual v in dc max d 74% 100% 0% d max_reset d xdo d max_actual d xhl v dropout v uvlo v min v max duty ratio (%) figure 8. boundaries of voltages and duty ratio related to the selection of r a , r b , r c and r d with c vs in figure 1.
AN-30 15 b 12/02 voltage, and the voltage on the l pin as shown in figure 1. the zener diode is chosen as required to raise the curve of d xmax at the low input voltages. it may not be necessary in all applications. the zener voltage is 6.8 v in this example. next, select a value for d xhl that is between d hl_actual and d hl_reset . (40) (41) find the range of permissible values for d xdo . to compute the upper and lower bounds on d xdo , define the intermediate variable k xdo. (42) the upper bound for d xdo is then (43) and the lower bound for d xdo is (44) choose an appropriate value for d xdo between d max_reset and d max_actual that also satisfies the boundaries of (43) and (44). next, compute the intermediate constants r 1 and r 2 . (45) while there are four resistors, only three are unknown because r a and r b are identical by definition. they are connected in series to keep the voltage across each one below its maximum rating. the three unknown resistors and one capacitor make four unknown quantities that are determined by the four constraints. figure 8 illustrates the general case where d xdo is between the actual duty ratio d max_actual and d max_reset at the input voltage v dropout . if the converter is not required to respond to transient loads at the end of the holdup time, d xdo and d max_actual can be set to d max_reset . since response to transient loads is usually required at v max , the designer will want to set d xhl at a comfortable margin between d hl_actual and d hl_reset . begin with the computation of values for r a and r b to set the line under-voltage threshold v acuv . (35) where v acuv is the ac input voltage (non-doubled) required for the converter to start, and i uv is the line under-voltage threshold current of the l pin of topswitch-gx from the datasheet. choose the nearest standard resistor value for r a and r b . define intermediate variables to make the expressions easier to write and interpret. (36) (37) (38) (39) in equation (36), d il1 and d il2 are respectively the values of dc max at currents i l1 and i l2 into the l pin. obtain these values from the data sheet. use the typical values at first. then check that the circuit will perform properly at the high and low ends of the tolerance range. in equation (37), d il is the value of dc max at current i l into the l pin. use the same d il1 with i l1 or d il2 with i l2 as in equation (36). either pair will give the same result. i ld0 has a physical interpretation that cannot be realized: if the duty ratio reduction characteristic continued along its linear slope, it would reach zero at the current i ld0 . the voltages v db , v z and v l are respectively the forward drop of the rectifier in series with the zener diode and r c , the zener rr v i ab acuv uv == 2 2 rrr ab a b + i d m i ld il il l 0 + vvvv bzl db z l ++ d vv vv n n vv hl actual main dmainc max ds s p dmainf dmainc _ = + ? () ? + d v v hl reset max dsop _ = ? 1 kmi v r d m v n n v v n n v xdo il ld max ab xhl il dropout b p bzl max b p bzl ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 dmi v r k xdo il ld dropout ab xdo < ? ? ? ? ? ? ? ? 0 d mi v r k d xdo il ld dropout ab xdo xhl > ? ? ? ? ? ? ? + 0 1 m dd ii il il il ll ? ? 12 21 r v n n vd i v r d m dropout b p bzl xdo ld dropout ab xdo il 1 0 ? ? ? ? ? ? ? ??
AN-30 16 b 12/02 figure 9. external under-voltage lockout circuit. pi-2824-121701 topswitch-gx control pin topswitch-gx x pin topswitch-gx source pin remote on/off r uvc r uva 5 k 3.3 k q1 2n3906 v in v b r uvb r v n n vd i v r d m max b p bzl xhl ld max ab xhl il 2 0 ? ? ? ? ? ? ? ?? r rr dd d xdo xhl = ? ? 12 rrdr c xdo d = ? 1 v i rr acuv uv ab =+ () 2 d vvvv v max bbac a = ++ 2 4 2 v r m a d il = vv ir r m v r r n n b bzl ld d c il in d ab b p =+ ?? + ? ? ? ? ? ? 0 vri v r ccld in ab = ? ? ? ? ? ? ? 0 ddmii xov il il ov l = ?? () c i v r dtt kir vs ov ov ab xov s ron ovhys ovhys d = ? ? ? ? ? ? ? ? () ? () () 1 (50) where (51) (52) (53) now choose an appropriate value for the capacitor. proper choice of the capacitor allows the converter to operate safely with transient input voltages greater than v max . the line overvoltage feature of topswitch-gx is not used in the conventional fashion in this application. the circuit operates in an over-voltage mode that reduces the maximum duty ratio further by reduction of the switching frequency. the value of the capacitor c vs is chosen to give the desired behavior in the over-voltage mode. select an input voltage v ov greater than v max that marks the onset of over-voltage operation. then compute the maximum duty ratio d xov that corresponds to the specification in the topswitch-gx data sheet for the line over-voltage threshold current i ov . (54) here d il , m il and i l are the same as in equations (36) and (37). finally, compute the capacitor value as (55) where t s is the switching period 1/f s in normal operation t r(on) is the remote on delay i ovhys is the hysteresis of the iov threshold k ovhys is a constant selected by the designer. the first three parameters are taken from the data sheet. the constant k ovhys is selected to provide sufficient ripple voltage (46) compute the values for the resistors r d and r c . (47) (48) select the nearest standard resistor values for r c and r d . verify that the parameters are within the desired range with the actual component values. (49) this is the ac input voltage (non-doubled) where the converter will begin to operate. the external duty ratio limit at any dc bus voltage v in may be computed from the expression
AN-30 17 b 12/02 resistor that can dissipate p ruva watts. (61) a typical resistor for this purpose will have a power rating of p ruva = 125 mw. choose the nearest standard value for r uva . then compute r uvb and r uvc . (62) (63) choose the nearest standard values for r uvb and r uvc . then check v acuvl and v acuvx with the actual resistor values. on the capacitor for reliable operation of the circuit. the recommended range for k ovhys is 3 to 5. choose the nearest standard value for capacitor c vs . these expressions to compute the component values have been simplified for ease of presentation. some variables related to parasitic elements have been ignored. if any of the results are not satisfactory, choose different standard values for the resistors or a different voltage for the zener diode. gross deviations from the desired results may require different values for the parameters chosen at the beginning of this step, since some sets of parameters may not be compatible. step 16. calculate values for resistors in optional external under-voltage lockout circuit. the resistor network that determines the characteristics of the external duty ratio limit sets the minimum voltage where the converter begins to operate. the contributions of current from the bias voltage create too much hysteresis for the circuit to be useful as an under-voltage detector after the converter begins to operate. therefore, the external under-voltage circuit in figure 9 is recommended for applications where a positive turn- off threshold is desired. choose a value v acuvl for the turn-off threshold and a value v acuvx that is approximately midway between v acuvl and v acuv : (56) the corresponding dc bus voltages (non-doubled) are (57) (58) (59) define the intermediate variable v 1 that considers the voltage v c(shunt) on the control pin and the base-emitter voltage on the transistor. (60) compute the approximate value of r uva to meet the constraint of maximum power dissipation. assume a 50% derating for a figure 10. recommended clamp circuit. pi-2825-121701 d s c control control topswitch-gx n main d1 vr1 c cp r cs c cs n p v in vr2 vr3 primary return vv uvx acuvx = 2 vvv acuvl acuvx acuv << vv v c shunt beq 11 = ? () rr n n vv vv uvb uva b p uvl uvx uvl = ? ? ? ? ? ? ? ? ? ? ? ? 1 rr v v uvc uva uvx = ? ? ? ? ? ? 1 r v p uva max ruva = 2 2 vv uvx acuv = 2 vv p f t c uvl acuvl o l c dc in = ? ? ? ? ? ? ? ? 2 2 1 2 2
AN-30 18 b 12/02 (64) (65) (66) if v acuvl and v acuvx are not satisfactory, adjust the values of the resistors. step 17. choose components for the clamp circuit. figure 10 shows connections for the elements of a zener clamp circuit that is suitable for many applications. capacitor c cp , diode d1 and the string of zener diodes are on the primary side of the transformer. resistor r cs and capacitor c cs are on the secondary side of the transformer. this arrangement limits the voltage on the drain of the topswitch-gx to approximately the sum of the voltages of the string of zener diodes. it also recovers most of the energy from leakage inductance and magnetization inductance, and returns it to the input or delivers it to the output. select the zener diodes to limit the drain voltage to v dsop . choose the voltage, size and number of diodes in the string to achieve the desired v dsop and to handle the power dissipation. this arrangement is adequate for applications where the clamp circuit dissipates less than 5 w. capacitor c cp supplements the natural stray capacitance on the drain node to absorb energy that comes mostly from the leakage inductance. the value must be selected empirically because it is difficult to predict natural stray capacitance and leakage inductance accurately enough to calculate a proper value. energy not absorbed by the capacitance will be dissipated in the zener string, so c cp cannot be too small. if c cp is too large, its voltage will change too slowly to allow the transformer to reset during transients. typical values for c cp are in the neighborhood of 2 nf. diode d1 must be a slow recovery type such as a 1n5407. the recovery of d1 removes enough charge from c cp to stabilize its voltage and to discharge some of its stored energy into the primary of the transformer. this energy returns to the input on the next switching cycle. pi-2826-121901 r5 r6 r7 r1 r3 r4 c2 r2 c1 rtn v main v aux n main n p u2 c f l f u1 tl431 figure 11. general configuration of feedback circuit for forward converter with topswitch-gx. v v r r r r n n uvl uvb uvc uvb uva b p = + ? ? ? ? ? ? + 1 1 v v p f t c acuvl uvl o l c dc in =+ ? ? ? ? ? ? ? 2 2 1 2 v vr r acuvx uva uvc =+ ? ? ? ? ? ? 1 2 1
AN-30 19 b 12/02 the remaining components are connected across the forward diode on the main output. energy from leakage inductance on the secondary and magnetization inductance of the transformer charges c cs when the topswitch-gx turns off. the energy from c cs is delivered to the output during the next switching cycle. resistor r cs provides damping for oscillations that would otherwise occur from the resonance of c cs with stray inductance. typical values are in the neighborhood of 0.1 f for c cs and 1 ? for r cs . the resistor must dissipate power that corresponds to the charge and discharge of c cs each cycle. it typically will dissipate less than 1 watt. proper values must be determined empirically from evaluation of prototype hardware. step 18. choose components for the feedback circuit. the pulse width modulator in topswitch-gx sets the duty ratio according to the current into the control pin. topswitch-gx senses the drain current for protection only, and does not use it for control purposes. thus, forward converters with topswitch-gx operate with a voltage-mode control that modulates the converter? duty ratio directly according to an error signal from the regulated output voltage. voltage mode control provides sufficient loop bandwidth and is fully able to meet all the specifications for pc main and other high power applications. the general configuration of the feedback circuit for a forward converter with topswitch-gx is illustrated in figure 11. it shows a typical connection of a tl431 voltage regulator with an optocoupler and components for frequency compensation. there is an optional connection to v aux to improve the regulation of the auxiliary output by sharing regulation with the main output. this general technique is common in all types of multiple output regulators. while the design of the feedback loop is beyond the scope of this application note, it is useful to consider the general circuit of figure 11. the components are chosen to provide regulation of output voltages and to shape the frequency characteristics of the control loop. proper design of the feedback components is important not only for the stability of the system, but also for transient response of the output. inductor l f with capacitor c f reduces high frequency noise on the main output. as such, it introduces phase shift in the small signal response that would make loop compensation difficult if the only feedback for the main output were taken from the voltage on c f . to avoid difficulties with the feedback loop, information about the main output is taken from two places. low frequency information that is most important to the dc regulation comes mainly through the path formed by resistor divider of r5, r6 and r7. the voltage on r7 is the reference voltage of the tl431 when v main and v aux are at their desired values. high frequency information that is most important in the transient response comes through the path formed by the optocoupler? diode and r2. this same technique is commonly used with topswitch-gx in flyback converter applications. the values of r1, r3, r4, c1 and c2 are chosen to shape the frequency response. the choices are influenced by the components on the control pin and equivalent series resistance of the output capacitor, which can be important features of the loop gain. designers must make proper measurements of loop gain and transient response on prototype hardware to confirm that the converter performs as desired under all specified conditions. evaluation of prototype hardware the design that results from the steps of the previous section contains the uncertainties of the initial assumptions. performance must be validated with measurements on prototype hardware before the design is complete. at this stage in the procedure, the designer will have enough information to build a circuit that will operate at nominal conditions for evaluation on the bench. the designer must test the circuit at all the limits of specified performance. measurements will indicate which changes to the original assumptions are necessary. a successful design is obtained after repetition of the procedure with parameters adjusted from measurements on the hardware. the evaluation should include observation of the drain-to- source voltage on topswitch-gx under steady state operation and transient conditions. apply power to the converter slowly with minimum loads. then exercise the loads on the outputs in different combinations, first at the nominal input voltage and then at the extremes of input voltage. observe the behavior at various static loads before going to transient loading. check for excessive power dissipation in the clamp circuit. a useful technique is to monitor the average current in the string of zener diodes in the clamp circuit with a low value resistor in series. a capacitor in parallel with the resistor will develop a voltage proportional to the average current through the diodes. the product of this voltage and the clamp voltage gives an indication of the power dissipation in the zener diodes. monitor the drain current when the output has steady-state overload and during transient loading. the waveform will provide important information about the operation of the converter and the limits of the design. check that the current
AN-30 20 b 12/02 limit of the topswitch-gx is sufficient for all the specified conditions. check that the transformer does not saturate under all steady- state combinations of line and load. verify the proper design of the circuit to limit maximum duty ratio with the procedure in appendix b. check the ripple on all the output voltages with several combinations of input voltage and output loading, particularly if the design uses a coupled inductor. verify that the under- voltage thresholds are within design limits for startup and for shutdown. key design considerations while the design of forward converters with topswitch-gx has much in common with designs that use discrete transistors and controllers, some important differences must be considered. attention to these items will significantly reduce the time to arrive at a successful design. ? proper clamp circuit is required to control the maximum drain voltage. resonant clamp circuits are not recommended. while the example clamp circuit in this document is suitable for moderate power levels, the circuit will need modification to adapt to applications that require the dissipation of more power. leakage inductance of the transformer affects the power dissipation in the clamp circuit. high leakage inductance will prohibit the use of simple clamp circuits. be aware that a magnetic amplifier post regulator will greatly increase the effective leakage inductance of the transformer. the primary inductance of the transformer affects the power dissipation in the clamp circuit. maximize the primary inductance to reduce the magnetizing current and the energy that must be processed by clamp circuit. use a slow diode for the rectifier d1 in the clamp circuit. a fast diode will greatly increase the amount of energy that the clamp must dissipate. remember that the components r cs and c cs on the secondary are important components of the clamp circuit. failure to include this network will cause excessive power dissipation in the clamp components on the primary. confirm in bench evaluations that c cp in the clamp circuit on the primary is not too large. perform transient load tests at low and high input voltages. monitor the drain voltage waveform for volt-second balance to be certain that the transformer does not saturate. check the temperature of the zener diodes vr1, vr2 and vr3 in the clamp circuit under maximum load at low input voltage and with repetitive transient loading. if the power supply does not have a latching shutdown for fault conditions, check it under a sustained short circuit on the output. there could be excessive heating if c cp is too small, the primary inductance of the transformer is too low, or if the leakage inductance it too high. ? atch the current limit to the load. use the x pin to program the current limit lower, especially if a larger topswitch-gx is selected for thermal or efficiency reasons. references [1] r. w. erickson and d. maksimovic, fundamentals of power electronics, second edition. kluwer academic publishers, 2001. isbn 0-7923-7270-0. [2] colonel wm. t. mclyman, transformer and inductor design handbook, second edition. marcel dekker, inc., 1988. isbn 0-8247-7828-6. [3] colonel wm. t. mclyman, magnetic core selection for transformers and inductors, a user? guide to practice and specification, second edition. marcel dekker, inc, 1997. isbn 0-8247-9841-4. [4] colonel w. t. mclyman, designing magnetic components for high frequency dc-dc converters. kg magnetics, inc., 1993. isbn 1-883107-00-8. [5] micrometals inc., 5615 e. la palma avenue, anaheim, ca 92807 usa; www.micrometals.com . [6] magnetics, p.o. box 391, butler, pa 16003-0391 usa, www.mag-inc.com .
AN-30 21 b 12/02 appendix a t able of nomenclature name in AN-30 description difference between actual and effective duty ratio that results from leakage inductance in the transformer. total system efficiency (lower case greek letter eta). efficiency excluding losses in ac input circuit and emi filter. used in computation of input capacitance required for holdup time. dc . permeability of free space (4 x 10 -7 h/m). relative permeability of ferrite core material (lower case greek letter mu). dimensionless. effective cross-sectional area of transformer core. inductance coefficient of ungapped transformer core. maximum ac flux density in transformer core. maximum flux density in the power transformer. total bulk capacitance at the dc input to the converter. capacitor in circuit for external reduction of dc max . diode in primary clamp circuit. duty ratio of topswitch-gx at a given operating point. duty ratio at the highest operational dc input voltage v max . maximum duty ratio to guarantee reset of the transformer at dc input voltage v max . maximum duty ratio at current i l . the dc max at current i l1 into the l pin of topswitch-gx . the dc max at current i l2 into the l pin of topswitch-gx . duty ratio at lowest steady state dc input voltage v min . maximum duty ratio to guarantee reset of the transformer at dc input voltage v min . the duty ratio of the magnetic amplifier. the maximum duty of t opswitch-gx at the lowest operational dc input voltage v dropout . actual duty ratio of topswitch-gx at the lowest operational dc input voltage v dropout . maximum duty ratio to guarantee reset of the transformer at dc input voltage v dropout . this is less than maximum duty cycle dc max . duty ratio at nominal input voltage. maximum duty ratio to guarantee reset of the transformer at a given operating point. highest maximum duty cycle as set by current into the l pin of topswitch-gx with external components. occurs at dc input voltage v dropout . the lowest maximum duty cycle as set by current into the l pin of topswitch-gx with external components at dc input voltage v max . the maximum duty ratio that corresponds to i ov . maximum default duty cycle of topswitch-gx (see data sheet). ac line frequency. topswitch-gx switching frequency. instantaneous current in secondary winding j of the transformer. output current of the auxiliary output current rating for the bridge rectifier. current into the l pin of topswitch-gx . d dc 0 r a e a l b m b peak c in c vs d1 d d hl_actual d hl_reset d il d il1 d il2 d ll_actual d ll_reset d ma d max d max_actual d max_reset d nom d reset d xdo d xhl d xov dc max f l f s i j i aux i davbr i l
AN-30 22 b 12/02 name in AN-30 description current into the l pin of topswitch-gx to give dc max of d il1 . current into the l pin of topswitch-gx to give dc max of d il2 . intermediate variable to compute values of components in circuit for external reduction of dc max . output current of the main output. output current of the magnetic amplifier on the secondary winding for the main output. current in the secondary winding of the main output required to stop conduction of the main catch diode. maximum average output current for a specific output. minimum average output current for a specific output. peak value of the magnetizing current of the transformer referred to the primary winding. output current of the independent output. average current on a given output. line over-voltage threshold current for the l pin of topswitch-gx (see data sheet). hysteresis of the i ov threshold (see data sheet). instantaneous current in the primary of the transformer. peak current in the primary of the transformer. rms current in an output capacitor. . hysteresis in line under-voltage threshold current (see data sheet). topswitch-gx current limit with external current limit reduction. external current limit reduction factor. maximum theoretical value of the ripple current factor for an output inductor, approached as d goes to zero. ripple current factor for an output inductor at a given operating point. constant used to compute value of capacitor in circuit for external reduction of dc max . intermediate variable to compute values of components in circuit for external reduction of dc max . effective path length of transformer core. length of air gap in transformer core. inductance of the coupled inductor measured at the winding for the main output with other windings open. leakage inductance of the transformer on the secondary winding for the main output. output inductor in the magnetic amplifier regulator on the secondary winding for the main output. maximum duty cycle reduction slope (a positive number). inductance of the primary of the transformer with all other windings open. turns ratio of the auxiliary output winding with respect to the main output winding. turns ratio of the independent output winding with respect to the main output winding. turns ratio of secondary winding j of the transformer with respect to the main output winding. turns ratio of the primary winding with respect to the main output winding. actual number of turns for secondary winding j on the transformer. number of turns for the auxiliary winding on the transformer. number of turns for the bias winding on the transformer. number of turns for the independent winding on the transformer. number of turns for the main output winding on the transformer. i l1 i l2 i ld0 i main i mainma i mainsec i maximum i minimum i mp i ind i output i ov i ovhys i p i pp i rms i uvhys i xlimit k i k ? i0 k ? i k ovhys k xdo l e l g l main l mainlk l mainma m il l p n aux n ind n j n p n j n aux n b n ind n main
AN-30 23 b 12/02 n p p o p ruva r 1 r 2 r a r ab r b r c r d r lmain r p r smain r uva r uvb r uvc t c t h t r(on) t s v 1 v a v b v c v acholdup v acmax v acmin v acnom v acuv v acuvl v acuvx v aux v auxref v bzl v dauxc v db v dindc v dindf v dmain name in AN-30 description number of turns for the primary winding on the transformer. total output power of the power supply. power dissipation in the resistor r uva . intermediate variable to compute values of components in circuit for external reduction of dc max . intermediate variable to compute values of components in circuit for external reduction of dc max . resistor in the network that sets the line under-voltage threshold v acuv . intermediate variable to compute values of components in circuit for external reduction of dc max . resistor in the network that sets the line under-voltage threshold v acuv . resistor in circuit for external reduction of dc max . resistor in circuit for external reduction of dc max . resistance of the winding of the output inductor for the main output. resistance of the primary winding of the transformer. resistance of the secondary winding for the main output. resistor in optional external under-voltage lockout circuit. resistor in optional external under-voltage lockout circuit. resistor in optional external under-voltage lockout circuit. conduction time of the bridge rectifier. holdup time. remote on delay of topswitch-gx . (see data sheet). switching period of topswitch-gx , equal to 1/f s . intermediate variable to compute resistors in optional external under-voltage lockout circuit. intermediate variable to compute values of d xmax . intermediate variable to compute values of d xmax . intermediate variable to compute values of d xmax . steady state ac input voltage that corresponds to the beginning of the holdup time. maximum steady-state ac input voltage. minimum steady-state ac input voltage. ac input voltage where independent output voltages should be at their nominal values. minimum ac input voltage where converter must start. ac input voltage where the converter shuts off with optional external uvlo circuit. ac input voltage where the optional external uvlo circuit enables the topswitch-gx when input voltage is rising from zero. voltage on the auxiliary output. reference voltage for the auxiliary output in the dc stacked topology. this is usually v main . intermediate variable in the computation of components for dc max reduction circuit. voltage drop on the catch diode of the auxiliary output when the diode is conducting. voltage drop on the diode of the bias winding when the diode is conducting. voltage drop on the catch diode of the independent output when the diode is conducting. voltage drop on the forward diode of the independent output when the diode is conducting. voltage drop on the catch diode and the forward diode of the main output when the two are identical.
AN-30 24 b 12/02 v dmainc v dmainf v dropout v ds v dsop v holdup v in v ind v l v ll v max v main v mainma v min v nom v pivac v uvh v uvl v uvlo v uvx v z w name in AN-30 description voltage drop on the catch diode of the main output when the diode is conducting. voltage drop on the forward diode of the main output when the diode is conducting. lowest dc input voltage that will guarantee a regulated output. average drain-to-source voltage on the topswitch-gx during its on-time. maximum drain-to-source voltage on the topswitch-gx during operation. dc input voltage that marks the beginning of the holdup time t h . voltage on the bulk input capacitance c in . voltage on the independent output. voltage on the l pin of topswitch-gx with positive current. average dc input voltage at v acmin . maximum dc input voltage, equivalent to the peak value of v acmax . regulated dc voltage on the main output. regulated dc voltage from the magnetic amplifier derived from the secondary winding for the main output. valley of the rectified ac input voltage at v acmin . nominal dc input voltage. midpoint between peak and valley of the ripple voltage on c in when the ac input voltage is v acnom . recommended voltage rating for the bridge rectifier. dc input voltage corresponding to v acuv . dc input voltage corresponding to v acuvl . minimum dc input voltage for topswitch-gx to start, set by resistor on from dc input voltage to l pin. dc input voltage corresponding to v acuvx . voltage of the zener diode in the dc max reduction circuit. number of secondary windings on the transformer.
AN-30 25 b 12/02 appendix b procedure for verifying duty ratio reduction circuit predictions from analytic expressions are only as accurate as their inputs. it is always advisable to confirm the desired operation of circuits with actual hardware before they are released to production. reduction of the maximum duty ratio of topswitch-gx is particularly important in the forward converter application. therefore, users are strongly advised to follow this simple procedure to confirm the correct operation of the circuit to reduce the maximum duty ratio. add the circuits and instrumentation as shown in figures b1 and b2 to the forward converter under evaluation as described in the steps below. this setup allows independent adjustment of the input voltage and the regulated main output voltage while monitoring the current into the l pin. 1. connect the ac input section in the non-doubling configuration. add enough extra bulk capacitance in parallel with c in to make the ripple voltage negligible. alternatively, the converter may be operated from a high voltage dc power supply instead of from the ac source. insert the parallel combination of a 100 ? resistor and a 0.1 f capacitor in series with the l pin. monitor the voltage across the resistor with a digital voltmeter. place a 1 k ? resistor in each lead of the voltmeter to avoid interference from common figure b1. setup to measure current into line-sense (l) pin. l pin current monitor circuit (190 a is 19 mv) digital voltmeter 1 k ? 100 ? to on/off circuit monitor drain current with oscilloscope to determine duty ratio 0.1 f 50 v 1 k ? added bulk cap 1800 f 400 v r c n p n b r d v z c vs r b c cp v in dl sxf c control control pi-2845-112102 u1 top247y rtn to pwm regulator circuit r a c in
AN-30 26 b 12/02 figure b2. circuit to adjust main regulated output voltage to higher value. v vir r d n nr r r d in bzl l d c il b pab d c il = ++ ? ? ? ? ? ? ++ ? ? ? ? ? ? 1 mode noise. monitor the current in the drain pin of topswitch-gx with a current probe and an oscilloscope. connect an adjustable low voltage dc power supply to the feedback circuit as shown in figure b2. 2. set the oscilloscope to read the duty ratio from the waveform of the topswitch-gx drain current. most digital oscilloscopes will provide a direct readout of the numerical value. 3. adjust the low voltage dc power supply to 15 v. 4. operate the converter at full load. adjust v in to the value that corresponds to the duty ratio limit specified in the data sheet for a device at the low end of the tolerance range. the dc input voltage for these conditions is given by (b1) where d il is the minimum dc max at the i l of 190 a, and the other terms are as they are defined in the text and appendix a . 5. adjust the duty ratio to d il by forcing the main output to regulate at a higher voltage. to do this, reduce the voltage of the bench power supply from 15 v until the duty ratio measured from the drain current is d il . 6. verify that the current into the l pin is within 5% of i l . the voltmeter should read 19 mv when i l is 190 a. if it is not possible to adjust the circuit to meet these conditions, the circuit is not guaranteed to operate properly with all devices in the specified range of tolerance. repeat the design with revised parameters. added network to adjust regulated output tl431 rtn opto 1n4148 3.3 k ? 3.3 k ? 0 vdc to +15 vdc adjustable power supply v main + _ start with the adjustable power supply at 15 v. by lowering the output of the external supply a threshold will be reached where the diode will become forward biased. lowering the adjustable supply further will force the main output to a higher regulation voltage. main output regulator pi-2846-041502
AN-30 27 b 12/02 appendix c introduction this appendix describes a worked example that shows how to use the topswitch-gx forward design spreadsheet, to calculate values for key components, such as the input capacitance, transformer number of turns and duty cycle reduction circuitry, used on the ep-12 145 w doubled mains prototype board. the design spreadsheet can be found in the pixls utility as part of the pi expert design tool version 4.0.3 and above. the worked example and spreadsheet uses the same design equations as presented in the design methodology. however, rather than following the flow chart in the methodology, the worked example follows the order of the spreadsheet. thus step (a) in worked example does not correspond to step 1 from AN-30, and so on. since the ep-12 has a doubler input stage, the calculations within this document address the design in the doubled mode. note that both AN-30 and the design spreadsheet assume single input voltage ranges. universal input designs are not supported. step by step example for ep-12 note: all user inputs are in column b and all calculated results are in column f of the spreadsheet. step (a). enter the power supply output specifications: v main , i main , v mainma , i mainma , v aux1 and i aux1 enter the mainwindingoutputvoltage v main = 5 v (vmain, b3) enter the main winding full load current i main = 12 a (imain, b4) enter the mag-amp winding output voltage v mainma = 3.3 v (vmainma, b5) enter the mag-amp winding full load current i mainma = 12 a (imainma, b6) enter the auxiliary winding output voltage v aux1 = 12 v (vaux1, b7) enter the auxiliary winding full load current i aux1 = 4 a (iaux1, b8) step (b). define system requirements: v acmax , v acmin , f l , f s , v o , p o , , t h set minimum ac input voltage = 90 v. (vacmin, b14) set maximum ac input voltage = 132 v (vacmax,b15) line frequency f l = 50 hz (fl, b19) power supply efficiency estimate: if no better value available use 75%. (eff, b22) hold-up time t h = 16 ms (th, b21) set bridge rectifier conduction time. if no better value available use default value t c = 3 ms (tc, b20) step (c). calculation of minimum and maximum dc input voltages: v min , v max the spreadsheet calculates the maximum dc input voltage, v max , at ac high line and minimum dc input voltage v min , at ac low line for which the supply remains in regulation under steady state operating conditions. for the ep-12 prototype, these values are calculated as follows v max = 373 v (vmax, f17) v min = 188 v (vmin, f16) step (d). determine dropout voltage: v dropout the dropout voltage determines the point where the converter looses regulation, at the end of holdup time, due to reaching maximum duty cycle. the dropout voltage, v dropout , and maximum duty cycle are linked. for a higher dropout voltage the designer has to enter a lower value for d max_goal and for a lower dropout voltage the designer should entger higher value of d max_goal . this ensures the operating duty-cycle is within an acceptable range.
AN-30 28 b 12/02 as an initial estimate for a 3:1 operating range (v max : v dropout ), d max_goal = 0.7 and for a 2:1 operating range, d max_goal = 0.5 . in ep-12 prototype the dropout voltage is low, to maximize holdup time, so a relatively high value for d max_goal has been selected. (operating range is 373 v to 132 v or 2.8:1). set dropout voltage v dropout = 132 v (vdropout, f24) set the maximum duty-cycle d max_goal = 0.7 v (dmax_goal, f25) step (e). determine the bulk capacitance: c in the spreadsheet checks for the input capacitance value based on hold-up time and output power. the user should decide on a hold-up time first and then try different values of input capacitance such that no warnings are shown. this indicates that with the chosen capacitor value, it is possible to meet the desired hold-up time. assume 1 f/w for doubled mains applications as a starting point. we thus have c in = 1 f/w x 147.6 w = 147.6 f select next larger standard value. note: the ep-12 design has a double input configuration. a doubler circuit has two capacitors in series, each of which have a value which is twice that calculated above. selecting the next larger standard value for twice 147.6 f, we have 2 x c in = 330 f, 200 v the actual value entered in the spreadsheet is c in = 165 f (cin, b18) step (f). selection of rectifier diode drops (vf): v dmain , v dmainma , v daux1 , v db the spreadsheet automatically selects the type of rectifier (ultra-fast or schottky) based on the output voltage. the corresponding diode drops are listed as follows: the voltage drop on main winding rectifier diode v dmain = 0.5 v (vdmain, f41) the voltage drop on mag-amp rectifier diode v dmainma = 0.5 v (vdmainma, f42) the voltage drop on auxiliary winding diode v daux1 = 0.7 v (vdaux1, f43) the voltage drop on bias winding rectifier v db = 0.7 v (vdb, f45) the values calculated by the spreadsheet may be overridden by entering the desired voltage drop in column b (b41 to b45). step (g). selection of bridge rectifier diode based on peak inverse voltage and average rectifier current : v pivac , i davbr the recommended voltage rating for input bridge rectifier is given in equation (29). v pivac = 467 v (vpivac, f49) current ratings for rectifiers have average values not rms values. the current rating for the bridge rectifier can be calculate d from equation (30) in AN-30. i davbr = 0.714 a (idavbr, f50) step (h). selection of ripple current factor: k ? i k ? i is defined in AN-30. it is a ratio of the ripple in the output current to the average current in the output inductor. this det ermines the size of the output inductor. as recommended in AN-30 choose k ? i between 0.15 and 0.3. for the ep12 design, this value was selected as k ? i = 0.15 (kdi, b27) step (i). selection of topswitch-gx and related parameters: i p , k i , rx, vds the operating peak drain current is calculated as i p = 2.45 a (ip, f84) select an appropriate topswitch according to peak primary current as well as for power dissipation. the top247y was selected and has a minimum current limit of 3.34 a. current limit should be externally programmed to approximately 8-12% above the operating peak drain current, that is i xlimit = i p x 1.11 = 2.45 x 1.11 = 2.712 a.
AN-30 29 b 12/02 the external current-limit reduction factor is given by equation (15) in AN-30 k i = = 0.81 set external current limit reduction factor k i = 0.81 (ki, b35) the external current limit is reduced from 3.34 a to 2.712 a using a current limit-program resistor. the external current limit resistor is calculated by the spreadsheet as rx = 7.78 k ? (rx, f36) topswitch switching frequency fs = 132 khz (fs, d34) on the prototype board an 8.3 k ? resistor was used. the larger value was required to compensate for the additional voltage drop caused by the remote on-off circuit. the spreadsheet also estimates the on state drain to source voltage drop. vds = 8.1 v (vds, f38) step (j). selection of the ?-factor the r-factor is an estimate of percentage of power lost in the transformer windings, diode and pc board trace resistance. typically this value is less than 10% for most well designed power supplies. use this value if no better data are available. r-factor = 9% (rfactor, b61) step (k). selection of number of turns for transformer windings: n main , n p , n aux1 , n b the number of turns for all outputs are calculated by the spreadsheet. in ep-12 these values are as follows: number of turns on main winding n main = 3 (nmain, f64) number of turns on primary winding n p = 45 (np, f67) number of turns on auxiliary winding n aux1 = 4 (naux1, f69) number of bias winding turns n b = 6 (nb, f68) check all outputs on prototype hardware to conform that they are within acceptable limits. step (l). selection of optocoupler and transformer core parameters. selection of optocoupler: v ceo the bias winding should provide a minimum of 8 v on the collector of the photo transistor at the lowest operating voltage. when no external under-voltage circuit is used the lowest operating voltage may be much lower than expected. increase bias turns to increase minimum bias voltage. at higher input voltages the collector voltage should not exceed v ceo , the collector to emitter breakdown voltage. the spreadsheet calculates this maximum blocking voltage imposed on the optocoupler as: v ceo = 49.8 (vceo opto, f120) select an optocoupler with a high blocking voltage. typically a 60 v ( v ceo ) optocoupler is used. transformer core parameters: m, l, bm, bp set safety margin m. use 3 mm for margin wound with 115 vac doubled input. set to zero if triple insulated secondary windings are used. in the ep-12 prototype 3 mm margin is selected. enter margin m = 3 mm (m, b62) calculate the number of primary layers. start with 1 layer, and check for warnings. the spreadsheet calculates the primary side wire cross sectional areas based on number of layers, number of turns and bobbin winding width. in the ep-12 prototype 1 layer corresponds to a wire size of awg 26, but due to skin effect is not fully utilized. using 0.8 layers, does not fill up the bobb in entirely, but has an acceptable winding resistance and current density. enter number of layers l = 0.8 (l, b63) 2.712 3.34
AN-30 30 b 12/02 the spreadsheet also calculates the wire gauge as (awg-28). maximum operating flux density, bm , is the flux density under conditions of full load, and high line. the spreadsheet calculates and returns this value. check that this value is less than 2000 gauss. bm = 1816 gauss (bm, f74) peak flux density is the maximum allowable flux density in the core under transient conditions. this value is also calculated b y the spreadsheet. check that this value does not exceed 3000 gauss. bp = 2884 gauss (bp, f75) step (m). transformer design parameters: verify that the maximum and minimum limits of the topswitch-gx duty-cycle reduction parameters for both high-end and low- end tolerance parts lie within the reset and regulating limits for any given input voltage. reset parameters: dmax reset , dll reset , dhl reset referring to the curve in figure 8 these three parameters define the core-reset curve for the transformer. dmax reset = 0.79 (dmax reset, f145) dll reset = 0.63 (dll reset, f152) dhl reset = 0.36 (dhl reset, f157) max duty-ratio (low-end tolerance part) parameters: dxdo min , dxll min , dxhl min to ensure correct operation with devices at the higher and lower ends of the maximum duty-ratio, the spreadsheet provides calculations assuming tolerance limits. referring to figure 8, the parameters with min correspond to the parameters for the low-end tolerance part. duty-ratios corresponding dropout voltage, low-line input voltage and high line input voltages are listed. these duty-ratios at the corresponding voltages define the lower limit curves for the maximum duty-cycle reduction circuit. this curve should be above the d actual curve. dxdo min = 0.70 (dxdo min, f146) dxll min = 0.55 (dxll min, f150) dxhl min = 0.24 (dxhl min, f155) max duty ratio (high-end tolerance part) parameters: dxdo min , dxll min , dxhl min again, referring to figure 8, the parameters with subscripts max correspond to the parameters for the high-end tolerance part. duty-ratios corresponding dropout voltage, low-line input voltage and high line input voltages are listed. these duty-ratios at the corresponding voltages define the higher limit curves for the maximum duty-cycle reduction circuit. this curve should be below the d reset curve. dxdo max = 0.79 (dxdo max, f147) dxll max = 0.67 (dxll max, f151) dxhl max = 0.35 (dxhl max, f156) to guarantee smooth operation, these 4 curves namely the regulation duty cycle ( d actual ) curve, the low-end tolerance part ( d min ) curve, the high-end tolerance part ( d max ) curve and the core reset ( d reset ) curve should never intersect each other. this guarantees that the power supply will not drop out of regulation and also ensures that there will be no transformer saturation. in the ep-12 example, the parameter dxdo max exceeds parameter dmax reset . this could possibly cause transformer saturation only during load transients or during shut down of the converter, which is not hazardous. regulating duty-ratio parameters: dmax actual , dll actual , dhl actual referring to figure 8, these three parameters correspond to the operating duty-ratio at dropout, low line input and high line i nput respectively. dmax actual = 0.69 (dmax actual, f144) dll actual = 0.40 (dll actual, f149) dhl actual = 0.23 (dhl actual, f154)
AN-30 31 b 12/02 step (n)-step (p). calculation of rms ripple currents in output capacitors, parameters for the coupled inductor and stresses on the rectifier diodes. calculations of rms ripple currents in output capacitors: i rms main , i rms mainma , i rms aux1 the rms currents in the output capacitors, for each individual output is calculated by the spreadsheet. the values for ep-12 supply are as follows: i rms main = 0.52 a (irmsmain, f108) i rms mainma = 0.52 a (irmsmainma, f109) i rms aux1 = 0.17 a (irmsaux1, f110) for the auxiliary output this ripple current calculation is only an estimate. this value varies with the coupling co-efficient, parasitic voltage drops and other quantities which are difficult to predict. choose output capacitors to meet the above ripple current requirements. parameters for the coupled output inductor, and mag-amp inductance: l main , l mainma the turn?-ratio for the coupled choke is the same as that of the transformer. = the inductor is computed by the spreadsheet l main = 10.1 h (lmain, f68) an inductor value of 10.2 h was tried in the ep-12 design. bench evaluation of the prototype for fine adjustment led to satisfactory performance with this value for the inductor. the mag-amp inductance is calculated by spreadsheet. this is calculated as 12.4 h . lmainma = 12.4 h (lmainma, b90) first select the closest standard value. if performance is not satisfactory, a more accurate inductor should be wound. for the ep-12 design a standard 15 h inductor was found to be satisfactory. piv stress on rectifier diodes: vpivmain, vpivmainma, vpivaux1, vpivb the spreadsheet calculates the peak inverse voltage that is imposed on the rectifier diodes. main output rectifier peak inverse voltage = 29.5 v (vpivmain, f114) magamp output rectifier peak inverse voltage = 29.5 v (vpivmainma, f115) auxiliary output rectifier peak inverse voltage = 34.9 v (vpivaux1, f116) bias winding output rectifier peak inverse voltage = 102.1 v (vpivb, f118) choose rectifier diodes with piv ratings typically 120% of the ratings calculated above. n lmain n laux 3 4
AN-30 32 b 12/02 optional under-voltage lockout circuit: r uva , r uvb , r uvc the external under-voltage lockout circuit is shown in figure 9. the circuit sets the minimum input voltage that should be present before the topswitch-gx is enabled. the circuit also sets the voltage at which the converter is shut off during power down. step (q). selection of r uva r uvb & r uvc : under worst-case input voltage conditions power dissipation in r uva must not exceed 150 mw. the spreadsheet calculates the value of this resistor. in ep-12 this resistor is: r uva = 2.23 m ? (ruva, f126) choose closest standard value; r uva = 2.2 m ? , 0.5 w choose v acuvl and v acuv and select r uvb & r uvc : choose a value for v acuvl and v acuv such that v acuvl < v acuvx < v acuv where v acuvx is the voltage at which the external under-voltage lockout circuit enables the topswitch-gx during start-up. this value is automatically calculated by the spreadsheet. set the voltage at which the converter shuts off with the external uvlo circuit, v acuvl = 67 v. enter the voltage at which the converter should begin its steady state operation v acuv = 80 v. this means that the voltage at which the external uvlo circuit enables the topswitch-gx while the input voltage is rising, v acuvx must lie within the limits 67 v AN-30 33 b 12/02 circuit for reduction of maximum duty ratio figure c1 shows the external circuit for limiting the maximum duty cycle of the topswitch-gx . figure c1: components that make up external duty-ratio limiting circuit. step (r). selection of duty-cycle limiting circuit components: r a , r b , r c , r d , v z , c vs selection of r a , r b these resistors provide l pin current that is proportional to the input voltage. the calculation formula for these resistors is as in equation (35) of AN-30. r a = r b = 2.25 m ? . selecting closest standard values: select r a = 2.26 m ? , 0.5 w (ra, f137) select r b = 2.26 m ? , 0.5 w (rb, f138) selection of zener: v z the zener diode increases the dynamic range of operation by allowing the low line duty-ratio to be a higher value, while still avoiding saturation. the zener diode should be used only in designs that operate over a very wide range of duty-cycle. whenever needed, a 4 v-9 v zener diode should be used. in ep-12 this value is set at 6.8 v, as this is the maximum value of the zener that avoids core saturation at low line, while allowing extended operating range. choose any standard low power (500 mw) zener diode. choose 6.8 v zener diode bzx79-c6v8, vz = 6.8 v (vz f134) selection of duty-ratio limits: d xdo , d xhl note that the spreadsheet takes default inputs corresponding to d xdo and d xhl . these values are based on the low-end parts. it can be seen by looking at the curves for core saturation ( d reset ) and the operating duty cycle ( d ), that the attempt here is to place the maximum limiting duty-ratio ( d max ) curve approximately mid-way these two limit curves. figure c2 shows an example curve taken from the design spreadsheet where the d reset limit is violated. figure c3 shows an example where the regulation limit, d actual is violated. selection of overvoltage onset level vov this determines the voltage at which frequency reduction commences. in ep-12 the default value was used. vov = 380 (vov, f135) r a c vs r b bias winding topswitch-gx l-pin topswitch-gx source -pin from dc bus r d r c v z 6.8 v pi-2888-061302
AN-30 34 b 12/02 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 duty cycle parameters (see graph) dro p out dut y -c y cle parameters dmax actual 0.67 o p eratin g dut y c y cle at dc bus dro p out volta g e dmax reset 0.79 transformer reset minimum dut y c y cle at dc bus dro p out volta g e dxdo min 0.68 device min dut y c y cle limit at dc bus dro p out volta g e dxdo ma x 0.78 device max dut y c y cle limit at dc bus dro p out volta g e dll actual 0.46 dut y c y cle at minimum dc bus volta g e dxll min 0.52 dut y c y cle minimum limit at minimum dc bus volta g e dxll ma x 0.64 dut y c y cle maximum limit at minimum dc bus volta g e dll reset 0.69 minimum dut y c y cle to reset transformer at low line hi g h line dut y -c y cle parameters dhl actual 0.23 dut y c y cle at minimum dc bus volta g e dx hl min warnin g 0.13 !!! < 103% of o p eratin g dut y c y cle at max dc bus volta g e: increase dxhl min, decre dxhl max 0.24 dut y c y cle maximum limit at maximum dc bus volta g e dhl reset 0.36 minimum dut y c y cle to reset transformer at hi g h line 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 100 150 200 250 300 350 400 450 dc bus voltage, v d_actual d_reset dx_min dx_max v_ov v_dropout duty cycle vs dc bus voltage 0.9 0.6 0.5 0.8 0.7 100 150 200 250 300 350 400 450 dc bus voltage, v duty cycle vs. dc bus voltage duty cycle pi-2892-121302 0 0.3 0.2 0.1 0.4 dx max exceeds d reset which means transformer saturation may occur at this point v dropout v ov d reset dx max dx min d actual figure c2. example of d reset limit violation.
AN-30 35 b 12/02 figure c3. example of d actual (regulation) limit violation. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 duty cycle parameters (see graph) dro p out dut y -c y cle parameters dmax actual 0.67 o p eratin g dut y c y cle at dc bus dro p out volta g e dmax reset 0.79 transformer reset minimum dut y c y cle at dc bus dro p out volta g e dxdo min 0.69 device min dut y c y cle limit at dc bus dro p out volta g e dxdo ma x 0.78 device max dut y c y cle limit at dc bus dro p out volta g e dll actual 0.46 dut y c y cle at minimum dc bus volta g e dxll min 0.56 dut y c y cle minimum limit at minimum dc bus volta g e dxll ma x 0.66 dut y c y cle maximum limit at minimum dc bus volta g e dll reset 0.69 minimum dut y c y cle to reset transformer at low line hi g h line dut y -c y cle parameters dhl actual 0.23 dut y c y cle at minimum dc bus volta g e dxhl min 0.30 dut y c y cle minimum limit at maximum dc bus volta g e dxhl max warnin g 0.39 !!! > reset dut y c y cle at vmax : decrease dxhl max, increase vdsop dhl reset 0.36 minimum dut y c y cle to reset transformer at hi g h line 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 100 150 200 250 300 350 400 450 dc bus voltage, v d_actual d_reset dx_min dx_max v_ov v_dropout duty cycle vs dc bus voltage 0.9 0.6 0.5 0.8 0.7 100 150 200 250 300 350 400 450 dc bus voltage, v duty cycle vs. dc bus voltage duty cycle pi-2891-121302 0 0.3 0.2 0.1 0.4 d actual exceeds dx min curve - hence low tolerance device will cause supply to drop out of regulation v dropout v ov d reset dx max dx min d actual
AN-30 36 b 12/02 selection of r c the value of r c is calculated by the spreadsheet. in ep-12 this value is calculated as: r c = 40.26 k ? (rc, f139) choose closest standard available value, r c = 43.2 k ? , 0.125 w selection of r d the value of r d is automatically calculated by the spreadsheet. in ep-12 this value is calculated as: r d = 126.70 k ? (rd, f143) choose closest standard available value, r d = 130 k ? , 0.125 w selection of capacitor c vs the capacitor c vs is also estimated by the spreadsheet. for ep-12, the value from the equation is approximately 93 pf. if the calculated value is unavailable choose next higher standard available value. choose c vs = 100 pf , 100 v (cvs, f141)
AN-30 37 b 12/02 spreadsheet a b d f g i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 acdc_topgxforward_rev_1.03_061802 copyright power integrations inc. 2002 input info output unit acdc_topgxfwd_061802_r103.xls: topswitch-gx forward transformer design spreadsheet output voltage and current ep12 pc main p ower su pp l y vmain 5 volts main out p ut volta g e imain 12 a m p sm ain out p ut curren t vmainm a 3.3 volts ma g am p out p ut volta g e imainma 12 a m p sma g am p out p ut current vaux1 12 volts a uxiliar y out p ut volta g e iaux1 4 a m p s a uxiliar y out p ut current vind1 volts inde p endant out p ut volta g e ind1 a m p s inde p endent out p ut current po 147.6 wa tts total out p ut p owe r enter application variables vacmin 90 a c volts minimum ac in p ut volta g e. in p ut volta g e doubler circuit is assumed. vacma x 132 a c volts maximum ac in p ut volta g e. in p ut volta g e doubler circuit is assumed. vmin 188 volts minimum dc bus volta g e at low line in p u t vma x 373 volts maximum dc bus volta g e at hi g h line in p u t ci n 165 ufarads e q uivalent bulk in p ut ca p acitance. in p ut volta g e doubler circuit is assumed. fl 50 hz in p ut ac line fre q uenc y tc 3.0 mseconds estimate in p ut brid g e diode conduction time th 16.0 mseconds minimum re q uired hold-u p time from vdropout to vholdup eff 0.75 efficienc y estimate to determine minimum dc bus volta g e vholdup 188 volts dc bus volta g e at start of hold-u p time ( default vmin ) vdropout 132 132 volts dc bus volta g e at end of hold-u p time dmax goal 0.7 0.70 maximum dut y c y cle at dc dro p out volta g e vdsop 580 volts maximum o p eratin g drain volta g e kdi 0.15 maximum out p ut current ri pp le factor at maximum dc bus volta g e ref aux1 1 dc stac k enter one ( '1' ) for dc stacked , zero ( '0' ) inde p endent windin g enter topswitch variables topswitch to p 247 universa l doubled 115v/230 v chosen device top24 7 power out - 165w ilimit 3.348 3.85 2 a m p sf rom topswitch-gx datashee t fs 124000 132000 hertz from topswitch-gx+h76 datasheet ki 0.81 ilimit reduction ( ki=1.0 for default ilimit, ki <1.0 for lower ilimit ) r x 7.78 kohm maximum current limit resistance to ensure ki >= 0.81 settin g ilimitext 2.712 a m p se xternal current limi t vds 8.1 volts topswitch-gx avera g e on-state drain to source volta g e diode vf selection vdmain 0.5 volts main out p ut rectifiers forward volta g e dro p ( schottk y) vdmainm a 0.5 volts ma g am p out p ut rectifiers forward volta g e dro p ( schottk y) vdaux1 0.7 volts a uxiliar y out p ut rectifiers forward volta g e dro p ( ultrafast ) vdind1 0v olts inde p endent out p ut rectifiers forward volta g e dro p ( schottk y) vdb 0.7 volts bias out p ut rectifier conduction dro p bridge rectifier diode selection vpivac 467 volts maximum volta g e across brid g e rectifier diode idavbr 0.773 a m p s a vera g e brid g e rectifier curren t transformer core selection core t yp e eer28l core eer28l p/n: pc40eer28l-z bobbin eer28l _ b o p/n: beer-28l-1112cph a e 0.814 cm^2 core effective cross sectional area le 7.55 cm core effective path len g th a l 2520 nh/ t^2 un g a pp ed core effective inductanc e bw 21.8 mm bobbin ph y sical windin g width lg ma x 0.02 mm maximum actual g a p when zero g a p s p ecified r factor 9% 9% % percenta g e of total ps losses lost in transformer windin g s; default 10% m 3.0 mm transformer mar g in l 0.80 transformer p rimar y la y ers nmain 3m ain rounded turns transformer design parameters np 45 45 primar y rounded turns nb 6 bias turns to maintain 8v minimum in p ut volta g e, li g ht load naux1 4 a uxiliar y rounded turns ( dc stacked on main windin g) vaux1 actual 11.63 volts app rox. aux out p ut volta g e with naux1 = 4 turns and dc stack nind1 0 inde p endent rounded turns ( se p arate windin g) vind1 actual 0.00 volts app roximate inde p endent out p ut volta g e with nind1 = 0 turns bm 1816 gauss maximum o p eratin g flux densit y at minimum switchin g fre q uenc y bp 2884 gauss maximum p eak flux densit y at minimum switchin g fre q uenc y lp min 3.419 mhenries minimum p rimar y ma g netizin g inductance ( assumes lgmax=20um ) imag 0.189 a m p s peak ma g netizin g current at minimum in p ut volta g e
AN-30 38 b 12/02 a b d f g i 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 od _ p 0.33 mm primar y wire outer diamete r a wg _ p 28 a wg primar y wire gau g e ( rounded to maximum awg value ) current waveshape parameters ip 2.451 a m p s maximum p eak p rimar y current at maximum dc bus volta g e iprms 1.460 a m p s maximum p rimar y rms current at minimum dc bus volta g e inductor output parameters lmain 10.0 uhenries main / auxiliar y cou p led out p ut inductance ( referred to main windin g) wlmain 2286 ujoules main / auxiliar y cou p led out p ut inductor full-load stored ener gy kdimain 0.150 current ri pp le factor of combined main and aux1 out p uts lmainm a 12.3 uhenries ma g am p out p ut inductance wlmainma 888 ujoules ma g am p out p ut inductor full-load stored ener gy kdimainm a 0.150 current ri pp le factor for ma g am p out p u t lind1 0.0 uhenries inde p endent out p ut inductance wlind1 0.0 ujoules inde p endent out p ut inductor full-load stored ener gy kdiind1 0.000 current ri pp le factor for inde p endent out p u t secondary output parameters ismainrmsll 15.61 a m p s maximum transformer secondar y rms current ( dc stack ) isaux1rmsll 2.42 a m p s maximum transformer secondar y rms current ( dc stack ) isind1rmsdll 0.00 a m p s maximum transformer secondar y rms current idavmain 12.3 a m p s maximum avera g e current, main rectifier ( sin g le device ratin g) idavmainm a 9.3 a m p s maximum avera g e current, ma g am p rectifier ( sin g le device ratin g) idavaux1 3.1 a m p s maximum avera g e current, auxiliar y rectifier ( sin g le device ratin g) idavind1 0.0 a m p s maximum avera g e current, inde p endent rectifier ( sin g le device ratin g) irmsmain 0.52 a m p s maximum rms current, main out p ut ca p acito r irmsmainm a 0.52 a m p s maximum rms current, ma g am p out p ut ca p acito r irmsaux1 0.17 a m p s maximum rms current, auxiliar y out p ut ca p acitor irmsind1 0.00 a m p s maximum rms current, inde p endent out p ut ca p acitor diode piv no deratin g vpivmain 29.5 volts main out p ut rectifiers p eak-inverse volta g e vpivmainm a 29.5 volts ma g am p out p ut rectifiers p eak-inverse volta g e vpivaux1 34.9 volts a uxiliar y out p ut rectifiers p eak-inverse volta g e vpivind1 0.0 volts inde p endent out p ut rectifiers p eak-inverse volta g e vpivb 102.1 volts bias out p ut rectifier p eak-inverse volta g e o p tocou p ler vceo opto 49.8 volts maximum o p tocou p ler collector-emitter volta g e under-voltage lockout circuit parameters vacuvl 68 a c volts a c undervolta g e lockout volta g e; on-off transition vacuv 78 a c volts a c undervolta g e lockout volta g e; off-on transition vacuv x 68 ruva 2.23 mohm resistor ruva value ruvb 523.73 kohm resistor ruvb value ruvc 75.91 kohm resistor ruvc value vacuvl actual 67.50 a c volts a ctual ac undervolta g e lockout volta g e; on-off transition vacuvx actual 70.36 a c volts a ctual ac undervolta g e lockout volta g e; off-on transition duty cycle limit circuit parameters vz 6.80 volts zener volta g e used within dlim circuit v ov 380 volts app roximate fre q uenc y reduction volta g e ( determines cvs value ) ra 2.20 mohm resistor ra value rb 2.20 mohm resistor rb value rc 40.26 kohm resistor rc value rd 126.70 kohm resistor rd value cvs 92.98 p fca p acitor cvs value duty cycle parameters (see graph) dro p out dut y -c y cle parameters dmax actual 0.69 o p eratin g dut y c y cle at dc bus dro p out volta g e dmax reset 0.79 transformer reset minimum dut y c y cle at dc bus dro p out volta g e dxdo min 0.70 device min dut y c y cle limit at dc bus dro p out volta g e dxdo ma x caution 0.79 !!! >dmaxreset from vmin to vdropout. not hazardous dll actual 0.47 dut y c y cle at minimum dc bus volta g e dxll min 0.55 dut y c y cle minimum limit at minimum dc bus volta g e dxll ma x 0.67 dut y c y cle maximum limit at minimum dc bus volta g e dll reset 0.69 minimum dut y c y cle to reset transformer at low line hi g h line dut y -c y cle parameters dhl actual 0.23 dut y c y cle at minimum dc bus volta g e dxhl min 0.24 dut y c y cle minimum limit at maximum dc bus volta g e dxhl max 0.35 dut y c y cle maximum limit at maximum dc bus volta g e dhl reset 0.36 minimum dut y c y cle to reset transformer at hi g h line
AN-30 39 b 12/02 a b d f g i 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 100 150 200 250 300 350 400 450 dc bus voltage, v d_actual d_reset dx_min dx_max v_ov v_dropout duty cycle vs dc bus voltage 0.9 0.6 0.5 0.8 0.7 100 150 200 250 300 350 400 450 dc bus voltage, v duty cycle vs. dc bus voltage duty cycle pi-2890-121302 0 0.3 0.2 0.1 0.4 v dropout v ov d reset dx max dx min d actual
AN-30 40 b 12/02 singapore power integrations, singapore 51 goldhill plaza #16-05 republic of singapore 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com world headquarters americas power integrations, inc. 5245 hellyer avenue san jose, ca 95138 usa main: +1 408-414-9200 customer service: phone: +1 408-414-9665 fax: +1 408-414-9765 e-mail: usasales@powerint.com for the latest updates, visit our web site: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it co nvey any license under its patent rights or the rights of others. the products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more u.s. and foreign patents or potentially by pending u.s. and foreign patent applications assigned to powe r integrations. a complete list of power integrations?patents may be found at www.powerint.com. the pi logo, topswitch , tinyswitch , linkswitch and ecosmart are registered trademarks of power integrations, inc. pi expert is a trademark of power integrations, inc. ?opyright 2002, power integrations, inc. taiwan power integrations international holdings, inc. 17f-3, no. 510 chung hsiao e. rdl, sec. 5, taipei, taiwan 110, r.o.c. phone: +886-2-2727-1221 fax: +886-2-2727-1223 e-mail: taiwansales@powerint.com china power integrations international holdings, inc. rm# 1705, bao hua bldg. 1016 hua qiang bei lu shenzhen guangdong, 518031 china phone: +86-755-8367-5143 fax: +86-755-8377-9610 e-mail: chinasales@powerint.com europe & africa power integrations (europe) ltd. centennial court easthampstead road bracknell berkshire, rg12 1yq united kingdom phone: +44-1344-462-300 fax: +44-1344-311-732 e-mail: eurosales@powerint.com korea power integrations international holdings, inc. rm# 402, handuk building 649-4 yeoksam-dong, kangnam-gu, seoul, korea phone: +82-2-782-2840 fax: +82-2-782-4427 e-mail: koreasales@powerint.com japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome kohoku-ku, yokohama-shi, kanagawa 222-0033, japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com india (technical support) innovatech #1, 8th main road vasanthnagar bangalore, india 560052 phone: +91-80-226-6023 fax: +91-80-228-9727 e-mail: indiasales@powerint.com applications hotline applications fax world wide +1-408-414-9660 world wide +1-408-414-9760

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