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eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m 8-bit mcu with 10-bit a/d converter features ? 2.2v to 5.5v input v o lt age rang e ? 8 i/o port s in eu101 0 ? 12 i/o port s in eu10 1 1 ? ram size: 1 28 x 8 bit s ? the st ack ram is incl u ded. ? program rom si ze: 4k x 8 bit s otp ? 10 bit s a/d conve r ter in p u t source. eu101 0: 2 ch annel s eu10 1 1 : 4 ch annel s ? one set of 16-bit d o wn count timer a n d one set of 8-bit timer . ? operating te mperature: -4 0 ~ +8 5 ? build-in lo w v o lt age reset (l vr) ci rcu i t. ? oscillator: internal rc oscillation. description the eu101x is an otp typ e 8-bit micro - controlle r with 2(eu1 0 1 0 )/4(e u 10 1 1 ) channel s of 10-bit a/d conve r ter usi ng adva n ced cmos pro c ess. the eu101x is spe c ially desi gne d for variou s indu strial fi eld ap plicat ions. th e eu101x inco rpo r ate s two set s o f 8-bit timer/counte r s, where timer0/1 is s p ec iall y designed for pwm (pulse wi d t h modulatio n) gene rato r . th ere a r e 8 i/o port s a n d 12 i/o port s with eu1 010 an d eu10 1 1 , re spectively . co nsid erin g form factor and ma nufa c turability , the eu101 0 is p a ckage d into 10-pin non-je dec-st anda rd com p a c t-size sop while th e eu1 0 1 1 is p a ckage d in to 14-pin non-je dec-st anda rd com p act-size sop . ordering information 1/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m pin assignment 1 2 3 4 5 6 7 13 12 11 10 9 8 vd d pa [ 0 ] pa [ 1 ] pa [ 2 ] pa [ 3 ] pa [ 4 ] pa [ 5 ] pb [ 0 ] pb [ 1 ] p b [ 2 ] pb [ 3 ] pb [4 ] pb [ 5 ] s o p - 1 4 ( 1 2 i/ o p o rt ) 14 vs s pin desc ription pin name i/o functio n v dd - positive power su pply v ss - g r o u n d pa 0 ~ pa 5 i/o input and out put port s . in input mod e , all p a pins could b e set an intern al pull-u p re si sto r (r=10 0 kohm ). in output mode, it could be optione d as cmos or nmos outp u t indepe nde ntly . also, p a 0~p a 3 coul d be optioned a s 4 cha nnel s of 1 0 -bit a/d con v erter inp u t pins. pb0~ p b 5 i / o input and out put port s . in input mode, it coul d have o p tioned inte rn al pull-u p resi st or with 100k ohm. also, it can be set as hal t an d st op mod e relea s e d sou r ce whe n the i nput si gnal is cha nge d fro m high to low . in output mode, it could be o p tioned a s cmos or nm o s output inde pe ndently . 2/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m m c u description item abbreviatio n de scription a ccu mulat o r a c c the eu101x has a n 8-bit regi ster use d for d a t a hold, excha nge, ari t hmetic , tran sfer and i/o op eration. index regi ste r (x,y) in eu101x t hat build s in two ind e x registe r s ( x and y ). these two in dex regi sters could be u s ed to count prog ram step s o r to provide an ind e x val ue to be use d in gen erating as ef fective address. whe n execu t ing an inst ructio n whi c h spe c ifies i ndexed addressin g , the mcu fetches the o peration co de a nd the base ad dre ss, and modifie s the a ddress by addin g th e index regi ster to it s prior to perf o rm the de sired ope ration. per or post-i ndex of indire ct add re ss i s po ssi ble . s pecial f u n c tion regi ster sfr the eu101x i n clu d e s som e sp eci a l fun c tion control registe r s in zero-p a ge. for mo re det ailed inform ation about the spe c ia l function regi sters, plea se refer to next section. s t ack p o int e r regi ster sp the st a c k po inter is an 8 - bit registe r th at is used to control the addressin g of the variable-le ngth st a ck. the st a c k pointe r is automatica lly increment ed and decre mented und e r control of the microp rocesso r the perfo rm st a c k manipulation s unde r dire ction of either the pro g ram or interru p t s . the st ack allow s a simple im pl ement atio n o f nested sub r outine s and multiple level interru pt s. the st a ck pointer i s initialize d by the user ? s sof t w a r e . program cou n ter pc the 14-bit p r og ram co unt er regi ster p r ovide s the address that step the micr oprocessor th rou gh seq uential p r ogra m inst ru ct ion s . program flag regi ster p the 8-bit st a t us flag regi ster cont ai ns seven st atu s flags. some of the flags are con t rolled by the program and others may be con t rolled both by the program and the mcu. instru ction set cont ai ns a numb e r of conditio nal bran ch instru ction s that are de sig ned to allo w testing of the s e flags. 3/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m me mor y the eu101 x has a 14-bit p r ogram counter w h ich can tot a lly addres s 16k x 8 bit s . all the spe c ial functio n registers, dat a ram, st ack ram and program rom are assigned in this area as the follo w ing diagr am. 0000 h s p ecial fun ction register 0022 h un-used 00a0h ( zero p age ) dat a ra m : 9 6 x 8 bit s 00ff h 0100 h dat a & s t ack ram : 3 2 x 8 bit s 01 1f h un-used 3 000 h program ro m : 4 k x 8 bit s 3fff h figure_a memory map p i ng diag ram progra m rom the eu10 1x cont ain s 4k x8 bit progra m otp and it s add re ssi n g size i s assigned from $ 3000 h to $3fff h. af ter po we r on reset, the d a t a re stored in addresse s $ 3 ffch a nd $3ff dh are loade d into program counter . it means that reset vector address is located in $3ffch and $3ffdh. data ram and st ack ram the eu10 1x dat a ram a r e located fro m $a0h to $1 1f h. all the dat a ram area from $a0 h to $0ffh coul d be a ccessed by ze ro-p age add re ssi ng mo de. that st ack ram could b e acce ssed from $10 0h to $1 1 f h. actu a lly , the area of $100 h ~ $ 1 1f h, co uld be a c cessed as d a t a ra m or st a c k ram. use r need s to pre s et st ack poi nter (sp) af te r power on re set. program cou n ter (p c) shoul d be init ialize d af ter power on re set that rom address $3 f f ch a nd $3 f f dh conte n t will be load ed into progra m counte r . 4/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m special function register (sfr) s pecial fun c tion regi ster a r ea is duri n g the addr esses from $00 h to $22h. these spe c i a l function regi sters con t rol all i/o a nd timer fu nction setting. some of me mory ad dre s se s a r e not defined an d un-u s e d . it is unne ce ssary for the u s e r s to read or write dat a fro m these und ef ined area s. user shoul d follow the de fault value or do not a c cess these un defined a r ea. all it s functions a r e li ste d in next se ct ion s . interrupt and t i mers addre s s 0 0 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n a m e i n t e n a d i n t # # t 1 i n t t 0 i n t p b i n t t b i n t r t ci nt rea d or w r it e r/w # # r/w r/w r/w r/w r/w d e f a u l t v a lu e 0 # # 0 0 0 0 0 the eu1 01x build s in 8 interrupt so urce s: real t i me clo ck inte rru p t, t i me base interru pt, pb input p o r t s f a lling edge i n t e rr upt , t i m e r0 und erf l o w int e rrupt , t i m e r1 und erf l o w int e rrupt , a / d conv ert e r int e rr upt and reset interrupt. by setting control register i n te n (00h) that can enable or disable correspondi ng interrupt sou r ce s. interrupt source, interrupt vect or a ddre s s mappi ng and it s pri o rity are sh o w n in the followin g t abl e. addre s s interrupt sourc e priority 3fff0 h/3ff 1 h a d c inte rru p t 7 3ff2 h/3ff3 h t i m e r 1 i n t e r r u p t 6 3ff4 h/3ff5 h t i m e r 0 i n t e r r u p t 5 3ff6 h/3ff7 h pb port interrupt 4 3ff8 h/3ff9 h t i me ba se int e rrupt 3 3ff a h/3 ffb h r t c inte rrupt 2 3ffc h/3ff d h r e s e t 1 3ffeh/3f ff h r e serv e d 0 5/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m r t c timer , base timer interrupt and w atch dog timer addre s s 0 3 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n a m e ucclk # b a s e 1 base0 r t c 1 r t c 0 r c s e l 2 r c s e l 1 resel0 rea d or w r it e w w w w w w w w d e f a u l t v a lu e 0 0 0 0 0 0 0 0 real time counter the eu1 01x build-in a re al time count er interrupt a nd its clo c k sou r ce is opt ioned in ucclk.7 bit (cksel). its freque ncy co uld be option ed by uccl k .4 & uccl k.3 that could sele ct real time interru pt frequency. f o r exampl e, if the clock source come f r om exclk/ pb3 (when cksel=1) and the input freque ncy i s 32,768 hz, se lect ?[rtc1, rtc0] = [0, 1]? and it will cau s e 2 h z i n terrupt wh e n real time cou n ter inte rrupt enabl ed (rtci n t = 1 ) & (rt c en=1 ). rt c 1 rt c 0 t rt c 0 0 t t /32 0 1 t t /64 1 0 t t /128 1 1 t t /256 6/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m base t i mer base timer i s optioned from [base1, base0] and it will cause a period time r base interrupt enabled (tbint =1 ) & (tben=1 ). but the real t i me co unte r have the sa me clo c k sou r ce and it i s optione d by ucclk.7($03h.7= c ksel). base1 base0 t base 0 0 t t /2 0 1 t t /4 1 0 t t /8 1 1 t t /16 m c u clock selection with a built-in internal rc oscilla tor , the mcu frequency is 4mhz 3% @4.5v . mc u sys tem c l ock of fers 4 m hz, 2mhz, 1m hz, 512khz o r 2 56khz by m cu clo ck opti ons bit; rcs el2~0. plea se refe r to the followin g t able. addre s s 0 3 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 nam e u c cl k # b a s e 1 base0 rtc 1 rtc 0 rcsel2 rcsel1 rcsel0 read o r w r it e # w w w w w w w d e f a u l t v a lu e 0 0 0 0 0 0 0 0 the mcu system clo ck co uld be swit ch ed by setting rcsel 2~0. first, pre-set rcsel 2~0 registe r an d then exe c ute ?ha l t? i n stru ction. af ter th en, mcu wa ke-up f r om ha l t mo de, mcu sy stem fre quen cy is alrea d y cha n ged to the ne w setting freq uen cy . rcsel 2 r c s e l 1 r c s e l 0 f r eq u e n c y o f mcu s ystem clo c k 0 0 0 256 k h z 0 0 1 512 k h z 0 1 0 1 m h z 0 1 1 2 m h z 1 # # 4 m h z 7/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m tmrc regis t er addre s s 0 1 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t m r c w d t divide wdten w d t f t b e n t b f r t ce n r t c f rea d or w r it e w w r/ w r / w r / w r / w r / w r / w d e f a u l t v a lu e 0 0 0 # 0 # 0 # *tmrc.0(rt cf) : real time counte r tra n sie n t flag. o n ce trtc si g nal is transi e nt, this flag will be set as rt cf =1 by hardwa r e. this bit co uld be cl eare d by softwa r e . *tmrc.1(rt cen) : real time cou n ter e nable/di sabl e flag. rtce n = 1, enabl e real ti me cou n ter; rtce n = 0, disa ble re al time cou n ter. *tmrc.2(tbf) : base timer transi ent flag. once tbase signal is transient, this flag will be set as tbf=1 by ha rdwa re. thi s b i t could be cle a red by software. *tmrc.3(tben) : base ti mer en able/di sabl e flag. tben = 1, en able ba se tim e r; tben = 0, di sabl e ba se timer. w atchdog t i mer watchdo g timer blo ck di ag ram is shown as figure_b. the clo c k so urc e co me s f r om cp u sy st em clo ck. fi g u re_b not e : *once tmrc.5 (wdten) is set a s ?1?, the wat c hdo g timer will sta r t to count till th e watchdog ti me r overflows, an d then the tm rc.4 (wdtf ) is set as ?1?. mean while, cpu will have a warm re set by hard w a r e an d the data in addresse s $3 ffch and $3 ffdh will be loaded into prog ram cou n ter. watchdo g timer can be clea red by setting tmrc.5 (wdten=0). please n o te w e ll tha t the eu101 x w a tc hdog timer is preset as disable after po w e r on re set. once w a tch dog timer is enabled b y setting tm rc.5 = 1, w a t c hdog timer w o n?t be stopp ed b y soft w a re. set tmrc.5=0 w ill just clear w a tchdog ti mer counter. 8/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m wdt div i der tmrc (01 h ) bit7 bit6 f sys/2 0 0 f sys/4 0 1 f sys/8 1 0 f sys/16 1 1 pb ports interrupt pb6~0, in in put mode, co uld be o p tion ed as extern al interrupt source by setting pbint (0 0h.2) = 1. whe n the int e rrupt en able d and extern al sig nal cha nged from hi gh to lo w, the pb port interrupt will ta ke into action a n d its interrupt vector i s $3f f6h an d $3f f7h. a falling edge signal at pb ports will wa ke up cpu fro m halt or s t op mode. whe n pb port interrupt is enabl ed (pbi nt =1), cpu will wake up f r om halt o r stop mode, and serve pb port inte rrupt first an d then execute next instru cti on. if pb port interrupt is disabl ed, cpu will just be waked up and then execute next instru ction o n l y. user sh ou ld che ck whi c h pb port the falling edge sign al com e s from by pbf control registe r . if the falling edge i s from pb0, th e pbf.0 will be set to ?1? by hard w are. th ese flag s coul d be cl ea red by soft wa re. addre s s 0 2 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p b f # p b f 6 p b f 5 p b f 4 p b f 3 p b f 2 p b f 1 p b f 0 rea d or w r it e # r/w r/ w r / w r / w r / w r / w r / w d e f a u l t v a lu e # 0 0 0 0 0 0 0 ti m e r 0 t i mer 0 is an 8-bit dow n cou n t t i mer . i t s clo ck sou r ce com e s f r om cp u ma in-o scill at or ( f os c ) o r exclk/pb3, whi c h is liste d in figure 4-3. user can pre s et timer0 counter by setting dat a i n to timer0 preload buf fer t0bf(04h). the dat a read from t0 bf(04h) will be t he current count of timer0. t i mer0 will down count by every input clock whe n t0en=1. wh en timer0 do wn cou n t from 00h to ffh, t0f will be se t to ?1? and if t0int =1, the timer0 interru pt will occu r . t i mer0 will automatically rel oad dat a from t0bf/0 4h (time r 0 p r eset buf fer). therefore, u s er ca n preset timer0 ne w dat a into t0bf(0 4h ) before time r0 underflo w a nd cau s e dif f erent inte rru p t time duties. that is, tim e r0 dat a w ill be loaded from t0 bf b u ffer af ter t0 en bit is set as ?1 ? or tim e r0 unde rflo w s . 9/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m addre s s 0 4 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t 0 b f 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 rea d or w r it e r/w r/w r / w r / w r / w r / w r / w r / w d e f a u l t v a lu e # # # # # # # # addre s s 0 5 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t 0 c t 0 e n t 0 f t 0 c k # # t i mer0 pre - s c a l e r rea d or w r it e r / w r / w r / w # # r / w r / w r / w d e f a u l t v a lu e 0 # # # # # # # not e : *t0en : timer0 enabl e flag t0en = 1, load t0bf cont ent (prel oad buf fer dat a ) into timer0 an d enable time r0 st a r t to down c o unt. t0en = 0, stop timer0 counting. use r can get timer0 dat a by readi ng t0b f registe r . (l da t0bf) * when t0en=0, writ e dat a to t0b f (04 h ), da t a will be directl y p a ssed to timer0 cou n ter . t0f : timer0 unde rflow fla g t0f = 1, time r0 und erflo w ; t0f = 0, time r0 not und erfl ow . *t0ck : timer0 clo ck sou r ce option bit t0ck = 1, cl oc k sou r ce f r om exclk/pb3 pin. us er c an set t0 ck=1, exclk/pb3 is option ed as external clock input pin t hat con n e c t to t i mer0. before this, u s e r sh ould set pbio.3=1 an d pbph.3 internal pull-up resistor could be enabl ed or disabled. t0ck = 0, cl o ck sou r ce f r o m fos c . *there is no defa ult dat a w i th t0 ck bi t, user shoul d prese t this bit af ter po w e r on res e t. bit2 bit1 bit0 t i mer0 pre - scaler(f clk0 = ) 0 0 0 f os c /1 0 0 1 f os c /2 0 1 0 f os c /4 0 1 1 f os c /8 1 # # f os c /16 10/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m not e : * b i t 2 ~0 a r e t i mer0 clo c k s our ce sel e ct i on bit s . they must follo w the setting listed b e lo w . if the bit2=1, it wou l d be divided by 16 while bi t1 and bit0 co uld be any da t a . when t 0 ck=1, d on?t care bit2~ 0 dat a . figure_ c ti m e r 1 addre s s 0 6 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t 1 b f 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 rea d or w r it e r/w r/w r / w r / w r / w r / w r / w r / w d e f a u l t v a lu e # # # # # # # # addre s s 0 7 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t 1 b f 1 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 rea d or w r it e r/w r/w r / w r / w r / w r / w r / w r / w d e f a u l t v a lu e # # # # # # # # t i mer1 is a 1 6 -bit do wn co unt timer . t1 bf0(06 h)/l ow byte and t1 bf1(07 h)/hig h byte are timer1 p r eloa d buf fer . t i mer1 clock source coul d com e from cpu m a in oscillator (fosc), refer to figure_d. t i mer1 can work in two ki nds of ope rati ng mode. on e mode is normal 16-bit timer/co unte r mode and the o t her one is spe c ially de si gned for dif f e r ent interrupt time perio d. figure_ d 1 1 /21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m t i mer/counter mode if t1c.4 (08h.4)= p wm1 = 0 , timer1 wo rks as 16-bit timer/counte r mode, re giste r timer1 will d o wn cou n t by every inp u t clock wh en t i mer1 tu rn s o n by t1e n =1 . whe n time r1 is d o wn coun t from 00 00 h to ffff h, t1f bit will be set to ?1?. at the same time, if t1 int=1, the timer1 interrupt occurs. t i mer1 will automatically reloa d dat a from prelo ad buf fer t1bf 0(06h) and t1 bf1(07 h). theref o r e, use r can preset t1bf0(06 h) and t 1 bf1(07h) buf fer dat a before dif f er ent interrupt time duties cau s ed by timer1 unde rflo w . it mean s that timer1 d a t a wil l be loade d from t1bf0 ( 06 h) an d t1bf 1(07 h) buf fer af ter t 1 e n bit is set as ?1? or time r1 u nderflo w . addre s s 0 8 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name t 1 c t 1 e n t 1 f t1ck pwm # `t ime r 1 p r e-scale r rea d or w r it e w r/w r/w w # w w w default v a lu e 0 # # 0 # # # # not e : *t1en : timer1 enabl e flag t1en = 1, en able timer1 st art to down count; t1en = 0, stop timer1 d o wn co unt. (whe n t1e n =0 and write dat a into t1 bf0(06 h) an d t1bf1(07h) , the dat a will be direct ly p a ssed to timer1 counter . ) *t1f : timer1 unde rflow fla g t1f = 1, time r1 und erflo w ; t1f = 0, time r1 not und erfl ow . bit2~bit0 are timer1 cl ock source sele cti on bits . it mus t follow the setting as below. bit2 bit1 bit0 t i mer1 pre - scaler (f clk 1 = ) 0 0 0 f os c /1 0 0 1 f os c /2 0 1 0 f os c /4 0 1 1 f os c /8 1 # # f os c /16 12/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m pw m mo de /1 /2 /4 /8 /16 t1int fosc t1en timer1 t1bf0(06 h) t1bf1(07h) f cl k 1 selector timer1 inte rru pt (pwm= 1 ) pb 3/tmr t1ck set t1c .4 =1(pwm=1), t i mer-1 will wo rk in pwm m ode. user ca n pre s et t1b f 0 and t1bf 1. t i mer1 interrupt will have two ki nd s of time duties ba se d on t1bf0 and t 1 bf1 dat a. i/o ports p a port s (p a 6 ~ p a 0) are 8-bit s i/o port s . system can either outp u t dat a by writing dat a into p a (10h) port s or read dat a from in p u t mode by re ading p a (10 h ) po rt s. whe n p a port s are set in output mode, it can be optio ned by sof t ware a s cmos or nmos output. set in input mod e , p a port s can be option ed a s internal p u ll up or in put with floating st atus. also, p a 6~0 coul d be option ed a s a/d co nvert e r anal og si g nal input pin s . please refe r to a/d con v erter se ct io n. addre s s 1 0 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p a # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # # # # # # # # pa i o regi ster: control p a p o rt eithe r a s i nput mo de o r output mo de. p a io regi ste r can be set p a rtially bit s in input mode and p a rtial bi t s in output m ode. addre s s 1 1 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p a i o # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # 1 1 1 1 1 1 1 not e : *p aio.n = 1, set as in put mode. ( p lease be no ted th at p a io.0 defa ult d a t a is ?0 ?.) p a io.n = 0, set as output mode. t hat n = 6 ~ 0. 13/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m pa c n regi ste r : control outp u t mode as cmos or nm o s output. addre s s 1 2 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p a c n # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # 0 0 0 0 0 0 0 not e : *p acn.n = 1, set as cmo s output; pacn.n = 0, set as nmos output. that n = 6 ~ 0. pa p h regi ste r : enable/di sa ble p a port s i n ternal p u ll hi gh wh en p a p o rt is set as i nput mode. addre s s 1 3 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p a p h # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # 0 0 0 0 0 0 0 not e : *p aph.n = 1, internal p u ll h i gh re siste r e nable; p aph.n = 0, internal p u ll hi gh re siste r di sabl e, whe r e n = 6 ~ 0. pb ports pb port s (pb6 ~ pb0) are 8-bit i/o port s . user can eit her outp u t dat a by writing dat a into pb(14h) p o rt s. or re ad dat a at input mode by reading p b (14 h ) po rt s. addre s s 1 4 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p b # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # # # # # # # # pbr regis t er addre s s 1 5 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p b r # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # 0 0 0 0 0 0 0 14/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m not e : *pbr.n = 1, e nable hal t o r st op mode relea s ed by i nput falling e dge si gnal; pbr.n = 0, disabl e hal t o r st op mode relea s e, wh e r e n = 6 ~ 0. *setting pbr.n regi ster a s ?1? can e nab le to relea s e hal t or st o p mode by pb port input signa l from high to l o w . af ter ha l t or st op m ode rele ased, the oscillator will oscill ate at the same ti me. if pbint=1, pb-interrupt subroutin e wi ll st art. if pbint = 0, the program counter will execute the next instru ction af ter hal t or st op . pbio regi ster: control pb port as input or output mode. al so, it can be set as p a rtial bit s in input mode and p a rtial bit s in output m ode. addre s s 1 6 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p b i o # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1/0 d e f a u l t v a lu e # 1 1 1 1 1 1 1 not e : *pbio.n = 1, set as in put mode; pbio.n = 0, set as output mode.; that n =6 ~0. pbmd re gister addre s s 1 7 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name p b m d # 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 1 / 0 d e f a u l t v a lu e # 0 0 0 0 0 0 0 not e : *whe n pbio corre s p ondi ng bit is o p tioned a s o u tp ut mode (pb i o.n=0 ) , pbmd.n will wo rk a s cmos o r nm os option bit. (pbio.n=0, pb.n works a s output mode ) pbmd.n = 0, pb.n is nmo s output. pbmd.n = 1, pb.n is cmo s output. *whe n pbio correspon di ng bit is optioned a s in p u t mode (pbio.n=1 ) , pbmd.n will wo rk a s internal p u ll-u p resi sto r ena ble bit or disa ble bit. (pbio.n=1, pb.n works a s input mode ) pbmd.n = 0, disa ble pb.n internal p u ll-u p resi sto r , pbmd.n = 1, enabl e pb.n internal p u ll-u p resi sto r . that n = 6 ~ 0. 15/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m a/d converter the eu10 1x is built-in with 4 chan nels of 10-bit analog to digit a l converter . th e analo g signal input pins are sha r ed from p a 3~0. these option s are cont rolled by adin(0 9h) and a d cc(0ah) regi sters. adi n regist e r : pa 3 ~p a0 p o rt s could b e o p tioned a s a/ d converte r a nalog si gn al i nput pin s . user can sele ct p a rtial or all pa 3 ~p a0 pin s as a nalo g input pin s by adi n3 ~0 for corre s p ondin g bit. addre s s 0 9 h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name a d i n # # # comp adin3 a d i n 2 a d i n 1 adin0 rea d or w r it e # # # w w w w w d e f a u l t v a lu e # # # 0 0 0 0 0 not e : *adin3 ~0: o p tion of p a 3~p a 0 as an alo g sign al input pin. *adinn = 1, set p a 3~0 pin as an alog sig nal input pin; adinn = 0, set p a 3~0 a s norm a l input/ output pin, where n = 3 ~ 0. * wh en p a 3 ~ 0 is set a s a nalog i nput pi n(s), p a p o rt s cont rol regi ster will be in a c tive to a c ce ss. that is, whe n p a port is se t as analo g si gnal inp u t pin, all p a i/o p o rt function s will be blo c ke d out. not e : *comp = 0, disa ble intern al com p a r ator; comp = 1, e nable inte rnal com p arator . whe n comp =1, p a 4 an d p a 5 will a c t a s comp arat or input pin, an d then com p a r ator output p i n will be conne cted to pb4 internally . adcc register addre s s 0 a h b i t 7 bit6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name a d c c a d e n stc # a d s 1 a d s 0 # # # rea d or w r it e w r/w # w w # # # d e f a u l t v a lu e 0 # # # # # # # 16/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m not e : *adcc.7(a d en) : enabl e a/d conve r ter adcc.7 = 1, turn on o r en able a/d con v erter; adcc.7 = 0, turn of f or disable a/d con v erter . *adc c.6 ( stc ) : a/d co nverter finish ed interru pt flag, write a high to this bit to st art adc conve r si on. adcc.6 = 1, a/d conve r ter trans lation is c o mpleted; adcc.6 = 0, a/d conve r ter is in busy or st a ndby st atus. ads1/bit4 ads0/bit3 select pin 0 0 p a 0 0 1 p a 1 1 0 p a 2 1 1 p a 3 not e : * adcc.4~3(ads1~0) : se lect actin g an alog chan nel input * use r can preset a/d co n v erter sam p li ng rate fr om adcc.2~0 co ntrol regi ste r . the sam p ling clock come s fro m internal ring o scill ator . th e re feren c e sa mpling rate setting is listed below . a/d con f igur ation and c o ntrol block 17/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m not e : *user should sele ct p a 3~0 port s as an al og signal inp u t pin(s) by setting adin.3 ~0. set adcc.7 (aden) = 1 to enable a/d converte r circuit, and then select input pin fr om adcc.4 ~3 (ads1/ads0). the conve r ter clo c k com e s fro m f adc. af ter system compl e ted a n a/d conve r ting c y c l e, adc interrupt t a kes into ac tion (if adint= 1). use r can re ad the co nve r ting dat a from adr h and a d r l regi ster s. [adrh + ad rl] are tot a lly 14 bit s in 2 bytes contr o l registe r s. th e s e 2 bytes of re gister will ke e p the last a/d conv ert dat a. when a/d conver sion are all completed, use r sh ould t u rn of f a/d co nverter by setting adcc.7 (aden) =0. adsp2 ~0 co ntrol regis t e r : a/d co nverter sam p ling rate setting addre s s 0 b h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name a d r l a d 1 a d 0 # # # a d s p 2 a d s p 1 adsp0 rea d or w r it e r r # # # w w w d e f a u l t v a lu e # # # # # # # # adc s a mpli n g rate adsp2 adsp1 adsp0 8 hz 0 0 0 16 hz 0 0 1 32 hz 0 1 0 64 hz 0 1 1 128 hz 1 0 0 256 hz 1 0 1 512 hz 1 1 0 1024 hz 1 1 1 addre s s 0 c h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 name a d r h a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2 rea d o r w r it e r r r r r r r r d e f a u l t v a lu e # # # # # # # # 18/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m low v o ltage reset circuit ( or power failed detector ) 2.4v the eu1 01x is built in lo w-v o l t age -re s et ci rcuit to detect an d a gain s t power noise. th e low volt ag e reset will be active wh en vdd is dropp ed lower than 2.4v . note that, in st op mode, low v o lt age reset function will be disa bled by hard w are. the low volt age re set fun c tion will be active whe n cpu is not workin g in st op mode. hal t mode the eu101x will ente r ha l t mo de by se tting an in struction as ?st a $0eh?. the dat a in a c c could be any dat a am ong # 0 0 h ~# ffh. in hal t mode, cp u core will susp end and j u st hol d at t hat program cou n ter . all the internal ci rcuit will susp end, exce pt system clo c k and timer/ cou n ter kept run n ing. ha l t mode could b e relea s e d fro m timer unde rflow o r pb por t s input sig nal from high to low . whe n halt mod e is rel e ased, program counter will execute next instruct ion af ter ?st a $0eh?. if ti mer interrupt is enabled, it serve s time r interrupt first, and then e x ecute n e xt instru ction af t e r ?s t a $0e h?. whe n ha l t mo de i s relea s e d by pb port s falli ng-e dge, p r o g ram co unte r ex ecute next instructio n. if pb interru pt is en able d , pbint =1, pb interrupt subroutine will be activated. addre s s 0 e h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n a m e hal t # # # # # # # # st op mode when execut ed ?st a $0f h?, whole chi p will enter st op mode. the dat a in a c c could be any dat a of #00 h~#ff h . in stop mode, system clo ck and timer/co unter will be stopp ed. at this co ndition, operatin g curre n t coul d be do wn le ss than 1a. onl y input sign al from high to l o w of pb port s can relea s e the chi p from st op mode. when st op mode is rele ased by pb/pd port s , prog ram cou n ter will e x ecute next instru ction of ?st a $0f h?. if pb interrupt is enabled, pbint=1, pb interrupt su b r outine will b e activated firs t. addre s s 0 f h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 n a m e st o p # # # # # # # # m c u system clock this cpu is built-in inte rn al rc o s cillat o r who s e fr e quen cy is 4m hz. th e tolerance of the freque ncy i s within 3% . 19/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m package description sop-10l dimensio n s millimeters ref . m i n m a x a 5 . 8 0 6 . 2 0 b 4 . 8 0 5 . 0 0 c 3 . 8 0 4 . 0 0 d 0 8 e 0 . 4 0 0 . 9 0 f 0 . 1 9 0 . 2 5 m 0 . 1 0 0 . 2 5 h 0 . 3 0 0 . 4 4 l 1 . 3 5 1 . 7 5 j 0 . 3 7 5 ref . k 4 5 g 1 . 0 0 typ . 20/21
eor e x (preliminary) eu1010 / eu101 1 aug.2 007 www .e orex.co m sop-14l a h e b c m l d j k f e 0. 25 dimensio n s millimeters ref . m i n m a x a 5 . 8 0 6 . 2 0 b 4 . 8 0 5 . 0 0 c 3 . 8 0 4 . 0 0 d 0 8 e 0 . 4 0 0 . 9 0 f 0 . 1 9 0 . 2 5 m 0 . 1 0 0 . 2 5 h 0 . 2 0 0 . 3 0 l 1 . 3 5 1 . 7 5 j 0 . 3 7 5 ref . k 4 5 e 0 . 6 5 ref . 21/21

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