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GDC21D601 32-bit risc mcu v er 1. 6 hds-GDC21D601-9908 / 10
3 GDC21D601 the information contained herein is subject to change without notice. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by hyundai for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of hyundai or others. these hyundai products are intended for usage in general electronic equipment (office equipment, communication equipment, measuring equipment, domestic electrification, etc.). please make sure that you consult with us before you use these hyundai products in equipment which require high quality and / or reliability, and in equipment which could have major impact to the welfare of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of safety devices, etc.). hyundai cannot accept liability to any damage which may occur in case these hyundai products were used in the mentioned equipment without prior consult at ion with hyundai. copyright 199 9 hyundai micro electronic s co.,ltd. all rights reserved
4 GDC21D601 table of contents section 1. overview ................................ ................................ ................................ ..................... 8 1. general description ................................ ................................ ................................ .............. 8 2. feature ................................ ................................ ................................ ................................ 10 3. package ................................ ................................ ................................ .............................. 12 4. pin assignment ................................ ................................ ................................ ................... 13 5. pin descriptions ................................ ................................ ................................ .................. 15 section 2. system architecture ................................ ................................ ................................ 20 1. internal bus architecture ................................ ................................ ................................ ..... 20 2. arbiter ................................ ................................ ................................ ................................ . 20 3. system decoder ................................ ................................ ................................ ................. 21 4. memory map ................................ ................................ ................................ ....................... 21 5. memory format ................................ ................................ ................................ ................... 22 6. boot mode ................................ ................................ ................................ ........................... 22 7. multi-function pin ................................ ................................ ................................ ............... 23 section 3. arm720t core ................................ ................................ ................................ .......... 24 1. general description ................................ ................................ ................................ ............ 24 2. feature ................................ ................................ ................................ ................................ 24 3. core block diagram ................................ ................................ ................................ ............ 26 section 4. dram controller ................................ ................................ ................................ ...... 27 1. general description ................................ ................................ ................................ ............ 27 2. hardware interface and signal description ................................ ................................ ........ 28 3. functional description ................................ ................................ ................................ ........ 31 4. register description ................................ ................................ ................................ ............ 34 section 5. on-chip sram ................................ ................................ ................................ ......... 37 1. general description ................................ ................................ ................................ ............ 37 2. signal description ................................ ................................ ................................ ............... 37 3. function description ................................ ................................ ................................ ........... 37 section 6. static memory controller ................................ ................................ ........................ 38 1. general description ................................ ................................ ................................ ............ 38 2. signal description ................................ ................................ ................................ ............... 39 3. functional description ................................ ................................ ................................ ........ 43 4. programmer ? s model ................................ ................................ ................................ .......... 45
5 GDC21D601 section 7. mcu controller ................................ ................................ ................................ ......... 48 1. general description ................................ ................................ ................................ ............ 48 2. signal description ................................ ................................ ................................ ............... 48 3. register description ................................ ................................ ................................ ............ 49 section 8. power management unit ................................ ................................ ......................... 54 1. general description ................................ ................................ ................................ ............ 54 2. hardware interface and signal description ................................ ................................ ........ 55 3. operation modes ................................ ................................ ................................ ................ 56 4. register description ................................ ................................ ................................ ............ 58 5. power management unit register map ................................ ................................ .............. 63 6. test mode guide for mcu ................................ ................................ ................................ .. 64 7. signal timing diagram ................................ ................................ ................................ ........ 66 section 9. watchdog timer ................................ ................................ ................................ ....... 68 1. general description ................................ ................................ ................................ ............ 68 2. hardware interface and signal description ................................ ................................ ........ 69 3. watchdog timer introduction ................................ ................................ ............................. 71 4. watchdog timer operation ................................ ................................ ................................ 72 5. watchdog timer memory map ................................ ................................ ........................... 74 6. watchdog timer register descriptions ................................ ................................ .............. 75 7. examples of register setting ................................ ................................ .............................. 77 section 10. interrupt controller ................................ ................................ ................................ 81 1. general description ................................ ................................ ................................ ............ 81 2. hardware interface and signal description ................................ ................................ ........ 82 3. interrupt controller ................................ ................................ ................................ .............. 84 4. interrupt controller memory map ................................ ................................ ........................ 86 5. interrupt controller register descriptions ................................ ................................ ........... 87 section 11. real time clock ................................ ................................ ................................ ..... 91 1. general description ................................ ................................ ................................ ............ 91 2. signal description ................................ ................................ ................................ ............... 92 3. hardware interface ................................ ................................ ................................ ............. 93 4. functional description ................................ ................................ ................................ ........ 94 5. real time clock memory map ................................ ................................ ........................... 95 6. real time clock register descriptions ................................ ................................ .............. 95
6 GDC21D601 section 12. general purpose timer unit ................................ ................................ ................. 96 1. general description ................................ ................................ ................................ ............ 96 2. hardware interface and signal description ................................ ................................ ........ 97 3. general purpose timer unit introduction ................................ ................................ ......... 100 4. general purpose timer unit operation ................................ ................................ ............ 101 5. general purpose timer unit memory map ................................ ................................ ....... 102 6. general purpose timer unit register descriptions ................................ .......................... 104 7. examples of register setting ................................ ................................ ............................ 108 section 13. pio ................................ ................................ ................................ ......................... 111 1. general description ................................ ................................ ................................ .......... 111 2. signal description ................................ ................................ ................................ ............. 112 3. hardware interface ................................ ................................ ................................ ........... 115 4. functional description ................................ ................................ ................................ ...... 116 5. programmer ? s model ................................ ................................ ................................ ........ 117 section 14. synchronous serial peripheral interface ................................ ........................... 118 1. general description ................................ ................................ ................................ .......... 118 2. signal description ................................ ................................ ................................ ............. 119 3. hardware interface ................................ ................................ ................................ ........... 120 4. functional description ................................ ................................ ................................ ...... 121 5. register memory map ................................ ................................ ................................ ....... 123 6. sspi data clock timing diagram ................................ ................................ ..................... 124 section 15. uart ................................ ................................ ................................ ..................... 125 1. general description ................................ ................................ ................................ .......... 125 2. features ................................ ................................ ................................ ............................ 125 3. signal description ................................ ................................ ................................ ............. 126 4. internal block diagram ................................ ................................ ................................ ...... 129 5. registers description ................................ ................................ ................................ ........ 130 section 16. smart card interface ................................ ................................ ............................ 142 1. general description ................................ ................................ ................................ .......... 142 2. signal description ................................ ................................ ................................ ............. 143 3. hardware interface ................................ ................................ ................................ ........... 144 4. functional description ................................ ................................ ................................ ...... 145 5. programmer ? s model ................................ ................................ ................................ ........ 146
7 GDC21D601 section 17. i 2 c controller ................................ ................................ ................................ ........ 149 1. general description ................................ ................................ ................................ .......... 149 2. i 2 c controller key features ................................ ................................ .............................. 150 3. i 2 c controller clocking and pin functions ................................ ................................ ........ 150 4. i 2 c master mode transmit / receive process ................................ ................................ .. 150 5. i 2 c restart capability (combined mode) ................................ ................................ .......... 151 6. i 2 c controller programming model ................................ ................................ ................... 152 7. i 2 c module signal description ................................ ................................ .......................... 154 8. hardware interface ................................ ................................ ................................ ........... 155 9. register memory map ................................ ................................ ................................ ....... 156 section 18. direct memory access controller ................................ ................................ ...... 157 1. general description ................................ ................................ ................................ .......... 157 2. signal description ................................ ................................ ................................ ............. 158 3. programmer ? s model ................................ ................................ ................................ ........ 159 4. address modes ................................ ................................ ................................ ................. 163 section 19. debug and test interface ................................ ................................ .................... 167 1. general description ................................ ................................ ................................ .......... 167 2. software development debug and test interface ................................ ............................ 167 3. test access port and boundary scan ................................ ................................ .............. 167 section 20. electrical ratings ................................ ................................ ................................ . 169 1. absolute maximum ratings ................................ ................................ .............................. 169 2. thermal characteristics ................................ ................................ ................................ .... 169 3. d.c electrical characteristics ................................ ................................ ........................... 169 apendix a. register map ................................ ................................ ................................ ....... 170
8 GDC21D601 section 1. overview 1. general description the GDC21D601 is the hme ? s 32bit high performance microcontroller unit (mcu). the GDC21D601 contains arm720t, which is a general-purpose 32bit microprocessor, and extensive peripherals: 6 channel 16bit timer, watch dog timer, 2 channel uart, 2 channel sspi, 3 channel i 2 c, programmable priority interrupt controller, 10 port pio, 2 channel dma controller, external memory controller and bus controller including chip select logic. arm720t is a 32bit microprocessor with the cpu of the arm7tdmi, 8kb cache, enlarged write buffer and memory management unit (mmu). the arm720t is fully software compatible with the arm processor family. figure. 1 GDC21D601 block diagram 32- bit arm 720t core internal sram (8kb) amba logic apb bridge jtag int controller dma controller dram controller bus controller asb apb port i[0:7] portj[0:7] port b[0:7] / timer tcio / pwm port c[0:3] / timer tcio / pwm tclk a,b,c / port c[4:6] i 2 c channel 0 i 2 c channel 1 i 2 c channel 2 uart channel 0 , 1 smart card / uart channel 2 ( port d[0:7] ,port e[0:4] ) irq[0:5] / port a[0:5] ras[0:1] / port g[6:7] cas[0:3] / port g[0:3] dreq[0:1] / port g[2:3] dack[0:1] / port g[4:5] reset jtag[0:4] a[0:31] d[0:31] ncs [0:3] ncs [4:7] / port h[4:7] timer uart pio sspi i 2 c controller wdt rtc mcu controller sspi 0, 1 ( port e[5:7], port f[0:4] ) bclkout / port f[5] bwait / port f[4] exprdy expclk dram oe, we wr[0:3], rd rd&wr rtcin /out (32.768khz) npdm pmu wdtout mode[0:2] GDC21D601 GDC21D601 32-bit risc mcu
9 GDC21D601 the general descriptions of the GDC21D601 like following : on-chip modular architecture (using amba) utilizes the arm720t( ? arm7tdmi with 8kbyte cache and mmu ? ) 32bit risc family 8kbyte internal sram support 8bit/16bit/32bit external data bus width eight programmable chip select output s with exprdy support little and big endian memory format low power consumption using power management unit full y static operation : max. 8 0mhz two 32bit dma controller s (external request only) programmable priority interrupt controller (6 external sources) two dram bank s support six 16bit multi function timer s / counters for general purpose applications one 8bit watch dog timer (wdt) real time clock : 32.768 khz three uart s (universal asynchr o nous receiver transmitter) compatible with 16c550 uart , one uart with smart card interface two sspi s (synchronous serial peripheral interface) with fifo three i 2 c master/slave controller s programmable input/ o utput (8bit 10 channel) 208 mqfp package
10 GDC21D601 2. feature arm720t core - this is an arm7tdmi cpu core with . 8kb cache . enlarged write buffer . mmu (memory management unit) . on-chip icebreaker debug support . 32-bit x 8 hardware multiplier . thumb decompressor . high-performance 32-bit risc architecture . high-density 16-bit insturction set enhanced arm software toolkit thumb code is able to provide up to 6 5% of the code size of arm, and 160% of the performance of an equivalent arm processor connected t o a 16-bit memory system . the mmu supports 4g bytes virtual address. the allocation of virtual addresses with different task id improves performance in task switching operations with the cache enabled. dma controller - two channels with identical function - four gigabytes of address space - 256 kbytes transfers to the maximum - data transfer unit : byte, half-word, word - two kinds of bus mode . burst mode . exception mode(cycle steal) - two kinds of address mode . single address mode . dual address mode - two types of transfer request source . external i/o request . auto-request - two kind of fixed priority for channels - interrupted when the data transfers are complete dram controller - dram access - support word, half-word, and byte transaction - cbr refresh in normal operation and self-refresh in power-down mode - support programmable refresh rate - support various dram access time by setting the wait count control register static memory controller - chip select up to 8 (each bank is 256 mbyte) - exchangeable chip select active high/low (cs6 and cs7 only) - little - endian and big-endian memory support - programmable wait-state (up to 16 wait-state) - support external bus ready strobe - support various type bus control timing - support word, half-word, and byte transaction on-chip sram - 8k bytes(2048x32) - asynchronous sram - can write 8/16/32bits data, and read 32bits data mcu controller - the memory map structure control signals - dram power-down request and powr-down ack signal - generate the multi function pin control signals - device code : $gdc601 power management unit - power on reset, wd_of reset, and s/w reset - status : reset, power down, run _ fast, run _ slow - provide separated clock for each modules on chip - provide bclkout, wd_of, p ower- d own pins for external devices watch dog timer - watchdog timer mode & interval timer mode - eight counter clock sources - generate the power down reset or the watch dog overflow interrupt controller - asynchronous interrupt controller - six external interrupt - twenty internal interrupt - level or edge triggered - mask for each interrupt source request of irq, fiq for each interrupt source
11 GDC21D601 real time clock - 32bit counter clocked by a 32.768khz clock. - 32bit match register programmable input output - up to 80 pin (8bit 10channel) - each pin can be configurable as either input or output timer - 6 channel 16 - bit up-count - 4- internal pre - sca leable , 4- external input clock . 1 interrupt per 1 channel . 2 inout pin per 1 channel for input capture or output compare - basic function : . compare match waveform output . input capture . match clear . capture clear - synchronous mode . synch. clear at two or more channel . synch. write at two or more channel - pwm waveform output mode synchronous serial interface - supports full duplex communication - sends and receives data continuously, using 16 x 8 bit fifos - built-in baud rate generator capable of generation 4 clock rate - selectable clock source : either built-in buad-rate generator or e xternal clock - 4 independent interrupts : transmit-end, rx-full, tx-empty and tx-full uart - 2 channel : uart only . compatible with 16550 . 16 byte each fifo for tx / rx . start, stop and parity bit can be added or deleted from/to serial data . modem control functions (cts, rts, dsr, dtr, ri and dcd ) . fully programmable serial-interface characteristics : 5-, 6-, 7- or 8-bit characters : even, odd or no-parity bit generation and detection : 1-, 1.5- or 2-stop bit generation and detection smartcard interface - 1 channel : support smartcard interface . supports only asynchronous operation . supports cards that have internal reset capability . supports cards that have an active low reset input . supports cards that use the internal clock . generate the clock for a card expecting the external clock . use the serial in/out ports for i/o . use the pio ports for other interface signals like rst, detect, etc i 2 c - 3 channels - master / slave function - programmable clock speed - 8bit data transfer - slave clock stretch support - maskable interrupt - support clock rates up to 1.84mhz baud
12 GDC21D601 3. package figure 2. package outline GDC21D601r1 99 21 rev. es arm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 96 95 94 93 92 91 90 89 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 135 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 134 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 45 46 47 48 49 50 51 52 157 158 159 160 161 162 163 164 104 103 102 101 100 99 98 97 156 155 154 hme 32bit mcu (top view)
13 GDC21D601 4 . pin assignment pin name pin name pin name pin name 1 a0 45 irq0/pa0 89 vdd 133 nras0/pg6 2 a1 46 vdd 90 smdi/pe2 134 vss 3 vdd 47 irq1/pa1 91 smdo/pe3 135 nras1/pg7 4 a2 48 irq2/pa2 92 smclk/pe4 136 ncas0/ph0 5 a3 49 irq3/pa3 93 vss 137 ncas1/ph1 6 a4 50 vss 94 sin0/ pe5 138 ncas2/ph2 7 vss 51 irq4/pa4 95 sout0 /pe6 139 ncas3/ph3 8 a5 52 irq5/pa5 96 sclk0 /pe7 140 vss 9 a6 53 pa6 97 vdd 141 x out 10 a7 54 pa7 98 scs0 /pf0 / membyte0 142 x in 11 vdd 55 tcioa0/pb0 99 sin1 /pf1 / membyte1 143 vdd 12 a8 56 vdd 100 sout1 /pf2 144 ndramoe 13 a9 57 tciob0/pb1 101 vss 145 ndramwe 14 a10 58 tcioa1/pb2 102 sclk1 /pf3 146 vss 15 vss 59 tciob1/pb3 103 scs1 /pf4 147 nwr0 16 a11 60 vss 104 bclkout/pf5 148 nwr1 17 a12 61 tcioa2/pb4 105 nfiqout/pf6 149 nwr2 18 vdd 62 tciob2/pb5 106 nirqout/pf7 150 vdd 19 a13 63 tcioa3/pb6 107 vdd 151 nwr3 20 a14 64 vdd 108 i 2 csda0 152 nrd 21 a15 65 tciob3/pb7 109 i 2 cscl0 153 rdnwr 22 vss 66 pc0/tcioa4 110 i 2 csda1 154 vss 23 a16 67 pc1/tciob4 111 vss 155 nexprdy 24 a17 68 vss 112 i 2 cscl1 156 expclk 25 a18 69 pc2/tcioa5 113 i 2 csda2 157 ncs0 26 vdd 70 pc3/tciob5 114 i 2 cscl2 158 ncs1 27 a19 71 pc4/tclka 115 vdd 159 ncs2 28 a20 72 vdd 116 mode0/treqa 160 vdd 29 a21 73 pc5/tclkb 117 mode1/treqb 161 ncs3 30 vss 74 pc6/tclkc 118 mode2/tack 162 ncs4/ph4 31 a22 75 pc7/tclkd 119 vss 163 ncs5/ph5 32 a23 76 rxd0 / pd0 120 uclk out 164 vss 33 wdtout 77 vss 121 uclk in 165 cs6/ph6 34 np dn 78 txd0 / pd1 122 vdd 166 cs7/ph7 35 vss 79 rxd1/ pd2 123 test 167 d31/pj7 36 rtcosc in 80 txd1/pd3 124 nextreq/pg0 168 vdd 37 rtcosc out 81 vdd 125 nreset 169 d30/pj6 38 vdd 82 ncts/ pd4 126 vss 170 d29/pj5 39 ntrst 83 ndsr/ pd5 127 nextack/pg1 171 d28/pj4 40 tdi 84 ndcd/ pd6 128 ndreq0/pg2 172 vss 41 tck 85 vss 129 ndack0/pg3 173 d27/pj3 42 vss 86 nri/ pd7 130 vdd 174 d26/pj2 43 tdo 87 ndtr/pe0 131 ndreq1/pg4 175 d25/pj1 44 tms 88 nrts/pe1 132 ndack1/pg5 176 vdd
14 GDC21D601 pin name pin name pin name pin name 177 d24/pj0 185 vdd 193 vdd 201 vdd 178 d23/pi7 186 d17/pi1 194 d11 202 d5 179 d22/pi6 187 d16/pi0 195 d10 203 d4 180 d21/pi5 188 d15 196 d9 204 d3 181 vss 189 vss 197 vss 205 vss 182 d20/pi4 190 d14 198 d8 206 d2 183 d19/pi3 191 d13 199 d7 207 d1 184 d18/pi2 192 d12 200 d6 208 d0
15 GDC21D601 5 . pin descriptions pin number pin name type description 1~2, 4~6, 8~10, 12~14, 16~17, 19~21, 23~25, 27~29, 31~32 a[31:0] o address bus valid after reset. 33 wdtout o watch dog timer overflow output 34 npdn o power down signal from pmu block when it is low, mcu entered the power down mode. when high, normal 3 7 rtcoscin i real time clock oscillator input 32.768khz 3 6 rtcoscout o real time clock oscillator output 39 nrst i jtag reset 40 tdi i jtag data input 41 tck i jtag clock input 43 tdo o jtag data output 44 tms i jtag mode signal irq0 external interrupt input 0, when pinmux_pa[0] = 0 programmable i/o ports. each pin can be mapped to specified function pin name. (external irq0,irq1, ? ) 45 pa0 i/o pio port a[0], when pinmux_pa[0] = 1 irq1 external interrupt input 1, when pinmux_pa[1] = 0 47 pa1 i/o pio port a[1], when pinmux_pa[1] = 1 irq2 external interrupt input 2, when pinmux_pa[2] = 0 48 pa2 i/o pio port a[2], when pinmux_pa[2] = 1 irq3 external interrupt input 3, when pinmux_pa[3] = 0 49 pa3 i/o pio port a[3], when pinmux_pa[3] = 1 irq4 external interrupt input 4, when pinmux_pa[4] = 0 51 pa4 i/o pio port a[4], when pinmux_pa[4] =1 irq5 external interrupt input 5, when pinmux_pa[5] = 0 52 pa5 i/o pio port a[5], when pinmux_pa[5] = 1 53 pa6 i/o pio port a[6] tbclk clock input for tic test 54 pa7 i/o pio port a[7] tfclk clock input for tic test tcioa0 timer channel 0 input capture a, when pinmux_pb[0] = 0 55 pb0 i/o pio port b[0], when pinmux_pb[0] = 1 tciob0 timer channel 0 input capture b, when pinmux_pb[1] = 0 57 pb1 i/o pio port b[1], when pinmux_pb[1] = 1 tcioa1 timer channel 1 input capture a, when pinmux_pb[2] = 0 58 pb2 i/o pio port b[2], when pinmx_pb[2] = 1 tciob1 timer channel 1 input capture b, when pinmux_pb[3] = 0 59 pb3 i/o pio port b[3], when pinmux_pb[3] = 1 tcioa2 timer channel 2 input capture a, when pinmux_pb[4] = 0 61 pb4 i/o pio port b[4], when pinmux_pb[4] = 1 tciob2 timer channel 2 input capture b, when pinmux_pb[5] = 0 62 pb5 i/o pio port b[5], when pinmux_pb[5] = 1
16 GDC21D601 pin number pin name type description tcioa3 timer channel 3 input capture a, when pinmux_pb[6] = 0 63 pb6 i/o pio port b[6], when pinmux_pb[6] = 1 tciob3 timer channel 3 input capture b, when pinmux_pb[7] = 0 65 pb7 i/o pio port b[7], when pinmux_pb[7] = 1 pc0 pio port c[0], when pinmux_pc[0] = 0 66 tcioa4 i/o timer channel 4 input capture a, when pinmux_pc[0] = 1 pc1 pio port c[1], when pinmux_pc[1] = 0 67 tciob4 i/o timer channel 4 input capture b, when pinmux_pc[1] = 1 pc2 pio port c[2], when pinmux_pc[2] = 0 69 tcioa5 i/o timer channel 5 input capture a, when pinmux_pc[2] = 1 pc3 pio port c[3], when pinmux_pc[3] = 0 70 tciob5 i/o timer channel 5 input capture b, when pinmux_pc[3] = 1 pc4 pio port c[4], when pinmux_pc[4] = 0 71 tclka i/o external timer clock source a, when pinmux_pc[4] = 1 pc5 pio port c[5], when pinmux_pc[5] = 0 73 tclkb i/o external timer clock source b, when pinmux_pc[5] = 1 pc6 pio port c[6], when pinmux_pc[6] = 0 74 tclkc i/o external timer clock source c, when pinmux_pc[6] = 1 pc7 pio port c[7], when pinmux_pc[7] = 0 75 tclkd i/o external timer clock source d, when pinmux_pc[7] = 1 rxd0 uart channel 0 receive data, when pinmux_pd[0] = 0 76 pd0 i/o pio port d[0], when pinmux_pd[0] = 1 txd0 uart channel 0 transmit data, when pinmux_pd[1] = 0 78 pd1 i/o pio port d[1], when pinmux_pd[1] =1 rxd1 uart channel 1 receive data, when pinmux_pd[2] = 0 79 pd2 i/o pio port d[2], when pinmux_pd[2] = 1 txd1 uart ch 1 transmit data, when pinmux_pd[3] = 0 80 pd3 i/o pio port d[3], when pinmux_pd[3] =1 ncts uart ch 1 clear to send, when pinmux_pd[4] = 0 82 pd4 i/o pio port d[4], when pinmux_pd[4] = 1 ndsr uart ch 1 data set ready, when pinmux_pd[5] = 0 83 pd5 i/o pio port d[5], when pinmux_pd[5] = 1 ndcd uart ch 1 data carrier detect, when pinmux_pd[6] = 0 84 pd6 i/o pio port d[6], when pinmux_pd[6] = 1 nri uart ch 1 ring indicator, when pinmux_pd[7] = 0 86 pd7 i/o pio port d[7], when pinmux_pd[7] =1 ndtr uart c 1 data terminal ready, when pinmux_pe[0] = 0 87 pe0 i/o pio port e[0], when pinmux_pe[0] = 1 nrts uart ch 1 ready to send data, when pinmux_pe[1] = 0 88 pe1 i/o pio port e[1], when pinmux_pe[1] = 1 smdi smart card interface data in, when pinmux_pe[2] = 0 90 pe2 i/o pio port e[2], when pinmux_pe[2] = 1 smdo i/o smart card interface data out, when pinmux_pe[3] = 0 91 pe3 pio port e[3], when pinmux_pe[3] =1 smclk i/o smart card interface clock out, when pinmux_pe[4] = 0 92 pe4 pio port e[4], when pinmux_pe[4] = 1
17 GDC21D601 pin number pin name type description sin0 ssi channel 0 data in, when pinmux_pe[5] = 0 pe5 pio port e[5], when pinmux_pe[5] =1 94 bprot0 i/o amna bprot[0] signal, when pinmux_pe[8] = 1 sout0 ssi channel 0 data out, when pinmux_pe[6] = 0 pe6 pio port e[6], when pinmux_pe[6] = 1 95 bprot1 i/o amba bprot[1] signal, when pinmux_pe[8] = 1 sclk0 ssi channel 0 clock out, when pinmux_pe[7] = 0 pe7 pio port e[7], when pinmux_pe[7] =1 96 blok i/o amba blok signal out, when pinmux_pe[8] = 1 scs0 ssi channel 0 channel control, when pinmux_pf[0] = 0 pf0 pio port f[0], when pinmux_pf[0] = 1 98 membyte0 i/o membyte[0] signal from ebi block, when pinmux_pf[8] = 1 sin1 ssi channel 1 data in, when pinmux_pf[1] = 0 pf1 pio port f[1], when pinmux_pf[1] = 1 99 membyte1 i/o membyte[1] signal from ebi block, when pinmux_pf[8] = 1 sout1 ssi channel 1 data out, when pinmux_pf[2] = 0 pf2 pio port f[2], when pinmux_pf[2] = 1 100 btrans0 i/o amba btrans[0] signal, when pinmux_pf[8] = 1 sclk1 ssi channel 1 clock out, when pinmux_pf[3] = 0 pf3 pio port f[3], when pinmux_pf[3] = 1 102 btrans[1] i/o amba btrans[1] signal, when pinmux_pf[8] = 1 scs1 ssi channel 1 channel control, when pinmux_pf[4] = 0 pf4 pio port f[4], when pinmux_pf[4] =1 103 bwait i/o amba bwait signal, when pinmux_pf[8] = 1 bclkout amba bclk signal, when pinmux_pf[5] = 0 104 pf5 i/o pio port f[5], when pinmux_pf[5] = 1 nfiqout amba nfiq signal, when pinmux_pf[6] = 0 105 pf6 i/o pio port f[6], when pinmux_pf[6] =1 nirqout amba nirq signal, when pinmux_pf[7] = 0 106 pf7 i/o pio port f[7], when pinmux_pf[7] = 1 108 i 2 csda0 i/o data signal for i 2 c channel 0 pins (108~110,112~114) are required to be pull-up externally. when bus is free, this pin goes logical ? high ? after reset, sda pins enter idle state 109 i 2 cscl0 i/o clock signal for i 2 c channel 0 110 i 2 csda1 i/o data signal for i 2 c channel 1 112 i 2 cscl1 i/o clock signal for i 2 c channel 1 113 i 2 csda2 i/o data signal for i 2 c channel 2 114 i 2 cscl2 i/o clock signal for i 2 c channel 2 mode0 boot mode0, when test pin = 0 by default, 32-bit access ( mcu can boot from 32- bit memory) 116 treqa i treqa signal for tic test, when test pin = 1 mode1 boot mode 1 117 treqb i treqb signal for tic test mode[0:1] = 00 32-bit mode[0:1] = 01 8-bit mode[0:1] = 10 16-bit mode[0:1] = 11 reserved
18 GDC21D601 pin number pin name type description mode 2 boot mode 2 (bigendian pin) big-endian selection pin, when this pin = 1(high) note) when this pin is high, external data will be transferred ? big-endian ? format. 118 tack i/o tack signal for tic test 120 uclkin i uart clock oscillator clock input uart block dedicated clock source supported. (this clock source is used for uart and smart card only) 121 uclkout o uart clock oscillator clock output 123 test i test input pin, select 116~118 pin as boot mode or tic signal nextreq external master request bus mastership, when pinmux_pg[0] = 0 124 pg0 i/o pio port g[0], when pinmux_pg[0] = 1 125 nreset i system power on reset input to ensure proper initialization after power is stable, assert nreset pin for at least 20 m s nextack bus granted signal for external master, when pinmux_pg[1] = 0 127 pg1 i/o pio port g[1] = 1, when pinmux_pg[1] = 1 ndreq0 dma channel 0 request, when pinmux_pg[2] = 0 128 pg2 i/o pio port g[2], when pinmux_pg[2] = 1 ndack0 dma channel 0 acknowledge, when pinmux_pg[3] = 0 129 pg3 i/o pio port g[3], when pinmux_pg[3] = 1 ndreq1 dma channel 1 request, when pinmux_pg[4] = 0 131 pg4 i/o pio port g[4], when pinmux_pg[4] = 1 ndack1 dma channel 1 acknowledge, when pinmux_pg[5] = 0 132 pg5 i/o pio port g[5], when pinmux_pg[5] = 1 nras0 dram bank #0 ras signal, when pinmux_pg[6] = 0 133 pg6 i/o pio port g[6], when pinmux_pg[6] = 1 nras1 dram bank #1 ras signal, when pinmux_pg[7] = 0 135 pg7 i/o pio port g[7], when pinmux_pg[7] = 1 ncas0 dram cas0 signal, when pinmux_ph[0] = 0 136 ph0 i/o pio port h[0], when pinmux_ph[0] = 1 ncas1 dram cas1 signal, when pinmux_ph[1] = 0 137 ph1 i/o pio port h[1], when pinmux_ph[1] = 1 ncas2 dram cas2 signal, when pinmux_ph[2] = 0 138 ph2 i/o pio port h[2], when pinmux_ph[2] = 1 ncas3 dram cas3 signal, when pinmux_ph[3] = 0 139 ph3 i/o pio port h[3], when pinmux_ph[3] = 1 142 xin i system clock input (<80mhz) external ttl oscillator input 141 xout o system clock oscillator output 144 ndramoe o dram output enable 145 ndramwe o dram write enable 147 nwr0 o write enable 0 for static memory(byte) 148 nwr1 o write enable 1 for static memory(byte) 149 nwr2 o write enable 2 for static memory(byte) 151 nwr3 o write enable 3 for static memory(byte)
19 GDC21D601 pin number pin name type description 152 nrd o output enable signal for static memory 153 rdnwr o read/write signal 155 exprdy i ready signal input when this pin is low, current memory transfer extended. 156 expclk o clock output signal active only during external cycles. output is same phase and speed as the bus clock 157 ncs0 o chip select signal for bank #0 ncs pins are required to be pull-up for proper operation. all ncs pins are active low see fig.1 memory map(section 2) 158 ncs1 o chip select signal for bank #1 159 ncs2 o chip select signal for bank #2 161 ncs3 o chip select signal for bank #3 162 ncs4 i/o chip select signal for bank #4, when pinmux_ph[4] = 0 ph4 pio port h[4], when pinmux_ph[4] = 1 ncs5 chip select signal for bank #5, when pinmux_ph[5] = 0 163 ph5 i/o pio port h[5], when pinmux_ph[5] = 1 cs6 chip select signal for bank #6, when pinmux_ph[6] = 0 cs6 pin can be programmed active high/low 165 ph6 i/o pio port h[6], when pinmux_ph[6] = 1 cs7 chip select signal for bank #7, when pinmux_ph[7] = 0 cs7 pin can be programmed active high/low 166 ph7 i/o pio port h[7], when pinmux_ph[7] = 1 167, 169~171, 173~175, 177~180, 182~184, 186~188, 190~192, 194~196, 198~200, 202~204, 206~208 d[31:0] i/o data bus 167, 169~171, 173~175, 177 pj[7:0] i/o pio port j[7:0], when pinmux_pj[7:0] = 1 178~180, 182~184, 186~187 pi[7:0] i/o pio port i[7:0] , when pinmux_pj[7:0] = 1 3, 11, 18, 26, 38, 46, 56, 64, 72, 81, 89, 97, 107, 115, 122, 130, 143, 150, 160, 168, 176, 185, 193, 201 vdd i power 7, 15, 22, 30, 35, 42, 50, 60, 68, 77, 85, 93, 101, 111, 119, 126, 134, 140, 146, 154, 164, 172, 181, 189, 197, 205 vss i ground
20 GDC21D601 section 2. system architecture 1. internal bus architecture the GDC21D601 take the advantage of the amba(advanced micro-controller bus architecture) as the internal bus architecture. the amba specification defines an on-chip communication standard for designing high- performance embedded micocontrollers. two distinct buses are defined within the amba: - the advanced system bus (asb) - the advanced peripheral bus (apb) the amba asb is for high-performance system modules. the modules connected to asb are dram controller, static memory controller, dma controller, on-chip sram, arm720t cpu core, arbiter, decoder, apb bridge, and tic. the amba apb is for low-power peripherals. amba apb is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. the modules connected to apb are pio, interrupt controller, pmu, wdt, rtc, timer, uart, sspi, and i 2 c. see also amba specification rev. d (arm ihi 0001d), and amba specification rev. 2.0 (arm ihi 0011a) for detail. 2. arbiter the amba bus specification is a multi-master bus standard. as a result, a bus arbiter is needed to ensure that only one bus master has an access to the bus at any particular point of time. each bus master can request the bus; the arbiter decides which has the highest priority and issues a grant signal accordingly. the GDC21D601 can have the four bus master: arm720t cpu core, dma controller, tic, and external bus master. every system must have a default bus master which grant s the use of bus during reset, when no other bus master requires the bus. during power on reset, the arbiter will grant the use of bus to the default bus master and hold all other grant signals inactive. the arm720t core , the default bus master will grant for the use of bus under the following conditions: reset , standby , power-down , and no other master requesting the bus the arbiter processes the requests of the ownership of the asb and grants one asb master according to the arbitration scheme. the arbitration scheme of this implementation is a simple priority encoded scheme where the highest priority master requesting the asb is granted. the priority order is as follows: case 1) aripri = ? 0 ? 1. tic 2. dma 3. external bus master 4. arm (default bus master) case 2) aripri = ? 1 ? 1. tic 2. external bus master 3. dma 4. arm (default bus master)
21 GDC21D601 3 . system decoder the decoder in an amba system is used to perform a centralized address decoding function, which gives two main advantages: - it improves the portability of peripherals, by making them independent of the system memory map. - it simplifies the design of bus slaves, by centralizing the address decoding and bus control functions. the decoder performs three main tasks : - address decoder - default transfer response - protection unit the decoder generates a select signal for each slave on the asb bus and, under certain circumstances, will not select any slaves and provide the transac-tion response itself. the mcu system memory map is shown in figure 1. the decoder greatly simplifies the slave interface and removes the need for the slave to understand the different types of transfer that may occur on the bus. 4. memory map the system decoder controls the memory map of the system and generates a slave select signal for each memory region. the remap signal is used to provide a different memory map : rom is required at address 0 when power on reset, and ram also may be used at address 0 during normal operation. the remap signal is typically provided by a power management unit (pmu) which drives remap to low at reset. the signal is only driven to high after a particular register in the pmu is accessed (see section. 9 power management unot for detail) . when remap is high and isram signal is high, then memory map configuration is mode a which the internal sram is located at address 0x00. and when remap is high and drambank0 signal is high, then memory map configuration is mode b which the dram bank #0 is located at address 0x00. the isram and drambank0 signal come from mcu controller. see section 8. mcu controller for detail. figure 2 . memory map configuration shows both the reset (mode r) and the normal (mode b and mode a) memory map figure 1. shows the system memory map.
22 GDC21D601 5 . memory format the arm720t cpu core supports both the big-endian and little-endian format. and the GDC21D601 can also support the big-endian and little-endian memory format. the GDC21D601 can support the little-endian format by default. when using the GDC21D601 as big-endian format: 1) set boot mode 2 pin to vdd, and 2) set the arm720t as big-endian mode with using coprocessor instruction. 3) set the big-endian flag of the compile options when compile. the example of the coprocessor instruction is in the below. it is noted that cp15 register (cpu control register) can only be accessed with mrc and mcr instructions in a privileged mode. see the arm720t data sheet (arm ddi 0087d) for detail. the arm720t data sheet is downloadable from arm home page (http://www.arm.com). for example : mrc p15, 0, r3, c1, c1 orr r3, r3, #0x80 mcr p15, 0, r3, c1, c1 note : the GDC21D601 has a ebi (external bus interface) block which can copy the byte or half- word of the lower position in data bus to higher data bus position, so you can use the GDC21D601 as bigend mode by only set the boot mode 2 pin to vdd and in this case you may not set the arm720t as bigend mode. 6 . boot mode the GDC21D601 can support 32/16/8 bit boot rom. by default mcu can boot from 32 bit rom. in this case boot mode[1:0] (pin number 116 and 117) are ? 00 ? . if you want use 16 bit boot rom, then you must set boot mode[1:0] are ? 10 ? . and in case of booting from 8 bit rom, you must set boot mode[1:0] are ? 01 ? . it is for reserved in case that boot mode[1:0] are ? 11 ? . see the table 1. the description of the mode pin. in all case of boot mode the wait cycle of boot area is 3 cycles. if you want to know about boot mode for detail you must see the section 6. static memory controller. table 1. the description of the mode pin mode[1:0] bus width of booting rom 00 32 bit 01 8 bit 10 16 bit 11 reserved
23 GDC21D601 7 . multi-function pin the GDC21D601 has 80 bit pio pins with multiplexed by other functional pins. so you must use properly these multi-function pins by setting the pinmux control registers in mcu controller. (see section 8. mcu controller for detail) figure 1. system memory map address 0x00ffffff 0x00000fff 0x00000000 mode r mode a mode b 0x01ffffff 0x2ffffff ncs0 ncs 1 ncs2 on-chip ram ncs0 or dram #0 ncs 1 ncs2 ncs2 ncs1 dram #0 1. mode r : reset mode : default mode from power-on reset (remap is low) 2. mode a : on-chip sram in 0x0000 ~ 0x0 7 ff range : remap is high and isram is high 3. mode b : dram bank #0 in 0x00000000 ~ 0x00ffffff range : remap is high and drambank0 is high figure 2 . memory map configuration chip select area asb register apb register 0 xffff ffff 0 xffff e000 0 xffff f000 0 x0000 0000 0 x0800 0000 memory area 0 xffff ffff reserved f900 f800 f500 f400 f300 f200 f100 f000 ef00 ee00 ed00 ec00 eb00 ssi uart0 wdt timer pmu intc pio arm7 test reg dmac dramc smi mcuc 0 xffff eaff reserved 0 x4000 0000 0 x3000 0000 0 x2000 0000 0 x1000 1000 0 x1000 0000 0 x0800 0000 0 x0700 0000 0 x0600 0000 0 x0500 0000 0 x0400 0000 0 x0300 0000 0 x0200 0000 0 x0100 0000 0 x0000 0000 dram bank #1 dram bank #0 window area on-chip ram window area ncs7 ncs6 ncs5 ncs4 ncs3 ncs2 ncs1 ncs0 fc00 rtc i2c0 uart1 uart2/smart i2c1 i2c2 f600 f700 fa00 fb00 fd00 0 x5000 0000 0 x6000 0000 reserved cs7 cs6
24 GDC21D601 section 3. arm720t core 1. general description arm720t is 32bit microprocessor of general purpose with 8kb cache, enlarged write buffer and memory management unit (mmu), which are combined in a single chip. the cpu within arm720t is the arm7tdmi. the arm720t is software compatible with the arm processor family. the arm7tdmi is a member of the arm family of general purpose 32bit microprocessors, which offer s high performance for very low power consumption and price. this processor employs a unique architectural strategy known as thumb , which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue. the key idea behind thumb is a super reduced instruction set. essentially, the arm7tdmi has two instruction sets, the standard 32bit arm set and 16bit thumb set. the thumb set ? s 16bit instruction length allows it to approach twice the density of standard arm code while retain ing most of the arm`s performance advantage over a traditional 16bit processor by using 16bit registers. this is possible because thumb code operates on the same 32bit register set as arm code. see also arm720t datasheet (arm ddi 0087d) for detail. 2. feature 32bit risc architecture low power consumption arm7tdmi core with; - on-chip icebreaker debug support - 32bit x 8 hardware multiplier - thumb decompressor utilizes the arm7tdmi embedded processor - high performance 32 bit risc architecture - high density 16 bit instr u ction set fully static operation : 0 ~ 8 0mhz 3 - stage pipeline architecture (fetch, decode, and execut ion stage) enhanced arm software toolkit mmu, write buffer, 8kb i/d cache
25 GDC21D601 thumb code is able to provide up to 65% of the code size of arm, and 160% of the performance of an equivalent arm processor connected t o a 16-bit memory system. figure 1. arm720t b lock diagram mmu 8 kb cache arm7tdmi cpu internal data bus data and address buffers control and clocking logic system control coprocessor amba interface coprocessor interface jtag debug interface amba bus interface virtual address bus
26 GDC21D601 3. core block diagram ice breaker scan chain 0 rangeout0 rangeout1 estern1 extern0 tap controller tck tms ntrst tdi tdo taspm [3:0] ir [3:0] screg [3:0] address register ale abe a [ 31:0] address incrementer register bank (31 x 32-bit registers) (6 status registers) p c b u s a l u b u s i n c r e m e n t e r b u s 32 x 8 multiplier barrel shifter 32-bit alu write data register b b u s a b u s instruction pipeline & read data register & thumb instruction decoder nenout nenin dbe d [ 31:0] core dbgrqi breakpti dbgack eclk nexec isync bl [3:0] ape mclk nwait nirq nfiq nreset abort seq lock ncpi cpa cpb nm [4:0] tbe tbit highz instruction decoder & control logic scan control d [0:31] din [0:31] dout [0:31] bus splitter nrw mas [1:0] ntrans nmreq nopc a [0:31] scan chain 1 scanchain2 figure 2. arm7tdmi core block diagram
27 GDC21D601 section 4. dram controller 1. general description the dram controller interfaces the amba advanced system bus (asb) to external dram memory banks. the dram controller provides the following features: u p to two banks of dram s upport. fast page-mode sequential access support. edo dram support word, half-word and byte transaction support. little / big endian format support. dram refresh controller using cas-before-ras (cbr) refresh mode. programmable refresh rate. power-down mode where all dram accesses (including self-refresh) are disabled. programmable dram timing control. r ow/column addresses m ultiplexes according to dram capacity. figure 1 . dram controller module block diagram main state machine & control refresh timer & controller asb interface & address generator ebi signal control mux dram controller asb bus chip pad aout [23:0] datain [31:0] dataout [31:0] bd[31:0] nouten [3:0] ndramwe ndramoe nras [1:0] ncas [3:0] ncasfb [3:0] bclk pdreq pdack dseldram dselreg bnres blast berror bwait bwrite bsize[1:0] bd[31:0] ba[29:0] mux mux lat lat lat ndramalatch ndrama [12:0] ndramamux ndramouten [3:0] ndramoutlen ndraminlen [3:0] ndraminen drambyte [1:0]
28 GDC21D601 2 . hardware interface and signal description the dram controller module is connected to the asb bus. table 1 . dram interface asb signal descriptions shows the internal bus interface signals to the dram controller. table 1 . dram i nterface asb s ignal d escriptions name description ba [27:0] system address bus (excluding high order bits). bclk the asb clock timing all bus transfers. bd [7:0] bidirectional system data bus. berror error slave response signal. it is d riven to phase 1 if the dram controller is selected. this signal will be asserted , when an access to the dram is attempted while the dram controller is in its power down mode. blast last transfer of burst slave response signal. it c an be driven to phase 1 if the dram controller is selected. i t i s asserted in order to indicate a 256-word boundary to force a non- sequential access. bnres these signals indicate the reset status of the asb. bsize [1:0] these signals indicate the size of the transfer that may be byte, half - word , or word. bwait wait slave response signal. it is d riven to phase 1 when the dram controller is selected. it is a sserted while the dram transaction is u ncomplete d . bwrite when this signal is high , it indicates a write transfer and when low a read. dseldram when this signal is high , it indicates that the dram is selected. dselreg when this signal is high , it indicates that the dram configuration register is selected. table 2 . dram interface external dram signal descriptions describes the dram controller connections to external devices of the system and to ebi (external bus interface) block . table 2 . external dram signal descriptions name description nras[1:0] active low row address strobes, one for each dram bank. ncas[3:0] active low column address strobes, one for each byte. n dramoe active low output enable. ndramwe active low write enable. ncasfb[ 3 :0] this is the ncas[3:0] signal fed back from the output of the ncas[3:0] pads. pdreq power down request. this signal indicate s that the dram controller should enter into its low-power state, causing the drams to enter into self-refresh state if refresh is enabled. when it is deasserted, the dram controller will exit from low power state. pdack power down acknowledge. this signal is asserted when the dram controller has successfully entered into its low-power mode. at this point bclk may be stopped safely. it is d easserted when the dram controller has successfully exited from its low power state. dramamux dram address multiplex select. when this signal is high , it indicates to the ebi that the drama[12:0] address should be used to generate drama[12:0] . this signal provides the support for a shared ebi, and may not be needed in a system where the dram controller does not share the ebi with other memory controllers. dramamux is low wh en dram accesses are not performed .
29 GDC21D601 name description ndramalatch dram address latch. when this signal is low, it opens the ebi address latch. this signal is high when dram operations do not occur. this signal provides support for a shared ebi and may not be needed in a system where the dram controller does not share the ebi with other memory controllers. drama[12:0] these multiplexed address lines are connect ed to the dram address. ndraminen dram input enable. when this signal is low, it enables the ebi drivers from latched xd to bd. this signal is high when dram read operations are not performed. ndraminlen[3:0] dram input latch enable. when this signal is high , it shuts the ebi latches on x d. this signal is low when dram read operations are not performed. ndramouten dram output enable. when this signal is high , it disables the ebi drivers from latched bd to x d. this signal is low when dram write operations are not performed. ndramoutlen dram output latch enable. when this signal is low , it opens the ebi latches on bd. this signal is high when dram write operations are not performed. accesses to the dram controller module are generated as a result of the address decode put out on the asb address bus by the current bus master (which could be the arm cpu or the dma engine, for example). the following three diagrams show the timing of the external interface for read, write and refresh cycles (figure 2, 3, 4) . bclk drama[12:0] nras [1:0] xdata [31:0] noe ncas [1:0] nwe row col row col1 col2 col3 figure 2. dram external signal timing: read cycles
30 GDC21D601 bclk drama[12:0] nras [1:0] xdata [31:0] noe ncas [1:0] nwe row col row col1 col2 col3 data data1 data2 data3 figure 3. dram external signal timing: write cycles bclk nras [1:0] ncas [1:0] noe nwe figure 4. dram controller refresh cycle
31 GDC21D601 3 . functional description 3. 1 introduction the dram controller provides connections allowing a direct interface to up to two banks of dram. each bank is 32 /16/8 bits wide and up to 256mb in size. two ras lines are provided (one per bank) and four cas lines (one per byte line). 3. 2 functional breakdown the dram controller consists of four main blocks: the main state machine & control block , the ebi signal control block, the asb interface & address g eneration block, and the r efresh t imer & counter block . 3. 3 main state machine this block contains the main dram timing control state machine and the decode for the external strobe signals for the dram interface. the state machine generates the timing for the ncas and nras strobes, and the multiplexing of the dram row and column address lines for standard dram cycles and refresh cycles. the n dram we and n dram oe signals are asserted appropriately depending on the access type. word, h alf-word , and byte accesses are decoded from the lower bits of the ba address bus in order to assert the appropriate ncas line(s). for word accesses all four ncas lines are asserted. figure 5. descibes the main state machine diagram. local arbitration for refresh cycles is also carried out here as refresh requests are received from the refresh timer block. the block also supports the self refresh dram; enter to and exit from this self refresh state are initiated by the pdrreq signal. this is illustrated in figure 6. dram signal timing: power down mode. figure 5. main state machine diagram r_idle r_wait r_ rnr r_ wnr r_wnc1 r_wnc2 r_rnc1 r_rnc2 r_crwait dsel ras cas cas cas cas ! bwrite bwrite refreq or !dsel refreq or !dseld1 r_rnc3 r_rnc4 r_wnc3 r_wnc4 r_cwwait
32 GDC21D601 3.4 ebi control block this also generates the control signals required by the ebi (external bus interface) . the ebi control signals are divided into three main groups; those related to the control of the a ddress path, the datain path, and the dataout path. address path control there are three signa z ls related to the address path of the ebi: ndramalatch used to open the address latch of the ebi. this can be used to hold the external address xa while internal accesses are performed. when this signal is asserted (active low) the ebi address latch should be opened. when a dram access is not performed, the dram controller will de-assert this signal. in a shared ebi scheme, other memory controllers (static memory controller,...) must exhibit this behavior when they do not perform memory accesses. dramamux used to select the drama[12:0] address as the address to be used on xa. this signal will be asserted (active high) when a dram access occur s , and will be de-asserted when the transfer is complete d . drama[12:0] th e multiplexed row/column address used to access the dram. data in and dataout path control there are four signals related to the data path of the ebi: ndramouten used to enable the ebis data drivers onto xdata. when this signal is de-asserted (high) , the ebi should disable its drive onto xdata. this signal is de-asserted during read cycles and is asserted at other times. in a shared ebi scheme, other memory controllers must exhibit this behavi o r when they do not perform memory accesses. ndramoutlen used to latch the value of bd into the ebis data output latches. when this signal is asserted (active low), the ebi data output latch is opened. this signal will be asserted during dram write transfers, and is de-asserted at other times. ndraminen used to enabl e the ebi data drivers onto bd. when this signal is asserted (active low) , the ebi should be drive n onto bd. this signal is asserted during dram read transfers and is de-asserted at other times. ndraminlen[3:0] used to latch the value of xdata into the eb i data input latches. when this signal is de- asserted (high), the ebi data input latch is shut. four signals are provided to enable latching of byte / half-word data. ndraminlen[0] is used to latch the data on m_d[7:0]. this signal is normally asserted and will be de-asserted during dram read transfers to latch the current data on xdata.
33 GDC21D601 3. 5 refresh control block the refresh timer is a 7 -bit timer counter which counts down and generates a refresh request when it reaches zero, at this point it is reloaded with the value in the refresh control register. this allows refresh frequencies from the refresh control register and bclk input clock. 3. 6 asb interface block the asb interface provides the interaction with the main amba bus. the dram controller will initiate a dram access when the dseldram signal is asserted, or access the control register s when the dselreg strobe is asserted. the timing of the asb transfers is described in detail in the amba specification rev. d . at a 256-word boundary, the blast signal will be asserted to indicate to the bus master that the burst sequence should be broken within the page boundary. th is block also generates the row and column addresses. during burst mode accesses, the column address is provided by a 10-bit column address incrementor to provide adequate column address timing. bclk pdreq pdack ncas [3:0] noe nras [1:0] nwe figure 6. dram signal timing : power down mode
34 GDC21D601 4. register description 4.1 memory map the base address (=dram reg base) of the dram controller register bank is 0xffffed00. table 5 . memory map o f t he dram controller peripheral address write location read location initial base + 0x0 dram refresh control register (rcr) n/a 16 ? h0000 base + 0x4 dram control register for cpu dram control register for cpu 7 ? b0000000 base + 0x8 dram control register for dma dram control register for dma 6 ? b000000 base + 0xc dram test control register (tcr) n/a 4 ? b0000 4.2 dram refresh control register(rcr) the dram refresh period register is an 16- bit write register which enables the refresh and selects the refresh period used by the dram controller for its periodic cas-before-ras refresh. the value in the dram refresh period register is only cleared by a power on reset (bnres = 0). 15 8 7 6 0 refcnt rfshen rfdiv figure 7. dram controller refresh register refcnt dram refresh clock divisor. refresh clock is setting by this bit field : refclock = bclk/refcnt the r e f cnt field should not be programmed with zero s ince this results in no initiated refresh cycles. rfshen dram refresh enable. setting this bit enables periodic refresh cycles to be generated by the dram controller at the rate set by the rfdiv field. setting this bit also enables self - refresh mode when the dram controller is in the power down state. rfdiv this 7-bit field sets the dram refresh rate. the refresh period is derive n from internally generated clock and is given by the following formula: frequency (khz) = 2*[refclock /(rfdiv + 1) ] or rfdiv = ( refclock / 0.5* refresh frequency (khz) ) - 1 the rfdiv field should not be programmed with zero s ince this results in no initiated refresh cycles.
35 GDC21D601 4.3 dram control register for cpu (dramconcpu) this register controls the dram control signals when dram accessed by cpu. in normal condition, the dram access time is changed by the bus master is cpu or dma controller. in case of bus master is dma controller, the transfer timing should be properly set to the external i/o device and dram, so for the optimal system performance the dram access by the cpu is set in this dram control register for cpu (dramconcpu) and in case of the dram access by the dma controller dram control signals are controlled by the dram control register for dma (dramcondma). 15 7 6 5 4 3 2 1 0 reserved dmaen trp tcp waitcnt banksize figure 8. dram control register for cpu (dramconcpu) dmaen if dma transfer, then the dram control signals are controlled by dram control re gister for dma (dramdondma) by this bit setting. when this bit is ? 0 ? , then the dram control signals are controlled by bit fields in this control register (dramconcpu) during dram access. trp control the timing of difference between the ras and cas signal by this bit field setting. when this bit is ? 0 ? , then dram access are absolutely no wait, so dram access time is very short, but should be considered the operating frequency of the mcu and dram access time. tcp control the timing of the low phase of cas signals. when this bit is ? 1 ? , then the low phase of the cas signals are enlarged to one cycle of bclk. when this bit is ? 0 ? , then the low phase of the cas signals are half clock of bclk. waitcnt this bit fields control the dram access time. the wait sta te is inserted in asb bus by the value of these waitcnt fields. (00=0-wait, 01=1-wait, 10=2-wait, 11=3-wait) banksize these bits indicate the data width of the dram bank. the data width of the dram by banksize are shown table 6. table 6. data width of the dram by banksize[1:0] fields banksize[1:0] data width of dram 00 byte 01 half word 10 word 11 reserved
36 GDC21D601 4.4 dram control register for dma this register controls the dram control signals when dram accessed by dma. setting the register is effective only when the dmaen bit set by dramconcpu(dram control register from cpu). 15 6 5 4 3 2 1 0 reserve trp tcp waitcnt banksize figure 9. dram control register for dma (dramcondma) 4.5 dram test control (tcr) the dram test control register is for test and should not be used during normal operation. it is a write-only register with the following format. 15 4 3 2 1 0 reserved testinc forceadv forcesize figure 10. dram test control register test inc test increment (testinc). this bit puts the column address increment into a test mode. in this mode each nibble of the column address increment increments indepe n dently. reset s it to 0. force adv force refresh advance (forcerefadv). this bi t forces the refresh counter to advance every bclk. reset s it to 0. forcesize[1:0] force access size. these bits force the size of accesses to the dram bank. when this is set to 10 (default), the asb b_size is used to determine the size of the access. when this is set to 00 or 01, a byte or half-word access is forced respectively. reset s it to 10.
37 GDC21D601 section 5. on-chip sram 1. general description the GDC21D601 has 8-kbytes of on-chip ram. the on-chip ram is linked to the cpu and direct memory access controller(dmac) with 32-bit data bus. the cpu and dma controller can write data in to the on-chip ram in byte, half-word, or word units. 2 . signal description table 1 . signal descriptions name type description ba[31:0] i system address bus. bd[31:0] i/o bi-directional system data bus. bwait i/o low during phase one of bclk. blast i/o low during phase one of bclk. berror i/o low during phase one of bclk. bwrite i when this signal is high, it indicates a write transfer and when low a read. dselmem i when this signal is high, it indicates that on-chip ram is selected. bnres i these signals indicate the reset status of the asb. 3. function description on-chip sram can read data from sram and can write data in to sram in a single clock cycle through asb bus. and sram is single module which have 32 bit data bus and control lines. the data in the on-chip ram can always be accessed in one cycle that mak e the ram ideal for use as a program area, stack area, or data area, which require s high-speed access. the contents of the on-chip ram are held in both standby and power-down modes. memory area 0x10000000 to 0x1000 1f ff is allocated to the on-chip ram as default. when isram signal from mcu controller is set to high, memory area 0x00000000 to 0x0000 1f ff can be allocated to the on-chip ram.
38 GDC21D601 section 6. static memory controller 1. general description the static memory controller interfaces the amba advanced system bus (asb) to the external bus interface (ebi); controlling the external sram, rom, flash memory or off-chip peripherals. eight separate chip select banks are provided by this block. each bank is 256mb in size and can be programmed individually to support: 8-, 16- or 32-bit wide, l ittle- e ndian and big-endian m emory format variable wait states (up to 16 waits) exchangeable active low/high chip select signal ( only for cs6 and cs7) various type control signal timing bus transfers can be extended using the exprdy input signal. exprdy signal can be used by exchangeablely active high or low in according to control register setting. figure 1. static memory controller block diagram main state machine bank config . reg . asb interface & chip select encode ebi signal control mux static memory controller asb bus chip pad aout [23:0] datain [31:0] dataout [31:0] bd[31:0] nouten [3:0] nwen [3:0] nsramoe ncs [5:0] cs[7:6] nwef [3:0] bclk bnres dselsmi dselreg btran[1:0] blast berror bwait bwrite bsize[1:0] bd[31:0] ba[26:24, 4:0] mux mux lat lat lat nsramalatch nsrama [1:0] nsramamux nsramouten [3:0] nsramoutlen nsraminlen[3:0] nsraminen membyte[1:0] exprdy expclk mode[1:0] rnw
39 GDC21D601 2. signal description the static memory controller module is connected to the asb bus. in t able 1. static memory controller asb signal descriptions show the internal bus interface signals (amba signals) to the static memory controller table 1. static memory controller asb signal descriptions name type description ba[26:24, 4:0] i system address bus. the sram controller only requires seven bits of this bus to do the necessary encoding/decoding. bclk i the asb clock. bd[31:0] i/o bi - directional system data bus. the data bus is driven by this block during read transfers from configuration registers only. berror o low during phase one of bclk when the static memory controller is selected. blast o low during phase one of bclk when the static memory controller is selected. bwait o this slave response is driven during phase one of bclk when the static memory controller is selected and is used to indicate if the memory has completed its current transfer. bnres i t he reset status of the asb. bsize[1:0] i t he size of the transfer data which may be byte, half - word , or word. btran[1:0] i these signals are used to determine sequential and non-sequential accesses . bwrite i when this signal is high, it indicates a write transfer and when low a read. dselsram i when this signal is high, it indicates that the static memory controller is selected. dselreg i when high, this signal indicates that one of the bank configuration registers is selected.
40 GDC21D601 table 2. static memory controller external signal descriptions name type description exprdy i expansion channel ready. this signal is active low by default , when this signal is low, it will force the current memory transfer to be extended. when the rdon bit field in configuration register is set, then the polarity of the exprdy signal is reversed to active high. expclk o expansion clock output. clock output at the same phase and speed as the bus clock. active only during sram/rom cycles. nwen[3:0] o these signals are active low write enables for each of the memory byte lanes on the external bus. for example nwen[0] controls the writes to d[7:0]. nwef[3:0] i these optional connections use pads feedback from the external side of the nwen[3:0] pads. they are used to guarantee address and chip select hold time when any write enable is low. if not used , they should be tied to high. nsramoe o this is the active low output enable for devices on the external bus. this is low during reads from external memory and during the time that the selected bank should drive the external data bus. ncs[ 5 :0] o active low c hip s elect cs[7:6] o active high chip select srama [1:0] o these signals form the lower two bits of the external address bus. they are used to control accesses to 16- or 8-bit memories when the amba bus request s an access size larger than the memory (this is handled using multiple external transfers). nsramalatch o this signal is an active low transparent address latch enable. it is normally high to prevent power wasting transitions on the external address bus. membyteseq[1:0] o these signals control the data path muxes which allow 16- or 8-bit memories to read and write 32-bit values on the amba bus. nsramoutlen o active low transparent latch enable for the data out path (writes). nsramouten[1:0] o active low byte lane data output driver enable. nsraminlen[1:0] o active low transparent latch enable for the data in path (reads). nsraminen o active low data input driver enable (to amba bus). mode[1:0] i booting mode c onfiguration input. if these signals are ? 00 ? during bnres low then the sram controller will select bank zero (ncs[0]) as 32 -bit memory. if these signals are ? 10 ? then select bank zero as 16-bit memory. if these signals are ? 01 ? then bank zero as 8-bit memory.
41 GDC21D601 accesses to the static memory controller module can be two basic types; control register accesses and memory area accesses. the following timing diagrams relate to the external pin timings for sram/rom read and write cycles in minimum wait states. bclk btran[1:0] ba[23:0] dselsram bwait bd[31:0] expclk ncs [5:0] nsramoe a[23:0] d[31:0] n_tran s_tran s_tran s_tran s_tran address n address n+4 address n+8 address n address n+4 address n+8 exprdy deocde wait read read read figure 2. rom read timing
42 GDC21D601 bclk btran[1:0] ba[23:0] dselsram bwait bd[31:0] expclk ncs [5:0] xa[23:0] xd[31:0] exprdy n_tran s_tran s_tran s_tran address n address n+4 address n address n+4 deocde wait nwen [3:0] write data write data write write write figure 3. sram write timing
43 GDC21D601 3. functional description the static memory controller has following functions: memory bank select off-chip expansion clock driver wait states generation byte lane write control burst read access various type control signal generation these are described below. 3.1 memory bank select the chip select signal generation is controlled by ba[26:24]. from table 3 s tatic memory bank select coding is show n that these signals cod ed to cs[7:6] and ncs[5:0]. table 3. static memory bank select coding (mode r) dsel ba[26:24] cs[7:6] ncs[5:0] memory configuration 1 000 00 111110 ncs0 configuration 1 001 00 1111 01 ncs0 configuration 1 010 00 111011 ncs2 configuration 1 011 00 110111 ncs3 configuration 1 100 00 101111 ncs4 configuration 1 101 00 011111 ncs5 configuration 1 110 01 111111 cs6 configuration 1 111 10 111111 cs7 configuration 3.2 off-chip expansion clock driver in the static memory controller, the system clock input bclk is passed directly to expclk during memory cycles if the expansion clock enable bit of the corresponding memory bank configuration is set. 3.3 access sequencing bank configuration also determines the width of the external memory devices. when the external memory bus is narrower than the transfer initiated from the current master, the internal transfer will take several external bus transfers to complete. for example, in case that bank zero is configured as 8-bit wide memory and a 32-bit read is initiated, the asb bus will stall while the sram controller reads four consecutive bytes from the memory. during these accesses the data path is controlled (using the membyteseq[1:0] signals) to de-multiplex the se four bytes into one 32-bit word on the asb bus.
44 GDC21D601 3.4 wait state generation the static memory controller supports wait states for read and write accesses. this is configurable between one and 16 wait states for standard memory access and zero and 15 wait states for burst mode reads from roms. note wait state control refers to external transfer wait states. the number of cycles wh ere an amba transfer com p letes is controlled by two other factors; access width and external memory width. the static memory controller also allows transfers to be extended indefinitely , by asserting exprdy to low. to hold the current transfer exprdy must be asserted on the falling edge of bclk before the last cycle of the access. the transfer cannot be complete d until exprdy is high for at least one cycle. 3.5 burst read control this supports sequential access burst reads of up to four consecutive locations in 8-, 16- or 32-bit memories. this feature supports burst mode rom devices and increases the bandwidth by using a reduced (configurable) access time for three sequential reads following a quad-location boundary read. (note that q uad-location boundaries occur when a[1:0]=00 for byte wide memories.) 3.6 byte lane write control this controls nwen[1:0] according to amba transfer width (indicated by bsize[1:0]), external memory width, ba[1:0] , and the access sequencing. the following table shows the basic coding assuming 32-bit external memory: table 4 . nwen coding bsize[1:0] ba[1:0] nwen[3:0] 10 (word) xx 0000 01 (half - word) 1x 0011 01 (half - word) 0x 1100 00 (byte) 11 0111 00 (byte) 10 1011 00 (byte) 01 1101 00 (byte) 00 1110
45 GDC21D601 4. programmer ? s model 4.1 memory map the base address for the static memory controller registers is 0xffffec00 table 5 . static memory controller memory map address description initial value sramregbase + 00000 memory configuration register 1 (memcfg1) 32 ? h00000004 sramregbase + 00004 memory configuration register 2 (memcfg2) 32 ? h00000000 sramregbase + 00008 memory configuration register 3 (memcfg3) 32 ? h00000000 sramregbase + 0000c memory configuration register 4 (memcfg4) 32 ? h00000000 4.2 memory configuration registers 31 16 15 0 ncs[n+1] configuration register ncs[n] configuration register figure 4. memory configuration register memory configuration register (memcfg1 , 2, 3, 4 ) is a 32-bit read-write register which sets the configuration of the two expansion and rom selects. each select is configured with a two - byte field. 31 30 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 20 19 16 reserved rdon cscntl flashon clken mem width buren burst wait normal wait 15 14 13 12 11 10 9 8 7 6 4 3 0 reserved rdon cscntl flashon clken mem width buren burst wait normal wait figure 5 . two - byte fields in the memory configuration register for cs[ 5 :0] (note : gray areas are reserved for another feature.) 15 14 13 12 11 10 9 8 7 6 4 3 0 rsv . cson rdon cscntl flashon clken mem width buren burst wait normal wait figure 6 . two - byte fields in the memory configuration register for cs[6] 31 30 2 9 28 27 2 6 2 5 2 4 23 22 21 16 lcdon cson rdon cscntl flashon clken mem width reserved lcd wait figure 7 . two - byte fields in the memory configuration register for cs[7]
46 GDC21D601 lcdon lcd enable. when the bank 7 is connected to lcd panel for text display, setting this bit enables lcd wait to access directly lcd device. lcd wait bit is 6 bits therefore wait cycle is from 1 to 64. cson ncs enable. setting this bit is enables the cs6 and cs7 to be active low signal from active high signal that support s v arious devices. rd on select the polarity of exprdy . when this bit is set to 0, exprdy signal act as positive active signal. when this bit is set to 1, exprdy signal act as negative active signal. cscntl make the control signals (address, data, cs, rnw, etc . ) of external device to be similar motorolar type cpu. f lashon flash memory enable. when this bit is set to 1, memory control signals, ncs, nwen[1:0], and nsramoe, are adjusted to flash memory control sig n al timing. clken expansion clock enable. setting this bit enables the expclk to be active during accesses to the specified bank. this provides a timing reference for devices that need to extend bus cycles using the exprdy input. back to back sequential accesses result in a continuous clock. buren burst enable. setting this bit enables burst reads to take advantage of faster access time from rom devices that support burst mode. note banks using expclk and exprdy for off-chip peripheral control should not enable burst mode , and should be designed and set up to use a specific number of wait states in each access. the peripheral should time the access by counting expclk cycles (there is no explicit indication of access start or end) and determine the access direction and width by using nwen[3:0]. table 6 . values of the mem width field define the bus width field. table 6 . values of the mem width field mem width field expansion transfer mode 00 32-bit wide bus access 01 16-bit wide bus access 10 8-bit wide bus access 11 reserved
47 GDC21D601 table 7 . the v alues of the normal w ait field define the values of the normal access wait state field. and the values of the lcd wait define likely as table 7. table 7 . values of the normal access wait state field. value number of wait states 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 table 8 . values of the b urst w ait field define the values of the burst read wait state field. table 8 . values of the burst read wait state field value number of wait states 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
48 GDC21D601 section 7. mcu controller 1. general description designing the microcontroller unit (mcu), some control signals needed by any functional block, but not drive any other block, must be generated. so these control signals are generated in mcu controller. the mcu controller (mcuc) is composed of registers which are for selecting the function of multi-function pins, for defining the memory map structure, arbiter priority, mcu device code , and dram power d own r eq/ a ck signals. 2. signal description table 1 . signal descriptions name type description bclk i system bus clock. bnres i the reset status of the asb ba[31:0] i system address bus bd[31:0] i / o bi-directional system data bus. bwait o low during phase one of bclk blast o l ow during phase one of bclk berror o l ow during phase one of bclk bwrite i when this signal is high, it indicates a write transfer and when low a read. dsel i when this signal is high, it indicates that mcu controller is selected. pwrdwnack i this signal indicate s that dram is entered into self-refresh mode pwrdwnreq o t h e request of entering the self-refresh node of dram ari_pri o determine arbiter priority. see section.2 system architecture for detail isram o allocate on-chip sram address area at 0x00000000 drambank0 o allocate dram address area at 0x00000000 pinmux_sigs o these signals are for multi- function pin
49 GDC21D601 3 . register description 3.1 register memory map the base address of mcu control register is 0xffffeb00. table 2 . mcu controller memory map address r/w initial value description mcuregbase + 0x0000 r/w 0x00 mcu control register mcuregbase + 0x0004 r/w 0x00 pinmux_pa register, multi-function pin mux control signals for port a[5:0] mcuregbase + 0x0008 r/w 0x00 pinmux_pb register, multi-function pin mux control signals for port b[7:0] mcuregbase + 0x000c r/w 0x00 pinmux_pc register, multi-function pin mux control signals for port c[7:0] mcuregbase + 0x00010 r/w 0x00 pinmux_pd register, multi-function pin mux control signals for port d[7:0] mcuregbase + 0x00014 r/w 0x00 pinmux_pe register, multi-function pin mux control signals for port e[8:0] mcuregbase + 0x00018 r/w 0x00 pinmux_pf register, multi-function pin mux control signals for port f[8:0] mcuregbase +0x0001c r/w 0x00 pinmux_pg register, multi-function pin mux control signals for port g[7:0] mcuregbase + 0x00020 r/w 0x00 pinmux_ph register, multi-function pin mux control signals for port h[7:0] mcuregbase + 0x00024 r/w 0x00 pinmux_pi register, multi-function pin mux control signals for port i[7:0] mcuregbase + 0x00028 r/w 0x00 pinmux_pj register, multi-function pin mux control signals for port j[7:0] mcuregbase +0x0002c r $lg601 mcu device code register mcuregbase + 0x00030 r 0x0 dram power down ack mcuregbase + 0x00034 w 0x0 dram power down req 3.2 mcuc_con register 31 2 1 0 reserved ari_pri isram drambank0 drambank0 when this register is high, dram memory address bank #0 area is located at 0. isram when this register is high, on-chip sram address area is located at 0 ari_pri arbiter priority control signal. see also section 2 system architecture for detail s . figure 1. mcu controller register
50 GDC21D601 3.3 pinmux register table 3 . pinmux_ pa register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_pa [0 ] irq0 pa0 45 1 pinmux_ pa[1] irq1 pa1 47 2 pinmux_ pa[2] irq2 pa2 48 3 pinmux_ pa[3] irq3 pa3 49 4 pinmux_ pa[4] irq4 pa4 51 5 pinmux_ pa[5] irq5 pa5 52 table 4. pinmux_ pb register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p b[0 ] tcioa0 p b 0 55 1 pinmux_ pb[1] tciob0 p b 1 57 2 pinmux_ pb[2] tcioa1 p b 2 58 3 pinmux_ pb[3] tciob1 p b 3 59 4 pinmux_ pb[4] tcioa2 p b 4 61 5 pinmux_ pb[5] tciob2 p b 5 62 6 pinmux_ pb[6] tcioa3 pb6 63 7 pinmux_ pb[7] tciob3 pb7 65 table 5. pinmux_ pc register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p c[0 ] pc0 tcioa4 66 1 pinmux_ pc[1] pc1 tciob4 67 2 pinmux_ pc[2] pc2 tcioa5 69 3 pinmux_ pc[3] pc3 tciob5 70 4 pinmux_ pc[4] pc4 tclka 71 5 pinmux_ pc[5] pc5 tclkb 73 6 pinmux_ pc[6] pc6 tclkc 74 7 pinmux_ pc[7] pc7 tclkd 75
51 GDC21D601 table 6. pinmux_ pd register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p d[0 ] rxd0 p d 0 76 1 pinmux_ pd[1] txd0 p d 1 78 2 pinmux_ pd[2] rxd1 p d 2 79 3 pinmux_ pd[3] txd1 p d 3 80 4 pinmux_ pd[4] ncts p d 4 82 5 pinmux_ pd[5] ndsr p d 5 83 6 pinmux_ pd[6] ndcd pd6 84 7 pinmux_ pd[7] nri pd7 86 table 7. pinmux_ pe register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p e[0 ] ndtr p e 0 87 1 pinmux_ pe[1] nrts p e 1 88 2 pinmux_ pe[2] smdi p e 2 90 3 pinmux_ pe[3] smdo p e 3 91 4 pinmux_ pe[4] smclk p e 4 92 5 pinmux_ pe[5] sin0 p e 5 94 6 pinmux_ pe[6] sout0 pe6 95 7 pinmux_ pe[7] sclk0 pe7 96 table 8. pinmux_ pf register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p f[0 ] scs0 p f 0 98 1 pinmux_ pf[1] sin1 p f 1 99 2 pinmux_ pf[2] sout1 p f 2 100 3 pinmux_ pf[3] sclk1 p f 3 102 4 pinmux_ pf[4] scs1 p f 4 103 5 pinmux_ pf[5] bclkout p f 5 104 6 pinmux_ pf[6] nfiqout pf6 105 7 pinmux_ pf[7] nirqout pf7 106
52 GDC21D601 table 9. pinmux_ pg register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p g[0 ] extreq p g 0 124 1 pinmux_ pg[1] extack p g 1 127 2 pinmux_ pg[2] dreq0 p g 2 128 3 pinmux_ pg[3] dack0 p g 3 129 4 pinmux_ pg[4] dreq1 p g 4 131 5 pinmux_ pg[5] dack1 p g 5 132 6 pinmux_ pg[6] ras0 pg6 133 7 pinmux_ pg[7] ras1 pg7 135 table 10. pinmux_ ph register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p h[0 ] cas0 p h 0 136 1 pinmux_ ph[1] cas1 p h 1 137 2 pinmux_ ph[2] cas2 p h 2 138 3 pinmux_ ph[3] cas3 p h 3 139 4 pinmux_ ph[4] cs4 p h 4 161 5 pinmux_ ph[5] cs5 p h 5 162 6 pinmux_ ph[6] cs6 ph6 165 7 pinmux_ ph[7] cs7 ph7 166 table 11. pinmux_ pi register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p i[0 ] d16 p i 0 187 1 pinmux_ pi[1] d17 p i 1 186 2 pinmux_ pi[2] d18 p i 2 184 3 pinmux_ pi[3] d19 p i 3 183 4 pinmux_ pi[4] d20 p i 4 182 5 pinmux_ pi[5] d21 p i 5 180 6 pinmux_ pi[6] d22 pi6 179 7 pinmux_ pi[7] d23 pi7 178
53 GDC21D601 table 12. pinmux_ pj register pin function description bit no. signal name when 0 when 1 pin no. 0 pinmux_p j[0 ] d24 p j 0 177 1 pinmux_ pj[1] d25 p j 1 175 2 pinmux_ pj[2] d26 p j 2 174 3 pinmux_ pj[3] d27 p j 3 173 4 pinmux_ pj[4] d28 p j 4 171 5 pinmux_ pj[5] d29 p j 5 170 6 pinmux_ pj[6] d30 pj6 169 7 pinmux_ pj[7] d31 pj7 167 3.5 mcu device code register this register is read only. device code value is ? $lg601 ? binary value : 0000 0100 1100 0100 0111 0110 0000 0001 3.6 dram power down acknowledge register this register is 1 bit read only register. this register is set when dram is entered to power down mode. 3.7 dram power down request register this register is 1 bit read/write register. when this register bit is high, request to dram controller to enter into power down mode of the dram .
54 GDC21D601 section 8. power management unit 1. general description the pmu block provides: clock distribution of all over system reset, run and power down modes control figure 1. shows the pmu block diagram. reset debounce digital filter bclk freq. control reset control pclk freq. control pmu control pmu registers fclk, bclk distribution control pclk distribution control npor b_resetn_out p_resetn0_out p_resetn1_out resetn_ext wd_of_in man_reset_in npdm sclk_in pclk_in p_a[7:0] p_d[15:0] remap p_sel p_stb p_write int_req_in spclk fclk pclk_xxxx for peripherals fastbus bclk_xxx for peripherals wd_of_out bclk_xxx for asb block tfclk tbclk figure 1. pmu block diagram
55 GDC21D601 2. hardware interface and signal description the pmu block is connected to the apb bus. table 1. describes the apb signals and clock signals used and produced. table 1. pmu signal descriptions name type description npor i external reset input. int_req_in i i nterrupt request signal from the interrupt controller. wd_of_in i watch dog timer overflow signal. man_rst_in i s/w manual reset pin from watch dog timer. p_d[15:0] i /o this is the bi-directional peripheral data bus. this block drives the data bus during read cycle, when p_write is low. p_a[7:0] i this is the peripheral address bus, which uses individual peripheral for decoding register accesses to that peripheral. the addresses become valid before pstb goes to high and remain valid after pstb goes to low. p_write i this signal indicates a write to a peripheral when it is high and a read from a peripheral when low. it has the same timing as the peripheral address bus. p_stb i this strobe signal is used to time all accesses on the peripheral bus. the falling edge of pstb is coincident with the falling edge of bclk p_sel i when high, this signal indicates that module has been selected by the apb bridge. sclk_in i system clock input . this is the clock input from external clock circuit . pclk_in i uart clock. this is the clock input from external uart clock module. tfclk i when it is in tic test mode, this s the fclk clock input signal. when tstcr[1] is set to 1 (high) for entering tic test mode. tbclk i when it is in tic test mode, bclk clocks signal. first set the tstcr[1] to 1 for entering tic test mode. bclk_xxx o system bus clock is generated from sclk_in. all asb block and some apb blocks are operated by this clock. pclk_xxx o apb peripheral bus clocks. all apb blocks are operated by the clocks. fclk o fclk pin for arm720t. it is used in standard mode, when fastbus is low. fastbus o arm720t bus mode control signal . when it is low, it is in standard bus mode. when high, fast bus mode. npdm o indicates the pdm mode of pmu. when it is low, mcu entered in power down mode. when high, normal operation mode. remap o indicates that the reset memory map is in operation. wd_of_out o watch dog overflow output signal for external devices . b_resetn o reset signal for asb devices p_resetn0 o reset signal for apb devices p_resetn1 o same as p_resetn0, but in manual reset mode this is not asserted. resetn_out o reset signal for external devices.
56 GDC21D601 3. operation modes 3.1 introduction the reset protocol guarantees that the multi-master system starts up with at most one bus driver enabled on each shared signal on the bus, and also permits a protocol reset mechanism for time-out or ? watchdog ? reset support. to improve power management, support for a power-saving mode where bus clocks may be disabled (or dropped to lower clock) is included. the reset and power-down mechanism provides: stable power-up sequence hard initialization (power on reset) soft initialization (s/w manual restart) additionally a system bus, once operational, benefits from well-defined modes of operation: r un in the standard bus mode run in the fast bus mode power-down mode 3.2 reset and operation modes a set of four useful states or modes is defined as follows: reset when it is power-on, watchdog timer overflow, watchdog timer manual reset or s/w reset, the mcu is initialized rower on reset the most severe form of reset which ensures that no more than one tri-state driver is enabled on each bus and initializes all system states to ensure that the power supply can in fact rise to normal operating voltage. this state should be forced by any on-chip power- on-reset cell or external power-on signal and maintained until bus clock is safe and stable. the por is forced to be in an asynchronous start-up condition and must be recognized by all master and slave devices to disable output drives (and wait for a valid clock) manual rese t / software reset the manual reset, which may need to apply to allow all soft resetting of the bus for a number of clock cycles. in this reset states the pmu block initializes all the asb blocks, bus controller, dram controller, dma controller, arm cpu core, and arbiter, decode. however some apb blocks are all valid in warm reset. watchdog timer overflow and manual reset the watchdog timer can generate reset signal, when timer overflows or sets the register value. detailed information are in the watchdog timer manual, please refer to it. run - arm720t standard mode. the arm720t works using the fclk and bclk. the fclk is used for cpu operation clock, and the b_clk is used for internal bus access, i.e. amba bus. so cpu can operate very high frequency. this mode can control the clock of asb and apb devices, so user can disable the clocks of unused devices or peripherals. it is possible to control the bclk or pclk mask register.
57 GDC21D601 run -arm720t fast-bus extension mode. the arm720t works using only the bclk. the cpu operation clock and amba bus access clock are the same. this mode can control the clock of asb and apb devices, so user can disable the clock of devices or peripherals that are not using now. it is possible to control the bclk mask register or pclk mask register. pdn ? power-down mode when mcu system is in the pdn state, pmu block disables all of the blocks in the asb and apb, so the power consumption of system is dramatically low. although mcu is in the power down mode, user can set some blocks are working in the power down mode. it is possible control the bclk or pclk mask register for power-down. wake-up from the pdn mode. the wake-up is a temporal state for wake-up from power down state through the interruption. after wake-up state, next state becomes run state automatically. run (use fclk) run (use b_clk only) power down reset npor wd_of s/w control s/w control s/w control wake-up by interrupt s/w control man_reset s/w control man_reset wake-up by npor figure 2. reset and power management state machine.
58 GDC21D601 4. register description the pmu supplies the clock to all of the blocks in the mcu. 4.1 pmu control register this register controls the operation mode of pmu. when power on reset states, register value is initialized by run state (00). the address of register is pmu_base (=0xffff f000) + 0x00h. table 2. pmucr bit functions bit initial name function 7~0 0x0 pmucr 0x0 - clear pmu status register. 0x03 ? entering the pd(power down) mode the other values - none effect. 4.2 pmu status register this register holds the previous status and reset state of pmu. the address of register is pmu_base + 0x00h. table 3. pmusr bit functions bit initial name function 5, 4 00 pmust[5:4] previous reset status bits 00 - the power-on reset state (npor). 01 - s/w reset state using pmu. 10 - s/w manual reset state using wdt. 11 - wd overflow reset state using wdt. 3, 2 00 pmust[3:2] current status bits 00 - running (fast, slow) after npor. 01 - running (fast, slow) after wd_of. 10 - running (fast, slow) after man_reset 1, 0 00 pmust[1:0] previous status bits 00 - start (fast, slow) after npor. 01 - start (fast, slow) after wd_of. 10 - start (fast, slow) after man_reset 11 - start (fast, slow) after pd mode. 4.3 remap register the remap register controls re-mapping operation when the reset (por or man_rst) signal is asserted or s/w is reset by rstcr. the address is pmu_base + 0x10h. table 4. remap bit functions bit initial name function 0 0 remap 0 ? reset operation mode map 1 ? normal operation mode map
59 GDC21D601 4.4 bclk and fclk control register and bclk frequency control register this register controls bclk of asb and fclk of arm720t. user can save the power by reduce of the clock speed. at any moment, user can change the bclk speed but it may push the system into unstable stage, so user must change the clock speed only in bus idle; this means there is no interaction between the devices used by bclk and any other devices used by pclk. user can control the bus mode that are standard-bus mode and fast- bus mode. the bclk is only used in the fast-bus mode and arm720t uses the both clock fclk and bclk in the fast bus mode. the address is pmu_base + 0x04h. table 5. clkcr bit functions bit initial name function 2 - 0 000 bclkcr[2:0] control register for bclk selection 000 - bclk is divided sys_clk by 2 001 - bclk is divided sys_clk by 4 010 - bclk is divided sys_clk by 8 011 - bclk is divided sys_clk by 16 100 - bclk is divided sys_clk by 32 101 - bclk is divided sys_clk by 64 110 - bclk is divided sys_clk by 128 111 - bclk is sys_clk. table 6. clkcr bit functions bit initial name function 3 1 bclkcr[3] control register to use in fclk mode 1 ? fast-bus mode (not use the fclk) 0 ? standard-bus mode use the fclk that same the sys_clk 4.5 bclk mask register for the run & pd mode. this register is used for masking bclk of asb devices in the run and pd mode. when each control bits are written to ? 1 or 0 ? , each clock of devices is controlled by enabled or disabled clock in the run and pd mode. the address of the mask control register are as follows.; bclkmsk_run is pmu_base + 0x08h, bclkmsk_pd is pmu_base + 0x0ch. when this is 1, it is enable clock. when 0, disable clock. table 7. bclkmsk bit functions for run mode bit initial name function 15-13 1 bclkmsk_run reserved bit 12 1 apb bridge clock mask bit 11 1 bus controller clock mask bit 10 1 dram controller clock mask bit 9 1 dma controller clock mask bit 8 1 test controller clock mask bit 7 1 sram clock mask bit 6 - 1 111111 reserved bit 0 1 b_clk out mask bit
60 GDC21D601 table 8. bclkmsk bit functions for pd mode bit initial name function 15 0 bclkmsk_pd arm7tdmi core clock mask bit 14 0 amba arbiter clock mask bit 13 0 amba decoder clock mask bit 12 0 apb bridge clock mask bit 11 0 bus controller clock mask bit 10 0 dram controller clock mask bit 9 0 dma controller clock mask bit 8 0 test controller clock mask bit 7 0 sram clock mask bit 6 - 1 000000 reserved bit 0 0 b_clk out mask bit 4.6 pclk mask register these registers are used for masking pclk or bclk of apb devices in the run or pd mode. the default values are all the clocks of the apb devices enabled in the run mode, and the clocks of the apb devices disabled in the pd mode. wdt and timer are apb devices but they uses the bclk for their operation. the address of the mask control register in run mode is pmu_base + 0x18h, and that of the power-down mask control register is pmu_base + 0x1ch. when this is 1, it enables clock. when 0, disables clock. table 9. pclkmsk bit functions in the run mode bit initial name function 9 1 pclkmsk_run watch dog timer clock mask bit 8 1 i 2 c 2 clock mask bit 7 1 i 2 c 1 clock mask bit 6 1 i 2 c 0 clock mask bit 5 1 sspi 1 clock mask bit 4 1 sspi 0 clock mask bit 3 1 uart 2 / smart card i/f clock mask bit 2 1 uart 1 clock mask bit 1 1 uart 0 clock mask bit 0 1 timer clock mask bit table 10. pclkmsk bit functions in the pd mode bit initial name function 9 0 pclkmsk_pd watch dog timer clock mask bit 8 0 i 2 c 2 clock mask bit 7 0 i 2 c 1 clock mask bit 6 0 i 2 c 0 clock mask bit 5 0 sspi 1 clock mask bit 4 0 sspi 0 clock mask bit 3 0 uart 2 / smart card i/f clock mask bit 2 0 uart 1 clock mask bit 1 0 uart 0 clock mask bit 0 0 timer clock mask bit
61 GDC21D601 4.7 pclk frequency control register this register is used to selecting the frequency of pclk in the apb at run mode. default value is 0000. the address of access the register is pmu_base + 0x14h table 11. clkmode bit functions bit initial name function 2 - 0 000 pclkcr select the pclk source 000 ? pclk is external pclk source 001 ? pclk is the sclk divided by 2 010 ? pclk is the sclk divided by 4 011 ? pclk is the sclk divided by 8 100 ? pclk is the sclk divided by 16 101 ? pclk is the sclk divided by 32 110 ? pclk is the sclk divided by 64 111 ? pclk is the sclk divided by 128 4.8 reset control register this register is used for generating the s/w reset operation. the mcu is entered in reset state, when this register is set to high, it is cleared automatically at the end of manual reset procedure. the address is pmu_base + 0x30h. table 12. rstcr bit functions bit initial name function 0 0 rstcr manual reset control bits 0 - normal , 1 - manual reset 4.9 test control register tstcr controls the normal mode, pmu test mode or the tic test mode. the address is pmu_base + 0x40h. table 13. tstcr bit functions bit initial name function 1 0 tstcr 0 ? normal operation mode 1 ? tic test mode 0 0 0 ? normal operation mode 1 ? pmu test mode
62 GDC21D601 4.10 test register this register is used to store some controls and data values for test mode. the tstr0 is readable/writable register and the tstr1 is a read only register. the address of tstr0 is pmu_base + 0x48h and that of tstr1 is pmu_base + 0x4ch. table 14. tstr0 bit functions bit initial name function 2 0 tstr0 test bit for int_req_in input 1 0 test bit for wd_of_in input 0 0 test bit for man_reset_in input table 15. tstr1 bit functions bit initial name function 15 0 tstr1 test bit for bclk_wdt 14 0 test bit for pclk_i 2 c2 13 0 test bit for pclk_i 2 c1 12 0 test bit for pclk_i 2 c0 11 0 test bit for pclk_sspi 1 10 0 test bit for pclk_sspi 0 9 0 test bit for pclk_uart 2, smart card 8 0 test bit for pclk_uart 1 7 0 test bit for pclk_uart 0 6 0 test bit for bclk_timer 5 0 test bit for b_resetn 4 0 test bit for p_resetn0 3 0 test bit for p_resetn1 2 0 test bit for p_resetn 1 0 test bit for wd_of_out 0 0 test bit for remap
63 GDC21D601 5. power management unit register map the base address of the pmu(power management unit) is 0xffff f000 . may be different for any particular system implementation. however, the offset address of registers is fixed. table 16. register map of the pmu address name description pmu base + 0x00 pmucr / pmusr in write operation, pmu operation mode controls register. in read operation, pmu status register shows the just previous pmu state. pmu base + 0x04 bclkcr bclk frequency selection and bus mode control(standard / fast bus mode) pmu base + 0x08 bclkmsk_run bclk masking controls register in the run mode. pmu base + 0x0c bclkmsk_pd bclk masking controls register in the pd mode. pmu base + 0x10 remap remap register pmu base + 0x14 pclkcr pclk control register pmu base + 0x18 pclkmsk_run pclk masking controls register for the run mode. pmu base + 0x1c pclkmsk_pd pclk masking controls register for the pd mode. pmu base + 0x20 reserved reserved. pmu base + 0x30 rstcr reset control register pmu base + 0x40 tstcr tic test mode and pmu test control register pmu base + 0x44 - reserved pmu base + 0x48 tstr0 test write register for external input signals pmu base + 0x4c tstr1 test read register for clocks of asb devices and reset signals
64 GDC21D601 6. test mode guide for mcu 6.1 tic test mode step 1. set-up tic test environment, connect the tclk to tbclk (=xpa[6]) pin and fclk of fclkgen to tfclk (=xpa[7]) pin. until the mode of the pmu is changed to the tic test mode, sys_clk has to feed same tclk to the clock. step 2. reset the mcu using pin npor low. step 3. then tic becomes the bus master step 4. change the mode of pmu by setting the tstcr to ? 10 ? and set tstcr[1] to hig h. step 5. start tic test using tbclk and tfclk pins. figure 3. shows tic test environment of internal blocks. tic box treqa treqb tack tbus tclk fclkgen fclk tic ebi pmu sys_clk arm720t apb asb sclk_in pclk_in tbclk tfclk npor fclk bclk pclk bclk reset gen figure 3. internal blocks tic test environment
65 GDC21D601 6.2. tic test for pmu block step 1. set-up tic test environment, connect the tclk to tbclk and fclk of fclkgen to tfclk pin. until the mode of the pmu is changed to the tic test mode, sys_clk has to feed the clock. it is easier to test the sys_clk and the tbclk separately. step 2. reset the mcu using pin npor low. step 3. then tic be comes the bus master step 4. change the mode of pmu by setting the tstcr[1:0] to ? 11 ? . step 5. set value to tstr0 for test vector, and read output value in the tstr1 of the pmu and compare it with desired test vector. figure 4. shows pmu tic test environment tic box treqa treqb tack tbus tclk fclkgen fclk tic ebi pmu sys_clk arm720t apb asb sclk_in pclk_in tbclk tfclk npor fclk bclk pclk bclk reset gen testclk gen figure 4. tic test environment
66 GDC21D601 7. signal timing diagram the pmu signal timing is as shown below. 7.1 power on reset resetn_in b_resetn p_resetn0/1 resetn_out s_clk figure 5. power on reset timing diagram 7.2 watch dog timer overflow wd_of_in b_resetn p_resetn0/1 wd_of_out b_clk 512 b_clk 256 b_clk figure 6. watch dog timer overflow timing diagram 7.3 manual reset there are two manual reset cases. the first reset operation is switched by man_rst signal from wdt. another case is called s/w reset.
67 GDC21D601 b_resetn p_resetn0 man_rst b_clk 512 b_clk p_resetn1 high figure 7. manual reset (from wdt) timing diagram b_resetn p_resetn0 rstcr b_clk 512 b_clk p_resetn1 high figure 8. s/w reset timing diagram
68 GDC21D601 section 9. watchdog timer 1. general description the watchdog timer has: watchdog timer mode and interval timer mode interrupt signal int_wdt to interrupt controller in the watchdog timer mode & interval timer mode output signal poreset and mnreset to pmu(power management unit) eight counter clock sources selection whether to reset the chip internally or not two type s of reset signal : power-on reset and manual reset tcnt : timer counter (8bit) t r cr : timer /reset control register (8bit) rstsr : reset status register ( 2 bit) system clock module data bus rstsr clock generation clock selection internal data bus tcnt t rc r overflow reset control interrupt control control logic clock int _wdt porst mnrst bus interface figure 1 . watchdog timer module block diagram
69 GDC21D601 2. hardware interface and signal description the watchdog timer module is connected to the apb bus. table 1 . apb signal descriptions name type source/ destination description b_clk i clock controller system (bus) clock. this clock times all bus transfers. the clock has two distinct phases - phase 1 wh en b_clk is low, and phase 2 wh en b_clk is high. p_a[4:2] i apb bridge this is the peripheral address bus used by an individual peripheral for decoding register accesses to that peripheral. the addresses become valid before p_stb goes to high and remain valid after p_stb goes to low. p_d[7:0] i / o apb peripherals, b_d bus this is the bi-directional peripheral data bus. the data bus is driven by this block during read cycles (when p_write is low). p_stb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of p_stb is coincident with the falling edge of b_clk. p_write i apb bridge when this signal is high, it indicates a write to a peripheral. when low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before p_stb goes to high and remains valid after p_stb goes to low. p_sel i apb bridge when this signal is high, it indicates that this module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). see amba peripheral bus controller for more details. nb_res i power management unit reset signal generated from the apb bridge int_wdt o interrupt controller when this signal is high, it indicates that a system becomes uncontrolled , and the timer counter overflows without being rewritten correctly by the cpu or it overflows in the interval timer mode. mnrst o power management unit when this signal is high, this signal indicates that the manual reset signal has selected as the internal reset signal , and the timer counter overflows without being rewritten correctly by the cpu or it overflows in the interval timer mode.. porst o power management unit when this signal is high, this signal indicates that the power-on reset signal has selected as the internal reset signal. writes to the watchdog timer module are generated from the peripheral bus controller module. figure 2 . watchdog timer module apb write cycle summarizes this description .
70 GDC21D601 b_clk p_sel p_write p_stb p_d p_a register data address data figure 2 . watchdog timer module apb write cycle b_clk p_sel p_write p_stb p_d p_a register address data data figure 3 . watchdog timer module apb read cycle
71 GDC21D601 3 . watchdog timer introduction the GDC21D601 has a one-channel watchdog timer(wdt) for monitoring system operations. if a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the cpu, an reset signal is output to pmu. when this watchdog function is not needed, the wdt can be used as an interval timer. in the interval timer operation, an interval timer interrupt is generated at each counter overflow. the wdt has a clock generator which products eight counter clock sources. the clock signals are obtained by dividing the frequency of the system clock(b_clk). users can select one of eight internal clock sources for input to the tcnt by cks2 - cks0 in the trcr. table 2 . internal counter clock sources bit 2 - 0 (cks2-cks0) clock source (system clock = 40 mh z ) overflow interval 000 the system clock is divided by 2 12.8 us 001 the system clock is divided by 8 51.2 us 010 the system clock is divided by 32 204.8 us 011 the system clock is divided by 64 409.6 us 100 the system clock is divided by 256 1.64 ms 101 the system clock is divided by 512 3.28 ms 110 the system clock is divided by 2048 13.11 ms 111 the system clock is divided by 8192 52.43 ms
72 GDC21D601 4 . watchdog timer operation the watchdog timer mode to use the wdt as a watchdog timer, set the wt/nit and tmen bits of the trcr to 1. software must prevent tcnt overflow by rewriting the tcnt value(normally by writing 0x00) before overflow occurs. if the tcnt fails to be rewritten and overflow due to a system crash or the like , int_wdt signal and poreset/mnreset signal are output. the int_wdt signal is not output if inten is disabled (inten = 0). tcnt value time ox00 oxff 0x00 written in tcnt wtovf = 1 fault and internal reset generated tmen = 1 wt/nit = 1 figure 4 . operation in the watchdog timer mode if the rsten bit in the trcr is set to 1, a signal to reset the chip will be generated internally when tcnt overflows. either a power-on reset or a manual reset can be selected by the rstsel bit.
73 GDC21D601 the interval timer mode to use the wdt as an interval timer, clear wt/nit to 0 and set tmen to 1. a watchdog timer interrupt (int_wdt) is generated each time the timer counter overflows. this function can be used to generate interval timer interrupts at regular intervals. tcnt value time ox00 oxff itovf = 1 wdtint generated tmen = 1 wt/nit = 0 figure 5. operation in the interval timer mode 4.1 timing of setting and clearing the overflow flag timing of setting the overflow flag in the interval timer mode when the tcnt overflows , the itovf flag is set to 1 and an watchdog timer interrupt (int_wdt) is requested. in the watchdog timer mode when the tcnt overflows , the wtovf bit of the sr is set to 1 and a wdtout signal is output. when rsten bit is set to 1, tcnt overflow enables an internal reset signal to be generated for the entire chip. timing of clearing the overflow flag when the reset status register ( rst sr) is read, the overflow flag is cleared.
74 GDC21D601 5 . watchdog timer memory map the wdt has five registers. they are used to select the internal clock source, switch to the wdt mode , control the reset signal , and test it . the base address of the watchdog timer is fixed to 0xffff f100 and the offset of any particular register from the base address is fixed. table 3 . memory map of the watchdog timer apb peripheral address read location write location wdtbase + 0x00 timer/reset control timer/reset control wdtbase + 0x04 reset status wdtbase + 0x08 timer counter timer counter wdtbase + 0x10 test input wdtbase + 0x14 test output
75 GDC21D601 6 . watchdog timer register descriptions the following registers are provided for watchdog timer: timer counter (tcnt) 8- bit readable and writable upcounter. when the timer is enable d , the timer counter starts counting pulse of the selected clock source. when the value of the tcnt changes from 0xff-0x00(overflows), a watchdog timer overflow signal is generated in the both timer mode s . the tcnt is initialized to 0x00 by a power-reset(nb_res). timer/reset control register (trcr) 8 -bit readable and writable register. the following functions are provided : selecting the timer mode selecting the internal clock source selecting the reset mode setting the timer enable bit being enable interrupt request being enable reset signal occurrence the clock signals are obtained by dividing the frequency of the system clock. table 4 . trcr bit description bit initial value function 0 (clock select : cks0) 0 000 = /2 select one of eight internal clock sources for input to the tcnt. 1 (clock select : cks1) 0 001 = /8 2 (clock select : cks2) 0 010 = /32 011 = /64 100 = / 256 101 = /512 110 = /2048 111 = /8192 3 (reset select : rstsel) 0 0 = poser-on reset 1 = manual reset select the type of generated internal reset if the tcnt overflows in the watchdog timer mode. 4 (reset enable : rsten) 0 0 = disable 1 = enable select whether to reset the chip internally or not if the tcnt overflows in the watchdog timer mode. 5 (timer enable : tmen) 0 0 = disable 1 = enable enable or disable the timer 6 (timer mode select : wt/nit) 0 0 = interval timer mode 1 = watchdog timer mode select whether to use the wdt as a watchdog timer or interval timer 7 (interrupt enable : inten) 0 0 = disable 1 = enable enable or disable the interrupt request
76 GDC21D601 reset status register ( rst sr) two-bit read only register. the rst sr indicates whether tcnt is overflowed or not. the rst sr is initialized to 0x0 by the reset signal, nb_res. bit 0 (wtovf) indicates that the tcnt has overflowed in the watchdog timer mode. bit 1 (itovf) indicates that the tcnt has overflowed in the interval timer mode. table 5 . sr bit description bit initial value function 0 (watchdog timer overflow flag : wtovf) 0 indicate that the tcnt has overflowed in the watchdog timer mode. 1 (interval timer overflow flag : itovf) 0 indicate that the tcnt has overflowed in the interval timer mode
77 GDC21D601 7 . examples of register setting 7.1 interval timer mode tcnt = 0x00 trcr = 0xa0 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d tcsr tcnt rstcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 b8 10 12 13 14 00111000 10111000 00111000 00 11 figure 6 . interrupt clear in the interval timer mode
78 GDC21D601 7.2 watchdog timer mode with internal reset disable tcnt = 0x00 (normally) trcr = 0xe0 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d rstcsr tcnt tcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 78 10 12 13 14 00011111 10011111 00011111 00 11 ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- 01111000 01111000 figure 7 . interrupt clear in the watchdog timer mode with reset disable
79 GDC21D601 7.3 watchdog timer mode with power-on reset tcnt = 0x00 trcr = 0xf0 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d rstcsr tcnt tcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 78 10 12 00 01011111 11011111 00011111 00 11 ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- 01111000 00011000 11011111 01111000 figure 8 . interrupt clear in the watchdog timer mode with power-on reset
80 GDC21D601 7.4 watchdog timer mode with manual reset tcnt = 0x00 trcr = 0xf8 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d rstcsr tcnt tcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 10 12 13 14 01111111 11111111 01111111 11 ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- ?- 01111000 01111000 figure 9 . interrupt clear in the watchdog timer mode with manual reset
81 GDC21D601 section 10. interrupt controller 1. general description the interrupt controller has the following features : asynch r onous interrupt controller six external interrupt s n ineteen internal interrupt s low interrupt latency selection of the active mode s of all interrupt source inputs (level or edge trigger) maskable for each interrupt source and output signal selection of the output path s (irq or fiq for each interrupt source) mask register trigger mode register trigger polarity register direction register fiq status register irq status register fiq mask register irq mask register bus interface 0 1 2 3 4 5 6 7 status clear register 8 control block irq [25:0] nirq nfiq internal data bus figure 1 . interrupt controller module block diagram
82 GDC21D601 2 . hardware interface and signal description the interrupt controller module is connected to the apb bus. table 1 . apb signal descriptions name type source/ destination description p_a[5:2] i apb bridge this is the peripheral address bus, which is used by an individual peripheral for decoding register accesses to that peripheral. the addresses become valid before p_stb goes to high and remain valid after p_stb goes to low. p_d[26:0] i / o apb peripherals, b_d bus this is the bidirectional peripheral data bus. the data bus is driven by this block during read cycles (when p_write is low). p_stb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of p_stb is coincident with the falling edge of b_clk. p_write i apb bridge when this signal is high, it indicates a write to a peripheral. when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before p_stb goes to high and remains valid after p_stb goes to low. p_sel i apb bridge when this signal is high, it indicates that this module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). see amba peripheral bus controller (arm ddi - 0044) for more details. intesource[25:0] i apb peripherals/ external world fiq/irq interrupt signals into the interrupt module. these active high signals indicate that interrupt requests have been generated (irqesource[ 25 ] is internally generated in the interrupt controller module and used to provide a software triggered irq). nfiq o arm core nfiq interrupt input to the arm core. nirq o arm core nirq interrupt input to the arm core. bnres i pmu reset signal generated from the power management unit.
83 GDC21D601 writes to the interrupt controller module are generated from the peripheral bus controller module. figure 2 . interrupt control module apb write cycle summarizes this. b_clk p_sel p_write p_stb p_d p_a register data address data figure 2 . interrupt control module apb write cycle
84 GDC21D601 3 . interrupt controller 3.1 introduction the interrupt controller provides a interface between multiple interrupt source and the processor. the interrupt controller supports internal and external interrupt sources. internally there are 19 peripheral interrupt sources. externally there are 6 interrupt sources. therefore certain interrupt bits can be defined for the basic functionality required in any system, while the remaining bits are available for use by other devices in any particular implementation. table 2 . interrupt controller default setting value int # interrupt source int 0 external int0 int 1 external int1 int 2 external int2 int 3 external int3 int 4 external int4 int 5 external int5 int 6 com tx int 7 com rx int 8 dma int 9 rtc int 10 wdt int 11 i 2 c0 int 12 i 2 c1 int 13 i 2 c2 int 14 uart0 int 15 uart1 int 16 smart card interface int 17 ssi cha int 18 ssi chb int 19 timer cha int 20 timer chb int 21 timer chc int 22 timer chd int 23 timer che int 24 timer chf int 25 software interrupt the users can set the active mode of all interrupt source inputs. the default mode is the falling-edge trigger mode. any inversion or latching required to provide edge sensitivity must be provided at the generating source of the interrupt. no hardware priority scheme or any form of interrupt vectoring is provided, but the priority can be determined using fiq mask register and irq mask register under software control. fiq mask register and irq mask register are also provided to generate an interrupt under software control. typically these registers may be used to determine either a fiq interrupt or an irq interrupt.
85 GDC21D601 3.2 interrupt control the interrupt controller provides interrupt source status and interrupt request status. the interrupt mask register s are used to determine whether an active interrupt source should generate an interrupt request to the processor or not. a logic high in the interrupt mask register indicates that the interrupt source is masked and then doesn ? t generate a request. fiq mask register and irq mask register indicate whether the interrupt source caus es a processor interrupt or not. the interrupt mode is configured by interrupt trigger mode register and interrupt trigger polarity register. and interrupt direction register indicates whet h er each interrupt source drive s irq or fiq. the fiq and irq status register is used to reflect the status of all channels set to produce an fiq interrupt or irq interrupt. and the status registers are cleared by writing ? 1 ? to the status clear register at the edge trigger mode only. mask control irq source0 irq source25 irq source1 irq source2 irq source3 irq source4 irq source5 : : : : : : irq source20 irq source21 irq source22 irq source23 irq source24 edge/ level control high/ low, rising/ falling control fiq or irq irq fiq irq mask fiq mask nfiq nirq source mask control trigger mode control polarity control direction control status control request control clear control 26 26 26 26 26 26 figure 3 . interrupt control flow diagram tic registers are used only for the production test. tic input register is used to drive interrupt request sources by the cpu. when this register bit 26 is set, other bits of tic input register are regarded as interrupt sources. this bit is cleared by system reset and should be cleared in normal operation. bit 25 is used as a software interrupt source. when source mask control register bit 25 is high, an interrupt request occurs. to disable the software interrupt, source mask control register bit 25 should be low. software interrupt source input is fixed active high and level sensitive.
86 GDC21D601 4 . interrupt controller memory map the base address of the interrupt controller is 0xffff f200 . t he offset of any particular register from the base address is fixed. table 3 . memory map of the interrupt controller apb peripheral address read location write location intbase + 0x000 mask register mask register intbase + 0x004 trigger mode register trigger mode register intbase + 0x008 trigger polarity register trigger polarity register intbase + 0x00c direction register direction register intbase + 0x010 fiq status register (read-only) intbase + 0x014 irq status register (read-only) intbase + 0x018 fiq mask register fiq mask register intbase + 0x01c irq mask register irq mask register intbase + 0x020 status clear register (write-only) intbase + 0x024 ticinput register intbase + 0x028 ticoutputregister
87 GDC21D601 5 . interrupt controller register descriptions the following registers are provided for both fiq and irq interrupt controllers: (1) mask register readable and writable. the interrupt mask register is used to mask the interrupt input sources and defines which active sources will generate an interrupt request to the processor. if certain bits within the interrupt controller are not implemented, the corresponding bits in the interrupt ma s k register must be masked. a bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. a bit value 1 indicates that the interrupt is masked. once a bit is masked, the corresponding bit in the status register is cleared. on reset, all interrupt input sources are masked. ? 1 ? : mask ? 0 ? : unmask initial value : 0x 3 ffffff 2 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) trigger mode register readable and writable. the interrupt trigger mode register is used to configure the interrupts with the interrupt trigger polarity register. each interrupt can be configured to level or edge triggered. a bit value 0 indicates that the interrupt is configured to edge triggered and a bit value 1 indicates that the interrupt is configured to level triggered. on reset, all interrupt input sources are configured to edge triggered. ? 1 ? : level trigger mode ? 0 ? : edge trigger mode initial value : 0x 2000000 2 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
88 GDC21D601 (3) trigger polarity register readable and writable. the interrupt trigger polarity register is used to configure the interrupts with the interrupt trigger mode register. each interrupt can be configured to rising/high or falling/low active. a bit value 0 indicates that the interrupt is configured to falling active for edge trigger mode and to low active for level trigger mode. a bit value 1 indicates that the interrupt is configured to rising active for edge trigger mode and to high active for level trigger mode. on reset, all interrupt input sources are configured to falling/low active. ? 1 ? : rising or high ? 0 ? : falling or low initial value : 0x 2000000 2 5 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4 . interrupt source trigger mode of the interrupt controller trigger mode register trigger polarity register description 0 0 falling-edge (default) 0 1 rising-edge 1 0 low-level 1 1 high-level (4) direction register readable and writable. the interrupt direction register is used to determine whether each interrupt source drive s irq or fiq. a bit value 0 indicates that the interrupt is driven to irq and a bit value 1 indicates that the interrupt is driven to fiq. on reset, all interrupt input sources drive irq. ? 1 ? : request fiq ? 0 ? : request irq initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
89 GDC21D601 (5) fiq status register read-only. the fiq status register is used to reflect the status of all channels set to produce an fiq interrupt (idr(i) = 1). when an interrupt is set for an fiq occu r r ing , the corresponding bit is set in fiq status register. the interrupt handler will examine this register to determine the channel(s) that caused the fiq interrupt. when the status clear register is written to ? 1 ? , the corresponding bit is cleared if that channel is configured to edge trigger mode. a high bit indicates that the interrupt is active and will generate an interrupt to the processor. ? 1 ? : interrupt event occur ? 0 ? : no interrupt event initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (6) irq status register read-only. the irq status register is used to reflect the status of all channels set to produce an irq interrupt (idr(i) = 0). when an interrupt is set for an irq occur ring , the corresponding bit is set in irq status register. the interrupt handler will examine this register to determine the channel(s) that caused the irq interrupt. when the status clear register is written to ? 1 ? , the corresponding bit is cleared if that channel is configured to edge trigger mode. a high bit indicates that the interrupt is active and will generate an interrupt to the processor. ? 1 ? : interrupt event occur ? 0 ? : no interrupt event initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) fiq mask register readable and writable. the fiq request mask register is used to mask the request to generate an interrupt to a processor. if certain bits within the interrupt controller are not implemented, the corresponding bits in the fiq requ es t mask register must be masked. a bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. a bit value 1 indicates that the interrupt is masked. on reset, all fiq requests are unmasked. ? 1 ? : request mask ? 0 ? : request unmask initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
90 GDC21D601 (8) irq mask register readable and writable. the irq request mask register is used to mask the request to generate an interrupt to a processor. if certain bits within the interrupt controller are not implemented, the corresponding bits in the irq requ e st mask register must be masked. a bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. a bit value 1 indicates that the interrupt is masked. on reset, all irq requests are unmasked. ? 1 ? : request mask ? 0 ? : request unmask initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (9) status clear register write-only. the status clear register is used to clear bits in the status register configured to the edge trigger mode. if the channels are configured to the level trigger mode, the corresponding bits in the fiq status register and the irq status register ha ve no effect. this register is cleared when the signal, p_stb, is low after this register is written to ? 1 ? . when writing to this register, each data bit that is high causes the corresponding bit in the status register to be cleared. data bits that are low have no effect on the corresponding bit in the status register. note that the status clear register ha s an effect on the status register in the edge trigger mode. ? 1 ? : clear the status register ? 0 ? : not clear initial value : 0x0000000 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
91 GDC21D601 section 11. real time clock 1 . general description this module is a 32-bit counter clocked by a 32.768khz clock. this clock needs to be provided by the system, s ince there is no oscillator inside the block. the clock is divided in the rtc core to provide a 1hz clock used to drive a 32-bit counter which forms the real time clock (rtc). it also contains a 32-bit match register which can be programmed to generate an interrupt signal when the time in the rtc matches the specific value written to this register (alarm function - rtc event). the rtc has one event output which is synchronized with pclk. rtc irq is to be connected to the system interrupt controller. apb interface rtc core (counter + registers) bnres pclk pselrtc pstb pwrite pa[4:2] pd[31:0] from/to apb clk32k from xtal oscillator rtcirq synchronized event output to interrupt controller figure 1 . real time clock connections diagram
92 GDC21D601 2 . signal description the rtc module is connected to the apb bus. table 1 . apb signal descriptions describes the apb signals used and produced. table 1 . apb signal descriptions name type source/ destination description pclk i power management unit the slow apb clock used to re-synchronize data is transfer red between the 32.768khz clock and the apb. p_a[4:2] i apb bridge this is the peripheral address bus , which is used by an individual peripheral for decoding register accesses to th is peripheral. the addresses become valid before p_stb goes to high and remain valid after p_stb goes to low. p_d[31:0] i / o apb peripherals, b_d bus this is the bi-directional peripheral data bus. the data bus is driven by this block during read cycles (when p_write is low). p_stb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of p_stb is coincident with the falling edge of b_clk. p_write i apb bridge when this signal is high, it indicates a write to a peripheral. when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before p_stb goes to high and remains valid after p_stb goes to low. p_sel i apb bridge when this signal is high, it indicates that this module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). see amba peripheral bus controller for more details. bnres i power management unit reset signal generated from the pmu rtcirq o interrupt controller interrupt signal to the interrupt module. when this signal is high, it indicates a valid comparison between the counter value and the match register. it also indicates 1hz interval with enable bit in control register.
93 GDC21D601 3 . hardware interface the apb interface is fully apb-compliant. the apb is a non-pipelined low-power interface designed to provide a simple interface to slave peripherals. b_clk p_sel p_write p_stb p_d p_a register data address data figure 2 . rtc module apb write cycle b_clk p_sel p_write p_stb p_d p_a register address data data figure 3 . rtc module apb read cycle
94 GDC21D601 4 . functional description the counter is loaded by writing it to the rtc data register. the counter will count up on each rising edge of the clock and loops back with 0 when the maximum value (0xffffffff) is reached. at any moment the counter value can be obtained by reading the rtc data register. the value of the match register can also be read at any time, and the read does not affect the counter value. the status of the interrupt signal is available in the status register. the status bit is set if a comparator match event has occur r ed or 1 second has elapsed. reading from the status register will clear the status register. rtc apb registers match register sync control rtc counter 32-bit comparator ripple counter module core 1hz interface to apb data in data out pclk rtcirq clk32k a p b b u s figure 4 . rtc block diagram
95 GDC21D601 5 . real time clock memory map the base address of the rtc is fixed as 0xffff f300 and the offset of any particular register from the base address is fixed. table 2 . rtc memory map address read location write location rtc base + 0x00 rtc data register (rtcdr) rtc data register (rtcdr) rtc base + 0x04 rtc match register (rtcmr) rtc match register (rtcmr) rtc base + 0x08 rtc status (rtcs) rtc base + 0x0c rtc clock divider (rtcdv) rtc clock divider (rtcdv) rtc base + 0x10 rtc control register (rtccr) rtc control register (rtccr) rtc base + 0x14 rtc tic selection register (rtcts) rtc base + 0x18 ticclk32k rtc base + 0x1c ticclkpclk note the rtc clock divider register may only be written to when in test mode. 6 . real time clock register descriptions the following user registers are provided : rtc data register (rtcdr) read/write. writing to this 32-bit register will load the counter. a read will give the current value of the counter. rtc match register (rtcmr) read/write. writing to this 32-bit register will load the match register. this value can also be read back. rtc status register (rtcs) read-only. when performing a read from this location the interrupt flag will be cleared. if a match event occur s , bit[1] will be set. for a second event, bit[0] will be set. this register is affected by the control register. rtc clock divider (rtcdv) read/write. the r eads to the register will return only four bits of the clock divider output. bits [3:0] will return bits (14, 11, 7, 3) of the divider output. w rit ing zero to bit[0] clears this divider. rtc control register (rtccr) read/write. this register enables the interrupt. bit[1] enables the match event interrupt (default disable = 0). bit[0] enables second event interrupt (default disable = 0). rtc tic selection (rtcts) write-only. this register is for production test purposes. bit[0] enables ticclk32k for 32khz clock replacement. bit[1] enables ticclkpclk for pclk clock replacement. ticclk32k write-only. this generates 32khz clock for production test purposes. ticclkpclk write-only. this generates pclk clock for production test purposes.
96 GDC21D601 section 12. general purpose timer unit 1. general description the general-purpose timer unit has: six channels with 16bit counter 12 different pulse outputs and 12 different pulse inputs independent function with 12 general registers compare match waveform output function input capture function counter-clearing function at compare match or input capture mode synchronizing mode pwm mode 18 interrupt sources selectable 4 internal clock sources and 4 external clock sources internal data bus clock generation clock selection control ext_clk1- ext_clk4 pclk 16-bit timer channel1 16-bit timer channel0 16-bit timer channel2 16-bit timer channel3 module data bus 16-bit timer channel4 tint0 - tint5 t cio 0a - t cio 5a t cio 0b - t cio 5b bus interface tstartr tsynr tpwmr figure 1 . general -p urpose timer unit module block diagram
97 GDC21D601 2. hardware interface and signal description the general-purpose timer unit module is connected to the apb bus. table 1. apb signal descriptions name type source/ destination description pclk i pmu peripheral clock. this clock times all bus transfers. bnres i pmu reset signal generated from the pmu pa[7:2] i apb bridge this is the peripheral address bus, which is used by an individual peripheral for decoding register accesses to that peripheral. the addresses become valid before pstb goes to high and remain valid after pstb goes to low. pd[31:0] i / o apb peripherals, b_d bus this is the bi-directional peripheral data bus. this block drives the data bus during read cycles (when pwrite is low). pstb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of pstb is coincident with the falling edge of pclk. pwrite i apb bridge when this signal is high, it indicates a write to a peripheral. when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before pstb goes to high and remains valid after pstb goes to low. psel i apb bridge when this signal is high, it indicates that the apb bridge has selected this module. this selection is a decode result of the system address bus (asb). see amba peripheral bus controller for more details. ext_clk1 i external external clock1 input. this signal is selected independently from ext_clk2, ext_clk3, and ext_clk4. ext_clk2 i external external clock2 input. this signal is selected independently from ext_clk1, ext_clk3, and ext_clk4. ext_clk3 i external external clock3 input. this signal is selected independently from ext_clk1, ext_clk2, and ext_clk4 ext_clk4 i external external clock4 input. this signal is selected independently from ext_clk1, ext_clk2, and ext_clk3. t cio 0a i / o external this signal is used as gra0 input in input capture mode, gra0 output in output compare mode , and pwm output in pwm mode. t cio 0b i / o external this signal is used as grb0 input in input capture mode, grb0 output in output compare mode , and pwm output in pwm mode. t cio 1a i / o external this signal is used as gra1 input in input capture mode, gra1 output in output compare mode , and pwm output in pwm mode. t cio 1b i / o external this signal is used as grb1 input in input capture mode, grb1 output in output compare mode , and pwm output in pwm mode. t cio 2a i / o external this signal is used as gra2 input in input capture mode, gra2 output in output compare mode , and pwm output in pwm mode. t cio 2b i / o external this signal is used as grb2 input in input capture mode, grb2 output in output compare mode , and pwm output in pwm mode.
98 GDC21D601 name type source/ destination description t cio 3a i / o external this signal is used as gra3 input in input capture mode, gra3 output in output compare mode , and pwm output in pwm mode. tcio3b i / o external this signal is used as grb3 input in input capture mode, grb3 output in output compare mode , and pwm output in pwm mode. t cio 4a i / o external this signal is used as gra4 input in input capture mode, gra4 output in output compare mode , and pwm output in pwm mode. t cio 4b i / o external this signal is used as grb4 input in input capture mode, grb4 output in output compare mode , and pwm output in pwm mode. t cio 5a i / o external this signal is used as gra5 input in input capture mode, gra5 output in output compare mode , and pwm output in pwm mode. t cio 5b i / o external this signal is used as grb5 input in input capture mode, grb5 output in output compare mode , and pwm output in pwm mode. tint0 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel0. tint1 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel1. tint2 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel2. tint3 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel3. tint4 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel4. tint5 o interrupt controller interrupt signal to the interrupt controller module. this signal indicates that an interrupt has been generated in channel5.
99 GDC21D601 the w rites to the general-purpose timer unit module are generated from the peripheral bus controller module. figure 2 . general-purpose timer unit module apb write cycle summarizes this. pclk psel pwrite pstb pd pa register address data data figure 2 . general-purpose timer unit module apb read cycle b_clk p_sel p_write p_stb p_d p_a register data address data figure 3 . general-purpose timer unit module apb write cycle
100 GDC21D601 3 . general purpose timer unit introduction the GDC21D601 has a general-purpose timer unit (gptu) with six channels of 16-bit timer. there are two counter operation modes: a free running mode and a periodic mode. and each channel has independent operating modes. there are common functions for each channel: counter operation, input capture, compare match, pwm, and synchronized clear and write. it is possible to select one of eight counter clock sources for all channels. internal clock : counting at falling edge bclk / 2 bclk / 4 bclk / 16 bclk / 64 external clock: counting at rising , falling , or both edge that are user-selectable. there are four kinds of counter clear source s which can be selected by user ? s setting. n one : never clear until overflow for free running mode gra match or tpa input capture grb match or tpb input capture s ynchronous clear
101 GDC21D601 4 . general purpose timer unit operation the operation modes are described below. free running mode each channel can run from 0 to ffff repeatedly. when it reache s ffff, the interrupt signal is generated as user's setting. compare match mode each channel has 2 general registers and user can read or write from/to the registers. if user wrote some value s to general register, and the counter reached that value, the channel generates interrupt and external output by user's setting. the output value can be '1', '0' , or toggle value. the counter can be cleared by user's setting when the match with general register is detected. input capture mode when set to input capture mode and ris ing any event at tpa or tpb, the counter value is transferred to gra or grb respectively. the interrupt can be generated and the external event may be rising edge , falling edge or any edge by user's setting. the counter can be cleared by user's setting when the event at tpa or tpb is detected. synchronized clear & write mode when some channels are set to synchronization mode, and one of them is cleared by compare match or input capture, the other channels can be cleared simultaneously by user's setting. when some channels are set to synchronization mode and user would write any value to one of them, the other channels can be written with same value simultaneously by user's setting. pwm mode when a channel is set to pwm mode, the channel operat es like a compare match mode and the output on compare match event is generated only at tpa. the tpa value is '1' when it is the match with gra, and '0' when it is the match with grb.
102 GDC21D601 5 . general purpose timer unit memory map the base address of the general-purpose timer unit is 0xfffff 4 00 and the offset of any particular register from the base address is fixed. table 2 . general purpose timer unit register memory map address read location write location gptu base + 0x00 tstartr tstartr gptu base + 0x04 tsyncr tsyncr gptu base + 0x08 tpwmr tpwmr gptu base + 0x0c tstinr gptu base + 0x10 tstoutr gptu base + 0x14 tstmoder gptu base + 0x18 tstintr gptu base + 0x20 gptu base + 0x24 gptu base + 0x28 gptu base + 0x2c gptu base + 0x30 gptu base + 0x34 gptu base + 0x38 tcontr0 tiocr0 tier0 tstatusr0 tcount0 gra0 grb0 tcontr0 tiocr0 tier0 tcount0 gra0 grb0 gptu base + 0x40 gptu base + 0x44 gptu base + 0x48 gptu base + 0x4c gptu base + 0x50 gptu base + 0x54 gptu base + 0x58 tcontr1 tiocr1 tier1 tstatusr1 tcount1 gra1 grb1 tcontr1 tiocr1 tier1 tcount1 gra1 grb1 gptu base + 0x60 gptu base + 0x64 gptu base + 0x68 gptu base + 0x6c gptu base + 0x70 gptu base + 0x74 gptu base + 0x78 tcontr2 tiocr2 tier2 tstatusr2 tcount2 gra2 grb2 tcontr2 tiocr2 tier2 tcount2 gra2 grb2 gptu base + 0x80 gptu base + 0x84 gptu base + 0x88 gptu base + 0x8c gptu base + 0x90 gptu base + 0x94 gptu base + 0x98 tcontr3 tiocr3 tier3 tstatusr3 tcount3 gra3 grb3 tcontr3 tiocr3 tier3 tcount3 gra3 grb3 gptu base + 0xa0 gptu base + 0xa4 gptu base + 0xa8 gptu base + 0xac gptu base + 0xb0 gptu base + 0xb4 gptu base + 0xb8 tcontr4 tiocr4 tier4 tstatusr4 tcount4 gra4 grb4 tcontr4 tiocr4 tier4 tcount4 gra4 grb4
103 GDC21D601 address read location write location gptu base + 0xd0 gptu base + 0xd4 gptu base + 0xd8 gptu base + 0xdc gptu base + 0xe0 gptu base + 0xe4 gptu base + 0xe8 tcontr5 tiocr5 tier5 tstatusr5 tcount5 gra5 grb5 tcontr5 tiocr5 tier5 tcount5 gra5 grb5
104 GDC21D601 6 . general purpose timer unit register descriptions the following registers are provided for general purpose timer unit : timer start register (tstartr) eight-bit readable and writable register that starts and stops the counter of each channel . table 3 . tstartr bit description bit initial value function 7 (reserved) 1 6 (reserved) 1 5 (str5) 0 4 (str4) 0 1 = start counting start and stop counting 3 (str3) 0 0 = stop counting 2 (str2) 0 1 (str1) 0 0 (str0) 0 timer synch. register (tsyncr) eight-bit readable and writable register that select s timer synchronizing mode for each channel. table 4 . tsyncr bit description bit initial value function 7 (reserved) 1 6 (reserved) 1 5 (sync5) 0 4 (sync4) 0 0 = operate independently select the synchronizing mode 3 (sync3) 0 1 = operate synchronously with 2 (sync2) 0 other sync. channel 1 (sync1) 0 0 (sync0) 0
105 GDC21D601 timer pwm mode register (tpwmr) eight-bit readable and writable registers that select the pwm mode for each channel. table 5 . tpwmr bit description bit initial value function 7 (reserved) 1 6 (reserved) 1 5 (pwm5) 0 4 (pwm4) 0 0 = operate normally select the pwm mode 3 (pwm3) 0 1 = operate in pwm mode 2 (pwm2) 0 1 (pwm1) 0 0 (pwm0) 0 timer control register (tcontr) eight-bit readable and writable register for each channel that selects the timer counter clock source, the edges of the external clock source, and the counter clear source. table 6 . tcontr bit description bit initial value function 7 (reserved) 1 6 (cclr1) 5 (cclr0) 0 0 00 = not cleared - free running mode 01 = cleared by gra compare match or input capture - periodic mode 10 = cleared by grb compare match or input capture - periodic mode 11 = cleared in synchronization with other sync. timer select the counter clear source 4 (reserved) 1 3 (reserved) 1 2 (tpsc2) 1 (tpsc1) 0 (tpsc0) 0 0 0 000 = internal clock 1 (bclk/2) 001 = internal clock 2 (/4) 010 = internal clock 3 (/16) 011 = internal clock 4 (/64) 100 = external clock 1 (ext_clk1) 101 = external clock 2 (ext_clk2) 110 = external clock 3 (ext_clk3) 111 = external clock 4 (ext_clk4) select the counter clock source
106 GDC21D601 timer i/o control register (tiocr) eight-bit readable and writable register that selects the output compare or input capture function for gra and grb , and selects the function of the tp#a and tp#b pins. tiocr# controls the grs. table 7 . tiocr bit description bit initial value function 7 (reserved) 1 6 (iob2) 5 (iob1) 4 (iob0) 0 0 0 000 = compare match with pin output disabled 001 = 0 output at grb compare match 010 = 1 output at grb compare match 011 = toggle output at grb compare match 100 = grb captures the rising edge of input 101 = grb captures the falling edge of input 110 = grb captures both edge of input select the grb function 3 (reserved) 1 2 (ioa2) 1 (ioa1) 0 (ioa0) 0 0 0 000 = compare match with pin output disabled 001 = 0 output at gra compare match 010 = 1 output at gra compare match 011 = toggle output at gra compare match 100 = gra captures rising edge of input 101 = gra captures falling edge of input 110 = gra captures both edge of input select the gra function timer interrupt enable register (tier) eight-bit readable and writable register that controls the enabling/disabling of overflow interrupt request and the general register compare match/input capture interrupt requests. tier# controls the interrupt enable/disable. table 8 . tier bit description bit initial value function 7 (reserved) 1 6 (reserved) 1 5 (reserved) 1 4 (reserved) 1 3 (reserved) 1 2 (ovfie) 0 0 = disable interrupt requests by the ovfi 1 = enable interrupt requests from the ovfi 1 (mcibe) 0 0 = disable interrupt requests by the mcib 1 = enable interrupt requests from the mcib 0 (mciae) 0 0 = disable interrupt requests by the mcia 1 = enable interrupt requests from the mcia
107 GDC21D601 timer status register (tstatusr) eight-bit readable register contain s the flags that indicate tcount overflow/underflow and gra/grb compare match or input capture. this flags are interrupt source s . table 9 . tier bit description bit initial value function 7 (reserved) 1 6 (reserved) 1 5 (reserved) 1 4 (reserved) 1 3 (reserved) 1 2 (ovfi) 0 0 = clear condition 1 = setting condition indicate tcount overflow/underflow 1 (mcib) 0 indicate a grb compare match or input capture 0 (mcia) 0 indicate a gra compare match or input capture timer counter (tcount) 16-bit readable and writable counter. the clock source is selected by tcontr of each channel. tcount is cleared to 0x0000 by compare match with the corresponding gra or grb, or by input capture to gra or grb. when tcount is overflow or underflow, ovfi in the tstatusr is set to ? 1 ? . tcnt0 (16 bit) : upcounter tcnt1 (16 bit) : upcounter tcnt2 (16 bit) : upcounter tcnt0 (16 bit) : upcounter tcnt0 (16 bit) : upcounter tcnt0 (16 bit) : upcounter general register a, b (gra, grb) 16-bit readable and writable register. there are 2 general registers for each channel (total 12). each general register can function as either an output compare register or an input capture register by setting it in the tiocr.
108 GDC21D601 7 . examples of register setting 7.1 six channels channel 0 : in free-running counter (compare match - 0 output at grb and 1 output at gra) channel 1 : in a periodic counter cleared by grb ( compare match - toggle output at gra and grb) channel 2 : in a periodic counter cleared by tpb ( input capture - tpa with both edge s , tpb with the falling edge) channel 3 : in a periodic counter cleared by gra ( pwm mode ) channel 4 : in a periodic counter cleared by gra ( pwm mode : duty cycle 0% ) channel 5 : in a periodic counter cleared by gra ( pwm mode : duty cycle 100%) # setting example reset . . tstart = 0xc0 ; tcontr0 = 0x81 ; //i nternal clock2 tcontr1 = 0xc2 ; // internal clock3 tcontr2 = 0xc3 ; // internal clock4 tcontr3 = 0xa5 ; // external clock2 - rising edge tcontr4 = 0xce ; // external clock3 - falling edge tcontr5 = 0xbf ; // external clock4 - both edge tier0 = 0xfb ; // enable interrupt requests from the mcia, mcib tier1 = 0xfa ; // enable interrupt requests from the mcia tier2 = 0xfa ; // enable interrupt requests from the mcia tier3 = 0xfb ; // enable interrupt requests from the mcia, mcib tier4 = 0xfb ; // enable interrupt requests from the mcia, mcib tier5 = 0xfb ; // enable interrupt requests from the mcia, mcib tiocr0 = 0x9a ; tiocr1 = 0xbb ; tiocr2 = 0xdf ; tcount0 = 0xfff0 ; tcount1 = 0xfff0 ; tcount2 = 0x0000 ; tcount3 = 0x0000 ; tcount4 = 0x0000 ; tcount5 = 0x0000 ; gra0 = 0xfff4 ; gra1 = 0xfff2 ; gra3 = 0x0a ; gra4 = 0x04 ; gra5 = 0x0a ; grb0 = 0xfffa ; grb1 = 0xfff5 ; grb3 = 0x04 ; grb4 = 0x0a ; grb5 = 0x04 ; tpwmr = 0xf8 ; tstartr = 0xff ; . {running...}
109 GDC21D601 7.2 free-running mode # setting example tstartr = 0xc0 ; tcontr4 = 0x80 ; tier4 = 0xfc ; tcount4 = 0xfff0 ; tstartr = 0xd0 ; 7.3 periodic mode : gra compare match # setting example tstartr = 0xc0 ; tcontr4 = 0xa0 ; tier4 = 0xf9 ; tcount4 = 0x0000 ; gra4 = 0x0f ; tstartr = 0xd0 ; 7.4 synchronizing mode : in a periodic mode counter cleared by gra of channel0 in a periodic mode counter cleared by grb of channel1 in a periodic mode counter cleared, synchronized with other sync. timer (channel2, 3, 4, 5) toggle output at gra of channel0, 2, 4 toggle output at grb of channel1, 3, 5 # setting example tstartr = 0xc0 ; tcontr0 = 0xa0 ; tcontr1 = 0xc1 ; tcontr2 = 0xe0 ; tcontr3 = 0xe1 ; tcontr4 = 0xe0 ; tcontr5 = 0xe1 ; tiocr0 = 0x8b ; tiocr1 = 0xb8 ; tiocr2 = 0x8b ; tiocr3 = 0xb8 ; tiocr4 = 0x8b ; tiocr5 = 0xb8 ; tier0 = 0xfd ; tier1 = 0xfe ;
110 GDC21D601 tier2 = 0xfd ; tier3 = 0xfe ; tier4 = 0xfd ; tier5 = 0xfe ; tcount0 = 0xff10 ; tcount1 = 0xff11 ; tcount2 = 0xff12 ; tcount3 = 0xff13 ; tcount4 = 0xff14 ; tcount5 = 0xff15 ; gra0 = 0xff1a ; grb1 = 0xff15 ; gra2 = 0xff1c ; grb3 = 0xff1d ; gra4 = 0xff1e ; grb5 = 0xff1f ; tsyncr = 0xff ; tstartr = 0xff ;
111 GDC21D601 section 13. pio 1. general description the pio is an apb peripheral which provides 80 bits of programmable input /output divided into ten 8-bit ports ; port a, port b, port c, port d, port e , port f, port g , port h, port i , and port j. each pin is configurable as either input or output. at system reset, port a, c, e, g, i set their default s to input and port b, d, f, h, j set their default s to output. apb i/f port a data reg. port a dir. reg. port b data reg. port b dir. reg. port b port a epa[7:0 pa[7:0] paoe[7:0] epb[7:0 pb[7:0] pboe[7:0] pd[7:0] pa[7:2] bnres psel pstb pwrite figure 1 . pio block diagram and pads connections( port a and port b) each port has a data register and a data direction register that both are 8 bits wide. the data direction register defines whether each individual pin is an input or an output. the data register is used to read the value of the pio pins, both input and output, as well as to set the values of pins that are configured as outputs.
112 GDC21D601 2 . signal description the pio module is connected to the apb bus. table 1 . signal descriptions describe the apb signals used and produced. table 2 . specific block signal descriptions show the non-amba signals from the block. table 1. signal descriptions name type source/ destination description bnres i pmu this signal indicates a power on reset status of the bus (active low). pa[7:2] i apb bridge this is the part of the peripheral address bus, which is used by the peripheral for decoding its own register accesses. the addresses become valid before pstb goes to high and remain valid after pstb goes to low. pd[7:0] i/o apb peripherals, bd bus this is the part of the bi-directional peripheral data bus. the data bus is driven by this block during read cycles (when pwrite is low). pstb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of pstb is coincident with the falling edge of bclk (asb system clock). pwrite i apb bridge when this signal is high, it indicates a write to a peripheral and when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before pstb goes to high and remains valid after pstb goes to low. psel i apb bridge when this signal is high, it indicates the pio module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). for more details , see amba peripheral bus controller
113 GDC21D601 table 2 . specific block signal descriptions name type source/ destination description pa[7:0] o pads port a output driver. values written on padr register are put onto these lines and driven out to the port a pins if the corresponding data direction bits are set to high (paddr register). epa[7:0] i pads port a input driver. it reflects the external state of the port. this information is obtained when the padr register is read. paoe[7:0] o pads port a output enable (active low). values written on paddr register are put onto these lines. pb[7:0] o pads port b output driver. values written on pbdr register are put onto these lines and driven out to the port a pins if the corresponding data direction bits are set to high (pbddr register). epb[7:0] i pads port b input driver. it reflects the external state of the port. this information is obtained when the pbdr register is read . pboe[7:0] o pads port b output enable (active low). values written on pbddr register are put onto these lines. pc[7:0] o pads port c output driver. values written on pcdr register are put onto these lines and driven out to the port a pins if the corresponding data direction bits are set high (pcddr register). epc[7:0] i pads port c input driver. it reflects the external state of the port. this information is obtained when the pcdr register is read . pcoe[7:0] o pads port c output enable (active low). values written on pcddr register are put onto these lines. pd[7:0] o pads port d output driver. values written on pddr register are put onto these lines and driven out to the port d pins if the corresponding data direction bits are set to high (pdddr register). epd[7:0] i pads port d input driver. it reflects the external state of the port. this information is obtained when the pddr register is read . pdoe[7:0] o pads port d output enable (active low). values written on pdddr register are put onto these lines. pe[7:0] o pads port e output driver. values written on pedr register are put onto these lines and driven out to the port e pins if the corresponding data direction bits are set to high (peddr register). epe[7:0] i pads port e input driver. it reflects the external state of the port. this information is obtained when the pedr register is read . peoe[7:0] o pads port e output enable (active low). values written on peddr register are put onto these lines. pf[7:0] o pads port f output driver. values written on pfdr register are put onto these lines and driven out to the port f pins if the corresponding data direction bits are set to high (pfddr register). epf[7:0] i pads port f input driver. it reflects the external state of the port. this information is obtained when the pfdr register is read . pfoe[7:0] o pads port f output enable (active low). values written on pfddr register are put onto these lines. pg[7:0] out pads port g output driver. values written on pgdr register are put onto these lines and driven out to the port g pins if the corresponding data direction bits are set to high (pgddr register).
114 GDC21D601 name type source/ destination description epg[7:0] i pads port g input driver. it reflects the external state of the port. this information is obtained when the pgdr register is read . pgoe[7:0] o pads port g output enable (active low). values written on pgddr register are put onto these lines. ph[7:0] o pads port h output driver. values written on phdr register are put onto these lines and driven out to the port h pins if the corresponding data direction bits are set to high (phddr register). eph[7:0] i pads port h input driver. it reflects the external state of the port. this information is obtained when the phdr register is read . phoe[7:0] o pads port h output enable (active low). values written on phddr register are put onto these lines. pi[7:0] o pads port i output driver. values written on pidr register are put onto these lines and driven out to the port i pins if the corresponding data direction bits are set to high (piddr register). epi[7:0] i pads port i input driver. it reflects the external state of the port. this information is obtained when the pidr register is read. pioe[7:0] o pads port i output enable (active low). values written on piddr register are put onto these lines. pj[7:0] o pads port j output driver. values written on pjdr register are put onto these lines and driven out to the port j pins if the corresponding data direction bits are set to high (pjddr register). epj[7:0] i pads port j input driver. it reflects the external state of the port. this information is obtained when the pjdr register is read. pjoe[7:0] o pads port j output enable (active low). values written on pjddr register are put onto these lines.
115 GDC21D601 3 . hardware interface the apb interface is fully apb-compliant. the apb is a non-pipelined low-power interface, designed to provide a simple interfac e to slave peripherals. b_clk p_sel p_write p_stb p_d p_a register address data data figure 1 . apb read b_clk p_sel p_write p_stb p_d p_a register data address data figure 2 . apb write
116 GDC21D601 4 . functional description all block registers are cleared during power on reset (bnres low). this disables the output drivers for port a, c, e, g and i (input as default) and enables the drivers for port b, d, f, h , and j (output as default). for each port there is a data register and a data direction register. on reads, the data register contains the current status of correspondent port pins whether they are configured as input or output. writing to a data register only affects the pins that are configured as outputs. the data direction registers operates in a different manner on each port: for every port , a ? 0 ? in the data direction register indicates the port is defined as an output (default), a ? 1 ? in the data direction register indicates the port is defined as an input.
117 GDC21D601 5 . programmer ? s model 5.1 pio registers the following user registers are provided: pndr port n data register. values written to this 8-bit read/write register will be output on port a pins if the corresponding data direction bits are set to high (port output). values read from this register reflect the external state s of port n, not necessarily the value should be written to it. all bits are cleared by a system reset. pnddr port n data direction register. bits set in this 8-bit read/write register will select the corresponding pin s in port n to become an output, clearing a bit sets the pin to input. all bits are cleared by a system reset. n : a, b, c, d, e, f, g, h, i and j 5.2 register memory map the base address of the pio is 0xffff fc00 and the offset of any particular register from the base address is determined. table 3 . pio register memory map address read location write location pio base + 0x00 padr register padr register pio base + 0x04 paddr register paddr register pio base + 0x08 pbdr register pbdr register pio base + 0x0c pbddr register pbddr register pio base + 0x10 pcdr register pcdr register pio base + 0x14 pcddr register pcddr register pio base + 0x18 pddr register pddr register pio base + 0x1c pdddr register pdddr register pio base + 0x20 pedr register pedr register pio base + 0x24 peddr register peddr register pio base + 0x28 pfdr register pfdr register pio base + 0x2c pfddr register pfddr register pio base + 0x30 pgdr register pgdr register pio base + 0x34 pgddr register pgddr register pio base + 0x38 phdr register phdr register pio base + 0x3c phddr register phddr register pio base + 0x40 pidr register pidr register pio base + 0x44 piddr register piddr register pio base + 0x48 pjdr register pjdr register pio base + 0x4c pjddr register pjddr register
118 GDC21D601 section 14. synchronous serial peripheral interface 1 . general description the synchronous serial interface (sspi) is a high-speed synchronous serial i/o system. the sspi can be used for simple i/o expansion or for allowing several mcus to be interconnected in a multi-master configuration. clock polarity, clock phase, chip select polarity , and msb /lsb first ordering are software programmable to allow direct compatibility with a large number of peripheral devices. the sspi system can be configured as either a master or a slave . psel pwrite pstb pd[7:0] pa[ 5 :2] pclk bnres apb interface from asb from/to apb from clock generator sspi irq to interrupt controller sscr0 sscr1 sssr ssdr tx 16*8 fifo rx 16*8 fifo ssiout ssiin clock scaler sstr ssiclk ssics figure 1 . signal connections of the sspi an 8-bit shift register feeds the output channel, ssiout. during transfers, the busy bit in the system status register sssr is set. valid data can be read from a 16-bit shift register when the busy bit is cleared. there is also an interrupt signal, ssiirq , which is asserted at the end of data transfer. reading data clears the interrupt signal.
119 GDC21D601 2 . signal description the sspi module is connected to the apb bus. table 1 . signal descriptions describe the apb signals used and produced. table 2. signal descriptions show the non-amba signals from the block. table 1 . signal descriptions name type source/ destination description bnres i pmu asb reset signal (active low). pa[ 5 :2] i apb bridge this is the part of the peripheral address bus, and is used by the peripheral for decoding its own register accesses. the addresses become valid before pstb goes to high and remain valid after pstb goes to low. pd[7:0] i / o apb peripherals, b_d this is the part of the bi-directional peripheral data bus. this block drives the data bus during read cycles (when pwrite is low). pstb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of pstb is coincident with the falling edge of b_clk (asb system clock). pwrit e i apb bridge when this signal is high, it indicates a write to a peripheral, when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before pstb goes to high and remains valid after pstb goes to low. psel i apb bridge when this signal is high, this signal indicates that the apb bridge has selected the sspi module. this selection is a decode result of the system address bus. for more details , see amba peripheral bus controller. table 2 . specific block signal descriptions name type source/ destination description clk i pmu sspi clock input at a frequency of 3.6 8 mhz., scaled /4, /8, /32, /64 ssiin i ssiin pad serial data input. ssiout o ssiout pad serial data output. ssics i / o ssics pad chip select signal. sclk i / o sclk pad serial data clock to the external ssi. ssiirq o interrupt controller active high interrupt request.
120 GDC21D601 3 . hardware interface the apb interface is fully apb-compliant. the apb is a non-pipelined low-power interface, designed to provide a simple interfac e to slave peripherals. p_sel p_write p_stb p_d p_a register address data data figure 2 . apb read p_sel p_write p_stb p_d p_a register address data data figure 3 . apb write
121 GDC21D601 4 . functional description the following user registers are provided: sscr ss control register. in the synchronous mode, data transfer is synchronized with a clock pulse. this mode is suitable for continuous, high-speed serial communication. data length: 8 bits per character. uses the built-in baud rate generator as the transmit clock. support both lsb first and msb first (receive and send). writing to the sscr register controls the sspi. a write is encoded as follows. bit name function 7 tstmode default 1 : normal mode, 0: test mode 6 cs_pol default 1 : cs polarity(low), 0 : high 5 ssi_en default 1 : ssi enable signal 4 ms_mode default 1 : master mode , 0: slave mode 3 sin_msb default 1 : msb first sin (1: msb first , 0: lsb first) 2 sout_msb default 1 : msb first sout (1: msb first,0:lsb first) 1 ck_pol default 1 : clock polarity 0 cs_en default 1 : cs enable ( use only when slave mode) sscr0 registers (write) bit name function 7 tx end interrupt enable default 0 : disable 1: enable 6 tx fifo empty interrupt enable default 0 : disable 1: enable 5 rx fifo full interrupt enable default 0 : disable 1: enable 4 tx fifo full interrupt enable default 0 : disable 1: enable 3 rx fifo enable default 0 : disable 1: enable 2 tx fifo enable default 0 : disable 1: enable 1 cksel1 default 0 : clock rate selects 0 cksel0 default 0 : clock rate selects sscr1 registers (write)
122 GDC21D601 sssr ss status register. this is automatically set when data transfer is complete between processor and external device. the flag is cleared by a read of sssr followed by a read or write of ssdr. sstr ss term register. this is a register, which has a term between this byte and next byte by user ? s setting. the value can be 0 through 255. this is used only when master mode. table 4 . sssr registers (read) bit name function 7 rx fifo empty active high 6 tx fifo empty active high 5 rx fifo full active high 4 tx fifo full active high 3 tx end active high 2 r reserved 1 r reserved 0 busy when ssi transmitting and receiving
123 GDC21D601 5. register memory map the base address of the sspi interface is 0xffff f 8 00 and the offset of any particular register from the base address is as followed. address read location write location ssi base sscr0 sscr0 ssi base + 0x04 sscr1 sscr1 ssi base + 0x08 ssdr ssdr ssi base + 0x0c sssr ssi base + 0x10 sstr ssi base + 0x20 sscr0 sscr0 ssi base + 0x24 sscr1 sscr1 ssi base + 0x28 ssdr ssdr ssi base + 0x2c sssr ssi base + 0x30 sstr ssi register memory map sscr0 : control register0 sscr1 : control register1 ssdr : data register sssr : status register sstr : term register the output frequency is selected by programming the lower two bits of the sscr1 register, sscr1[1:0]. the following table shows the possible settings: sscr1[1..0] div frequency (when pclk=3.6864mhz) 00 4 921.6 khz 01 8 460.8 khz 10 32 115.2 khz 11 64 57.6 khz sscr1[1:0] encoding
124 GDC21D601 6. sspi data clock timing diagram siclk clk(ckpol=1) s(slaves) siout(cpha=1) msb clk(ckpol=0) siout(cpha=0) msb lsb lsb figure 4 . timing diagram
125 GDC21D601 section 15. uart 1. general description this module is an universal asynchronous receiver/transmitter(uart) with fifos, and is functionally identical to the 16450 on power - up (character mode). the gm16550 can be put into an alternate mode (fifo mode) to relieve the cpu of excessive software overhead. in this mode internal fifos are activated allowing 16 bytes plus 3 bit of error data per byte in the rcvr fifo, to be stored in both receive and transmit modes. all the logic is on the chip to minimize the system overhead and maximize system efficiency. the uart performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the cpu. the cpu can read the complete status of the uart at any time during the functional operation. status information reported includes the type and condition of the transfer operations performed by the uart, as well as any error conditions(parity, overrun, framing, or break interrupt). the uart includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uart has complete modem-control capability and a processor-interrupt system. interrupts can be programmed to the user ? s requirements, minimizing the computing required to handle the communications link. 2. features capable of running all exist ing 16450 software. after reset, all registers are identical to the 16450 register set. the fifo mode transmitter and receiver are each buffered with 16 byte fifo ? s to reduce the number of interrupts presented to the cpu. adds or deletes standard asynchronous communication bits (start, stop , and parity) to or from the serial data. hold and shift registers in the 16450 mode eliminate the need for precise synchronization between the cpu and serial data. independently controlled transmit, receive, line status and data set interrupts. programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock independent receiver clock input. modem control functions (cts, rts, dsr, dtr, ri , and dcd). fully programmable serial-interface characteristics: ? 5-, 6-, 7- or 8-bit characters ? even, odd , or no-parity bit generation and detection ? 1-, 1.5- or 2-stop bit generation and detection ? baud generation (dc to 256k baud) false start bit detection. complete status reporting capabilities. line break generation and detection. internal diagnostic capabilities . loopback controls for communications link fault isolation full prioritized interrupt system controls.
126 GDC21D601 3. signal description the GDC21D601 uart module is connected to the apb bus. table 1 . signal descriptions name type source/ destination description u_clk i cpg uart external clock input this connects the main timing reference to the uart. 3.6864mhz is recommend able input clock frequency. nb_res0 i pmu reset signal generated from the apb bridge(master reset) when this input is low, it clears all the registers (except the receiver buffer, transmitter holding , and divisor latches) and the control logic of the uart. the states of various output signals (sout, int_uart, nrts, ndtr) are affected by an active nb_res[0] input. p_a[2:0] i apb bridge register select. address signals connected to these 3 inputs select a uart register for the cpu to read from or write to during data transfer. a table of registers and their addresses is shown below. note that the state of the divisor latches p_d[7:0] i / o apb bridge data bus. this bus comprises eight tri-state input/output lines. the bus provides bi-directional communications between the uart and the cpu . data, control words and status information are transferred via the p_d[7:0] data bus. p_stb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of p_stb is coincident with the falling edge of b_clk.(asb system clock) p_write i apb bridge when this signal is high, it indicates a write to a peripheral. when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before p_stb goes to high and remains valid after p_stb goes to low. p_sel i apb bridge when this signal is high, it indicates that this module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). int_uart o intc interrupt. this pin goes to high whenever any one of the following interrupt types has an active high condition and is enabled via eir: receiver error flag; received data available:timeout(fifo mode only); transmitter holding register empty; and modem status. the int_uart signal is reset to low upon the appropriate interrupt service or a master reset operation. ncts i external clear to send. when this signal is low, it indicates that the modem or data set is ready to exchange data. the ncts signal is a modem status input whose conditions can be tested by the cpu reading bit 4 (cts) of the modem status register indicates whether the ncts input has changed its state since the previous reading of the modem status register. ncts has no effect on the transmitter. ** note : whenever the cts bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled.
127 GDC21D601 name type source/ destination description sin i external serial input. serial data input from the communications link (peripheral device, modem or data set). ndsr i external data set ready. when this signal is low, it indicates that the modem or data set is ready to establish the communications link with the uart. the ndsr signal is a modem status input whose conditions can be tested by the cpu reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the ndsr signal. bit 1(ddsr) of modem status register indicates whether the ndsr input has changed its state since the previous reading of the modem status register. ** note : whenever the dsr bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled. ndcd i external data carrier detect. when this signal is low, it indicates that the data carrier has been detected by the modem data set. the signal is a modem status input whose condition can be tested by the cpu reading bit 7 (dcd) of the modem status register. bit 7 is the complement of the signal. bit 3 (ddcd) of the modem status register indicates whether the input has changed its state since the previous reading of the modem status register. ndcd has no effect on the receiver. ** note : whenever the dcd bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled. nri i external ring indicator. when this signal is low, i t indicates that a telephone ring signal is received by the modem or data set. the nri signal is a modem status input whose condition can be tested by the cpu reading bit 6 (ri) of the modem status register. bit 6 is the complement of the nri signal. bit 2 (teri) of the modem status register indicates whether the nri input signal has changed from a low to a high state since the previous reading of the modem status register. ** note : whenever the ri bit of the modem status register changes from a high to a low state, an interrupt is generated if the modem status interrupt is enabled. ndtr o external data terminal ready. when this is low, it informs the modem or data set that the uart is ready to establish communication link. the ndtr output signal can be set to an active low by programming bit 0 (dtr) of the modem control register to high level. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. nrts o external request to send. when low, this informs the modem or data set that the uart is ready to exchange data. the nrts output signal can be set to an active low by programming bit 1 (rts) of the modem control register. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. sout o external serial output. composite serial data output to the communications link (peripheral, modem or data set). the sout signal is set to the marking (logic 1) state upon a master reset operation.
128 GDC21D601 table 2 . register address dlab p_a[2] p_a[1] p_a[0] register 0 0 0 0 receiver buffer(read), transmitter holding register(write) 0 0 0 1 interrupt enable x 0 1 0 interrupt identification(read) x 0 1 0 fifo control(write) x 0 1 1 line control x 1 0 0 modem control x 1 0 1 line status x 1 1 0 modem status x 1 1 1 scratch 1 0 0 0 divisor latch(least significant byte) 1 0 0 1 divisor latch(most significant byte) table 3 . uart reset configuration register / signal register control register state interrupt enable register master reset 0000 0000 interrupt identification register master reset 0000 0001 fifo control register master reset 0000 0000 line control register master reset 0000 0000 modem control register master reset 0000 0000 line status register master reset 0110 0000 modem status register master reset xxxx 0000 sout master reset high int_uart (rcvr errs) read lsr / reset low int_uart (rcvr data ready) read rbr / reset low int_uart (thre) read iir / write thr / reset low int_uart(modem status changes) read msr / reset low nrts master reset high ndtr master reset high
129 GDC21D601 4. internal block diagram apb i/f & control logic baud generator transmitter timing & control transmitter fifo receiver timing & control modem control logic data bus buffer receiver buffer register receiver fifo line control register divisor latch(ls) divisor latch(ms) line status register transmitter holding register modem control register modem status register interrupt enable register interrupt id register fifo control register receiver shift register transmitter shift register select interrupt control logic select int_uart p_a[0] p_a[1] p_a[2]] nb_res[0] p_d[7:0] p_sel p_write p_stb u_clk nrts ncts ndtr ndsr ndcd nri sout sin figure 1 . internal block diagram
130 GDC21D601 5 . registers description there are two urats implemented in the design, the base addresses are 0xffff f500 in uart0 and 0xffff f600 in uart1. in table 4 . uart register address map, x can be either 0 or 1. table 4 . uart register address map address name description uartxbase + 0x00 receiver buffer (rbr) 8-bit r/o set dlab = 0 uartxbase + 0x00 transmitter holding (thr) 8-bit w/o set dlab = 0 uartxbase + 0x04 interrupt enable (ier) 8-bit r/w uartxbase + 0x08 interrupt identification (iir) 8-bit r/o uartxbase + 0x08 fifo control (fcr) 8-bit w/o uartxbase + 0x0c line control (lcr) 8-bit r/w uartxbase + 0x10 modem control (mcr) 8-bit r/w uartxbase + 0x14 line status (lsr) 8-bit r/w uartxbase + 0x18 modem status (msr) 8-bit r/w uartxbase + 0x1c scratch (scr) 8-bit r/w uartxbase + 0x00 divisor latch ls (dll) 8-bit r/w set dlab = 1 uartxbase + 0x04 divisor latch ms (dlm) 8-bit r/w set dlab = 1
131 GDC21D601 table 5 . summary of registers gives the details of the uart registers. table 5 . summary of registers register address 0 dlab = 0 0 dlab = 0 1 dlab = 0 2 2 3 4 5 6 7 0 dlab = 1 1 dlab = 1 bit no. receiver buffer register transmitter holding register interrupt enable register interrupt ident register fifo control register line control register modem control register line status register modem status register scratch register divisor latch (ls) divisor latch (ms) rbr thr ier iir fcr lcr mcr lsr msr scr dll dlm 0 data bit 0 (note 1) data bit 0 enable received data available interrupt 0 if interrupt pending fifo enable word length select bit 0 data terminal ready (dtr) data ready (dr) data clear to send (dcts) bit 0 bit 0 bit 8 1 data bit 1 data bit 1 enable transmitter holding register empty interrupt interrupt id bit 0 rcvr fifo reset word length select bit 1 request to send (rts) overrun error (oe) delta data set ready (ddsr) bit 1 bit 1 bit 9 2 data bit 2 data bit 2 enable receiver line status interrupt interrupt id bit 1 xmit fifo reset number of stop bit parity error (pe) trailing edge ring indicator (teri) bit 2 bit 2 bit 10 3 data bit 3 data bit 3 enable modem status interrupt interrupt id bit 2 (note 2) parity enable framing error (fe) delta data carrier detect (ddcd) bit 3 bit 3 bit 11 4 data bit 4 data bit 4 0 0 reserved even parity select loop break interrupt (bi) clear to send (cts) bit 4 bit 4 bit 12 5 data bit 5 data bit 5 0 0 reserved stick parity 0 transmitter holding register empty (thre) data set ready (dsr) bit 5 bit 5 bit 13 6 data bit 6 data bit 6 0 fifo enabled (note 2) rcvr trigger (lsb) set break 0 transmitter empty (temt) ring indicator (ri) bit 6 bit 6 bit 14 7 data bit 7 data bit 7 0 fifo enabled (note 2) rcvr trigger (msb) divisor latch access bit 0 error in rcvr fifo (note 2) data carrier detect (dcd) bit 7 bit 7 bit 15 note 1 : bit 0 is the least significant bit seriously transmitted or received. note 2 : these bits are always 0 in the gm16c450 mode. the system programmer may access any of the uart registers summarized in table 5 . summary of registers via the cpu. these registers control uart operation including transmission and reception of data. each register bit in the table has its name and reset state as shown.
132 GDC21D601 line control register the system programmer specifies the format of the asynchronous data communications exchange and set the divisor latch access bit via the line control register (lcr). the programmer can also read the contents of the line control register. the read capability simplifies the system programming and eliminates the need for separate storage in system memory of the line characteristics. table 5 . summary of registers shows the contents of the lcr. details on each bit are : bit 0 and 1 : these two bits specify the number of bits in each transmitted and received serial character. the encoding of bits 0 and 1 is as follows: table 6 . line control register encoding bit 1 bit 0 character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits bit 2 : this bit specifies the number of stop bits transmitted and received in each serial character. if bit 2 is a logic 0, one stop bit is generated in the transmitted data. if bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, one and a half stop bits are generated. if bit 2 is a logic 1 when either a 6-, 7- , or 8-bit word length is selected, two stop bits are generated. the receiver checks the first stop-bit only, regardless of the number of selected stop bits. bit 3 : this bit is the parity enable bit. when bit 3 is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1s when the data word bits and the parity bit are summed.) bit 4 : this bit is the even parity select bit. when bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. when bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. bit 5 : this bit is the stick parity bit. when bits 3, 4 , and 5 are logic 1 , the parity bit is transmitted and checked as a logic 0. if bits 3 and 5 are 1 and bit 4 is a logic 0 , then the parity bit is transmitted and checked as a logic 1. if bit 5 is a logic 0 stick parity is disabled. bit 6 : this bit is the break control bit. it causes a break condition to be transmitted to the receiving uart . when it is set to a logic 1, the serial output (sout) is forced to be the spacing (logic 0) state. the break is disabled by setting bit 6 to a logic 0. the break control bit acts only on sout and has no effect on the transmitter logic. ** note : this feature enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. bit 7 : this bit is the divisor latch access bit (dlab) , it must be set to high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set to low (logic 0) to access the rec e iver buffer, the transmitter holding register , or the interrupt enable register.
133 GDC21D601 programmable baud generator the uart contains a programmable baud generator that is capable of taking any clock input from dc to 8.0 mhz and dividing it by any divisor from 2 to 65535. 4mhz is the highest input clock frequency recommended when the divisor=1. the output frequency of the baud generator is 16 x the baud [divisor # = (frequency input) / (baud rate x 16)]. two 8-bit latches store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization to ensure the proper operation of the baud generator. upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. table 7 . baud rates provide decimal divisors to use with crystal frequencies of 1.8432 mhz and 3.6864 mhz. for baud rates of 38400 and below, the error obtained is minimal. the accuracy of the desired baud rate depend s on the chosen crystal frequency. using a divisor of zero is not recommended. table 7 . baud rates 1.8432 mhz 3.6864 mhz desired baud rate decimal divisor used to generate 16 x clock percent error difference between desired and actual desired baud rate decimal divisor used to generate 16 x clock percent error difference between desired and actual 50 2304 - 50 4608 - 75 1536 - - - - 110 1047 0.026 110 2094 0.026 134.5 857 0.058 - - - 150 768 - - - - 300 384 - 300 768 - 600 192 - - - - 1200 96 - 1200 192 - 1800 64 - - - - 2000 58 0.69 - - - 2400 48 - 2400 96 - 3600 32 - - - - 4800 24 - 4800 48 - 7200 16 - - - - 9600 12 - 9600 24 - 19200 6 - 19200 12 - 38400 3 - 38400 6 - 57600 2 2.86 57600 4 - 115200 1 115200 2 -
134 GDC21D601 line status register this register provides status information to the cpu concerning the data transfer. table 5 . summary of registers shows the contents of the line status register. details on each bit are : bit 0 : this bit is the receiver data ready (dr) indicator. bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic 0 by reading all of the data in the receiver buffer register or the fifo. bit 1 : this bit is the overrun error (oe) indicator. bit 1 indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is set to a logic 1 upon the detection of an overrun condition , and reset whenever the cpu reads the contents of the line status register. if the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error will occur only after the fifo is full and the next character has been completely received in the shift register. oe is indicated to the cpu as soon as it happens. the character in the shift register is overwritten, but it is not transferred to the fifo. bit 2 : this bit is the parity error (pe) indicator. bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even-parity-select bit. the pe bit is set to a logic 1 upon the detection of a parity error and is reset to a logic 0 whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo where it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. bit 3 : this bit is the framing error (fe) indicator. bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic 1 whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit (spacing level). the fe indicator is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo where it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. the uart will try to resynchronize after a framing error. to do this , it assumes that the framing error was due to the next start bit, so it samples this ? start ? bit twice and then takes it in the ? data ? . bit 4 : this bit is the break interrupt (bi) indicator. bit 4 is set to a logic 1 whenever the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). the bi indicator is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo where it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. the next character transfer is enabled after sin goes to the marking state and receives the next valid start bit. ** note : bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions is detected and the interrupt is enabled. bit 5 : this bit is the transmitter holding register empty (thre) indicator. bit 5 indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the cpu when the transmit holding register empty interrupt enable is set to high. the thre bit is set to a logic 1 when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo.
135 GDC21D601 bit 6 : this bit is the transmitter empty (temt) indicator. bit 6 is set to a lo gic 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to a logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmitter fifo and register are both empty. bit 7 : in the 16450 mode , this is 0. in the fifo mode , lsr7 is set when there is at least one parity error, framing error or break indication in the fifo. lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. ** note : the line status register is intended for read operations only. fifo control register this is a write only register at the same location as the iir (the iir is a read only register). this register is used to enable the fifos, clear the fifos and set the rcvr fifo to trigger level. bit 0 : writing a 1 to fcr0 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to 16c450 mode and vice versa , data is automatically cleared from the fifos. this bit must be a 1 when other fcr bits are written to or they will not be programmed. bit 1 : writing a 1 to fcr1 resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clear ed . bit 2 : writing a 1 to fcr2 resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clear ed . bit 3 : fcr3 is not used. bit 4,5 : fcr4 to fcr5 are reserved for futu re use. bit 6,7 : fcr6 and fcr7 are used to set the trigger level for the rcvr fifo interrupt. table 8 . rcvr fifo interrupt fcr[7:6] rcvr fifo trigger level (bytes) 00 01 (default) 01 04 10 08 11 14
136 GDC21D601 interrupt identification register in order to provide minimum software overhead during data character transfers, the uart prioritizes interrupts into four levels and records the m in the interrupt identification register. the four levels of interrupt conditions are as follows in order of priority : receiver line status received data ready transmitter holding register empty modem status when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access occur s , the uart records new interrupts, but does not change its current indication until the access is complete. table 5 . summary of registers shows the contents of the iir. details on each bit are : bit 0 : this bit can be used in a prioritized interru pt environment to indicate whether an interrupt is pending or not . when bit 0 is a logic 0, an interrupt is pending and the iir contents may be used as a pointer for the appropriate interrupt service routine. when bit 0 is a logic 1, no interrupt is pending. bit 1 and 2 : these two bits of the iir are used to identify the highest priority interrupt pending as indicated in table 9 . interrupt control functions. bit 3 : in the 16450 mode this bit is 0. in the fifo mode this bit is set along with bit 2 when a time-out interrupt is pending. bit 4 and 5 : these two bits of the iir are always logic 0. bit 6 and 7 : these two bits are set when fcr0 = 1.
137 GDC21D601 table 9 . interrupt control functions fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error , parity error , framing error or break interrupt reading the line status register 0 1 0 0 second receiver data available receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level 1 1 0 0 second character time-out indication no characters have been removed from or input to the rcvr fifo during the last 4 char. times and there is at least 1 char. in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if it is the source of interrupt) or writing it into the transmitter holding register 0 0 0 0 fourth modem status clear to send , data set ready , ring indicator , or data carrier detect reading the modem status register interrupt enable register this register enables the five types of uart interrupts. each interrupt can individually activate the interrupt (int_uart) output signal. it is possible to totally disable the interrupt enable register (ier). similarly, setting bits of the ier register to a logic 1 enable the selected interrupt(s). disabling an interrupt prevents it from being indicated as active in the iir and from activating the int_uart output signal. all other system functions operate in their normal manner s , including the setting of the line status and modem status registers. table 5 . summary of registers shows the contents of the ier. details on each bit are : bit 0 : this bit enables the received data available interrupt (and time-out interrupts in the fifo mo de) when it is set to logic 1. bit 1 : this bit enables the transmitter holding register empty interrupt when set to logic 1. bit 2 : this bit enables the receiver line status interrupt when it is set to logic 1. bit 3 : this bit enables the modem stat us interrupt when it is set to logic 1. bit 4 through 7 :these four bits are always logic 0.
138 GDC21D601 modem control register this register controls the interface with the modem or data set (or a peripheral device emulating a modem). the contents of the modem control register are indicated in table 5 . summary of registers , and are described below. bit 0 : this bit controls the data terminal ready (ndtr) output. when this bit is set to a logic 1, the ndtr output is forced to be a logic 0. when bit 0 is reset to a logic 0, the ndtr output is forced to be a logic 1. ** note : the ndtr output of the uart may be applied to an eia inverting line driver (such as the ds1488) to obtain the proper polarity input at the succeeding modem or data set. bit 1 : this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a n identical manner that described above for bit 0. bit 2 : not used bit 3 : not used bit 4 : this bit provides a local loopback feature for diagnostic testing of the uart. wh en bit 4 is set to logic 1, the transmitter serial output (sout) is set to the marking (logic 1) state . t he receiver serial input (sin) is disconnected; the output of the transmitter shift register is ? looped back ? into the receiver shift register input . t he four modem control inputs (ncts, ndsr, ndcd , and nri) are disconnected . t he two modem control outputs (ndtr and nrts) and two internal node s (out1 and out2) are internally connected to the four modem control inputs and the modem control output pins are forced to be their inactive state (high). on the diagnostic mode, the transmitted data is immediately received. this feature allows the processor to verify the transmit- and received-data paths of the uart. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. their sources are external to the part. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits of the modem control register instead of the four modem control inputs. the interrupts are still controlled by the interrupt enable register. bit 5 through 7 :these bits are permanently set to logic 0.
139 GDC21D601 modem status register this register provides the current state of the control lines from the modem (or peripheral device) to the cpu. in addition to this current-state information, four bits of the modem status register provide change information. these bits are set to a logic 1 whenever a control input from the modem change s its state. they are reset to logic 0 whenever the cpu reads the modem status register. the contents of the modem status register are indicated in table 5 . summary of registers , and are described below. bit 0 : this bit is the delta clear to send (dcts) indicator. bit 0 indicates that the ncts input to the chip has changed its state since the last time it was read by the cpu. bit 1 : this bit is the delta data set ready (ddsr) indicator. bit 1 indicates that the ndsr input to the chip has changed its state since the last time it was read by the cpu. bit 2 : this bit is the trailing edge of ring indicator (teri) detector. bit 2 indicates that the nri input to the chip has changed from a low to a high state. bit 3 : this bit is the delta data carrier detect (ddcd) indicator. bit 3 in dicates that the ndcd input to the chip has changed its state since the last time it was read by the cpu. ** note : whenever bit 0, 1, 2 or 3 is set to logic 1, a modem status interrupt is generated. bit 4 : this bit is the complement of the clear to sen d (ncts) input. if bit 4 (loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. bit 5 : this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to 1, this bit is equivalent to dtr in the mcr. bit 6 : this bit is the complement of the ring indicator (nri) input. if bit 4 of the mcr is set to 1, this bit is equivalent to out1 in the mcr. bit 7 : this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to 1, this bit is equivalent to out2 in the mcr. scratch register this 8-bit read/write register does not control the uart in any way. it is intended to be used as a scratchpad register by the programmer to hold data temporarily.
140 GDC21D601 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr 0 = 1, ier 0 = 1) , rcvr interrupts occur as follows : 1. the received data available interrupt will be issued to the cpu when the fifo has reached its programmed trigger level; it will be cleared as soon as the fifo drops below its programmed trigger level. 2. the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt it is cleared when the fifo drops below the trigger level. 3. the receiver line status interrupt (iir-06), as before, has higher priority than the received data available(iir-04) interrupt. 4. the data ready bit (lsr 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occurs as follows : 1. a fifo timeout interrupt occurs i n the following conditions : - at least one character is in the fifo - the latest serial character received was longer than 4 continuous character times (if 2 stop bits are programmed, the second one is included in this time delay). - the latest cpu read of the fifo was longer than 4 continuous character times. this will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12 bit character. 2. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baud rate). 3. when a timeout interrupt has occurred, it is cleared and the timer is reset when the cpu reads one character from the rcvr fifo. 4. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr 0 = 1, ier 1 = 1), xmit interrupts occur as follows : 1. the transmitter holding register interrupt (02) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the xmit fifo while this interrupt is servic ed or the iir is read. 2. the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre = 1 and there has not been at least two bytes at the same time in the transmit fifo since the last thre = 1. the first transmitter interrupt affect changing fcr 0 will be immediate if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt.
141 GDC21D601 fifo polled mode operation when fcr 0 = 1 resetting, ier 0, ier 1, ier 2, ier3 or all to zero puts the uart in the fifo polled mode. since the rcvr and xmitter are controlled separately, either one or both can be in the polled mode of operation.
142 GDC21D601 section 16. smart card interface 1. general description the smart card interface block is basically a general-purpose serial interface block that has the smart card interface features additionally. and some ports of gpio are necessary to provide complete interfaces to the smart card. as a general-purpose serial interface, it has the uart(16550) compatible register sets and bit definitions although it doesn ? t have the modem control pins. as a smart card interface, it has the following general features. supports only asynchronous operation. supports cards that have internal reset capability. supports cards that have an active low reset input. supports cards that use the internal clock. generate the clock for a card expecting the external clock. use the serial in/out ports for i/o. use the gpio ports for other interface signals like rst, detect, etc. figure 1 . signal connections of the smart card interface apb interface smart card interface smart card smclk smdoen p_sel p_write p_stb u_clk p_ a[3:0] p_ d[7:0] int_scif nb -res smdo smdi
143 GDC21D601 2. signal description the smart card interface module is connected to the apb. table 1 . signal descriptions describes the apb signals used and produced. table 2 . signal descriptions shows the non-amba signals from the block. table 1 . signal descriptions name type source/ destination description nb_res i reset controller this signal indicates system reset status of the bus (active low) p_a[3:0] i apb bridge this is part of the peripheral address bus, which is used by the peripheral for decoding its own register accesses. the addresses become valid before p_stb goes high and remain valid after p_stb goes low. p_d[7:0] i / o apb, b_d this is part of the bidirectional peripheral data bus. the data bus is driven by this block during read cycles (when p_write is low). p_stb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of p_stb is coincident with the falling edge of b_clk (asb system clock). p_write i apb bridge when high, this signal indicates a write to a peripheral, and when low, a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before p_stb goes high and remains valid after p_stb goes low. p_sel i apb bridge when high, this signal indicates the smart card interface module has been selected by the apb bridge. this selection is a decode of the system address bus (asb). for more details see amba peripheral bus controller (arm ddi 0044). table 2 . specific block signal descriptions name type source/ destination description smdi i smart card serial data input smdo o smart card serial data output smclk o smart card clock output for smart card that expects the external clock smdoen o smart card tri-state buffer enable signal for smdo output. for normal uart operation, it is always ? 1 ? . for smart card interface mode, it ? s used to prevent the serial i/o bus conflict because the serial i/o for smart card interface is bidirectional int_scif out interrupt controller smart card interrupt.
144 GDC21D601 3. hardware interface the apb interface is fully apb-compliant. the apb is a nonpipelined low-power interface, designed to provide a simple interfacing to slave peripherals. figure 2 . apb read figure 3 . apb write b_clk p_sel p_write p_stb p_d p_a register address data data b_clk p_sel p_write p_stb p_d p_a register data address data
145 GDC21D601 4. functional description 4.1 reset and detection of the card all the interface signals except the i/o and the clk are connected to the gpio ports. usually, rst and the card detect signal are connected to the gpio. (the number of the interface signals needed and their functionality can vary according to the physical application.) the iso/iec 7816 standard defined the timing requirements for rst and that can be controlled by software. the implementation of the detection of the card is not defined in the standard, but usual implementation uses the external circuit to generate the card-detect signal that can indicates the presence of the card. the smart card interface of the gdc27d601 also expects the ? card detect signal ? from the outside through the gpio port. optionally, gpio can also provide the voltage control signals that are needed to support the various kinds of smart cards that use the different vcc and vpp voltages. 4.2 transmitting the data transmitting the data to the smart card is performed with the following procedure. program the baud rate generator to the appropriate value. software writes the data to the transmit buffer. after transmission, card sends an error signal if there is a parity error. smart card interface detects the parity error and sets the error status for cpu to read the status. the cpu read s the error status and determine if re-transmission is necessary. if there is an error, write the same data again to the transmit buffer and re-transmit. guard time is controlled by software. 4.3 receiving the data receiving the data from the smart card is done with the following procedure. program the baud rate generator to the appropriate value. receive the data. if there is an parity error, smart card interface sets the internal error status and send the error signal back to the c ard through the i/o pin. software checks the error status and wait for data if there is an error. guard time is controlled by software.
146 GDC21D601 5. programmer ? s model smart card interface mode control register (smcr) smcr is a 3-bit readable/writable register, in which is used to control the pure smart card interface part except uart and apb interface. all the bits in this register are initialized to 0 at reset. table 3. smcr bit functions bit name function 0 mdsel mode select 0 : uart (initial value) 1 : smart card i/f 1 smclken smart card clock enable 0 : disable(initial value) 1 : enable 2 smpeden parity error detect enable 0 : disable(initial value) 1 : enable smart card clock devisior latch (smdll) smart card clock devisior latch (smdlm) the smart card interface has a programmable clock generator for smart card that uses the external clock. smdll and smdlm are two 8-bit latchs, in which is used to store in a 16-bit binary format. all the bits in this registers are initialized to 0 at reset. table 4 . smdll bit functions bit name function 7:0 devisior (ls) divisor for smclk table 5 . smdlm bit functions bit name function 7:0 devisior (ms) divisor for smclk smart card interface status register (smsr) smsr is a 1-bit read-only register which is used to indicate whether partty error is detected or not. it is cleared after reading it. table 6 . smsr bit functions bit name function 0 smpedi parity error 0 : no interrupt occurrenrce (initial value) 1 : interrupt occurrerce
147 GDC21D601 test register for input (tir) tir is a 3 -bit write-only register defined for test purpose. this register allows simulation of input signals to the block, as well as the generation of a special test clock signal aimed for production test vectors. table 7 . tir bit functions bit name function 2 tnmode mode select bit 0 : normal operation mode 1 : test mode 1 ticuclk programmable serial clock for test 0 ticsmdi programmable serial data input for test test register for output (tor) tor is a 3 -bit read-only register defined for test purpose. this register allows simulation of output signals from the block. table 8 . tor bit functions bit name function 2 tsmdo serial data output line 1 tsmdoen serial outputl data enable line 0 tsmclk serial clock line for smart card the following regitsers are same ones in the uart module. details on each register see the data sheet of GDC21D601 uart. receiver buffer register (rbr) transmitter holding register (thr) interrupt enable register (ier) interrupt identification register (iir) fifo control register (fcr) line control register (lcr) line status register (lsr) scratch register (scr) divisor latch (dll) divisor latch (dlm)
148 GDC21D601 5.2 register memory map the base address of the smart card interface is 0xfffff 7 00 and the offset of any particular register from the base address is determined. table 9 . smart card interface register memory map address register read location write location smart card i/f base rbr/thr (dlab = 0) dll (dlab = 1) receiver buffer divisor latch (ls) transmitter holding divisor latch (ms) smart card i/f base + 0b0001 ier (dlab = 0) dlm (dlab = 1) interrupt enable divisor latch (ms) interrupt enable divisor latch (ms) smart card i/f base + 0b0010 iir/fcr interrupt ident fif control smart card i/f base + 0b0011 lcr line control line control smart card i/f base + 0b0101 lsr line status smart card i/f base + 0b0111 scr scratch scratch smart card i/f base + 0b1000 smcr smart card control smart card control smart card i/f base + 0b1001 smdll divisor latch (ls) for smclk divisor latch (ls) for smclk smart card i/f base + 0b1010 smdlm divisor latch (ms) for smclk divisor latch (ms) for smclk smart card i/f base + 0b1011 smsr status for smped error smart card i/f base + 0b1100 tir test register for input smart card i/f base + 0b1101 tor test register for output
149 GDC21D601 section 17. i 2 c controller 1. general description the i 2 c controller allows the GDC21D601 to exchange data with a number of other i 2 c devices such as micro controller, eeproms, real-time clock devices, a/d converters, lcd displays, ntsc/pal encoder, and etc. the i 2 c is a synchronous bus that is used to connect several ics on a board. the i 2 c bus uses two wires, serial data (sda) , and serial clock (scl) to carry information between the ics connected to the bus. the i 2 c controller consists of transmitter and receiver sections, an independent baud rate generator, and a control unit. the transmitter and receiver sections use the same clock, which is derived from the i 2 c controller baud rate generator in master mode. refer to figure 1 . for the i 2 c controller block diagram. the GDC21D601 i 2 c bit7(msb) is shifted out first. figure 1. i 2 c block diagram apb(amba) interface clk p_sel p_write p_stb p_d p_a reset clock divider sda driver scl driver interrupt generate baud register control register status register address register test register data register sda_out sda_in scl_in scl_out interrupt fsm
150 GDC21D601 2 . i 2 c controller key features the i 2 c controller contains the following key features: two-wire interface s (sda and scl) both master and slave functions supports clock rates up to 400khz in master mode . independent programmable baud rate generator local loopback capability for testing slave clock stretching support 3 . i 2 c controller clocking and pin functions the i 2 c controller can be configured as a master or slave for the serial channel. when the i 2 c controller is a master, the i 2 c controller baud rate generator is used to generate the i 2 c controller transmit and receive clocks. the i 2 c baud rate generator takes its input from the block clock input. both serial data (sda) and serial clock (scl) are bi-directional pin s . these pins are connected to a positive supply voltage via an external pull up resister. when the bus is free, both lines are high. when the i 2 c controller is working as a master, scl is the clock output signal that shifts the received data in and shifts the transmit data out from/to the sda pin. when the i 2 c controller functions as a slave, its internal clock is synchronized by the incoming clock from scl line. 4 . i 2 c master mode transmit / receive process when the i 2 c controller functions in master mode, the i 2 c master initiates a transaction by transmitting a message to the peripheral (i 2 c slave) as a transmitter mode. the message specifies a read or write operation. if a read operation is specified, the direction of the transfer is changed at the moment of the first acknowledge, and the called slave receiver becomes a slave transmitter. otherwise, the master functions as master transmitter continuously. before the data exchange, core must check if the bus is used by other masters by reading the status register(stat_r). if the bus is not used, the address of the slave with which you want to communicate should be written to transmit register(tx_r), and configure the control register to start the cycle. a fter interrupt happens, confirm ing the bus i s acquired and called slave i s responded. when the slave i s not responded, the sequence must be ended by stop condition by configuring control register(ctrl_r). if bus i s lost and called address is not master itself, i 2 c block i s gone to initial state. but if bus winner call s this master, master i s gone into slave mode. if all these processes are okay, then the data transfer follows. data transfer cycle are started by writing transmit register(tx_r) and configuring control register. when the i 2 c controller functions as a receiver, tx_r is written with 0xff. detailed sequence is described below.
151 GDC21D601 4.1 master transmitter sequence step 1 : read status register. check if bbusy is clear ed step 2 : write slave address to data register write 5 ? b10111 to control register step 3 : wait for interrupt write 5 ? b x 0011 to control register step 4 : read status register. check blost, ack_rpy if blost is 1, go to step 1. else if ack_rpy is 1 go to step 6. step 5 : write data to transmit register if this dat a is the last, go to step 6. wait for interrupt. go to step 4. step 6 : write 5 ? b11011 to control register 4.2 master receiver sequence step 1 : read status register. check if bbusy is clear ed step 2 : write slave address to data register write 5 ? b10111 to control register step 3 : wait for interrupt read status register. check blost, ack_rpy if blost is 1, go to step 1. else if ack_rpy is 1, go to step 5. write 5 ? b10001 to control register write 0xff to transmit register step 4 : if this data is the last, go to step 5. wait for interrupt read data from data register read status register. check ack_rpy if ack_rpy is 0 go to step 4. step 5 : write 5 ? b11011 to control register 5. i 2 c restart capability (combined mode) the i 2 c controller can restart without going to stop condition. if a i 2 c master wants to restart after sending/receiving 1 byte data , just keep the start_ctrl and ack_ctrl bit in ctrl_r, and if a master wants to restart after sending/receiving several bytes data, set start_ctrl and ack_ctrl bit in ctrl_ r just before sending/receiving last data. the followings shows the restart operation after transfer 1 byte. it sets start_ctrl and ack_ctrl to 1 at first interrupt. 1. read status register. check if bbusy is clear ed 2. write slave address to data register write 5 ? b10111 to control register 3. wait for interrupt read status register. check ack_rpy if ack_rpy is 1, go to step 5. else write 5 ? b10111 to control register to restart 4. wait for interrupt. write slave address to data register. write 5 ? b10001 to control register. 5. wait for interrupt if this data is the last, go to step 6. read status register. check ack_rpy if ack_rpy is 0 go to step 5. 6. write 5 ? b11011 to control register if above data transfer is transmitter, write data to transmit register else if recevier write 8 ? hff to transmit register.
152 GDC21D601 6. i 2 c controller programming model the following paragraphs describe the registers in the i 2 c controller. 6 .1 i 2 c co n trol register (ctrl_r). ctrl_r is a write-only register that controls the i 2 c operation mode. ctrl_r is cleared by reset excluding ack_ctrl bit. 7 6 5 4 3 2 1 0 reserved reserved reserved include0 stop_ctrl start_ctrl ack_ctrl int_en bit name function 7:5 reserved 4 include0 i ndicates whether addr_r[0] bit should be used or not in compari ng address es in slave mode c lear ed by reset 3 stop_ctrl i ndicates the transfer cycle should be ended by generating stop condition in master mode c lear ed by reset 2 start_ctrl indicates the transfer cycle should be started by generating start condition in master mode clear ed by reset 1 ack_ctrl t his bit value directly goes to the sda pin in acknowledge phase in both master and slave mode s et by reset 0 int_en i nterrupt enable bit c lear ed by reset 6 .2 i 2 c status register (stat_r). the stat_r register is an 8-bit memory mapped and read-on l y register. the stat_r register shows the state of i 2 c block. 7 6 5 4 3 2 1 0 reserved reserved reserved intr bbusy blost ack_rpy slave bit name function 7:5 reserved 4 intr i ndicates that interrupt is generated. used when interrupt polling is used 3 bbusy i ndicates that i 2 c bus is used 2 blost i ndicates that bus is lost during bus arbitration 1 ack_rpy i ndicates the real state of sda line in acknowledge phase 0 slave indicates that i 2 c block was called. this bit is set when i 2 c block was called by other master
153 GDC21D601 6 .3 i 2 c address register (addr_r). the addr_r is an 8-bit write-only register that is used to be accessed by other master. 7 6 5 4 3 2 1 0 addr_r bit name function 7:0 addr_r i ndicates the slave address of the i 2 c controller. this address is used in comparing the incoming address es in slave mode 6 .4 i 2 c baud-rate register (baud_r). i 2 c block uses the clock generated by dividing system clock which is set in baud_r . additionally this clock is used to generate the scl clock which is eight-divided by internal clock. the default value is 4. assuming system clock is 29mhz, scl clock is 300khz and maximum scl frequency is 1.8mhz 7 6 5 4 3 2 1 0 baud_r bit name function 7:0 baud_r indicates the clock dividing value wh ose clock signal is used in internal operation internal clock frequency is (baud_r + 2) *2 and when it is set as 255, the internal clock is half- divided . 6 .5 i 2 c data register (data_r). data register is the 8bit read/write register which is used to send or receive data. internally this register consists of two registers, transmit register and receive register respectively. written data is transfer red to transmit register, and read data from receive register. in every phase, sda line is driven by transmit register and sda line is read by receive register. 7 6 5 4 3 2 1 0 data_r bit name function 7:0 data_r w ritten data is serially transmitted through the sda line, and sda line data is written in rec e ive register
154 GDC21D601 7. i 2 c module signal description the i 2 c module is connected to the apb bus. table 1 . signal descriptions describes the apb signals used and produced, table 1 . signal descriptions show s the non-amba signals from the block. table 1 . signal descriptions name type source/ destination description bnres i reset controller asb soft reset signal (active low). pa[3:2] i apb bridge this is part of the peripheral address bus, and is used by the peripheral for decoding its own register accesses. the addresses become valid before pstb goes to high and remain valid after pstb goes to low. pd[7:0] i/o apb peripherals this is the part of the bi - directional peripheral data bus. the data bus is driven by this block during read cycles (when pwrite is low). pstb i apb bridge this strobe signal is used to time all accesses on the peripheral bus. the falling edge of pstb is coincident with the falling edge of bclk (asb system clock). pwrite i apb bridge when this signal is high, it indicates a write to a peripheral, when this signal is low, it indicates a read from a peripheral. this signal has the same timing as the peripheral address bus. it becomes valid before pstb goes to high and remains valid after pstb goes to low. psel i apb bridge when this signal is high, it indicates the sspi module has been selected by the apb bridge. this selection is a decode of the system address bus. table 2 . specific block signal descriptions name type source / destination description sdain i pad serial data input. sdaout o pad serial data output. sclin i pad serial clock in sclout o pad serial clock output i 2 cirq o interrupt controller active high interrupt request
155 GDC21D601 8. hardware interface the apb interface is fully apb-compliant. the apb is a non pipelined low-power interface, designed to provide a simple interfacing to slave peripherals. b_clk p_sel p_write p_stb p_d p_a register address data data figure 2 . apb read b_clk p_sel p_write p_stb p_d p_a register data address data figure 3 . apb write
156 GDC21D601 9. register memory map the base address of the i 2 c interface is 0xffff f900(channel0), 0xffff fa000(channel1), and 0xffff fb00(channel2), the offset of any particular register from the base address is determined. address read location write location i 2 c base baud_r i 2 c base + 0x04 ctrl_r i 2 c base + 0x08 data_r data_r i 2 c base + 0x0c stat_r i 2 c base + 0x10 addr_r i 2 c base + 0x14 test_r test_r i 2 c register memory map
157 GDC21D601 section 18. direct memory access controller 1. general description this chip includes a 2- channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high speed data transfers among external devices equipped ; , external memories, memory-mapped external devices. using the dmac reduces the burden on the cpu and increases operating efficiency of the mcu . the features of the dma controller are listed below : two channels with identical function four gigabytes of address space m ax . 256 kbytes transfer data transfer unit : byte, half-word, w ord bus mode : burst mode, exception mode (cycle steal mode ) two kinds of address mode s - single address mode - dual address mode two types of transfer request source s - external i/o request - auto request two kind s of fixed priorit ies for channels - channel 1 ? s priority > channel 0 ? s priority - channel 0 ? s priority > channel 1 ? s priority cpu can be interrupted when the specified number of data transfers are complete d. figure 1 . dmac top block diagram dma controller areq agnt bprot[1:0] btran[1:0] asb interface registers control block bnres bclk bsize[1:0] blok ba[31:0] bd[31:] bwrite dsel trendint bwait beror blast ndmack [1:0] ndmareq [1:0] dmatrans
158 GDC21D601 2 . signal description table 1 . dma controller signal descriptions name type description bclk i amba system bus clock. this clock times all bus transfers. the clock has two distinct phases - phase 1 w h ere bclk is low, and phase 2 wh ere bclk is high. bnres i this signal indicate s the reset status of the bus. ba[31:0] i / o asb address. output for dmac operation. input for register access. bd[31:0] i / o this is the part of b i - directional system data bus. areq o request signal for asb bus mastership. agnt i bus grant signal from asb arbiter. berror i / o asb error signal. blast i / o asb break burst signal from dram controller. block o asb locked transfer signal bprot[1:0] o asb master protection information. bsize[1:0] o asb transaction size signal. btran[1:0] o asb transaction type signal. bwait i / o asb wait transfer signal. input for dma cycle stretch. out for register access. bwrite i / o asb transfer direction signal dsel i register select signal n dmar eq [1:0] i dma transfer request signal from the external i/o device . these are connected to ndmareq[1:0] pins ndma ck [1:0] i dma transfer acknowledge signal to the external i/o device . these are connected to ndmaack[1:0] pins. dmatrans o indicate the dram access during dma transfer. this signal connected to dram controller. trendint o dma transfer end interrupt signal to cpu
159 GDC21D601 3 . programmer ? s model 3.1 memory map the base address es for the dmac ? s registers are not fixed and may be different for any particular system implementation. the base address of the dmac ? s register is 0xffffee00. however, the offset of any particular dmac ? s register from the base address is fixed. table 2 . external signal d escriptions abbreviation addr. offset name r/w initial value sar0 h ? 00 source address register for channel 0 r/w h ? 00000000 dar0 h ? 04 destination address register for channel 0 r/w h ? 00000000 tnr0 h ? 08 transfer number register for channel 0 r/w h ? 00001111 ccr0 h ? 0c channel control register for channel 0 r/w h ? 00000000 sar1 h ? 10 source address register for channel 1 r/w h ? 00000000 dar h ? 14 destination address register for channel 1 r/w h ? 00000000 tnr1 h ? 18 transfer number register for channel 1 r/w h ? 00001111 ccr1 h ? 1c channel control register for channel 1 r/w h ? 00000000 tstr0 h ? 20 test register 0 r/w h ? 00000000 tstr1 h ? 24 test register 1 r h ? 00000000 tstr2 h ? 28 test register 2 r h ? 00000000 dmaor h ? 2c dma operation register r/w h ? 00000000 3.2 source address register 0,1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit sab31 sab30 sab29 sab28 sab27 sab26 sab25 sab24 sab23 sab22 sab21 sab20 sab19 sab18 sab17 sab16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit sab 15 sab14 sab 13 sab 12 sab 11 sab 10 sab 9 sab 8 sab 7 sab 6 sab 5 sab 4 sab 3 sab 2 sab 1 sab 0 figure 2. source address register 3.3 destination address register 0, 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit dab31 dab30 dab29 dab28 dab27 dab26 dab25 dab24 dab23 dab22 dab21 dab20 dab19 dab18 dab17 dab16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit dab 15 dab14 dab 13 dab 12 dab 11 dab 10 dab 9 dab 8 dab 7 dab 6 dab 5 dab 4 dab 3 dab 2 dab 1 dab 0 figure 3. destination address register
160 GDC21D601 3.4 transfer number register 0, 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit tnb1 5 tnb 14 tnb 13 tnb 12 tnb 11 tnb 10 tnb 9 tnb 8 tnb 7 tnb 6 tnb 5 tnb 4 tnb 3 tnb 2 tnb 1 tnb 0 figure 4. transfer number register 3.5 channel control register 0, 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 14~12 11 10 9 8 7 6 - 5 4 3 2 1 0 bit dramacc acklen dadrm sadrm tsize1 tsize0 rev. rtype[1:0] areq tbusm tendfl intren chen figure 5. channel control register table 3 . channel control register bit init. value name description 15 0 dramacc indicate to the dram controller during dma transfer 0 : not dram access 1 : dram access 14 ~ 12 0 00 acklen enlarge the low phase of the dmack signal for single address transfer 11 0 dadrm destination addressing mode 0 : fixed addressing 1 : increment al addressing 10 0 sadrm source addressing mode 0 : fixed addressing 1 : increment al addressi n g 9 ~ 8 00 tsize[1:0] transfer size 00 : byte 01 : half-word 10 : word 11 : reserved 6 ~ 5 00 rtype[ 1 :0] dma request resource select ing 00 : memory space to memory space 01 : memory space to external io device 10 : external io device to memory space o thers : reserved 4 0 atreq auto request enable 3 0 tbusm transfer bus mode 0 : burst 1 : cycle-steal mode 2 0 tendfl transfer end flag 0 : incomplete transfer 1 : complete transfer write 1 to clear this flag bit 1 0 intren dma transfer complete interrupt enable 0 : interrupt disable 1 : interrupt enable 0 0 chen channel mode 0 : channel disable 1 : channel enable others 0 reserved
161 GDC21D601 3.6 test register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit -- -- -- -- -- -- -- -- -- -- -- tcin1 tcin0 treq1 treq0 tmen figure 6. test register 0 table 4 . test register 0 bit init. value name description 4 0 tcin1 c arry-in bit of c hannel 1 counter 0 : carry-in is not occurred 1 : carry-in is occurred 3 0 tcin0 c arry-in bit of c hannel 0 counter 0 : carry-in is not occurred 1 : carry-in is occurred 2 0 treq1 dmac request bit of channel 1 0 : request is not occurred 1 : request is occurred 1 0 treq0 dmac request bit of channel 0 0 : request is not occurred 1 : request is occurred 0 0 tmen test mode enable bit 0 : test mode is not enable 1 : test-mode is enable others 0 reserved 3.7 test register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit ta31 ta30 ta29 ta28 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 ta19 ta18 ta17 ta16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit ta 15 ta14 ta 13 ta 12 ta 11 ta 10 ta 9 ta 8 ta 7 ta 6 ta 5 ta 4 ta 3 ta 2 ta 1 ta 0 figure 7. test register 1 table 5 . test register 1 bit init. value name description 31 ~ 0 0 ta[31:0] latches ba[31:0] signal when tmen bit of test register 0 is high
162 GDC21D601 3. 8 test register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit -- -- -- -- -- -- -- -- -- -- btran1 btran0 bsize1 bsize0 areq bwrite figure 8. test register 2 table 6 . test register 2 bit init. value name description 5 ~ 4 00 btran[1:0] latches btran signal 3 ~ 2 00 bsize[1:0] latches bsize signal 1 0 areq latches areq signal 0 0 bwrite latches bwrite signal others 0 reserved 3.9 dma operation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- priom dmaen figure 9. dma operation register table 7 . dma operation register bit init. value name description 1 0 priom channel priority level selection bit 0 : ch0 > ch1 1 : ch1 > ch0 0 0 dmaen dmac operation enable bit 0 : dmac is not enabled 1 : dmac is enabled others 0 reserved
163 GDC21D601 4 . address modes 4.1 dual address mode the dual address mode of dmac are described in the figure. 10. the source and destination area can be external memory, internal sram, and external memory mapped i/o device. in dual address mode, both the transfer source and the destination are accessed by an address. dma controller read the data source device and store temporarily in temp register in dmac. and then transfer this data destination device. so read and write transactions are performed in one data transfer. figure 12 . show s the dma transfer timing in the dual address mode. the example of the register setting for dual address mode is following that : 1) set source address register (sar). in this register you write the source area address. 2) set destination address register (dar). in this register you write the destination area address. 3) set transfer number register (tnr). in this register you can write the transfer number value. 4) set channel control register (ccr). in this register you should write properly the control value. rtype[1:0] field value are should be ? 00 ? , and daram, sadrm fields should be ? 1 ? . you should set the tsize[1:0] field properly by the transferred data width. and you must set the chen field to ? 1 ? . intren field are set by your need. 5) finally set dmaen field to ? 1 ? in dma operation register (dmaor). if you set autoreq field in ccr, as soon as set dmaen field, dma transfer the data. figure 11. show the timing diagram of dma transfer when ccr value is 0x0d13. note) in the end of dma transfer, dma controller is initialized by clearing the tendfl field in ccr. this can be performed by writing ? 1 ? value in this field. figure 10. dmac dual address mode block diagram dmac temp internal / external memory space internal / external memory space (1) read (2) write internal of mcu data/address/control
164 GDC21D601 figure 11. transfer timing in dual address mode (memory space t o memory space) bclk areq agnt ba[31:0] bwrite bd[31:0] data source address destination address a n btran[1:0] xa[12:0] row address row address s s n col address col address ras cas xd[15:0] data data ndramoe ndramwe n a
165 GDC21D601 4.2 single address mode the single address mode of dmac are described in the figure 12. in single address mode, there are two types of transfer, one is memory-to-i/o device that source is memory area and destination is external i/o device, and the other is external i/o device ? to-memory that source is i/o device and destination is memory area. single address transfer mode is composed of only one data transaction, so it is very fast to transfer the data comparing with dual addres mode in which composed of 2 transactions : read transaction and write transactio. the i/o device is acessed by ndreq and ndack signals. ndack signals are controlled by the acklen field in ccr. and ndack signals are coincident with the ras and cas signals from dram controller. when memory is dram, you must set properly the control flags in the control register in dram controller and dma controller. the example of the register setting for memory-to-i/o device transfer in single address mode is following that : 1) set source address register (sar). in this register you write the source area address. 2) set destination address register (dar). in this register you write the destination area address. 3) set transfer number register (tnr). in this register you write the transfer number value. 4) set channel control register (ccr). in this register you should write properly the control value. when data transfer is the memory space to external i/o devices, rtype[1:0] field value are should be ? 01 ? , and daram field is should be ? 0 ? , and sadrm fields should be ? 1 ? . you should set the tsize[1:0] field properly by the transferred data width. and you must set the chen field to ? 1 ? . intren field are set by your need. 5) finally set dmaen field to ? 1 ? in dma operation register (dmaor). if you set autoreq field in ccr, as soon as set dmaen field, dma transfer the data. figure 13 shows the timing diagram of the memory-to-i/o device transfer when ccr value is 0x0523. figure 14 shows the timing diagram of the timing diagram of the i/o device-to-memory transfer when ccr value is 0x0943. in these case the contents of the control register for dram in dram controller is 0x69. in the end of dma transfer, dma controller is initialized by clearing the tendfl field in ccr. this can be performed by writing ? 1 ? value in this field. figure 1 2. dmac single address mode block diagram dmac temp internal / external memory space internal / external i/o module internal of mcu data address/control ndack ndreq
166 GDC21D601 figure 1 3. transfer timing in single burst address mode (memory space t o i/o device w ith n dmack ) figure 1 4. transfer timing in single burst address mode (i/o device w ith n dmack t o memory space) bclk areq agnt ba[31:0] bwrite address n address n+1 a btran[1:0] xa[12:0] row address col address n+1 s col address n col address n+2 ras cas xd[15:0] data n data n+2 ndramoe ndramwe n ndreq ndack address n+2 n data n+1 bclk areq agnt ba[31:0] bwrite address a btran[1:0] xa[12:0] row address col address n+1 s col address n col address n+2 ras cas xd[15:0] data n data n+2 ndramoe ndramwe n ndreq ndack n data n+1
167 GDC21D601 section 19. debug and test interface 1. general description the GDC21D601 has built-in features which enable debug and test in a number of different contexts. firstly, there are circuit structures to help with software development. secondly, the device contains boundary scan cells for circuit board test. finally, the device contains some special test modes which enable the generation production patterns for the device itself . 2 . s oftware development debug and test interface the arm720t core and numerous peripherals i mplemented inside GDC21D601 contain hardware extensions for advanced debugging features. these are intended to ease user development and debugging of application software, operating systems, and the hardware itself. full details of the debug interfaces and their programming can be found in arm720t data sheet (arm ddi-0087). the multiice product enables the arm720t to be debugged in one environment. refer to guide to multiice (arm dui-0048). 3. test access port and boundary scan GDC21D601 contains full boundary scan on its inputs and outputs to help with circuit board test. this supports both intest and extest, allowing patterns to be applied serially to the GDC21D601 when fixed in a board and for full circuit board connection respectively. the boundary-scan interface conforms to the ieee std. 1149.1- 1990, standard test access port and boundary-scan architecture. (please refer to this standard for an explanation of the terms used in this section and for a description of the tap controller states.) the boundary-scan interface provides a means of testing the core of the device when it is fitted to a circuit board, and a means of driving and sampling all the external pins of the device irrespective of the core state. this latter function permits testing of both the device ?s electrical connections to the circuit board, and (in conjunction with other devices on the circuit board having a similar interface) testing the integrity of the circuit board connections between devices. the interface intercepts all external connections within the device, and each such ?c ell?is then connected together to form a serial register (the boundary scan register). the whole interface is controlled via 5 dedicated pins: tdi , tms , tck , ntrst and tdo . full details of the debug interfaces and their programming can be found in arm720t data sheet (arm ddi- 0087 e, section 8 debug architecture ).
168 GDC21D601 3.1 reset the boundary-scan interface includes a state-machine controller (the tap controller). a pulldown resistor is included in the ntrst pad which holds the tap controller state machine in a safe state after power up. in order to use the boundary scan interface, ntrst should be driven high to take the tap state machine out of reset. the action of reset (either a pulse or a dc level) is as follows: * system mode is selected (i.e. the boundary scan chain does not intercept any of the signals passing between the pads and the core). * idcode mode is selected. if tck is pulsed, the contents of the id register will be clocked out of tdo . note : the tap controller inside arm7201 contains a scan chip register which is reset to the value b0011 thus selecting the boundary scan chain. if this register is programmed to any value other than b0011, then it must be reprogrammed with b0011 or a reset applied before boundary scan operation can be attempted. 3.2 pullup resistors the ieee 1149.1 standard requires pullup resistors in the input pins. however, to ensure safe operation an internal pulldown is present in the ntrst pin and therefore will have to be driven high when using this interface. table 1 . internal resistors for input pins pin internal resistor tclk pullup ntrst pulldown tms pullup tdi pullup
169 GDC21D601 section 20. electrical ratings 1. absolute maximum ratings 2. thermal characteristics 3. d.c electrical characteristics
170 GDC21D601 apendix a. register map the following diagram shows system memory map of GDC21D601. figure 1. system memory map chip select area asb register apb register 0 xffff ffff 0 xffff e000 0 xffff f000 0 x0000 0000 0 x0800 0000 memory area 0 xffff ffff reserved f900 f800 f500 f400 f300 f200 f100 f000 ef00 ee00 ed00 ec00 eb00 ssi uart0 wdt timer pmu intc pio arm7 test reg dmac dramc smi mcuc 0 xffff eaff reserved 0 x4000 0000 0 x3000 0000 0 x2000 0000 0 x1000 1000 0 x1000 0000 0 x0800 0000 0 x0700 0000 0 x0600 0000 0 x0500 0000 0 x0400 0000 0 x0300 0000 0 x0200 0000 0 x0100 0000 0 x0000 0000 dram bank #1 dram bank #0 window area on-chip ram window area ncs7 ncs6 ncs5 ncs4 ncs3 ncs2 ncs1 ncs0 fc00 rtc i2c0 uart1 uart2/smart i2c1 i2c2 f600 f700 fa00 fb00 fd00 0 x5000 0000 0 x6000 0000 reserved
171 GDC21D601 dma controller registers (@ 0xffff ee 00 ) a bbreviation address descriptions r/w initial value sar0 0xffffee00 source address register for channel 0 r/w 32h ? 00000000 dar0 0xffffee0 4 destination address register for channel 0 r/w 32h ? 00000000 tnr0 0xffffee0 8 transfer number register for channel 0 r/w 32h ? 00001111 ccr0 0xffffee0 c channel control register for channel 0 bit 15 : dram access indicator 0: not dram 1: dram transfer bit 14-12 : dmack low length bit 11 : destination addressing mode 0: fixed 1: incremental addressing bit 10 : source addressing mode 0: fixed 1: incremental addressing bit 9-8 : transfer size 00:byte 01:half-word 10:word 11:reserved bit 7 : reserved bit 6-5 : dma request mode 00 : mem . space to mem . space 01 : mem .external io device 10 : ext . io device to mem . 11 : reserved bit 4 : auto request enable bit 3 : transfer bus mode 0:burst 1:cycle-steal mode bit 2 : transfer end flag 0:incomplete 1: complete bit 1 : transfer complete interrupt enable 0: disabled 1: enabled bit 0 : channel control 0: ch 0 disabled 1: ch 0 enabled r/w 32h ? 00000000 sar1 0xffffee1 0 source address register for channel 1 r/w 32h ? 00000000 dar 0xffffee 14 destination address register for channel 1 r/w 32h ? 00000000 tnr1 0xffffee 18 transfer number register for channel 1 r/w 32h ? 00001111 ccr1 0xffffee 1c channel control register for channel 1 r/w 32h ? 00000000 tstr0 0xffffee 20 test register 0 r/w 32h ? 00000000 tstr1 0xffffee2 4 test register 1 r 32h ? 00000000 tstr2 0xffffee 28 test register 2 r 32h ? 00000000 dmaor 0xffffee 2c dma operation register bit 7-2 : reserved bit 1: channel priority level select 0: ch0 > ch1 1: ch0 < ch1 bit 0 : dmac operation control 0: enabled 1: disabled r/w 32h ? 00000000
172 GDC21D601 d ram controller registers(@0xffffed00) a bbreviation address descriptions r/w initial value dramrcr 0xffffed00 dram refresh control register bit 15-8: refcnt (dram refresh clock divisor) refclock = bclk / refcnt bit 7 : dram refresh clock control 0 / 1 = disabled / enabled bit 6-0 : refdiv(dram refresh rate) frequency (khz) = 2*[refclock /(rfdiv + 1) ] w 16h ? 0000 dramconcpu 0xffffed04 dram controller for cpu bit 15-7: reserved bit 6: dmaen(dma control signal ) 0 / 1 = dma disabled / enabled bit 5: trp( t rp = |ras-cas| ) bit 4 : tcp(t cp = |low phase of cas|) bit 3-2: wait count 00: 0-wait 01: 1-wait 10: 2-wait 11: 3-wait bit 1-0: bank size 00 : byte 01 : half-word 10 : word 11 : reserved r/w 7b ? 0000000 dramcdma 0xffffed08 dram controller for dma bit 15-6: reserved bit 5: trp( t rp = |ras-cas| ) bit 4 : tcp(t cp = |low phase of cas|) bit 3-2: wait count 00: 0-wait 01: 1-wait 10: 2-wait 11: 3-wait bit 1-0: bank size 00 : byte 01 : half-word 10 : word 11 : reserved r/w 6b ? 000000
173 GDC21D601 d ram controller registers(@0xffffed00) -- continued a bbreviation address descriptions r/w initial value dramtcr 0xffffed0c dram test control register bit 15-4: reserved bit 3: testinc(test increment) column address auto increment 0 / 1 = disabled / enabled bit 2: forceadv forces refresh counter by bclk 0 / 1 = disabled / enabled bit 1-0: force size 00 : byte 01 : half-word 10 : word (default) 11 : reserved w 4b ? 0010
174 GDC21D601 static memory controller registers (@ 0xffff f 0 00 ) a bbreviation address descriptions r/w initial value memory configuration register 1 ncs1 area control bit 31-30: reserved bit 29: exprdy polarity (0:active high) bit 28: control signal type 0/1=arm type / motorola type: bit 27: flashon ? reserved bit 26: expansion clock enable bit 25-24: mem width 00: 32-bit memory 01: 16-bit memory 10: 8-bit memory 11: reserved bit 23: burst mode enable ? reserved bit 22-20: burst wait cycle ? reserved bit 19-16: access wait cycle(1~16cycles) 0000(1 cycle) ~ 1111(16 cycles) 32 ? h0000000 4 0 : default 1 cycle memcfg1 0xffffec00 ncs0 area control bit 15-14: reserved bit 13: exprdy polarity (0:active high) bit 12: control signal type 0/1=arm type / motorola type: bit 11: flashon ? reserved bit 10 : expansion clock enable bit 9-8: mem width 00: 32-bit memory 01: 16-bit memory 10: 8-bit memory 11: reserved bit 7: burst mode enable ? reserved bit 6-4: burst wait cycle ? reserved bit 3-0: access wait cycle(1~16cycles) 0000(1 cycle) ~ 1111(16 cycles) r/w 4 : default 5 cycles
175 GDC21D601 static memory controller registers (@ 0xffff f 0 00 ) -- continued a bbreviation address descriptions r/w initial value memory configuration register 2 ncs3 area control bit 31-30: reserved bit 29: exprdy polarity (0:active high) bit 28: control signal type 0/1=arm type / motorola type bit 27: flashon ? reserved bit 26: expansion clock enable bit 25-24: mem width 00: 32-bit memory 01: 16-bit memory 10: 8-bit memory 11: reserved bit 23: burst mode enable ? reserved bit 22-20: burst wait cycle ? reserved bit 19-16: access wait cycle(1~16cycles) 0000(1 cycle) ~ 1111(16 cycles) 32 ? h0000000 0 default 1 cycle memcfg2 0xffffec0 4 ncs2 area control bit 15-14: reserved bit 13: exprdy polarity (0:active high) bit 12: control signal type 0/1=arm type / motorola type: bit 11: flashon ? reserved bit 10 : expansion clock enable bit 9-8: mem width 00: 32-bit memory 01: 16-bit memory 10: 8-bit memory 11: reserved bit 7: burst mode enable ? reserved bit 6-4: burst wait cycle ? reserved bit 3-0: access wait cycle(1~16cycles) 0000(1 cycle) ~ 1111(16 cycles) r/w default 1 cycle memcfg3 0xffffec0 8 memory configuration register 3 ncs4,3 area controls r/w 32 ? h0000000 0 memcfg4 0xffffec0 c memory configuration register 4 ncs6,5 area controls r/w 32 ? h0000000 0
176 GDC21D601 mcu controller registers (@ 0xffff ec 00 ) a bbreviation address descriptions r/w initial value mcuc 0xffffeb00 mcu control register r/w 8h ? 00 pinmux_pa 0xffffeb0 4 port a mux register (port a[5:0]) r/w 8h ? 00 pinmux_pb 0xffffeb0 8 port b mux register (port b[7:0]) r/w 8h ? 00 pinmux_pc 0xffffeb0 c port c mux register (port c[7:0]) r/w 8h ? 00 pinmux_pd 0xffffeb10 port d mux register (port d[7:0]) r/w 8h ? 00 pinmux_pe 0xffffeb14 port e mux register (port e[7:0]) r/w 8h ? 00 pinmux_pf 0xffffeb18 port f mux register (port f[7:0]) r/w 8h ? 00 pinmux_pg 0xffffeb1 c port g mux register (port g[7:0]) r/w 8h ? 00 pinmux_ph 0xffffeb20 port h mux register (port h[7:0]) r/w 8h ? 00 pinmux_pi 0xffffeb24 port i mux register (port i[7:0]) r/w 8h ? 00 pinmux_pj 0xffffeb28 port j mux register (port j[7:0]) r/w 8h ? 00 mcudc 0xffffeb2 c mcu device code register r 24h ? lg601 drampdack 0xffffeb30 dram power down ack r 8h ? 00 drampdreq 0xffffeb34 dram power down request r/w 8h ? 00
177 GDC21D601 pmu register s (@ 0xffff f 0 00 ) a bbreviation address descriptions r/w initial value pmucr 0xfffff000 pmu control register only following values are effective. 0x00 := clear pmu status register 0x03 := enters the power down mode pmu status register bit 7-6: reserved bit 5-4: previous reset status 00 : power-on reset status 01 : s/w reset state by pmu 10 : s/w manual reset by wdt 11 : wd overflow reset state by wdt bit 3-2: current status flag bits 00 : running state after npor 01 : running state after wd_of 10 : running state after man_reset 11 : reserved bit 1-0: previous status flag bits 00 : start state after npor 01 : start state after wd_of 10 : start state after man_reset 11 : start state after pd mode w r 8h ? 00 bclkcr 0xfffff00 4 bclk frequency selection and bus mode control(standard / fast bus mode) bit 7-4: reserved bit 3: fclk control bit 0 ? fast-bus mode (not use the fclk) 1 ? standard-bus mode use fclk as sys_clk bit 2-0: bclk selection bits 000 : bclk = sys_clk / 2 001 : bclk = sys_clk / 4 010 : bclk = sys_clk / 8 011 : bclk = sys_clk / 16 100 : bclk = sys_clk / 32 101 : bclk = sys_clk / 64 110 : bclk = sys_clk / 128 111 : bclk = sys_clk. r/w 8h ? 00
178 GDC21D601 pmu register s (@ 0xffff f 0 00 ) -- continued a bbreviation address descriptions r/w initial value bclk msk _run 0xfffff00 8 bclk masking controls register in the run mode. enable / disable clock : 1/0 bit 15-13 : reserved bit 12 : apb bridge clock control bit 11 : bus controller clock control bit 10 : dram controller clock control bit 9 : dma controller clock mask bit bit 8 : test controller clock mask bit bit 7 : sram clock mask bit bit 6-1 : reserved bit 0 : b_clk out mask bit r/w 16h ? ffff bclkmsk_pd 0xfffff00 c bclk controls register ( pd mode. ) enable / disable clock : 1/0 bit 15 : arm7tdmi core clock control bit 14 : amba arbiter clock control bit 13 : amba decoder clock control bit 12 : apb bridge clock control bit 11 : bus controller clock control bit 10 : dram controller clock control bit 9 : dma controller clock control bit 8 : test controller clock control bit 7 : sram clock control bit 6-1 : reserved bit 0 : b_clk out control r/w 16h ? 0000 remap 0xfffff010 remap register r/w 8h ? 00 pclkcr 0xfffff014 pclk control register bit 7-3 : reserved bit 2-0: pclk selection 000 : pclk = external pclk source 001 ? pclk = sclk / 2 010 ? pclk = sclk / 4 011 ? pclk = sclk / by 8 100 ? pclk = sclk / 16 101 ? pclk = sclk / 32 110 ? pclk = sclk / 64 111 ? pclk = sclk / 128 r/w 8h ? 00
179 GDC21D601 pmu register s (@ 0xffff f 0 00 ) -- continued a bbreviation address descriptions r/w initial value pclk msk _run 0xfffff018 pclk control register in run mode. enable / disable clock : 1/0 bit 9 : watchdog timer clock control bit 8 : i 2 c 2 clock control bit 7 : i 2 c 1 clock control bit 6 : i 2 c 0 clock control bit 5 : sspi 1 clock control bit 4 : sspi 0 clock control bit 3 : uart 2/ smic clock control bit 2 : uart 1 clock control bit 1 : uart 0 clock control bit 0 : timer clock control r/w 10h ? 11ff pclkmsk_pd 0xfffff01 c pclk control register in pd mode. enable / disable clock : 1/0 bit 9 : watchdog timer clock control bit 8 : i 2 c 2 clock control bit 7 : i 2 c 1 clock control bit 6 : i 2 c 0 clock control bit 5 : sspi 1 clock control bit 4 : sspi 0 clock control bit 3 : uart 2/ smic clock control bit 2 : uart 1 clock control bit 1 : uart 0 clock control bit 0 : timer clock control r/w 8h ? 00 reserved 0xfffff020 reserved r/w 8h ? 00 rstcr 0xfffff030 reset control register manual / normal reset : 1 / 0 bit 7-1 : reserved bit 0 : manual reset control r/w 8h ? 00 tstcr 0xfffff040 tic test mode and pmu test control register normal operation / tic-pmu test : 1 / 0 bit 7-2 : reserved bit 1 : tic test mode when set to 1 bit 0 : pmu test mode when set to 1 r/w 8h ? 00 device code 0xfffff044 reserved r $lg601 tstr0 0xfffff048 test write register for external input signals bit 7-3 : reserved bit 2 : test bit for int_req_in input bit 1 : test bit for wd_of_in input bit 0 : test bit for man_reset input r 8h ? 00
180 GDC21D601 pmu register s (@ 0xffff f 0 00 ) -- continued a bbreviation address descriptions r/w initial value tstr1 0xfffff04c test read register for clocks of asb devices and reset signals bit 15 : test bit for bclk_wdt bit 14 : test bit for pclk_ i 2 c 2 bit 13 : test bit for pclk_ i 2 c 1 bit 12 : test bit for pclk_ i 2 c 0 bit 11 : test bit for pclk_sspi 1 bit 10 : test bit for pclk_sspi 0 bit 9 : test bit for pclk_uart 2 bit 8 : test bit for pclk_uart 1 bit 7 : test bit for pclk_uart 0 bit 6 : test bit for bclk_timer bit 5 : test bit for b_resetn bit 4 : test bit for p_resetn0 bit 3 : test bit for p_resetn1 bit 2 : test bit for p_resetn bit 1 : test bit for wd_of_out bit 0 : test bit for remap r 16h ? 0000
181 GDC21D601 watchdog timer register (@ 0xffff f100 ) a bbreviation address descriptions r/w initial value wdtc 0xfffff100 watchdog timer control register bit 7: interrupt request 0 / 1 = interrupt dis able / enable bit 6: timer mode select 0 / 1 = interval / watchdog bit 5: timer control 0 / 1 = disable / enable bit 4: wd reset control 0 / 1 = disable / enable bit 3: reset select (if wd overflowed) 0 / 1 = por / manual reset bit 2-0: clock select 000 = cks0 / 2 001 = cks1 / 8 010 = cks2 / 32 011 = cks2 / 64 100 = cks2 / 256 101 = cks2 / 512 110 = cks2 / 2048 111 = cks2 / 8192 r/w 8b ? 00000000 wdts 0xfffff10 4 watchdog timer reset status register bit 1: itovf(internal timer overflowed) bit 0: wtovf(wd timer overflowed) r 2b ? 00 wdtcnt 0xfffff10 8 watchdog timer counter register r/w 8h ? 00 wdtest 0xfffff10c watchdog timer test input register r/w 8h ? 00 wdtesto 0xfffff114 watchdog timer test output register r/w 8h ? 00 rtc control register (@ 0xffff f300 ) a bbreviation address descriptions r/w initial value rtcdr 0xfffff300 rtc d ata r egister r/w 0x00 rtcmr 0xfffff30 4 rtc m atch r egister r/w 0x00 rtcs 0xfffff30 8 rtc status r 0x00 rtcdv 0xfffff30 c rtc clock divider r/w 0x00 rtccr 0xfffff310 rtc control register r/w 0x00 rtcts 0xfffff314 rtc t ic s election r egister w 0x00 rtctic32k 0xfffff318 ticclk32k w 0x00 rtcticpclk 0xfffff31 c ticclkpclk w 0x00
182 GDC21D601 interrupt controller register (@ 0xffff f200 ) a bbreviation address descriptions r/w initial value intc 0xfffff200 interrupt control/mask register int25 : swi(software interrupt) int24 : timer 5 int23 : timer 4 int22 : timer 3 int21 : timer 2 int20 : timer 1 int19 : timer 0 int18 : sspi 1 int17 : sspi 0 int16 : smart card interface int15 : uart 1 int14 : uart 0 int13 : i 2 c 2 int12 : i 2 c 1 int11 : i 2 c 0 int10: wdt(watchdog timer) int9 : rtc(real time clock) int8 : dma(direct memory access) int7 : com rx int6 : com tx int5 : external interrupt 5 int4 : external interrupt 4 int3 : external interrupt 3 int2 : external interrupt 2 int1 : external interrupt 1 int0 : external interrupt 0 r/w 26h ? 3 ffffff intmd 0xfffff20 4 interrupt trigger m ode control r/w 26h ? 2000000 interrupt trigger polarity control register . mode polarity triggered by 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level intpol 0xfffff20 8 r/w 26h ? 2000000 intdir 0xfffff20 c interrupt direction control register (0 / 1 = request irq / fiq) r/w 26h ? 0000000 intfiqs 0xfffff210 fiq status flag register ( 0/1 = clear/set) r 26h ? 0000000 intirqs 0xfffff214 irq status flag register( 0/1 = clear/set) r 26h ? 0000000 intfiqmsk 0xfffff218 fiq mask register( 0/1 = clear/masked) r/w 26h ? 0000000 intirqmsk 0xfffff21 c irq mask register( 0/1 = clear/masked) r/w 26h ? 0000000 intscl 0xfffff220 interrupt status clear register 0 / 1 = clear / set w 26h ? 0000000 intticin 0xfffff240 tic input register r/w 0x00 intticout 0xfffff280 tic output register r/w 0x00
183 GDC21D601 general purpose timer unit control register (@ 0xfffff400 ) a bbreviation address descriptions r/w initial value tstartr 0xfffff400 timer start register bit 7-6 : reserved bit 5-0 : 1:start counting, 0:stop counting r/w 8b ? 11000000 tsyncr 0xfffff40 4 timer sync. register bit 7-6 : reserved bit 5-0 : 1:sync. mode, 0:normal mode r/w 8b ? 11000000 tpwmr 0xfffff408 timer pwm register(1=pwm,0=normal) bit 7-6 : reserved bit 5-0 : 1: pwm mode, 0:normal mode r/w 8b ? 11000000 tstinr 0xfffff40 c w tstoutr 0xfffff4 1 0 r tstmoder 0xfffff4 1 4 w tstintr 0xfffff4 18 r tcontr0 0xfffff4 2 0 timer 0 control register 8b ? 1xx11yyy xx : mode selection 00 : not cleared-free running mode 01 : cleared by gra(periodic mode) 10 : cleared by grb(periodic mode) 11 : cleared in sync w/ other sync. timer yyy : timer clock prescaler selection 000 : timer clock = bclk/2 001 : timer clock = bclk/4 010 : timer clock = bclk/16 011 : timer clock = bclk/64 100 : timer clock = ext_clk/2 101 : timer clock = ext_clk/4 110 : timer clock = ext_clk/64 111 : timer clock = ext_clk/2 r/w 8b ? 10011000 tiocr0 0xfffff4 24 timer 0 i/o control register 8b ? 1xxx1yyy xxx : grb function select 000 : compare match with no output 001 : output 0 when matched 010 : output 1 when matched 011 : output toggle when matched 100 : grb input captured at rising edge 101 : grb input captured at falling edge 110 : grb input captured at both edge yyy : gra function select 000 : compare match with no output 001 : output 0 when matched 010 : output 1 when matched 011 : output toggle when matched 100 : gra input captured at rising edge 101 : gra input captured at falling edge 110 : gra input captured at both edge r/w 8b ? 10001000
184 GDC21D601 general purpose timer unit control register (@ 0xfffff400 ) -- continued a bbreviation address descriptions r/w initial value tier0 0xfffff4 28 timer 0 interrupt enable register 8b ? 11111xyz x,y,z = 0 : disable interrupt x,y,z = 1 : enable interrupt x = 1 : interrupt by overflow y = 1 : interrupt by mcib z = 1 : interrupt by mcia r/w 8b ? 11111000 tstatusr0 0xfffff4 2c timer 0 status register 8b ? 11111xyz x (ovfi)=1 timer counter overflow/underflow occurred y(mcib) =1 grb input capture/compare match occurred z(mcia) =1 gra input capture/compare match occurred r 8b ? 11111000 tcount0 gra0 grb0 0xfffff4 3 0 0xfffff4 34 0xfffff4 38 timer 0 counter register timer 0 general data a register timer 0 general data b register r/w r/w r/w 16h ? 0000 16h ? 0000 16h ? 0000 tcontr1 tiocr1 tier1 tstatusr1 tcount1 gra1 grb1 0xfffff4 4 0 0xfffff4 44 0xfffff4 48 0xfffff4 4c 0xfffff4 5 0 0xfffff4 54 0xfffff4 58 timer 1 control register timer 1 i/o control register timer 1 interrupt enable register timer 1 status register timer 1 counter register timer 1 data a register timer 1 data b register r/w r/w r/w r r/w r/w r/w 8b ? 10011000 8b ? 10001000 8b ? 11111000 8b ? 11111000 16h ? 0000 16h ? 0000 16h ? 0000 tcontr2 tiocr2 tier2 tstatusr2 tcount2 gra2 grb2 0xfffff4 6 0 0xfffff4 64 0xfffff4 68 0xfffff4 6c 0xfffff4 7 0 0xfffff4 74 0xfffff4 78 timer 2 control register timer 2 i/o control register timer 2 interrupt enable register timer 2 status register timer 2 counter register timer 2 data a register timer 2 data b register r/w r/w r/w r r/w r/w r/w 8b ? 10011000 8b ? 10001000 8b ? 11111000 8b ? 11111000 16h ? 0000 16h ? 0000 16h ? 0000 tcontr3 tiocr3 tier3 tstatusr3 tcount3 gra3 grb3 0xfffff4 8 0 0xfffff4 84 0xfffff4 88 0xfffff4 8c 0xfffff4 9 0 0xfffff4 94 0xfffff4 98 timer 3 control register timer 3 i/o control register timer 3 interrupt enable register timer 3 status register timer 3 counter register timer 3 data a register timer 3 data b register r/w r/w r/w r r/w r/w r/w 8b ? 10011000 8b ? 10001000 8b ? 11111000 8b ? 11111000 16h ? 0000 16h ? 0000 16h ? 0000 tcontr4 tiocr4 tier4 tstatusr4 tcount4 gra4 grb4 0xfffff4 a 0 0xfffff4 a4 0xfffff4 a8 0xfffff4 ac 0xfffff4 b0 0xfffff4 b4 0xfffff4 b8 timer 4 control register timer 4 i/o control register timer 4 interrupt enable register timer 4 status register timer 4 counter register timer 4 data a register timer 4 data b register r/w r/w r/w r r/w r/w r/w 8b ? 10011000 8b ? 10001000 8b ? 11111000 8b ? 11111000 16h ? 0000 16h ? 0000 16h ? 0000
185 GDC21D601 pio register (@ 0xffff fc00 ) a bbreviation address descriptions r/w initial value padr 0xfffff c00 p ort a d ata register at power-on default, set as irq pins. irq[5:0] when pinmux_pa[5:0 ] = 0 pioa[5:0] when pinmux_pa[5:0 ] = 1 pa[7:6] is always set to pio r/w 8b ? 00000000 paddr 0xfffff c04 port a direction control register 1: input port 0: output port r/w 8b ? 00000000 pbdr 0xfffff c08 p ort b d ata register at power-on default, set as timerout pins. timer out when pinmux_pb[7:0 ] = 0 piob[7:0] when pinmux_pb[7:0 ] = 1 r/w 8b ? 00000000 pbddr 0xfffff c0c port b direction control register 1: input port 0: output port r/w 8b ? 00000000 pcdr 0xfffff c10 p ort c d ata register at power-on default, set as timerin pins. timer in when pinmux_pc[7:0 ] = 0 pioc[7:0] when pinmux_pc[7:0 ] = 1 r/w 8b ? 00000000 pcddr 0xfffff c14 port c direction control register 1: input port 0: output port r/w 8b ? 00000000 pddr 0xfffff c18 p ort d d ata register at power-on default, set as uart pins nri when pinmux_pd[7] = 0 ndcd when pinmux_pd[6] = 0 ndsr when pinmux_pd[5] = 0 ncts when pinmux_pd[4] = 0 txd1 when pinmux_pd[3] = 0 rxd1 when pinmux_pd[2] = 0 txd0 when pinmux_pd[1] = 0 rxd0 when pinmux_pd[0] = 0 piod[7:0] when pinmux_pd[7:0 ] = 1 r/w 8b ? 00000000 pdddr 0xfffff c1c port d direction control register 1: input port 0: output port r/w 8b ? 00000000 pedr 0xfffff c20 p ort e d ata register at power-on default, set as sm/uart pins sclk0 when pinmux_pe[7] = 0 sout0 when pinmux_pe[6] = 0 sin0 when pinmux_pe[5] = 0 smclk when pinmux_pe[4] = 0 smdo when pinmux_pe[3] = 0 smdi when pinmux_pe[2] = 0 nrts when pinmux_pe[1] = 0 ndtr when pinmux_pe[0] = 0 pioe[7:0] when pinmux_pe[7:0 ] = 1 pioe[7:0] when pinmux_pe[7:0 ] = 1 r/w 8b ? 00000000 peddr 0xfffff c24 port e direction control register 1: input port 0: output port r/w 8b ? 00000000
186 GDC21D601 pio register (@ 0xffff fc00 ) -- continued a bbreviation address descriptions r/w initial value pfdr 0xfffff c28 p ort f d ata register at power-on default, set as sspi pins nirqout when pinmux_pf[7] = 0 nfiqout when pinmux_pf[6] = 0 bclkout when pinmux_pf[5] = 0 scs1 when pinmux_pf[4] = 0 sclk1 when pinmux_pf[3] = 0 sout1 when pinmux_pf[2] = 0 sin1 when pinmux_pf[1] = 0 scs0 when pinmux_pf[0] = 0 pioe[7:0] when pinmux_pf[7:0 ] = 1 pioe[7:0] when pinmux_pf[7:0 ] = 1 piof[7:0] when pinmux_pf[7:0 ] = 1 r/w 8b ? 00000000 pfddr 0xfffff c2c port f direction control register 1: input port 0: output port r/w 8b ? 00000000 pgdr 0xfffff c30 p ort g d ata register at power-on default, set as dma pins ras1 when pinmux_pg[7] = 0 ras0 when pinmux_pg[6] = 0 dack1 when pinmux_pg[5] = 0 dreq0 when pinmux_pg[4] = 0 smdo when pinmux_pg[3] = 0 smdi when pinmux_pg[2] = 0 nrts when pinmux_pg[1] = 0 ndtr when pinmux_pg[0] = 0 piog[7:0] when pinmux_pg[7:0 ] = 1 r/w 8b ? 00000000 pgddr 0xfffff c34 port g direction control register 1: input port 0: output port r/w 8b ? 00000000 phdr 0xfffff c38 p ort h d ata register at power-on default, set as dram pins cas[3:0] when pinmux_ph[3:0 ] = 0 pioh[3:0] when pinmux_ph[3:0 ] = 1 cs[7:4] when pinmux_ph[7:4 ] = 0 pioh[7:4] when pinmux_ph[7:4 ] = 1 r/w 8b ? 00000000 phddr 0xfffff c3c port h direction control register 1: input port 0: output port r/w 8b ? 00000000 pidr 0xfffff c40 p ort i d ata register at power-on default, set as dbus pins d[23:16] when pinmux_pi[7:0 ] = 0 pioi[7:0] when pinmux_pi[7:0 ] = 1 r/w 8b ? 00000000 piddr 0xfffff c44 port i direction control register 1: input port 0: output port r/w 8b ? 00000000 pjdr 0xfffff c48 p ort j d ata register at power-on default, set as dbus pins d[31:24] when pinmux_pj[7:0 ] = 0 pioj[7:0] when pinmux_pj[7:0 ] = 1 r/w 8b ? 00000000 pjddr 0xfffff c4c port j direction control register 1: input port 0: output port r/w 8b ? 00000000
187 GDC21D601 sspi register (@ 0xffff f 8 00 ) a bbreviation address descriptions r/w initial value sscr0a 0xfffff 800 sspi 0 control register a bit 7 : enters test mode when set to 0 bit 6 : cs is active high when set to 0 bit 5 : sspi 0 disabled when set to 0 bit 4 : slave mode when set to 0 bit 3 : lsb input first when set to 0 bit 2 : lsb out first when set to 0 bit 1 : rising edge clock when set to 0 bit 0 : slave: cs disabled when set to 0 r/w 8b ? 11111111 1: normal 1: active low 1: enabled 1: master 1: msb in 1: msb out 1: falling 1: cs enabled sscr0b 0xfffff 804 sspi 0 control register b bit 7 : tx interrupt enabled when set to 1 bit 6 : tx fifo empty interrupt enable bit 5 : rx fifo full interrupt enable bit 4 : tx fifo full interrupt enable bit 3 : rx fifo enabled when set to 1 bit 2 : tx fifo enabled when set to 1 bit 1 : rising edge clock when set to 0 bit 0 : slave: cs disabled when set to 0 r/w 8b ? 00000000 0: disable 0: disable 0: enabled 0: master 0: msb in 0: msb out 0: falling 0: cs enabled ssdr0 0xfffff 808 sspi 0 data register r/w 8b ? 11111111 sssr0 0xfffff 80c sspi 0 status register bit 7 : rx fifo empty bit 6 : tx fifo empty bit 5 : rx fifo full bit 4 : tx fifo full bit 3 : tx end bit 2 : reserved bit 1 : reserved bit 0 : sspi busy r 8b ? 00000000 sstr0 0xfffff 810 sspi 0 term register w 8b ? 11111111 sscr1a 0xfffff 820 sspi 1 control register a bit 7 : enters test mode when set to 0 bit 6 : cs is active high when set to 0 bit 5 : sspi 0 disabled when set to 0 bit 4 : slave mode when set to 0 bit 3 : lsb input first when set to 0 bit 2 : lsb out first when set to 0 bit 1 : rising edge clock when set to 0 bit 0 : slave: cs disabled when set to 0 r/w 8b ? 11111111 1: normal 1: active low 1: enabled 1: master 1: msb in 1: msb out 1: falling 1: cs enabled sscr1b 0xfffff 824 sspi 1 control register b bit 7 : tx interrupt enabled when set to 1 bit 6 : tx fifo empty interrupt enable bit 5 : rx fifo full interrupt enable bit 4 : tx fifo full interrupt enable bit 3 : rx fifo enabled when set to 1 bit 2 : tx fifo enabled when set to 1 bit 1 : rising edge clock when set to 0 bit 0 : slave: cs disabled when set to 0 r/w 8b ? 00000000 0: disable 0: disable 0: enabled 0: master 0: msb in 0: msb out 0: falling 0: cs enabled
188 GDC21D601 sspi register (@ 0xffff f 8 00 ) -- continued a bbreviation address descriptions r/w initial value ssdr1 0xfffff 828 sspi 1 data register r/w 8b ? 11111111 sssr1 0xfffff 82c sspi 1 status register bit 7 : rx fifo empty bit 6 : tx fifo empty bit 5 : rx fifo full bit 4 : tx fifo full bit 3 : tx end bit 2 : reserved bit 1 : reserved bit 0 : sspi busy r 8b ? 00000000 sstr1 0xfffff 830 sspi 0 term register w 8b ? 11111111 uart register (@ 0xffff f500 ) a bbreviation address descriptions r/w initial value rbr0 thr dll dlm 0xfffff 500 receiver buffer register (dlab=0) transmitter holding register (dlab=0) divisor latch ls (dlab=1) divisor latch ms (dlab=1) r w r/w r/w 8b ? 10011000 8b ? 10011000 8b ? 10011000 8b ? 10011000 ier 0xfffff 504 interrupt enable register bit 7-4 : reserved bit 3 : modem status interrupt bit 2 : receiver line status interrupt bit 1 : thr empty interrupt bit 0 : rx data available interrupt r/w 8b ? 00000000 iir / fcr 0xfffff 508 interrupt identification register fifo control register bit 7 : rcvr trigger to msb bit 6 : rcvr trigger to lsb bit 5-3 : reserved bit 2 : xmit fifo reset bit 1 : rcvr fifo reset bit 0 : fifo enable r w 8b ? 00000001 lcr 0xfffff 50c line control register bit 7 : dlab (divisor latch access bit) bit 6 : break control bit bit 5 : stick parity bit bit 4 : even parity control bit 3 : parity control (0: disabled) bit 2 : stop bit(s) (0 : disable d ) bit 1,0 : character bits 00(5-bit),01(6-bit), 10(7-bit), 11(8-bit) r/w 8b ? 00000000
189 GDC21D601 uart register (@ 0xffff f500 ) -- continued a bbreviation address descriptions r/w initial value mcr 0xfffff 510 modem control register bit 7-5 : reserved bit 4 : loop control bit 3,2 : reserved bit 1 : rts bit 0 : dtr r/w 8b ? 00000000 lsr 0xfffff 514 line status register bit 7 : rx fifo error bit 6 : transmitter empty bit 5 : thr empty bit 4 : break interrupt bit 3 : framming error bit 2 : parity error bit 1 : overrun error bit 0 : data ready r/w 8b ? 01100000 msr 0xfffff 518 modem status register bit 7 : dcd(data carrier detect) bit 6 : ri(ring indicator) bit 5 : dsr(data set ready) bit 4 : cts(clear to send) bit 3 : ddcd(delta data carrier detec) bit 2 : teri(trailing edge ring indi.) bit 1 : ddsr(delta data set ready) bit 0 : dcts(data clear to send) r/w 8b ? xxxx0000 scr 0xfffff 51c scratch register r/w 8b ? 10011000
190 GDC21D601 i 2 c registers (@ 0xffff f900 : channel 0) a bbreviation address descriptions r/w initial value baud_r0 0xfffff 900 i 2 c baud rate register for channel 0 w 8b ? 00000100 ctrl0 0xfffff 904 i 2 c control register for channel 0 bit 7-5 : reserved bit 4 : include address bit bit 3 : transfer end bit 2 : transfer start bit 1 : sda pin set/clear bit 0 : interrupt enable (0: disabled) w 8b ? xxx00010 data_r0 0xfffff 908 i 2 c data register for channel 0 r/w 8b ? xxxxxxxx stat_r0 0xfffff 90c i 2 c status register for channel 0 bit 7-5 : reserved bit 4 : interrupt flag bit bit 3 : bus busy flag bit bit 2 : bus lost flag bit bit 1 : sda pin ack bit bit 0 : slave called flag bit r 8b ? xxx00000 addr_r0 0xfffff 910 i 2 c address register for channel 0 w 8b ? 00000000 test_r0 0xfffff 914 test register for channel 0 r/w 8b ? 00000000 i 2 c registers (@ 0xffff fa000 : channel 1) a bbreviation address descriptions r/w initial value baud_r1 0xfffff a00 i 2 c baud rate register for channel 1 w 8b ? 10011000 ctrl1 0xfffff a04 i 2 c control register for channel 1 w 8b ? 10011000 data_r1 0xfffff a08 i 2 c data register for channel 1 r/w 8b ? 10011000 stat_r1 0xfffff a0c i 2 c status register for channel 1 r 8b ? 10011000 addr_r1 0xfffff a10 i 2 c address register for channel 1 w 8b ? 10011000 test_r1 0xfffff a14 test register for channel 1 r/w 8b ? 10011000 i 2 c registers (@ 0xffff fb00 : channel 2 ) a bbreviation address descriptions r/w initial value baud_r2 0xfffff b00 i 2 c baud rate register for channel 2 w 8b ? 10011000 ctrl2 0xfffff b04 i 2 c control register for channel 2 w 8b ? 10011000 data_r2 0xfffff b08 i 2 c data register for channel 2 r/w 8b ? 10011000 stat_r2 0xfffff b0c i 2 c status register for channel 2 r 8b ? 10011000 addr_r2 0xfffff b10 i 2 c address register for channel 2 w 8b ? 10011000 test_r2 0xfffff b14 test register for channel 2 r/w 8b ? 10011000

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