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L3913 monochip telephone advance data adjustable slope of dc charac- teristic adjustable automatic line lenght receiving and sending gain control (not used in dtmf), with possibility of fixed gain (pabx). adjustable automatic line lenght tracking antisidetone system adjustable dynamic impedance stabilized power supply for periph- erals confidence level during pulse and dtmf dialling receiving amplifier for dynamic or piezo-electric earpieces high impedance microphone inputs (80k ? min. in symmetrical and 40k ? min. in asymmetrical) suitable for dynamic, magnetic, piezo-electric or electret microphone dynamic limiting in sending (anticlip- ping) prevents distortion of line signal and sidetone antisquelch system in sending pre- vents ?room noise? to be transmit- ted, and improves the anti-larsen efficiency loudhearing programmable gain in 8 steps of 3 db using the serial bus, or linearly using a potentiometer antilarsen system which doesn?t cut the receiving voice antidistortion system by automatic gain control versus available loudhearing current ringing balanced output in dmos for higher power capability 4 ringing tones adjustable without external components internal speed up circuit permits a faster charge of v cc and v ram ca- pacitors logic bounce elimination pulse dialling 66/33 or 60/40 or dtmf di- alling selectable by programming pin adjustable flashing duration (90ms or 265ms) interdigital pause confidence tone (440hz) last number radial up to 23 digits standard low cost ceramic 455khz binary data input in serial mode test mode capability description the L3913 monochip is a bipolar cmos- dmos (bcd) integrated circuit that performs all the speech and line interface functions required in an electronic telephone set, the ringing function with 4 melodies, the pulse and dtmf dialling with redial, the loudhearing with antilarsen and antidis- tortion systems, a keyboard interface with the possilbility to interface with an external microcon- troller using the internal serial bus, and a power supply for peripheral. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. september 1993 plcc-44 1 2 3 5 64 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 34 35 33 32 31 30 29 40 41 42 44 43 23 22 21 19 18 20 28 27 26 24 25 c4 c3 flash ol reset dc/fv mf c1 c2 c5 c6 ea iea al v ram v e v cc ls vea hp2 gnd hp1 beat pair ck vir out1 out2 zall rec zalc e1 e2 m2 m1 rgab i ref eff self acl em/mf mod zac em/filt d93tl022 pin connection (top view) 1/14
dc stabilization 19 zall zalc d93tl032a l1 l2 + + r e 12 21 20 vcc supply 11 vea supply 14 + - - 32 31 33 agc 30 -1 +1 29 26 24 13 ea +gmm -gmm iea/vea control 17 15 8 28 ac impedance 9 filter 27 25 gm gav 22 23 agc keyboard/ serial bus interface internal supply loudspeaker control clock mcu + i/o interface dialer t/p ringer ram reset 10 41 42 2 1 44 43 36 34 35 38 39 keyboard/ or remoted controller 40 5 37 6 7 16 4 3 n.c. n.c. vcc s1a s1b v cc 18 pulse output on off reset(6) reset(6) gnd gnd mute block diagram L3913 2/14
pin functions n name description 1 c4 keyboards inputs 2 c3 keyboard inputs 3 flash flashing selection (80 or 265ms) 4 dc/fv dialling selection (33/66 pulse, 40/60 pulse or dtmf) 5 ol open line output 6 reset output reset in normal case, input reset in test mode 7 ea loudhearing on/off 8 iea antidistortion time constant adjustment in loudhearing 9 al antilarsen time constant adjustment in loudhearing 10 v ram ram and internal logic supply 11 v cc power supply for peripherals 12 v e line voltage 13 ls loudhearing input 14 vea loudhearing supply 15 hp2 loudspeaker output 16 gnd ground 17 hp1 loudspeaker output 18 eff line lenght agc adjustment 19 i ref bias adjustment 20 self electronic self input 21 rgab dc characteristic slope adjustment 22 m1 microphone input 23 m2 microphone input 24 zac dynamic impedance adjustment 25 em/filt first sending stage output 26 mod modulator output 27 em/mf nsecond sending stage input and dtmf input 28 acl anticlipping time constant adjustment 29 e2 receiver output 30 e1 receiver output 31 zalc short line sidetone network 32 rec receiver input 33 zall long line sidetone network 34 out1 buzzer output 35 out2 buzzer output 36 vir ringing supply 37 ck ceramic input (455khz) 38 pair ajustment between 2 pairs of ringing frequencies 39 beat beat ajustment of each pair 40 mf dtmf output 41 c1 keyboard inputs 42 c2 keyboard inputs 43 c6 keyboard inputs 44 c5 keyboard inputs L3913 3/14
electrical characteristics (t amb =25 c; f = 1khz; r e = 20k ? ; all resistance are specified at 1%, all capacitance at 2%) symbol parameter test condition min. typ. max. unit fig. dc characteristics v l line voltage i l = 15ma i l = 25ma i l = 60ma - 5.75 12.75 4.4 6.15 13.15 4.9 6.55 13.55 v v v 1 1 1 v cc stabilized voltage supply icc = 0.6ma i l = 8.3ma 2 2.5 - v 1 i cc = 2.1ma i l = 25ma 3.15 3.4 3.65 v 1 i ram operative vram = 3.5v - - 500 a i ram stand-by vram = 3.5v - - 300 na reception gr1 receiving gain i l = 25ma v l = 0.3vrms 10 11 12 db 2 gr2 receiving gain i l = 60ma (see agcr) 2.5 4 5.5 db 2 agcr delta gain receive i l = 60ma (to be applied only if gr2 is not respected) 6.3 7 7.7 db 2 r x distortion i l = 30ma; v ou t = 5vpp - 0.6 3 % 2 i l = 60ma; v ou t = 5vpp - 0.6 3 % 2 z out receiver i l = 25ma; v ou t = 50mvrms 45 65 85 ? 2 r x offset i l = 25ma / 60ma -500 - 500 mv 2 sidetone i l = 25ma v mi = 2mvrms i l = 60ma - - 30 16 - - db db 1 1 transmission gs1 sending gain i l = 25ma v mic = 2mvrms 47.5 48.5 49.5 db 1 gs2 sending gain i l = 60ma (see sgcs) 40.4 41.9 43.4 db 1 agcs delta gain sending i l = 60ma (to be applied only if gs2 is not respected) 5.9 6.6 7.3 db 1 cmrr common mode rejection i l = 25ma; v cm = 50mvrms - 75 - db 1 t x distortion i l = 36ma v mi = 5mvrms v mi = 5mvrms + 10db v mi = 5mvrms + 20db - - - - - - 3 5 7 % % % 1 1 1 as gain attenuation i l = 25ma v mi = 2mvrms 65 - - db 1 z in microphone impedance i l = 30ma 85 120 - k ? 1 t x offset pin 25 (dtmf - t x )i l = 25ma / 60ma - 100 + 100 mv 1 t x swing tx output voltage swing i l = 36ma v mi c= 5mvrms+10db 3.2 3.8 4.4 vpp 1 t x squelch dynamic range il = 25ma v mic = 1mvrms/0.15mvrms 7.5 9 10.5 db 1 z line matching i l = 25ma i l = 60ma 580 630 680 ? 2 noise t x noise i l = 25ma (psophometric) - - 78 - dbmp 1 r x noise i l = 25ma (psophometric) - 200 - vp 2 L3913 4/14
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit fig. loudhearing v ea loudhearing supply i l = 25ma i l = 60ma 3.5 7.8 3.8 8.2 4.1 8.9 v v 3 3 g ea loudhearing gain i l = 30 / 50ma v ls = 20mvrms 19.7 20.7 21.7 db 3 ? g ea 8 steps programmable gain using serial bus il = 25 / 60ma v ls = 20mvrms - 3 - db 3 z ih input impedance i l = 30ma 24 34 44 k ? 3 lh distortion load = 100 ? i l = 50ma v lline = 200mvrms v lline =350mvrms - - 1 4.5 3 7 % % 3 3 lh offset i l = 25ma -120 - +120 mv 3 i leak leakage pin i ea i l = 25ma - - 100 na 3 lh offset pin al i l = 25ma - - 150 mv 3 lh antilarsen attenuation i l = 30ma pin 9 to v cc 5.75 6.25 6.75 db 3 ringer v turn-on threshold on measured at pin v ir 14 15 17 v 4 v turn-off threshold off 10.5 12 14 v 4 i s supply current v s = 17v no load - 1.2 1.6 ma 4 f out frequencies pin 38 = gnd v ir = 32v 1450 1160 1458 1166 1465 1172 hz hz 4 4 pin 38 = open v ir = 32v 544 435 547 438 550 441 hz hz 4 4 pin 39 = gnd pin 39 = open v ir = 32v 3.9 9 4 9.1 4.1 9.2 hz hz 4 4 v out output voltage swing v ir = 32v 30 - - v 4 i il input low v ir = 32v beat, pair (pins 38, 39) v il =1v - 12 - 7 - 1.5 a4 dtmf generation dtmf frequency tolerances i l = 25ma -0.4 - +0.25 % 1 dtmf level i l = 25 / 60ma low group high group preemphasis -10 -8 1 -8 -6 2 -6 -4 3 dbm dbm db 1 1 1 dtmf distortion i l = 25ma bw = 20khz see mask fig. 6 dtmf feedback i l = 60ma referred to the line voltage rx lh - - -19 - 2.5 - - db db 5 5 flash operating current 8.3 - - ma 1 tmf transmission time 80.1 81.7 83.3 ms 1 t idmf interdigit time 87.4 89.2 91.5 ms 1 tm mf transmission mute 167.5 170.9 174.3 ms 1 confidence tone only by serial bus i l = 25ma - 440.9 hz 1 confidence tone level - - 9 - dbm 1 L3913 5/14
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit fig. leakage (v ram = 3.5v) i kl input low (keyboard current) c1 % c6 (pins 1, 2, 41 % 44) v il = 0.5v 1.5 - 5 a i il input low c1 % c6 (pins 1, 2, 41 % 44) v il = 0.4v 150 450 1300 a ck (pin 37) v il = 0.5v - - 1 a i ih input high ea (pin 7) v ih = 3.5v 5 11.5 16 a dcfv (pin 4), flash (3) v il =0v - 10 - 6 - 1.5 a c1 % c6 (pins 1, 2, 41 % 44) v ih = 3.1v - 1300 - 450 - 150 a dcfv (pin 4), flash (3), ck(37) v ih = 3.5v - - - - 1 1 a a i ol output low reset (pin 6) v ol = 0.4v ol (pin 5) 0.2 0.7 - - 1.3 3.7 ma ma i oh output high reset (pin 6) voh = 2.85v ol (pin 5) v oh = 0.7v - 1.8 -30 - 0.6 - - 0.2 -8 ma a timing and frequency t r reset time in mode dtmf in mode 60/40 in mode 66/33 - - - 34.3 30 33 - - - ms ms ms 7 7 7 t on clock start-up time - 5 - ms t lb time line break generating a reset in mode 60/40 in mode 66/33 in mode dtmf 290 319 341 - - - 300 330 343 ms ms ms 7 7 7 t e debounce time in mode 60/40 in mode 66/33 in mode dtmf 14 15.4 16 24 26.4 27.4 34 37.4 38.9 ms ms ms serial bus t wl ,t wh pulse width clock 2 - - s8 t el ,t eh pulse width enable signal 2 - - s8 t set up set-up time data to clock 0 - - ns 8 hold time data drom clock 100 - - ns 8 t e enable time 0 - - ns 8 t rrn time between two transmissions 900 - - s8 pulse dialling (ol) dialling pulse frequency in mode 60/40 (pin 4 tied to reset) -10-hz in mode 66/33 (pin 4 not connected) - 10.11 - hz t ol dialling pulse period pin 4 tied to reset pin 4 n.c. - - 100 98.9 - - ms ms t b break time pin 4 tied to reset pin 4 n.c. - - 60 66 - - ms ms t m make time pin 4 tied to reset pin 4 n.c. - - 40 33 - - ms ms L3913 6/14
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit fig. pulse dialling (ol) continued. t idol interdigit 830 813 - - 833 816.5 ms ms t mol transmission mute n pulses dialling see note below t fl flash pulse duration pin 3 to gnd, pin 4 n.c. pin 3 n.c., pin 4 n.c. pin 3 to gnd, pin 4 to reset pin 3 to gnd, pin 4 to gnd pin 3 n.c., pin 4 to reset pin 3 n.c., pin 4 to gnd pin 3 to reset, pin 4 to reset pin 3 to reset, pin 4 to gnd pin 3 to reset, pin 4 n.c. 99 264 90 92 240 264 110 115 121 - - - - - - - - - 101.2 266.2 92 94 242.2 266 112.2 117 123.2 ms ms ms ms ms ms ms ms ms t mfl transmission mute in mode 60/40 in mode 66/33 in mode dtmf 830 813 860 - - - 832 815.5 880 ms ms ms t p pause time in mode 60/40 in mode 66/33 in mode dtmf 3034 2994 3028 - - - 3038 2998 3032 ms ms ms clock keyboard: minimum time to respect, in order to take the pressed pushbutton into account pin 4 to pin 6 pin 4 n.c. pin 4 to gnd 14 15.4 16 24 26.4 27.4 34 37.4 38.9 ms ms ms clock keyboard: minimum time to respect, in order to take the released pushbutton into account pin 4 to pin 6 pin 4 n.c. pin 4 to gnd 24 26.4 27.4 24 26.4 27.4 34 37.4 38.9 ms ms ms note: min. max. unit n x 100 + 30 n x 100 + 32 ms n x 98.9 + 22 n x 100 + 24.2 ms L3913 7/14
470nf 19 20 61.9k dc v e 600 50 f 18 i l v e vz=18v r e 20k 21 12 470nf 32 26 52 470nf 24 15k 620 620 31 33 6k 6k v cc ra g1 51k ra g2 91k 1 f 1k 30 13 v r 4.7 f 220 f 470 f 11 14 29 17 15 8 28 r acl 6.8m c acl 470nf 9 s2 v mi r al 82k c al 470nf 22 23 22 f22 f 1m v cc 27 25 47nf 4.7nf 4.7nf 270 ? 330k 220pf s3 43 44 1 2 42 41 10 7 37 6 4 bis pause 3*r 286 1*5 9 78 470 f 455khz 240k 480 5 40 -1.7v 34 35 36 38 39 16 4 3 monochip L3913-5 d93tl019a test circuits figure 1. 470nf 19 20 61.9k dc v e 600 50 f 18 i l v e vz=18v r e 20k 21 12 470nf 32 26 52 470nf 24 15k 620 620 31 33 6k 6k v cc ra g1 51k ra g2 91k 1 f 1k 30 13 v r 4.7 f 220 f 470 f 11 14 29 17 15 8 28 r acl 6.8m c acl 470nf 9 r al 82k c al 470nf 22 23 1m 27 25 47nf 4.7nf 270 ? 43 44 1 2 42 41 10 7 37 6 4 bis pause 3*r 286 1*5 9 78 470 f 455khz 5 40 34 35 36 38 39 16 4 3 monochip L3913-5 d93tl023a v l figure 2. L3913 8/14
470nf 19 20 61.9k dc v e 600 50 f 18 i l v e vz=18v r e 20k 21 12 470nf 32 26 52 470nf 24 15k 620 620 31 33 6k 6k v cc ra g1 51k ra g2 91k 1 f 1k 30 v r 4.7 f 220 f 470 f 11 14 29 17 15 8 28 r acl 6.8m c acl 470nf 9 r al 82k c al 470nf 22 23 1m 27 25 47nf 4.7nf 270 ? 43 44 1 2 42 41 10 7 37 6 4 bis pause 3*r 286 1*5 9 78 470 f 455khz 40 34 35 36 38 39 16 4 3 monochip L3913-5 d93tl024a v l s2 v cc 5 r iea 1m c iea 470nf 13 s4 v iea 100nf v cc v ls figure 3. 19 20 36 21 12 32 26 24 31 33 51k 30 100nf 11 14 29 17 15 8 28 9 22 23 1m 27 25 43 44 1 2 42 41 10 7 37 6 455khz 40 34 35 18 38 39 16 4 3 monochip L3913-5 d93tl025 5 13 dc s5 s6 s5 s6 pair of freq hz sweep freq hz on on off off on off on off 1458/1166 1458/1166 547/438 547/438 4 9.1 4 9.1 figure 4. L3913 9/14
line break description after a line break longer than a time line break (tlb) an internal reset is generated. a short line break < tlb does not affect the reset. power on reset timings (after line break) 470nf 19 20 61.9k dc v e 600 50 f 18 i l v e vz=18v r e 20k 21 12 470nf 32 26 52 470nf 24 15k 620 620 31 33 6k 6k v cc ra g1 51k ra g2 91k 1 f 1k 30 v r 4.7 f 220 f 470 f 11 14 29 17 15 8 28 r acl 6.8m c acl 470nf 9 s2 v mi r al 82k c al 470nf 22 23 22 f22 f 1m v cc 27 25 47nf 4.7nf 4.7nf 270 ? 330k 220pf s3 43 44 1 2 42 41 10 7 37 6 4 bis pause 3*r 286 1*5 9 78 470 f 455khz 240k 480 5 40 -1.7v 34 35 36 38 39 16 4 3 monochip L3913-5 d93tl026 s1 13 v mp 100 47 f r iea c iea figure 5. 0.1 1 10 100 f (khz) -60 -50 -40 -30 dbm/ 600 ? d93tl027 figure 6: dtmf distortion french specification. vram t reset t trt trt=tr+ton d93tl028 figure 7a: v ram >v son at t = 0 L3913 10/14
dialer functional description the monochip includes a dialling circuit for either pulse dialling or dual tone multifrequency dialling. the dialler transmits the codes decoded by the logic keyboard on the outputs 0l and dtmf. dialing mode selection the default dialling mode is selected by the tri- level pin dc/fv (pin 4): ? dc/fv open: pulse dialling in 66/33ms ? dc/fv to pin reset: pulse dialling in 60/40ms ? dc/fv to pin gnd: dtmf dialling calibrated ? mixed mode when the circuit is in pulse mode, it is possible to change to dtmf dialling with the ? * ? key. the circuit returns in pulse mode after a reset condi- tion or after a flash pulse. dialling codes these are the numeric keys 0 to 9, and the non numeric keys a, b, c, d, *, #. all of them are stored in ram. the codes a, b, c, d can be only transmitted by the serial bus, not by standard key board. in pulse dialling, the code #, b, c, d have no ef- fect on the dialling. the code a (in pulse mode) corresponds to 11 pulses. serial bus description a microcontroller can be connected to the mono- chip by 4 pins c2, c3, c4, c5 (see fig. 8) c1 must be connected to v cc to select the serial mode operation. c2 sends the data, c3 the clock, c4 the enable vram t reset t trt trt=t(vram to v soff )+tr+ton d93tl029 tr v soff figure 7b: v ram L3913 c1 c2 c3 c4 c5 data clock enable signal state of dialer vcc d93tl031 figure 8. L3913 11/14
signal, c5 indicates the state of the dialler (if c5 = 0 the dialler is busy, if c5 = 1 the dialler is free). data is a 5 bits serial word shifted in a 5 bits reg- ister during the positive transition of the clock pulse. the positive transition of the enable signal validates the acquisition of the last 5 bits. timings diagram in fig. 9 shows the details of se- rial bus synchronization. table 1 explains the ?code entry? in serial bus mode. table 1: code enties. 00000 * 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 0 01011 a 01100 b 01101 c 01110 d 01111 * 1 0 0 0 0 reserved 1 0 0 0 1 r: flash 1 0 0 1 0 redial 1 0 0 1 1 loudspeaker on 1 0 1 0 0 confidence tone 1 0 1 0 1 microphone mute 1 0 1 1 0 pause 1 0 1 1 1 reserved 1 1 0 0 0 loudspeaker level 0db 1 1 0 0 1 loudspeaker level 3db 1 1 0 1 0 loudspeaker level 6db 1 1 0 1 1 loudspeaker level 9db 1 1 1 0 0 loudspeaker level 12db 1 1 1 0 1 loudspeaker level 15db 1 1 1 1 0 loudspeaker level 18db 1 1 1 1 1 loudspeaker level 21db L3913 12/14
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 0015887 L3913 13/14
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. L3913 14/14

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