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1/22 1. introduction this application note shows an example of how to use st52x420 to communicate with an eeprom memory with an i 2 c bus protocol. in this example, an m24c04 eeprom (4k bit) is taken into account, but the following considerations can be applied to applications with any kind of m24cxx memory. two software routines are proposed, the byte write and the random address read, for st52x420 microcontroller configured in single master communication. 2. communicating protocol the m24cxx is an eeprom supporting the i 2 c protocol. the m24cxx can communicate with a microcontroller, the master, only by a serial data i/o line (sda) and a serial clock (scl). during each data transfer, the m24cxx samples the sda bus signal on the rising edge of the clock signal scl. the sda signal must be stable during the clock low to high transition and the data must change only when the scl line is low. changes in the data line while the clock is high are interpreted as start and stop conditions. start is identified by a high to low transition of the sda line while the clock is stable in the high state. a start condition must precede any data transfer command. after the start, st52x420 sends onto the sda bus line 8 bits (msb first): the first 7 bits to select the device, the last ( rw bit) to indicate if it is a read ( rw high) or write ( rw low) operation. after sending each 8 bits data stream, the master releases the sda bus; during the 9th clock pulse period the receiver pulls the sda bus low to acknowledge the receipt of the 8 bit data. a complete data transfer is always terminated by a stop, identified by a low to high transition of the sda line while the clock scl is stable in the high state. AN1222 application note i 2 c communication between st52x420 and eeprom authors: v. marino, c. vinci figure 1 - i 2 c bus protocol ? february 2000
AN1222 - applicat ion note 2/22 3. hardware description the connection scheme between st52x420 and eeprom is shown in figure 2. pin pb1 of st52x420 is used to transfer data to and from the memory (sda); pin pb0 for data synchronization (scl). in this scheme m24c04 inputs e0, e1 and e2 are tied to vss (device select code is a0h), therefore, being e0 low, only 256 byte of memory, the low part, can be addressed. to address also the memory high part (address 1xxxxxxxx), e0 must be dynamically driven by using another i/o pin of st52x420. a maximum of four memories of the type m24c04 can be addressed by a microcontroller on the same two wire buses, setting e1 and e2 inputs (00, 01, 10, 11): each device is identified by its device select code and will only respond to the correct selection. pin wc , used to protect the contents of the memory from inadvertent erase/write operations, is unconnected, therefore with this scheme, write operations are always allowed. to allow enabling ( wc =v il ) and disabling wc =v ih ) write operations, wc must be driven dynamically. figure 2 - st52x420/eeprom i 2 c schematics 3.1 byte write mode in write mode, after the start condition, st52x420 sends a device select code with the rw bit set to `0', as shown in figure 3. the memory acknowledges the reception and waits for an address byte from the master, to which it responds with an acknowledge. after the acknowledge, st52x420 sends the data byte to be written in the defined memory location. st52x420 terminates the transfer by generating a stop condition. figure 3 - byte write mode sequence st52x420 start stop m240c04 vcc pb1 pb0 sda vcc e0 e1 e2 wc
AN1222 - application note 3/22 3.2 random address read mode in order to read a byte from an address of the memory, st52x420 performs a dummy write to load the address, as shown in figure 4. then, without sending a stop condition, st52x420 sends another start condition and sends the device select code again, with the rw bit set to `1'. after acknowledgment, the memory provides onto the bus the contents of the addressed byte. the master is not required to acknowledge the byte output and terminates the transfer with a stop condition. figure 4 - read mode sequence 4. software (i 2 c communication routines between st52x420 and m24c04 eeprom) the software project for st52x420 communicating with an eeprom m24c04 is described in the followings. two routines are developed in assembler language to show how to perform operations of writing and reading a page of memory (256 bytes). please refer to appendix 1 for writing operation and appendix 2 for reading operation assembler code. 4.1 write software routine chip configuration and eprom data store in the first part of the assembler code, as you can see in appendix 1, after the interrupt request vector definition, the adata page addr valueo instructions are performed. these instructions indicate to store data value in the st52x420 eprom, in the address of the specified page, in order to write these data into i 2 c eeprom. the configuration registers used for this program are: reg_conf0 to enable timer1 interrupt reg_conf1 to establish interrupt priority reg_conf8 and reg_conf9 to configure the timer1 reg_conf13 and reg_conf14 to configure the portb the timer1 peripheral has been configured in order to have a timer clock t=0.4 m s by setting the prescaler value to 4 and supposing that the master clock frequency is equal to 10 mhz. the choice to load the counting from the timer_count register, where the user can write values ranging from 10 to 255 (80 in this example), allows to set the communication speed within the range [250khz (fast mode), 9.8khz (standard mode)]. main program after the initialization of the used register, the start condition is performed calling the subroutine ` start_bit '. then three byte are serially sent (calling ` send_data ') onto sda bus, respectively the device select code, the address byte and the data byte to be written into i 2 c memory address location: after each byte is sent, st52x420 waits for m24c04 acknowledgment; at each ack receipt (reg30 is 0 after ` read_ack ' subroutine) the variable ` cont_ack ' (reg40), initially set to zero, is incremented of one unit. when ` cont_ack ' reaches 3, a stop condition (calling ` stop_bit' subroutine) is sent by st52x420 to the memory. if the signal ack is not returned from the memory (reg30 not equal to zero) the program provides to restart the communication protocol, jumping to the label ` init' . in order to write 256 bytes into the memory, the reg10 (address counter) is incremented of one unit after each `byte write' operation and only when the whole 256 bytes have moved to the eeprom the program terminates with a ` halt ' instruction, that stops the clock master so that the cpu and the peripherals are turned-off. start start stop
AN1222 - applicat ion note 4/22 `start_bit' subroutine this subroutine performs the start condition: at first, the sda line is pulled in high state through sending the reg21=2=00000010b into port b; then the scl line is pulled high by setting pin pb1 high sending reg21=3=00000011b ; finally sda is put low, and then also scl, to complete the start bit communication, as required from the protocol (figure 1). time delays among transitions between each block in the ` start_bit ' routine are managed thanks to the timer1 peripheral. in fact each transition on the port b is performed after a ` waiti ' instruction, that allows to synchronize the signal into port b with the interrupt generated on the falling edge of the timer1 out signal. `send_data' subroutine this routine has been planned for sending serially the 8 bits of a byte. in the first part of the routine, to decide whether the divice select code byte (160 in this case), or the address byte or the data byte must be sent, the variable ` cont_ack ' is used. if the byte to be sent is the data byte, an operation of reading from the eprom of st52x420 is performed, through the instruction ` ldre (19) (10)' , that loads in the register of ram pointed by reg19 (that is reg20) the content of the address of memory pointed by reg10 (that is 256*page+reg10). to send each byte, stored in reg50, bit by bit, a cycle scanned by reg23 (decremented from 8 to 1) is performed. at each step of the cycle, one data bit is sent onto sda bus (` ldpr 1 21 ') and the clock pulse on scl line is performed. to determine if the bit to send is `0' or `1', a simple operation of shift on the reg50 (` asl 50 ') is done. `read_ack' subroutine the routine ` read_ack ' is called by the main program after the routine ` send_data ' to check if the data sent is correctly received by the eeprom; if so, the variable ` ack ' (reg30) is `zero' and the procedure can continue, otherwise, if reg30 is `two', an error has occurred and the communication is restarted. `stop_bit' subroutine a data transfer is always terminated by a stop condition, that is identified by a low to high transition of sda line while the clock scl is stable in the high state. this condition is performed calling ` stop_bit ' subroutine. 4.2 read software routine main program after the initialization of the used register, the start condition is performed calling the subroutine ` start_bit '. three bytes are then sent serially onto sda bus (see also ` send_data ' subroutine). a cycle variable ` cont_ack ' (reg40) is used to discriminate which byte is going to be sent: the device select code (160) if reg40 is `0', the address byte (reg10) if it is `1', the device select code again with the r w bit set to `1' (i.e. a byte corresponding to 161), after a new start condition, if reg40 is `2'. if reg40 is `3', the data is read (with ` read_data ' subroutine) and the stop condition is executed. note that, if the signal ack is not returned from the memory (reg30 not equal to zero) the program provides to restart the communication protocol, jumping to the label ` init' . in order to read from the memory 256 bytes the reg10 (address counter) is incremented of one unit after each read operation and only when the whole 256 bytes have read from the eeprom the program terminates with a ` halt ' instruction, that stops the clock master so that the cpu and the peripherals are turned-off.
AN1222 - application note 5/22 `read_data' subroutine this subroutine is designated to read the data from the memory; the data is composed of eight bits, then, in order to read it, a cycle scanned by a counter initially set to `8' (reg23) is realized. to convert the serial data to parallel format, is necessary to associate to every bit the relative weight, that is given by 2 (reg23-1) ; to calculate the weight, the cycle ` power_of_two ' is performed. at the end of this cycle, the register 31 of the ram will contain 0 if the read bit was `0' or a value among 128, 64, 32, 16, 8, 4, 2, 1 if the bit was `1'; adding to reg20 reg31 at every cycle, the value of the read data is finally contained in reg20. `send_ack' subroutine in accordance with the i 2 c communicating protocol, at the end of the data byte receipt, st52x420 puts the pin pb0 (scl line) high, before sending the stop condition.
AN1222 - applicat ion note 6/22 appendix 1 ;*************** ********** ********** *********** ********** **** ; ; purpose: i 2 c communication ; ; date: 12/1/2000 ; ;*************** ********** ********** *********** ********** *********** ****** ; this program writes from the address 0 to the address 255 of ; an i2c the bytes contained to the page 2 of the eprom of st52x420 ;*************** ********** *****interrupt vector********************* ***** irq 2 tim1 ;*************** ********** ********** *********** ********** *********** ******* ;data to store in the eprom data 2 0 255 data 2 1 254 data 2 2 253 data 2 3 252 data 2 4 251 data 2 5 250 data 2 249 6 data 2 250 5 data 2 251 4 data 2 252 3 data 2 253 2 data 2 254 1 data 2 255 0 ;*************** ********** ********** *********** ********** *********** ******** ;*************** ***peripherals and chip configurations *************** **** ldrc 0 00001000b ; interrupt mask configuration ldcr 0 0 ; tm1 not masked, tm0, tm2, adc, ext masked ldrc 0 00011110b ; interrupt priority configuration ldcr 1 0 ; from the lowest: adc, tm0, tm2, tm1 ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer mode, int. on tm1out falling edge ldrc 0 00100010b ; pwm-timer 1 configuration
AN1222 - application note 7/22 ldcr 9 0 ; tm1out square wave, presc1=4 ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ldrc 0 00000000b ;port b mode configuration ldcr 14 0 ; pb7-pb0 digital i/o ldrc 0 80 ; reg0=80 ldpr 5 0 ; timer_count1=80 ;*************** ********** *******endconfiguration********************* ** ;*************** ********** ******main program***************** ********** * ;*************** ********** **variablesdefinition***************** ******** ;tm1 manages the communication speed ;pb0scl pb1sda ;reg10=address ;reg20=data ;reg30=ack ;reg40=cont_ack ;reg50=byte_to_send ;*************** ********** ********** *********** ********** *********** ***** start: ldrc 10 0 ;address=0 ldrc 19 20 ;reg19=20 (this instruction maids for the indirect ;addressing of reg20 through reg19) ldrc 21 0 ;register of support to send data into port b ldrc 22 2 ; register used to set bit1 of port b init: ldrc 40 0 ; init cont_ack call start_bit ; start condition routine send: call send_data ; send byte into sda bus call read_ack ; read ack (result is stored in reg30) and 30 30 ; if ack=0 the procedure goes on, else restarts jpnz init inc 40 ; increments cont_ack ldrc 41 3 ; after three acknowledge the data transfer is sub 41 40 ; terminated and a stop condition is performed jpnz send ; call stop_bit ; stop condition routine inc 10 ; increments address ; if before this operation reg10<255 flag c is
AN1222 - applicat ion note 8/22 ; cleared and then new write operation is performed. ; else, if reg10=255, this operation causes an ; overflow (flag c is setted) and the program jpnc init ; finishes. halt ; clock master is stopped ;*************** ********** *****end main program******************** ******* ;*************** ********** ********start_bitroutine****************** ********** * ;this routine performs the start of the communicating protocol start_bit: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;*************** ********** *******sdahigh************ *********** ********** add 21 22 ; reg21=2 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** *********** ********** waiti ; waits for timer1 interrupt ;*************** ********** ********** sclhigh**************** *********** **** inc 21 ; reg21=3 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** *********** ********** * waiti ; waits for timer1 interrupt ;*************** ********** ********** ***sdalow****************** ********** *** sub 21 22 ; reg21=1 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** *********** ********** ** waiti ; waits for timer1 interrupt ;*************** ********** **scllow****************** ********** *********** **** dec 21 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** *********** *********
AN1222 - application note 9/22 waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ret ; return from subroutine ;*************** *********** ********** ********** *********** ********** ********* ;*************** *********** ********send_dataroutine******************** ** send_data: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ;*************** *********** ********** byte_to_send******************* **** ldrc 0 0 ; if cont_ack==0 then sub 0 40 jpnz l0 ldrc 50 160 ; byte_to_send=160 (device select code) jp end 0 l0: ; else ldrc 0 1 ; if cont_ack==1 then sub 0 40 jpnz l1 ldrr 50 10 ; byte_to_send=address jp end0 l1: ; else pgset 2 ; sets the current eprom page ldre (19) (10) ; this instruction loads into ram location, whose ; address is contained in reg19 (that is into reg20) ; the contents of the eprom location to the ; address (256*pag_number+reg10) ldrr 50 20 ; byte_to_send=data end0:
AN1222 - applicat ion note 10/22 ;******** *********** ********** *********** ********** ********** ********* ;******** *********** ********** *********** ********** ********** ********** ldrc 23 8 ; init counter bit bit: ;******** *********** ********** **bitto send******************** *** ldrc 21 0 ; bit=0 asl 50 ; shift left byte_to_send jpnc l2 ; c is set if msb was high add 21 22 ; if c is set bit=1 (pb1=1) l2: ldpr 1 21 ; send bit of data into port b ;******** *********** ********** *********** ********** ********** ***** ;******** *********** *****sclpulse************* ********** ****** ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt inc 21 ldpr 1 21 ; scl high waiti ; waits for timer1 interrupt dec 21 ldpr 1 21 ; scl low waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ;******** *********** ********** *********** ********** ********** ******* ldrc 21 0 ; resets reg21 dec 23 ; decrements counter bit jpnz bit ; jumps to label `bit' if the data transfer is ; incomplete, goes out after 8 bits sent ;******** *********** ********** *********** ********* ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output
AN1222 - application note 11/22 ret ; return from subroutine ;*************** ********** ********** *********** ********** *** ;***********read_ack routine*********** *********** ******* read_ack: ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;*************** ********** ********** *********** *****sclhigh ****************** ********** *********** ********** **** inc 21 ; reg21=1 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** ********** *********** ********** *********** ********** ******* waiti ; waits for timer1 interrupt ldri 30 10 ; read port b and 30 22 ; (xxxxxxbx)b and (00000010)b=(000000b 0)b ;*************** ********** ********** *********** *****scllow **************** *********** ********** *********** ******** dec 21 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;*************** ********** ********** *********** ********** ********** *********** ********** * waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 21 0 ; resets reg21 ret ; return from subroutine ;*************** ********** ********** *********** ********** ********** *********** ********** *********** ********** ****** ;*************** ********** ********** *** **stop_bit routine************ *********** ********** *********** ********** **** stop_bit: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start
AN1222 - applicat ion note 12/22 waiti ; waits for timer1 interrupt *********** sda low************ ********** ********** *********** ********** *********** ********** **** ldrc 21 0 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;*********** *********** ********** ********** *********** ********** ********** *********** ********** ** waiti ; waits for timer1 interrupt *********** scl high************* ********** *********** ********** ********** *********** ********** ** inc 21 ; reg21=1 ldpr 1 21 ; send reg21 into port b *********** *********** ********** ********** *********** ********** *********** ********** ********** ** waiti ; waits for timer1 interrupt ;*********** sda high*************** ********** **************** ********** ********** *********** ****** add 21 22 ; reg21=3 ldpr 1 21 ; send reg21 into port b ;*********** *********** ********** ********** ****** ****************** ********** *********** ********* waiti ; waits for timer1 interrupt ;*********** scl low*************** *********** **** ********** ********** ********** *********** ******* dec 21 ; reg21=2 ldpr 1 2 ; send reg21 into port b ;*********** *********** ********** ********** ****** ****************** ********** *********** ********* waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 21 0 ; resets reg21 ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ;*********** *********** ********** ********** ***intssubroutines************* ********** *********** ********** ******** tim1: reti ; return from interrupt ;*********** *********** ********** ********** *********** ********** ********** *********** ********** *********** ********** *
AN1222 - application note 13/22 appendix 2 ;*********** *********** ********** *********** ********** ********** *********** * ; ; purpose: i 2 c communication ; ; date: 12/1/2000 ; ;*********** *********** ********** *********** ********** ********** *********** * ;this program reads from an i2c the byte from the address 0 to the address 255 ;*********** *********** ******interrupt vectors ************* ********** **** irq 2 tim1 ;*********** *********** ********** *********** ********** ********** *********** ;******** peripherals and chip configurations ****************** ********* ldrc 0 00001000b ; interrupt mask configuration ldcr 0 0 ; tm1 not masked, tm2, tm0, adc, ext masked ldrc 0 00011110b ; interrupt priority configuration ldcr 1 0 ; from the lowest: adc,tm0,tm2,tm1 ldrc 0 00000000b ; port a configuration ldcr 4 0 ; pa7-pa0 output ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer mode, int. on tm1out falling edge ldrc 0 00100010b ; pwm-timer 1 configuration ldcr 9 0 ; tm1out square wave, presc1=4 ldrc 0 00001000b ; port a mode configuration ldcr 12 0 ; port a 8 bits, pin22-pa3, pin23-pa2, pin24-pa1 ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ldrc 0 00000000b ; port b mode configuration ldcr 14 0 ; pb7-pb0 digital i/o ldrc 0 80 ; reg0=80 ldpr 5 0 ; timer_count1=80 ;*********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** *
AN1222 - applicat ion note 14/22 ;************ **** *************** ********** *mainprogram********************************* *********** ********** ** ;************ ********** *********** ********** *variablesdefinition*********** ********** *********** ********** ****** ;tm1 manages the communication speed ;pb0scl pb1sda ;reg10=address ;reg20=data ;reg30=ack ;reg40=cont_ack ;reg50=byte_to_send ;************ ********** *********** ********** ********** *********** ********** ********** *********** ********** *********** start: ldrc 10 0 ; address=0 ldrc 21 0 ; register of support to send data into port b ldrc 22 2 ; register used to set bit1 of port b init: ldrc 40 0 ; init cont_ack start: call start_bit ; start condition routine send: call send_data ; send byte into sda bus call read_ack ; read ack (result is stored in reg30) and 30 30 ; if ack=0 the procedure goes on, else restarts jpnz init inc 40 ; increments cont_ack ldrc 41 1 ; if cont_ack=1 then jumps to label `send' in order sub 41 40 ; to send another byte into sda bus jpz send ldrc 41 2 ; if cont_ack=2 then jumps to label `start'in order sub 41 40 ; to perform another start condition jpz start call read_data ; read procedure call send_ack ; send acknowledgment call stop_bit ; stop condition routine
AN1222 - application note 15/22 ldpr 0 20 ; send read data into port a inc 10 ; increments address ; if before this operation reg10<255 flag c is ; cleared and then new read operation is performed. ; else, if reg10=255, this operation causes an ; overflow (flag c is set) and the program jpnc init ; finishes. halt ; clock master is stopped ;****************** ********** ********** **end main program******************************** ********** ********** ;****************** ********** ********** ***start_bitroutine*********** *********** ********** ********** *********** ** ;this routine performs the start of the communicating protocol start_bit: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;****************** ********** ********** ******sdahigh******************** *********** ********** ********** ********* add 21 22 ; reg21=2 ldpr 1 21 ; send reg21 into port b ;****************** ********** ********** *********** ********** *********** ********** ********** *********** ********** ***** waiti ; waits for timer1 interrupt ;***********scl high****************** *************************** ********** *********** ********** ********** ******* inc 21 ; reg21=3 ldpr 1 21 ; send reg21 into port b ;****************** ********** ********** *********** ********** *********** ********** ********** *********** ********** ***** waiti ; waits for timer1 interrupt ;***********sda low***************** *********** ********** ********** *********** ********** ********** *********** **** sub 21 22 ; reg21=1 ldpr 1 21 ; send reg21 into port b
AN1222 - applicat ion note 16/22 ;**************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******* waiti ; waits for timer1 interrupt ;**************** ********** *********** ********** ******scl low **************** *********** ********** ********** ***** dec 21 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;**************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******* waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ret ; return from subroutine ;**************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******* ;**************** ********** *********** ********** ******send_dataroutine******************** *********** ********** ** send_data: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ;**************** ********** *********** ********** ******byte_to_send ***************** ********** *********** ***** ldrc 0 0 ; if cont_ack==0 then sub 0 40 jpnz l0 ldrc 50 160 ; byte_to_send=160 (device select code, rw=0) jp end0 l0: ; else ldrc 0 1 ; if cont_ack==1 then sub 0 40 jpnz l1 ldrr 50 10 ; byte_to_send=address
AN1222 - application note 17/22 jp end0 l1: ; else ldrc 50 161 ; byte_to_send=161 (device select code, rw=1) end0: ;*************** *********** ********** ********** *********** ********** *********** ********** ********** *********** ******* ;*************** *********** ********** ********** *********** ********** *********** ********** ********** *********** ******* ldrc 23 8 ; init counter bit bit: ;*************** *********** ********** ********** *********** ********** *********** ********** ********** *********** ******* ldrc 21 0 ; bit=0 asl 50 ; shift left byte_to_send jpnc l2 ; c is set if msb was high add 21 22 ; if c is set bit=1 (pb1=1) l2: ldpr 1 21 ;send bit of data into port b ;*************** *********** ********** ********** *********** ********** *********** ********** ********** *********** ******* ;*************** *********** ********** ********** *******scl pulse **************** *********** ********** *********** ** ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt inc 21 ldpr 1 21 ; scl high waiti ; waits for timer1 interrupt dec 21 ldpr 1 21 ; scl low waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ;*************** *********** ********** ********** *********** ********** *********** ********** ********** *********** ******* ldrc 21 0 ; resets reg21 dec 23 ; decrements counter bit
AN1222 - applicat ion note 18/22 jpnz bit ; jumps to label `bit' if the data transfer is ; incomplete, goes out after 8 bits sent ;********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ret ; return from subroutine ;********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** ;********** *********** ********** *********** *********read_ackroutine************* ********** *********** ********** *** read_ack: ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;********** *********** ********** *********** ********** *scl high ************ ********** *********** ********** ********** inc 21 ; reg21=1 ldpr 1 21 ; send reg21 into port b ;********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** waiti ; waits for timer1 interrupt ldri 30 10 ; read port b and 30 22 ; (xxxxxxbx)b and (00000010)b=(000000b0)b ;********** *********** ********** *********** ********** *scl low ****************** *********** ********** *********** *** dec 21 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 21 0 ; resets reg21 ret ; return from subroutine ;********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** ;********** *********** ********** *********** *******read_dataroutine************* ********** ********** *********** *** read_data:
AN1222 - application note 19/22 ldrc 20 0 ; reg20=0 (reg20 will contain the read data) ldrc 23 8 ; init counter bit of data to read ;*********** *********** ********** *********** ********** ********** *********** ********** ********** *********** ********** * read_bit: ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt inc 21 ; reg21=1 ldpr 1 21 ; scl high waiti ; waits for timer1 interrupt ldri 31 10 ; read port b and 31 22 ; (xxxxxxbx)b and (00000010)b=(000000b0)b asr 31 ; reg31=(0000000b)b ldrr 32 23 ; reg32=counter bit ;*********** *********** ********** *********** ********** ********** *********** ********** ********** *********** ********** * ;*********** *********** ********** *********** ********** ********** *********** ********** ********** *********** ********** * power_of_two: dec 32 ; this loop shifts left reg31 so many times jpz end 1 ; how much determines the weight of the read bit asl 31 ; (2^(reg32-1)) jp power_of_two end1: add 20 31 ; reg20=b7*2^7 + b6*2^6 +...+ b0*2^0 ;*********** *********** ********** *********** ********** ********** *********** ********** ********** *********** ********** * dec 21 ; reg21=0 ldpr 1 21 ; scl low waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset dec 23 ; decrement counter bit jpnz read_bit ; jump to label `read_bit' if the data transfer is ; incomplete, goes out after 8 bits read ldrc 21 0 ; resets reg21
AN1222 - applicat ion note 20/22 ret ; return from subroutine ;*************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******** ;*************** ********** *********** ********** ********send_ackroutine***************** *********** ********** ***** end_ack: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;*************** ********** *********** ********** ********sdahigh************** *********** ********** ********** ******* add 21 22 ; reg21=2 ldpr 1 21 ; send reg21 into port b ;*************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******** waiti ; waits for timer1 interrupt ;*************** ********** *********** ********** *******sclhigh *************** ********** ********** *********** ******* inc 21 ; reg21=3 ldpr 1 21 ; send reg21 into port b ;*************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******** waiti ; waits for timer1 interrupt ;*************** ********** *********** ********** *******scllow ************* ********** *********** ********** ********** dec 21 ; reg21=2 ldpr 1 21 ; send reg21 into port b ;*************** ********** *********** ********** ********** *********** ********** *********** ********** ********** ******** waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 21 0 ; resets reg21 ldrc 0 00000010b ; port b direction configuration
AN1222 - application note 21/22 ldcr 13 0 ; pb1 input, the whole other pins in output ret ; return from subroutine ;*********** *********** ********** *********** ********** ********** *********** * ;*********** *********** stop_bitroutine******************* *********** ******** stop_bit: ldrc 0 00000000b ; port b direction configuration ldcr 13 0 ; pb6-pb0 output ldrc 0 01000101b ; pwm-timer 1 configuration ldcr 8 0 ; timer set and start waiti ; waits for timer1 interrupt ;*********** *********** ********** *********** ********** *sda low ************** *********** ********** *********** ****** ldrc 21 0 ; reg21=0 ldpr 1 21 ; send reg21 into port b ;*********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** * waiti ; waits for timer1 interrupt ;*********** *********** ********** *********** ********** scl high *************** ********** *********** ********** ****** inc 21 ; reg21=1 ldpr 1 21 ; send reg21 into port b ;*********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** * waiti ; waits for timer1 interrupt ;*********** *********** ********** *********** ********** sda high ************* ********** *********** ********** ******** add 21 22 ; reg21=3 ldpr 1 21 ; send reg21 into port b ;*********** *********** ********** *********** ********** ********** *********** ********** *********** ********** ********** ** waiti ; waits for timer1 interrupt ;*********** *********** ********** *********** **********scl low ************ ********** *********** ********** ********* dec 21 ; reg21=2 ldpr 1 21 ; send reg21 into port b
AN1222 - applicat ion note 22/22 ;******** ********** ********** *********** ********** *********** ********** ********** *********** ********** ********** ****** waiti ; waits for timer1 interrupt ldrc 0 01000000b ; pwm-timer 1 configuration ldcr 8 0 ; timer reset ldrc 21 0 ; resets reg21 ldrc 0 00000010b ; port b direction configuration ldcr 13 0 ; pb1 input, the whole other pins in output ret ; return from subroutine ;******** ********** ********** *********** ********** *********** ********** ********** *********** ********** ********** ****** ;******** ********** ********** *********** *****ints subroutines ************* ********** *********** ********** ******** tim1: reti ; return from interrupt ;******** ********** ********** *********** ********** *********** ********** ********** *********** ********** ********** ****** information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no li- cense is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publi- cation are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved fuzzystudio tm is a registered trademark of stmicroelectronics stmicroelectronics group of companies http://www.st.com australia - brazil - china - finland - france - germany - hong kong india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a.

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