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1/53 product preview may 2000 this is preliminary information on a new product now in development. details are subject to change without notice. M58LW064a M58LW064b 64 mbit (x16 and x16/x32, block erase) low voltage flash memories n M58LW064a x16 organisation, n M58LW064b x16/x32 selectable n multi-bit cell for high density and low cost n supply voltage v dd = 2.7v to 3.6v supply voltage v ddq = 2.7v to 3.6v or 1.8v to 2.5v input/output supply voltage n pipelined synchronous burst interface n synchronous/asynchronous read synchronous burst read asynchronous random and latch enabled controlled read, with page read n access time synchronous burst read up to 66mhz asynchronous page mode read 150/25ns, random read 150ns n programming time 16 word or 8 double-word write buffer 12us word effective programming time n memory blocks 64 equal blocks of 1 mbit n electronic signature manufacturer code: 20h device code M58LW064a: 17h device code M58LW064b: 14h description the M58LW064 is a non-volatile flash memory that may be erased electrically at the block level and programmed in-system on a 16 word or 8 double-word basis using a 2.7v to 3.6v supply for the circuit and a supply down to 1.8v for the input and output buffers. the M58LW064a is organised as 4m by 16 bit. the M58LW064b has 4m by 16 bit or 2m by 32 bit organisation selectable by the word organisation word input. both devices are internally configured as 64 blocks of 1 mbit each. fbga 86 1 tsop56 (nf) lbga54 (za) pqfp80 (t) tsop86 ii (nh) figure 1. logic diagram note: 1. only on M58LW064b. ai03223 22 a1-a22 w dq0-dq31 v dd M58LW064a M58LW064b e v ss 32 g rp l v ddq b k rb r v pp word (1)
M58LW064a, M58LW064b 2/53 the devices support asynchronous random and latch enable controlled read with page mode as well as synchronous burst read with a config- urable burst. they also support pipelined synchro- nous burst read. writing is asynchronous or asynchronous latch enable controlled. the configurable synchronous burst read interface allows a high data transfer rate controlled by the burst clock k signal. it is capable of bursting fixed or unlimited lengths of data. the burst type, laten- cy and length are configurable and can be easily adapted to a large variety of system clock frequen- cies and microprocessors. a 16 word or 8 double- word write buffer improves effective program- ming speed by up to 20 times when data is pro- grammed in full buffer increments. effective word programming takes typically 12 m s. the array ma- trix organisation allows each block to be erased and reprogrammed without affecting other blocks. program and erase operations can be suspended in order to perform either read or program in any other block and then resumed. all blocks are pro- tected against spurious programming and erase cycles at power-up. any block can be separately protected at any time. the block protection bits can also be deleted, this is executed as one se- quence for all blocks simultaneously. block protec- tion can be temporarily disabled. each block can be programmed and erased over 100,000 cycles. block erase is performed in typically 1 second. an internal command interface (c.i.) decodes in- structions to access/modify the memory content. the program/erase controller (p/e.c.) automati- cally executes the algorithms taking care of the timings required by the program and erase opera- tions. verification is internally performed and a status register tracks the status of the operations. the ready/busy output rb indicates the comple- tion of operations. instructions are written to the memory through the command interface (c.i.) using standard micro- processor write timings. the device supports the common flash interface (cfi) command set defi- nition. a reset/power-down mode is entered when the rp input is low. in this mode the power consump- tion is lower than in the normal standby mode, the device is write protected and both the status and the burst configuration registers are cleared. a recovery time is required when the rp input goes high. the device is offered in various package versions, tsop56 (14 x 20 mm), tsop86 type ii (11.76 x 22.22 mm) and lbga54 1mm ball pitch for the M58LW064a and pqfp80 for the M58LW064b. table 1. signal names a1-a22 address inputs x16 organisation a2-a22 address inputs x32 organisation dq0-dq7 data input/output x16 and x32 organisation command input, electronic signature output, block protection ststus output, status register output dq8-dq15 data input/output x16 and x32 organisation dq16-dq31 data input/output x32 organisation b burst address advance e chip enable g output enable k burst clock l latch enable r valid data ready (open drain output) rb ready/busy (open drain output) rp reset/power-down v pp program/erase enable w write enable word word organisation (M58LW064b only) v dd supply voltage v ddq input/output supply voltage v ss ground nc no internal connection du don't use (internally connected)
3/53 M58LW064a, M58LW064b figure 2. tsop56 connections dq3 dq9 dq2 dq0 dq6 a16 a17 a18 dq14 dq12 dq10 rb v ddq dq4 dq7 ai03224 M58LW064a 14 1 15 28 29 42 43 56 dq8 v dd dq1 dq11 b a20 a21 nc a19 w a22 r e l k a6 a3 a8 a9 a10 a2 a7 v pp a1 a4 a5 a12 a13 a11 a15 a14 rp v ss nc dq13 dq15 v dd dq5 g v ss v ss figure 3. tsop86 type ii connections dq7 v ss dq6 dq12 a16 v ss v ss a8 v dd a20 dq14 a14 r a21 v dd ai03634 M58LW064a 21 1 22 43 44 65 66 86 dq5 a7 dq13 dq15 dq4 a10 a11 e a9 a12 v pp rp a2 v ddq v ddq dq2 dq11 dq9 dq1 dq8 v ss v dd a1 v ss dq3 dq10 a3 a4 dq0 a6 a5 b v dd v ddq a18 a15 v ss a19 a13 a17 a22 dq22 dq17 dq24 dq16 dq30 dq20 nc g w dq23 dq25 nc nc word nc nc nc nc l k dq27 dq19 dq18 dq26 dq21 dq31 dq28 nc dq29 rb
M58LW064a, M58LW064b 4/53 figure 4. lbga connections for M58LW064a (top view through package) ai03536 dq6 a1 v ss v dd dq10 v dd dq7 dq5 v ddq dq2 b h dq14 v ss dq13 d a16 a20 e a9 c a17 a21 a11 a15 k a8 b r a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 l a6 v pp a22 a18 a10 a12 rp dq15 r/b dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss
5/53 M58LW064a, M58LW064b figure 5. pqfp connections ai03546 32 12 M58LW064b 53 dq18 dq16 dq24 a5 a6 a7 a4 a1 nc nc nc a3 dq27 dq17 l k nc dq19 dq25 dq8 dq1 dq9 b dq0 dq5 dq11 dq13 dq12 a9 a10 a11 rp a13 e a16 a14 a15 a12 a17 a21 a20 a19 r nc nc nc w dq15 dq7 dq6 dq14 dq20 a2 dq26 dq3 dq2 dq10 v ss v ddq dq4 g word a22 a8 a18 73 v dd v ss v ss rb dq28 dq21 dq29 dq22 dq30 dq23 dq31 v dd v pp v ss v ddq 1
M58LW064a, M58LW064b 6/53 table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. cumulative time at a high voltage level of 10v should not exceed 80 hours on rp pin. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 40 to 85 t bias temperature under bias 40 to 125 c t stg storage temperature 55 to 150 c v io input or output voltage 0.6 to v ddq +0.6 v v dd ,v ddq supply voltage 0.6 to 5.0 v v hh rp hardware block unlock voltage 0.6 to 10 (2) v
7/53 M58LW064a, M58LW064b figure 6. memory map ai03228 1mbit or 64 kwords 3fffffh 3f0000h 1mbit or 64 kwords 01ffffh 010000h 1mbit or 64 kwords 00ffffh 000000h x64 1mbit or 32 kdouble-words 1fffffh 1f8000h 1mbit or 32 kdouble-words 00ffffh 008000h 1mbit or 32 kdouble-words 007fffh 000000h x64 M58LW064a, M58LW064b word (x16) organisation address lines a1-a22 M58LW064b double-word (x32) organisation address lines a2-a22 (a1 is don't care) organisation memory control is provided by chip enable e, out- put enable g and write enable w inputs. a latch enable l input latches an address for both read and write operations. the burst clock k and the burst address advance b inputs synchronize the memory to the microprocessor during burst read. reset/power-down rp is used to reset all the memory circuitry, excluding the block protection bits, and to set the chip in deep power down mode. erase and program operations are controlled by an internal program/erase controller (p/e.c.). a status register data output on dq7 provides a ready/busy signal to indicate the state of the p/ e.c. operations. a ready/busy rb output also in- dicates the completion of the internal algorithms. a valid data ready r output indicates the memory data output valid status during the synchronous burst mode operations. a word organisation word input selects the x16 or x32 data width for the M58LW064b. for the x16 only organisation of the M58LW064a or the x16 organisation of the M58LW064b the address lines are a1-a22 and the data input/output is on dq0- dq15. for the x32 organisation of the M58LW064b the address lines are a2-a22 and the data input/output is dq0-dq31. memory blocks the device has a uniform block architecture with an array of 64 separate blocks of 1mbit each. the memory features a software erase suspend of a block allowing read or programming within any other block. a suspended erase operation can be resumed to complete block erasure. a program suspend operation on a block allows reading only within any other block. a suspend program opera- tion can be resumed to complete programming. at any moment of the sequence the status register indicates the status of the operation. each block is erased separately. an erase or pro- gram operation is managed automatically by the p/e.c. individual block protection against program or erase provides additional data security. all blocks are protected during power-up. a software instruction is provided to cancel all block protec- tion bits simultaneously in an application and a higher level input on rp can temporarily disable the protection mechanism. a software instruction is provided to allow protection of some or all of the blocks in an application. all program or erase op- erations are blocked when the program/erase en- able input v pp is low.
M58LW064a, M58LW064b 8/53 bus operations the following operations can be performed using the appropriate bus configuration: asynchronous read array read electronic signature read block protection read status register read query write output disable standby reset/power-down synchronous address latch burst read burst read suspend burst read interrupt burst read resume burst address advance see tables 3, 4, 5, 6 and 7. command interface instructions, made up of commands written in cy- cles, can be given to the program/erase controller (p/e.c.) by writing to the command interface (c.i.). at power-up or on exit from power down or if v dd is lower than v lko , the command interface is reset to read array. any incorrect command will reset the device to read array. any improper com- mand sequence will cause the status register to report the error condition and the device will de- fault to read status register. the internal program/erase controller (p/e.c.) automatically handles all timing and verification of the program and erase operations. the status register information p/ecs on dq7 can be read at any time, during programming or erase, to mon- itor the progress of the operation. table 3. asynchronous bus operations (1) note: 1. x = don't care v il or v ih . high = v ih or v hh . 2. ? = need to check with designers - x or v il ??? operation e g w rp l dq0-dq31 read array v il v il v ih high x data output read electronic signature or block protection status v il v il v ih high x manufacturer or device code output block protection status read status p/e.c. active v il v il v ih high x status register output read query v il v il v ih high x cfi query output write v il v ih v il high v il data input output disable v il v ih v ih high x high z standby v ih x x high x high z reset/power-down x x x v il x high z
9/53 M58LW064a, M58LW064b table 4. synchronous burst read operations (1) note: 1. x = don't care, v il or v ih . 2. ? need to check with designers for various x and clock _/ definitions table 5. asynchronous read electronic signature operation note: 1. for M58LW064b, a1 = dont'care table 6. M58LW064a cfi block protection status query operation (1) note: 1. x = dont'care, v il or v ih . table 7. M58LW064b cfi block protection status query operation (1) note: 1. x = dont'care, v il or v ih . operation e g rp k l b a1-a22 dq0-dq31 address latch v il v ih v ih _/ v il v ih addess input burst read v il v il v ih _/ v ih v ih data output burst read suspend v il v ih v ih x v ih v ih high z burst read interrupt (e) v ih x v ih x v ih v ih high z burst read interrupt (rp) x x v il x x x high z burst read resume v il v il v ih _/ v ih v il data output burst address advance v il v ih v ih _/ v ih v il high z no data output burst address advance with valid data output v il v il v ih _/ v ih v il data output code device e g w a22-a1 a22-a2 dq7-dq0 manufacturer all v il v il v ih 00000h 00000h 20h device M58LW064a v il v il v ih 00001h 17h M58LW064b (1) v il v il v ih 00001h 14h block status e g w a1 a2 a3-a16 a17-a22 dq7-dq0 protected v il v il v ih v ih v ih x block address 01h unprotected v il v il v ih v ih v ih x block address 00h block status e g w a1 a2 a3 a4-a16 a17-a22 dq7-dq0 protected v il v il v ih x v ih v ih x block address 01h unprotected v il v il v ih x v ih v ih x block address 00h
M58LW064a, M58LW064b 10/53 signal descriptions see figure 1 and table 1. address inputs (a1-a22). a1 is used to select between the high and low word in the x16 config- uration of the M58LW064a or b. for the M58LW064b a1 is not used in the x32 mode. when chip enable e is at v il the address bus is used to input addresses for the memory array in read mode, or addresses for the data to be pro- grammed, or to input addresses associated with commands to be written to the command inter- face. the address latch is transparent when latch enable l is at v il . the address inputs for the memory array are latched on the rising edge of chip enable e or latch enable l or write enable w, whichever occurs first in a write operation. the address is also internally latched in the command for an erase or program instruction. data inputs/outputs (dq0-dq31). input data for a write to buffer and program operation and for writing commands to the command interface are latched on the rising edge of write enable w or chip enable e, whichever occurs first. when chip enable e and output enable g are at v il data is output from the array, the electronic signature - the manufacturer and the device code - the block protection status, the cfi query infor- mation or the status register. the data bus is high impedance when the device is deselected with chip enable e at v ih , output enable g is at v ih or rp is at v il . when the p/e.c. is active the status register content is output on dq0-dq7 and dq8- dq31 are at v il . chip enable (e). the chip enable e input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable e at v ih deselects the memory and reduces the power con- sumption to the standby level. output enable (g). the output enable g gates the outputs through the data output buffers during a read operation. when output enable g is at v ih the outputs are high impedance. output enable g can be used to suspend the data output in a burst read operation. write enable (w). the write enable w input controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of w (see also latch enable l). reset/power-down (rp). the reset/power- down rp input provides a hardware reset of the memory and power-down functions. reset/power- down of the memory is achieved by pulling rp to v il for at least t plph . writing is inhibited to protect data, the command interface and the p/e.c. are reset. the status register information is cleared and power consumption is reduced to deep power- down level. the device acts as deselected, that is the data outputs are high impedance. when rp rises to v ih , the device will be available for new operations after a delay of t phqv and will be configured by default for asynchronous ran- dom read. the minimum delay required to access the command interface by a write cycle is t phwl . if the rp input is activated during a block erase, a write to buffer and program or a block protect/un- protect operation the cycle is aborted and data is altered and may be corrupted. the ready/busy output rb may remain low for a maximum time of t plph +t phrh beyond the completion of the reset/ power-down rp pulse. applying the higher voltage v hh to the reset/pow- er-down input rp temporarily unprotects and en- ables erase and program operations on all blocks. thus it acts as a hardware block unprotect input. in an application, it is recommended to associate rp to the reset signal of the microprocessor. oth- erwise, if a reset operation occurs while the device is performing an erase or program cycle, the flash memory may output the status register in- formation instead of being re-initialized to the de- fault asynchronous random read. latch enable (l). latch enable l latches the ad- dress bits a1-a22 on its rising edge for the asyn- chronous latch enable controlled read or write, or synchronous burst read operations. the ad- dress latch is transparent when latch enable l is at v il . latch enable l must remain at v il for asyn- chronous random read and write operations.
11/53 M58LW064a, M58LW064b burst clock (k). the burst clock k is used only in burst mode. it is the fundamental synchronous signal that allows internal latching of the address from the address bus, together with latch enable l; increment of the internal address counter in as- sociation with burst address advance b; and to in- dicate valid data on the external data bus. all these operations are synchronously controlled on the valid edge of the burst clock k, which can be selected to be the rising or falling edge depending on the definition in the burst configuration regis- ter. for asynchronous read or write, the burst clock k input level is don't care. for synchronous burst read the address is latched on the first valid clock edge when latch enable l is at v il , or the rising edge of latch enable l, whichever occurs first. burst address advance (b). burst address ad- vance b enables increment of the internal address counter when it falls to v il during synchronous burst read. it is sampled on the last valid edge of the burst clock k at the expiry of the x-latency time. if sampled at v il , new data will be output on the next burst clock k valid edge (or second next depending on the definition in the burst configura- tion register). if it is at v ih when sampled, the pre- vious data remains on the data outputs. the burst address advance b may be tied to v il . ready (r). the valid data ready r is an output signal used during synchronous burst read. it in- dicates, at the valid clock edge (or one cycle be- fore depending on the definition in the burst configuration register), if valid data is ready on the data outputs. new data outputs are valid if valid data ready r is at v ih , the previous data outputs remain active if valid data ready r is at v il . in all operations except burst read, valid data ready r is at v ih . it may be tied to other compo- nents with the same valid data ready r signal to create a unique system ready signal. the valid data ready r output has an internal pull-up resis- tor of around 1 m w powered from v ddq , designers should use an external pull-up resistor of the cor- rect value to meet the external timing require- ments for r going to v ih . word organisation (word). the word organi- sation word input is present only on the M58LW064b and selects x16 or x32 organisation. the word input selects the data width as word wide (x16) or double-word wide (x32). when word is at v il , word-wide x16 width is selected and data is read and programmed on dq0-dq15, dq16-dq31 are at high impedance and a1 is the lsb address. when word is at v ih , the double- word wide x32 width is selected and the data is read and programmed on dq0-dq31, and a2 is the lsb address. ready/busy (rb). ready/busy rb is an open- drain output and gives the internal state of the p/ e.c. when ready/busy rb is at v il the device is busy with a program or erase operation and it will not accept any additional program or erase in- structions except for the program or erase sus- pend instructions. when a program or erase suspend is given the rb signal rises to v ih , after a latency time, to indicate that the command inter- face is ready for a new instruction. when rb is at v ih , the device is ready for any read, program or erase operation. ready/busy rb is also at v ih when the memory is in erase/program suspend or standby modes. program/erase enable (v pp ). program/erase enable v pp automatically protects all blocks from programming or erasure when at v il . supply voltage (v dd ). the supply voltage v dd is the main power supply for all operations (read, program and erase). input/output supply voltage (v ddq ). the in- put/output supply voltage v ddq is the input and output buffer power supply for all operations (read, program and erase). ground (v ss ). ground v ss is the reference for all the voltage measurements.
M58LW064a, M58LW064b 12/53 device operations see tables 5, 6, 7 and 10. address latch. an address is latched on the ris- ing edge of the latch enable l input for asynchro- nous latch enable controlled read. for asynchrouns latch enable controlled write, the address is latched on the rising edge of chip en- able e, write enable w or latch enable l, which- ever occurs first. for synchronous burst read the address is latched on the first valid burst clock k edge when latch enable l is at low, or on the rising edge of latch enable l, whichever occurs first. asynchronous random read. asynchronous random read outputs the contents of the array. both chip enable e and output enable g must be low in order to read the output of the memory. by first writing the appropriate instruction, the electronic signature (rsig), the status register (rsr), the read query instruction (rcfi) or the block protection status (rsig) can be read. asynchronous random read is the default read mode which the device enters on power-up or on return from reset/power-down. asynchronous page read. asynchronous page read may be used for random or latch en- able controlled reads of the array, which are per- formed independent of the burst clock signal. a page has a size of 4 words or 2 double-words and is addressed by the address inputs a1 and a2 in the x16, or a2 only in the x32 organisation. data is read internally and stored in the page buffer. the page read starts when both chip enable e and output enable g are low. the first data is in- ternally read and is output after the normal access time t avqv . successive words or double-words can be read with a much reduced access time of t avqv1 by changing only the low address bits. synchronous burst read. the memory sup- ports different types of burst access using a burst configuration register to configure the burst type, length and latency. in continuous burst read, one burst read operation can access the entire memory sequentially by keeping the burst address advance b low for the appropriate number of clock cycles. at the end of the memory address space the burst read restarts from the beginning at address 000000h. synchronous burst read is activated when the burst clock k input is clocking and chip enable e is low. the burst start address is latched and loaded into the internal burst address counter on the valid burst clock k edge (rising or falling de- pending on the m6 bit value for the burst clock edge configuration in the burst configuration register) when latch enable l is low, or upon the rising edge of latch enable l when the burst clock k is valid. after an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on m9 bit value de- fined in the burst configuration register). the burst address advance b input controls the mem- ory burst output. the second burst output is on the next clock valid edge after the burst address ad- vance b has been pulled low. the valid data ready output signal r monitors if the memory burst boundary is exceeded and the burst controller of the microprocessor needs to in- sert wait states. when valid data ready r is low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if burst address advance b is low. synchronous burst read will be suspended when burst address advance b is high. the valid data ready signal r may be configured (by bit m8 of burst configuration register) to be valid immedi- ately at the valid clock edge or one data cycle be- fore the valid clock edge. to increase the data throughput the device has been built with an internal pipelined architecture allowing the user to enter a burst read input com- mand and the next starting address location to be read while the device is filling the output data bus with its current burst content. this pipelined struc- ture is intended to produce no wait-states on the output data bus for successive burst read mode operations. asynchronous and latch enable controlled write. asynchronous write is used to give com- mands to the command interface for instructions to the memory or to latch addresses and input data to be programmed. to perform any instruction the command interface is activated starting with a write cycle. a write cycle is also required give the instruction to clear the status register informa- tion. two write cycles are needed to define the block erase and the write to buffer and program instructions. the first write cycle defines the in- struction selection and the second indicates the appropriate block address to be erased for the block erase instruction, or the address locations to program with the number of words or double- words in the write to buffer and program instruc- tion. an asynchronous write is initiated when chip en- able e, write enable w and latch enable l are low with output enable g high. commands and input data are latched on the rising edge of chip enable e or write enable w, whichever occurs first. for an asynchronous latch enable con- trolled write the address is latched on the rising edge of latch enable l, write enable w or chip enable e, whichever occurs first.
13/53 M58LW064a, M58LW064b data to be programmed in the array is internally latched in the write buffer before the programming operation starts and a minimum of 4 words or 2 double-words need to be programmed in the same sequence and must be contained in the same address location boundary defined by a1 to a2 for the x16 and a2 for the x32 organisation. write operations are asynchronous and the burst clock signal k is ignored during a write operation. output disable. the data outputs are high im- pedance when the output enable g is high. standby. the memory is in standby when chip enable e goes high and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic low power. after a short time of bus inactivity (no chip enable e, latch enable l or ad- dress transitions) the chip automatically enters a pseudo-standby mode where consumption is re- duced to the automatic low power standby value, while the outputs may still drive the bus. the auto- matic low power feature is available only for asynchronous read. power-down. the memory is in power-down when reset/power-down rp is low. the power consumption is reduced to the power-down level and the outputs are high impedance, independent of the chip enable e, output enable g or write enable w inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of the memory. the electronic signature is output by giving the rsig instruction. the manufacturer code is output when all the ad- dress inputs are low. the device code is output when a1 (M58LW064a) or a2 (M58LW064b) in- put is high, the other pins a3-a22 must be low. the codes are output on dq0-dq7. a return to read mode is achieved by writing the read array instruction. initialization the device must be powered up and initialized in a predefined manner. procedures other than specified may result in undefined operation. power should be applied simultaneously to v dd and v ddq with the rp input held low. when the supplies are stable rp is taken high. the output enable g, chip enable e and write enable w in- puts should also be held high during power-up. the memory will be ready to accept the first in- struction after the power-up time t pur . the device is automatically configured for asynchronous ran- dom read at power-up or after leaving reset/ power-down. burst configuration register see tables 8, 9, 10 and 11. the synchronous burst read, asynchronous random read, asynchronous latch enable con- trolled read are selected using the burst configu- ration register. for synchronous read the register defines the x and y latencies, valid data ready signal timing, burst type, valid clock edge and burst length. the burst configuration register is programmed using the set burst configuration register (sbcr) instruction and will retain the stored information until it is programmed again or the device is reset or goes into the reset/power-down. the burst configuration register bits m2-m0 specify the burst length (1, 2, 4, 8 or continuous); bit m3 specifies asynchronous random read or asynchronous latch enable controlled read; bits m4 and m5 are not used; bit m6 specifies the rising or falling burst clock edge as valid; bit m7 specifies the burst type (sequential or interleaved); m8 specifies the valid data ready output period; bit m9 specifies the y-latency; bit m10 is not used; m14-m11 specify the x-latency; and bit m15 se- lects between synchronous burst read or asyn- chronous read. m10, m5 and m4 are reserved for future use. m15 read select the device features three kinds of read operation: asynchronous random read, asynchronous latch enable controlled read and synchronous burst read. page read may be used in either of the asynchronous read operations. the burst configuration register bit m15 selects between synchronous burst and asynchronous read. m14 - m11 and m9 x and y latency. the values of x and y are used to define the burst latency for the data sequence. the x-latency de- fines the number of clock cycles before the output of the first data from the clock edge that latches the address. the x-latency can be set from 7 to 16. a value of 7 is only valid for continuous burst. the y-latency is the number of clock cycles need- ed to output the next data from the burst register, following the first data output. the latency can be set to 1 or 2 clock cycles. the minimum x-latency value to consider de- pends on the burst clock k signal frequency. the burst performance in terms of frequency is listed in table 11 and indicates the minimum x-latency and y-latency values (x.y.y.y) related to the burst type, burst length and x16 or x32 organisation.
M58LW064a, M58LW064b 14/53 m8 valid data ready r signal configuration. the valid data ready r output signal indicates when valid data is on the data outputs synchro- nous with the valid burst clock egde. it can be as- serted by the device synchronously with the valid clock edge or one clock cycle before. m7 burst type. accesses within a given burst may be pro- grammed to be either sequential or interleaved. this is referred to as the burst type and is selected by the burst configuration register m7 bit. the ac- cess order within a burst is determined by the burst length, the burst type and the starting ad- dress (see table 8). m6 valid clock edge configuration. all the synchronous operations such as burst read, output data or ready signal validation can be synchronized on the valid rising or on the falling edge of the burst clock signal k. m2 - m0 burst length. synchronous reads have a programmable burst length, set using the m2 - m0 bits of the burst con- figuration register. the burst length corresponds to the maximum number of words or double- words that can be output. burst lengths of 1, 2, 4 or 8 are available for both the sequential and in- terleaved burst types, and a continuous burst is available for the sequential type. the burst length of 8 is not available in the x32 configuration. when a read command is issued, a block of words or double-words equal to the burst length is selected. all accesses for that burst take place within this block, meaning that the burst wraps within the burst block if a boundary is reached. if a continuous burst read has been initiated the device will output data synchronously. depending on the starting address of the read, the device ac- tivates the valid data ready r output to indicate that it needs a delay to complete the internal read operation before outputing data. if the starting ad- dress is aligned to a four word boundary the con- tinuous burst mode will run without activating the valid data ready r output. if the starting address is not aligned to a four word boundary, valid data ready r is activated at the beginning of the con- tinuous burst read to indicate that the device needs an internal delay to read the content of the four successive words in the array. pipelined burst read. an overlapping burst read operation is possible. that is, the address and data phases of consecu- tive synchronous read operations can be over- lapped by several clock cycles. this is done by applying a pulse on latch enable l input to latch a new address before the completion of the data output of the current cycle. this reduces or avoids wait-states in the data output for the burst read mode. the minimum clock edge number for the following read sequence must be six before the last data output of the previous read cycle. the pipelined burst read mode is available in the x16 organisation for both burst length definitions of four and eight, and in the x32 organisation for the burst length of four. it is not possible for a burst length of one or two.
15/53 M58LW064a, M58LW064b table 8. burst type definition (x16 mode) table 9. burst type definition (x32 mode) burst length starting address (binary) sequential (decimal) interleaved (decimal) a3-a2-a1 2 0-0-0 0-1 0-1 0-0-1 1-0 1-0 4 0-0-0 0-1-2-3 0-1-2-3 0-0-1 1-2-3-0 1-0-3-2 0-1-0 2-3-0-1 2-3-0-1 0-1-1 3-0-1-2 3-2-1-0 8 0-0-0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-0-1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0-1-0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0-1-1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1-0-0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1-0-1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1-1-0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1-1-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 burst length starting address (binary) sequential (decimal) interleaved (decimal) a2-a1 2 0-0 0-1 0-1 0-1 1-0 1-0 4 0-0 0-1-2-3 0-1-2-3 0-1 1-2-3-0 1-0-3-2 1-0 2-3-0-1 2-3-0-1 1-1 3-0-1-2 3-2-1-0
M58LW064a, M58LW064b 16/53 table 10. burst configuration register (1) note: 1. the bcr defines both the read mode and the burst configuration. 2. synchronous burst length is defined as word or double-word, the data bus width depends only on the word input. asynchronous page read is two words or one double-word. 3. a burst length of 8 is not available for x32 organisation. 4. at f k > 50mhz when x-latency = 10 or 12, y-latency = 2 independent of the value of m9. at f k = 66mhz when x-lantency = 14 or 16, y-latency = 2 indepedent of the value of m9. 5. latency 7 valid only for continuous burst. otherwisw latency = 8. 6. latency 10 valid only for continuous burst. otherwisw latency = 12. 7. latency 11 valid only for continuous burst. otherwisw latency = 12. 8. latency 14 valid only for continuous burst. otherwisw latency = 16. bcr mode bit description value description m15 read select 0 synchronous burst read 1 asynchronous read m14-m11 x-latency (4) 0001 reserved 0010 7, only for f k = 33mhz (5) 0011 8, only for f k = 33mhz 0100 9, only for f k = 33mhz 0101 10, only for f k = 50mhz (6) 0110 11, only for f k = 50mhz (7) 1001 12, only for f k = 50mhz 1010 13, only for f k = 50mhz 1011 14, only for f k = 66mhz (8) 1101 16, only for f k = 66mhz m9 y-latency (4) 0 one burst clock cycle 1 two burst clock cycles m8 valid data ready 0 r valid low during valid burst clock edge 1 r valid low one data cycle before valid burst clock edge m7 burst type 0 interleaved 1 sequential m6 valid clock edge 0 falling burst clock edge 1 rising burst clock edge m3 asynchronous 0 random read 1 latch enable controlled read m2-m0 burst length (2) 100 1 word or double-word 101 2 words or double-words 001 4 words or double-words 010 8 words or double-words (3) 111 continuous
17/53 M58LW064a, M58LW064b table 11. burst performance (1) note: 1. the burst length of 8 is not available in the x32 organisation. x-y latencies (minimum) clock frequency x16 organisation x32 organisation x16 organisation x32 organisation sequential interleaved sequential interleaved v dd = 2.7 to 3.6v burst length: 1,2,4,8 burst length: 1,2,4,8 burst length: 1,2,4 burst length: 1,2,4 continuo us burst 8.1.1.1 8.1.1.1 8.1.1.1 8.1.1.1 7.1.1.1 7.1.1.1 33 mhz 12.1.1.1 12.1.1.1 12.1.1.1 12.1.1.1 10.1.1.1 10.1.1.1 50 mhz t.b.a. t.b.a. t.b.a. t.b.a. t.b.a. t.b.a. 60 mhz 16.2.2.2 16.2.2.2 16.2.2.2 16.2.2.2 14.2.2.2 14.2.2.2 66 mhz
M58LW064a, M58LW064b 18/53 read electronic signature instruction (rsig). an electronic signature can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of the device. the electronic signature instruction consists of a first write cycle giving the command 90h, followed by a subsequent read which will output the manu- facturer code, the device code or the block pro- tection status. the manufacturer code is output when all the address inputs are at vil. the device code is output when a1 (for the M58LW064a) or a2 (for the M58LW064b) is at v ih , with all other address inputs at v il . the code is output on dq0- dq7 with dq8-dq31 at v il . the rsig instruction also allows access to the block protection status for the selected block ad- dress defined by a17-a22. after the read elec- tronic signature (rsig) command, a1-a2 (for the M58LW064a) or a2-a3 (for the M58LW064b) are set to v ih , while a17-a22 define the address of the block to be queried. a read operation outputs 01h if the block is protected and 00h if the block is not protected. read query instruction (rcfi). the read que- ry instruction is initiated with one write cycle giving the command 98h at any address. subsequent read operations, depending on the address speci- fied, will output the block status information, the common flash interface id string, the system in- terface information, the device geometry config- uration or stmicroelectronics specific query information. the address mapping for the informa- tion is shown in table 14. read status register instruction (rsr). the read status register instruction consists of one write cycle giving the command 70h. subsequent read operations, independent of the address, out- put the status register information that indicates if a block erase, write to buffer and program, block protect or block unprotect operation has been completed successfully. see table 12. once initi- ated the rsr instruction is active until another command is given to the command interface. for asynchronous read, the status register in- formation is present on the output data bus when both chip enable e and output enable g are low. in synchronous burst read the status register in- formation is output on the data bus dq1-dq7 when latch enable l goes high or on a valid burst clock k edge (m6 in the burst configuration reg- ister specifies the rising or falling valid clock edge) when latch enable l is low. an interactive update of the status register information is possible by toggling output enable g, or when the device is instructions and commands the command interface latches commands writ- ten to the memory. instructions are made up of one or more commands to perform: read array (rd), read electronic signature or read block pro- tection (rsig), read status register (rsr), read query (rcfi), clear status register (clrs), block erase (ee), write to buffer and program (wbpr), erase/program suspend (pes), erase/program resume (per), set burst configuration register (sbcr), block protect (bp), and block unprotect (bu). instructions (see table 12) are composed of a first write sequence followed by either a second write sequence needed to confirm an erase or program instruction or by a read operation in order to read data from the array, the electronic signature, the block protection information, the cfi or the status register information. the instructions for write to buffer and program and block erase operations consist of two commands written into the memory command interface (c.i.) that start the automatic p/e.c. operation. erasure of a memory block may be suspended, in order to read data from or to pro- gram data in an other block, and then be resumed. write to buffer and program operation may be suspended, in order to read data from another block, and then be resumed. at power-up the command interface is reset to read array. the appropriate instruction must be given to access read query (rcfi), read elec- tronic signature or block protection status (rsig) or read status register (rsr). reading of the memory array is disabled during a block protect/ unprotect (bp, bu), a block erase (ee) or a write to buffer and program (wbpr) instruction. a erase/program suspend instruction (pes) must be given to read under these conditions. read array instruction (rd). the read array instruction consists of one write cycle giving the command ffh. subsequent read operations will read the array content addressed and output the corresponding data. the read array instruction remains active until another one is written into the command interface. at power-up or at the exit of the reset/power-down mode, the device is by de- fault initialised to read array.
19/53 M58LW064a, M58LW064b table 12. instructions mne- monic instruction cycles 1st cycle 2nd cycle comments op . address data op. add ress data rd read array 1+ write x ffh read array until a new write cycle is initiated rsig read manufacturer code 2 write x 90h read 000000h 20h read manufacturer code rsig read device code or block protection status 2 write x 90h read iah idh read device id code rsr read status register 2 write x 70h read x srdh srd = status register data rcfi read query 2 write x 98h read qah qdh qa = query address qd = query data clrs clear status register 1 write x 50h ee block erase 2 write x 20h write bah d0h ba = block address to erase wbpr write to buffer and program 2 write bah e8h write bah n ba = block address n = word/double-word count argument pes erase/ program suspend 1 write x b0h per erase/ program resume 1 write x d0h confirm command for write to buffer and program instruction sbcr set burst configuration register 2 write bcrh 60h write bcrh 03h bcr = burst configuration register bp block protect 2 write bah 60h write bah 01h keep the block protect bit active of the selected block ba = block address bu block unprotect 2 write x 60h write x d0h clear all the block protect bits simultaneously dis-activated by chip enable e high and then re- activated by chip enable e and output enable g low, during an erase or program operation. the content of status register may also be read at the completion of an erase/program and/or suspend operation.during a block erase, write to buffer and program, block protect or block unprotect in- struction, dq7 indicates the p/e.c. status. it is val- id until the operation is completed or suspended, dq0-dq7 output the status register content and dq8-dq31 are low.
M58LW064a, M58LW064b 20/53 table 13. status register definition note: 1. dq0-dq6 are high impedance when dq7 is indicating that the part is busy. status register p/ecs bit7 indicates the p/e. c. status, check during program or erase, and on completion before checking bit4 or bit5 for program or erase success. 2. dq6 indicates the erase suspend status. on an erase suspend instruction p/ecs and ess bits are set to '1'. ess bit remains '1' until an erase resume instruction is given. 3. erase status, es bit5 is set to '1' if the p/e. c. has applied the maximum number of erase pulses to the block without achieving an erase verify. 4. program status, ps bit4 is set to '1' if the p/e.c . has failed to program a word or double-word. 5. dq2 indicates the program suspend status. on a program suspend instruction p/ecs and pss bits are set to '1'. pss bit remains '1' until an program resume instruction is given. 6. dq1 defines the status of an erase or write to buffer and program instruction defined in a protected block. rp pin must be held at v hh to temporarily override the block protect feature once it has been enabled. 7. dq5 and dq4 simultaneously at '1' after an erase or block unprotect instruction indicates that an improper command was entered. mnemonic dq function status p/ecs dq7 p/e.c. status 1 = ready 0 = busy (1) ess dq6 erase suspend status 1 = block erase suspended 0 = block erase in progress/completed (2) es dq5 erase/block unprotect status (7) 1 = error in block erase operation or block unprotect 0 = successful block erase operation or block unprotect (3) ps dq4 write to buffer and program/block protect status (7) 1 = error in write to buffer and program, block protect (4) 0 = write to buffer and program, block protect completed successfully dq3 not used pss dq2 program suspend status 1 = program suspended 0 = program operation in progress/completed (5) eppb dq1 erase/write to buffer and program in a protected block 1 = error in the defined operation 0 = operation in progress/completed (6) dq0 not used
21/53 M58LW064a, M58LW064b clear status register instruction (clrs). the clear status register instruction is given with the command 50h at any address location. it is a reset instruction that resets dq5, dq4 and dq1 in the status register to '0'. if an operation such as block erase, write to buff- er and program block protect or block unprotect has failed, the p/e.c. will set dq5, dq4 or dq1 to '1' depending on the failure detected (see table 12, status register definition). the clear status register instruction must be given before restart- ing any corrective erase/program instruction. the clrs instruction should be given also after an erase or program suspend instruction failure or before a resume instruction if the previous in- struction has been detected to have failed. it is also a software reset solution that may allow the execution of several operations such as cumulat- ed erase or block protect operations of multiple blocks. the clear status register instruction is valid when the p/e.c. is inactive or the device is in a suspend mode and it is also valid independent of the voltage v ih or v hh applied on the rp input. write to buffer and program instruction (wb- pr). the write to buffer and program instruction is used to program the memory array. up to 16 words or 8 double-words can be loaded into the write buffer and programmed into the device. the write to buffer and program instruction is com- posed of three successive steps. the first step is to give the write to buffer and program command, e8h with the selected memory block address where the program operation should occur. the status register dq7 bit then indicates the obuffer availableo status. if the write buffer is not available (indicated by dq7 = 0) then the software can ei- ther continue monitoring dq7 until it transitions to 1, or else re-try later by reloading first the wbpr command, e8h, and then again monitoring the val- ue of dq7. once the owrite buffer availableo condition is valid (indicated by dq7 = 1), the second step is to write the block address again, along with the value n, where n+1 is the number of words (x16 organisa- tion) or double-words (x32 organisation) to be programmed. in the third step, a sequence of n+1 write cycles loads the addresses and data to the write buffer (see boundary constraints below). the addresses must lie between the starting address and the starting address + (n+1). the array must be programmed in 4 word or 2 double-word blocks, which must be aligned with an a2 = a1 = 0 starting address (or a2 = 0 for x32 organisation). invalid data will be flagged and the operation will abort with the status register bits dq4 and dq5 set to 1. the confirm command, d0h (the same as erase/ program resume per instruction) needs to be given immediately after the completion of the write to buffer and program instruction. it represents the last (that is the n+2) write operation. the p/e.c. is enabled only if the whole previous sequence is fully respected. otherwise an invalid command/sequence error will be generated with the status register dq5 and dq4 set to '1'. for additional write to buffer and program operations, after the initial input command the software can check the availability of the write buffer by check- ing dq7 status from the status register. if an error appears during a program sequence, the device will stop its operation and dq4 of the status register will be set to '1' to indicate a pro- gram failure. dq5 will indicate if an error has been detected during a block erase operation. if these bits, dq4 or dq5 are set to '1', the write to buffer and program input command is not accepted by the device until the status register has been cleared. additionally, if the block is protected and v ih M58LW064a, M58LW064b 22/53 block unprotect instruction (bu). the block unprotect instruction bu uses a two-cycle write sequence. all the block protect bits are simulta- neously erased. the block protect bit register is erased by giving the command 60h and then the confirm command d0h, at any address location. the sequence is aborted if the confirm command is not given and the device will output the status register data with dq4 and dq5 set to '1'. block erase instruction (ee). the block erase instruction ee uses a two-cycle command se- quence. the erase setup command 20h is written to any address location. then a second write cycle is given with the block address to be erased and the confirm command d0h. the sequence is aborted if the confirm command is not given and the device will output the status register data with dq4 and dq5 set to '1'. during the execution of the erase cycle by the p/ e.c., the memory accepts only the erase/program suspend instructions. read operations output the status register bits. a complete state of the erase operation is given by the status register bits. erase/program suspend instruction (pes). the block erase or write to buffer and program operations may be suspended by writing the com- mand b0h at any address. the erase/program suspend instruction interrupts the p/e.c. erase or program sequence at a predetermined point in the algorithm. after the suspend command is written the device outputs the status register data. it is possible to read or program data in a block other than the one in which the erase suspend op- eration is effective. it is only possible to read in a block other than the one in which a program sus- pend operation is effective. the suspended erase/ program operation has to be resumed in order to complete the previous erase/program sequence. the erase suspend instruction is accepted only during a block erase operation execution. pro- gram suspend also is valid only during the write to buffer and program instruction execution. block erase or erase/program suspend instructions are ignored if the memory is already in the suspend mode. the suspend instruction may be presented at any time during the execution of a block erase. for a write to buffer and program instruction the sus- pend instruction is accepted only when the p/e.c. is running. the device outputs information about the suspend in the status register information on dq7, dq6 and dq2. if the operation has been completed dq7 = '1' and dq6 = '0' (erase suspend) or dq2 = '0' (program suspend). if the suspend instruction occurred after the p/ e.c. has completed its operation (dq7 = 1, dq6 = 0 and dq2 = 0), the status register infor- mation remains available by toggling output en- able g. no command is accepted by the device with the exception of a read memory array in- struction ffh. after the ffh command is issued, the device is ready for read array (in the mode defined by the last set configuration register is- sued). when a program operation is completed inside a block erase suspend instruction, read array in- struction ffh will reset the device to read array. the erase resume instruction has to be issued to complete the whole sequence. when erase is suspended, the memory will re- spond only to the read array, read electronic signature, read query, read status register, clear status register, erase/program resume and the write to buffer and program instructions. when a write to buffer and program instruction is suspended, the memory will respond only to the read array, read electronic signature, read query, read status register, clear status regis- ter and erase/program resume instructions. erase/program resume instruction (per). if an erase suspend instruction was previously exe- cuted, the erase operation may be resumed by giving the command d0h, at any address. this also serves as the confirm command for the write to buffer and program (wpbr) instruction which is issued after the write buffer loading sequence is completed, and which starts the p/e.c.
23/53 M58LW064a, M58LW064b set burst configuration register (sbcr). this instruction uses two command cycles. the burst configuration setup command 60h is written with the address corresponding to the set burst configuration register content. then in the sec- ond write cycle the address bus a2-a17 specifies the bcr, burst configuration register, informa- tion and the command 03h. the burst length, type, latency, synchronous/asynchronous read mode and clock edge active configuration are defined in that operation. after the command 03h the device will default in the read array mode. status register bits. the p/e.c. status is indi- cated during execution with a ready/busy output available on dq7. any read attempt during pro- gram or erase command execution will automati- cally update the status register bits. the p/e.c. automatically sets bits dq1, dq2, dq4, dq5, dq6 and dq7. the bit dq0 is reserved for future use and should be masked. it is not necessary to specify an address when the status register bits are read. the status register is a static memory register that is reset when rp signal is active or on a power-down operation. power supply power down. the memory provides reset/pow- er-down control using the input rp. when reset/ power-down rp is pulled to vil the supply current drops to typically less than 1 m a, the memory is de- selected and the outputs are at high impedance. if rp is pulled to v il during a program or erase op- eration, this operation is aborted after a latency time of t plrh and the memory content is no longer valid. reset, power-down and power-up see fig 16. the device is reset if the reset/power-down rp input is pulled to v il for longer than tplph. if the device was in a read mode then it will recover from reset after a time of t phqv to give valid data output. if the device was executing an erase or program operation, with the p/e.c. active, the op- eration will abort in a time of t plrh maximum. the device will be ready to accept new write com- mends after a time of t phwl or t phel . the supply voltages v dd and v ddq must be high a time t vdhel or t vdhwl before a read or write cy- cle. at first power up reset/power-down should be held low for a time of t vdhph after v dd and v ddq are high. the device will be ready to accept its first read or write commands after a time of t pur or t puw . common flash interface - cfi the introduction to the jedec cfi specification rel. 1.2 quotes, othe common flash interface (cfi) specification outlines a device and host sys- tem software interrogation handshake which al- lows specific software algorithms to be used for entire families of devices. this allows device-inde- pendent, jedec, id independent and forward- and backward-compatible software support for the specified flash device families. it allows flash ven- dors to standardize their existing interfaces for long-term compatibility.o the cfi query instruction rcfi describes how the device enters the cfi query mode which enables information to be read from the flash memory. cfi allows a system software to query the flash device to determine various electrical and timing parame- ters, density information and functions supported by the device. cfi allows the system to easily in- terface to the flash memory, to learn about its fea- tures and parameters, enabling the software to upgrade itself when necessary. query structure overview the flash memory displays the cfi data structure when the cfi query instruction rcfi is issued. a list of the main subsections is detailed in tables 15 to 19.
M58LW064a, M58LW064b 24/53 table 14. query structure overview table 15. cfi - query address and data output in the x16/x32 organization note: 1. the x8 or byte address mode is not available. 2. in the x16 organization, the value of the address location of the cfi query is independent of a1 pad (M58LW064b). 3. query data are always presented on the lowest order data outputs (dq7-dq0) only. others data (dq31-dq8) are set to '0'. 4. for M58LW064b, a1 = don't care. offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash device layout p(h) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (ba+3)h block status register block-related information address (4) a22-a1 (M58LW064a) a22-a2 (M58LW064b) data instruction 10h 51h oqo 51h; oqo query ascii string 52h; oro 59h; oyo 11h 52h oro 12h 59h oyo 13h 20h primary vendor: command set and control interface id code 14h 00h 15h 31h primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 31h alternate algorithm extended query address table 1ah 00h
25/53 M58LW064a, M58LW064b table 16. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volt and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volt while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. 4. for M58LW064b, a1 = don't care. table 17. device geometry definition note: 1. for M58LW064b, a1 = don't care. address (4) a22-a1 (M58LW064a) a22-a2 (M58LW064b) data instruction 1bh 27h (1) v cc min, 2.7v 1ch 36h (1) v cc max, 3.6v 1dh 00h (2) v pp min not available 1eh 00h (2) v pp max not available 1fh 00h (3) 2 n ms word, dword prog. typical time-out 20h x07h 2 n ms, typical time out for max buffer write 21h 0ah 2 n ms, erase block typical time-out 22h 00h (3) 2 n ms, chip erase time-out typ. not available 23h 00h (3) 2 n times typ. for word dword time-out max not available 24h 04h 2 n times typ. for buffer write time-out max 25h 04h 2 n x typ. individual block erase time-out maximum 26h 00h (3) 2 n times typ. for chip erase max time-out not available address (1) a22-a1 (M58LW064a) a22-a2 (M58LW064b) data instruction 27h 17h 2 n nb. of bytes device size 28h 01h. device interface sync./async. 29h 00h organisation sync./async. 2ah 05h page size in bytes, 2 n 2bh 00h 2ch 01h bit7-0 = nb of erase block region 2dh 3fh number (n-1) of erase blocks of identical size; n=64 2eh 00h 2fh 00h x times 256 bytes per erase block (128k bytes) 30h 02h
M58LW064a, M58LW064b 26/53 table 18. block status register (see also, table 6 and 7 in the datasheet) note: 1. ba specifies the block address location, i-e, a22-a17. 2. not supported. table 19. extended query information note: 1. bit7 to bit4 are coded in hexadecimal and scaled in volt while bit3 to bit0 are in binary code decimal and scaled in mv. 2. not supported. address a22-a2 data (hex) x32 organization selected block information (ba+3)h (1) bit0 0 block unlocked 1 block locked bit1 0 last erase operation ended successfully (2) 1 last erase operation not ended successfully (2) bit7-2 0 reserved for future features M58LW064b - x32 M58LW064a - x16 M58LW064b - x16 organization instruction address offset address a22-a2 data (hex) x32 organization address a22-a1 data (p)h 31h 50h opo 62h, 63h 50h query ascii string - extended table (p+1)h 32h 52h oro 64h, 65h 52h (p+2)h 33h 49h oyo 66h, 67h 49h (p+3)h 34h 31h 68h, 69h 31h major version number (p+4)h 35h 31h 6ah, 6bh 31h minor version number (p+5)h 36h 0eh 6ch, 6dh 0eh optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, lock/unlock supported (1=yes) bit4, queue erase supported (0=no) bit 31-5 reserved for future use (p+6)h 37h 00h 6eh, 6fh 00h optional features (p+7)h 38h 00h 70h, 71h 00h (p+8)h 39h 00h 72h, 73h 00h (p+9)h 3ah 01h 74h, 75h 00h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h 3bh 00h (2) 76h, 77h 00h (2) block status register mask (p+c)h 3ch 33h 78h, 79h 33h v cc optimum program/erase voltage conditions (p+d)h 3dh 50h 7ah, 7bh 50h v pp optimum program/erase voltage conditions (p+e)h 3eh 00h 7ch, 7dh 00h reserved for future use (p+f)h 3fh 00h 7dh, 7fh 00h reserved for future use
27/53 M58LW064a, M58LW064b figure 8. ac testing load circuit ai03229 1.3v out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test figure 7. ac testing input output waveform note: v dd =v ddq . ai00610 v ddq 0v v ddq /2 table 20. ac measurement conditions clock rise and fall times 3ns input rise and fall times 4ns input pulses voltages 0v to v ddq input and output timing ref. voltages v ddq /2 table 21. capacitance (t a =25 c, f = 1 mhz) symbol parameter test condition typ max unit c in input capacitance v in =0v 68pf c out output capacitance v out =0v 812pf
M58LW064a, M58LW064b 28/53 table 22. dc characteristics (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. 2. biasing rp pin to v hh is allowed for a maximum cumulative period of 80 hours. 3. current increases to i cc +i cc5 during a read operation. symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 m a i lo output leakage current 0v v out v ddq 5 m a i cc supply current (random read) e=v il ,g=v ih ,f add = 6mhz 30 ma i ccb supply current (burst read) e=v il ,g=v ih ,f clock = 50mhz 50 ma i cc1 supply current (standby) e=v dd 0.2v, rp = v dd 0.2v 40 ma supply current (auto low-power) 2 ma i cc2 supply current (reset/power-down) rp = v ss 0.2v 1 m a i cc3 (1) supply current (program or erase, set lock bit, erase lock bit) write to buffer and program block erase in progress 30 ma i cc4 supply current (erase/program suspend) e=v ih 40 m a v il input low voltage 0.5 0.4 v v ih input high voltage v ddq 0.4 v ddq + 0.3 v v ol output low voltage i ol = 100 m a 0.1 v v oh output high voltage cmos i oh = 100 m av ddq 0.1 v v hh (2) rp hardware block unlock voltage block erase in progress, write to buffer and program 8.5 9.5 v v lko v dd supply voltage (erase and program lockout) 2.2 v
29/53 M58LW064a, M58LW064b table 23. asynchronous random read (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v, v ddq = 1.8v to v dd ) note: 1. output enable g may be delayed up to t elqv -t glqv after the falling edge of chip enable e without increasing t elqv . symbol parameter test condition min max unit t avav address valid to address valid e=v il ,g=v il 150 ns t avqv addrss valid to output valid e=v il ,g=v il 150 ns t axqx address transition to output transition e=v il ,g=v il 0ns t ehlx chip enable high to latch enable transition 0 ns t ehqx chip enable high to output transition g = v il 0ns t ehqz chip enable high to output hi-z g=v il 10 ns t elqv (1) chip enable low to output valid g=v il 150 ns t elqx chip enable low to output transition g=v il 0ns t ghqx output enable high to output transition e=v il 0ns t ghqz output enable high to output hi-z e=v il 10 ns t glqv output enable low to output valid e = v il 50 ns t glqx output enable to output transition e=v il 0ns t llel latch enable low to chip enable low 10 ns figure 9. asynchronous random read ac waveforms asynchronous read (m15 = 1), random (m3 = 0) ai03250 e g l a1-a22 (1) dq0-dqx (2) valid tllel taxqx telqv telqx tavqv tglqx tglqv tehqz tehqx tehlx tghqx tghqz see also page read (1) a1 is not used (don't care) in x32 organization (2) dq0-dq15 in x16 or dq0-dq31 in x32 organization output
M58LW064a, M58LW064b 30/53 table 24. asynchronous latch enable controlled read and page read (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v, v dd = 1.8v to v dd ) symbol parameter test condition min max unit t avll address valid to lacth enable low e=v il 10 ns t avqv1 address valid to output valid (page read) e = v il ,g=v il 25 ns t axqx address transition to output transition (page read) e=v il ,g=v il 6ns t ehlx chip enable high to latch enable transition 0 ns t ehqx chip enable high to output transition g=v il 0ns t ehqz chip enable high to output hi-z g = v il 10 ns t elll chip enable low to latch enable low 10 ns t ghqx output enable high to output transition e=v il 0ns t ghqz output enable high to output hi-z e=v il 10 ns t glqv output enable low to output valid e = v il 50 ns t glqx output enable low to output transition e=v il 0ns t lhax latch enable high to address transition e=v il 10 ns t lhll lacth enable high to latch enable low 10 ns t lllh latch enable low to latchenable high e = v il 10 ns t llqv latch enable low to output valid e=v il ,g=v il 125 ns t llqv1 lacth enable low to output valid (page read) e=v il ,g=v il 25 ns t llqx latch enable low to output transition e=v il ,g=v il 0ns figure 10. asynchronous read latch enable controlled read ac waveforms (x16, x32 organisation) asynchronous read (m15 = 1), latch enable controlled (m3 = 1) ai03251 l e g a1-a22 (1) dq0-dqx (2) valid tehlx tlhll tlhax tavll telll tlllh tehqx tehqz tghqx ghqz tllqv tllqx tglqx tglqv see also page read (1) a1 is not used (don't care) in x32 organization (2) dq0-dq15 in x16 or dq0-dq31 in x32 organization output
31/53 M58LW064a, M58LW064b figure 11. asynchronous page read for random or latch enable controlled read asynchrouns read (m15 = 1), random (m3 = 0) or latch enable controlled (m3 = 1) ai03699 l (2) a1-a2 (1) dq0-dqx a1 and/or a2 (x16), a2 (x32) tavqv1 (1) a1 and/or a2 only may change in x16 organization, a2 only in x32 organization (2) only for latch enable controlled read output tllqv1 taxqx page read up to - 4 words in x16 organization - 2 double-words in x32 orognization see asynchronous random read or asynchronous latch enable controlled read output + 1
M58LW064a, M58LW064b 32/53 table 25. synchronous burst read (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v, v dd = 1.8v to v dd ) note: 1. data output should be read on the valid clock edge. 2. for paramters not listed see asynchronous read. symbol (2) parameter test condit ion min max unit t avll address valid to latch enable low e=v il 10 ns t bhkh burst address advance high tovalid clock edge e = v il ,g=v il ,l=v ih 10 ns t blkh burst address advance low to valid clock edge e=v il ,g=v il ,l=v ih 10 ns t elll chip enable low to latch enable low 0 ns t glkh output enable low to valid clock edge e=v il ,l=v ih 20 ns t khax valid clock edge to address transition e=v il 0ns t khll valid clock edge to latch enable low e=v il 0ns t khlx valid clock edge to latch enable transition e=v il 0ns t khqx valid clock edge to output transition e=v il ,g=v il ,l=v ih 6ns t llkh latch enable low to valid clock edge e=v il 10 ns t qvkh (1) output valid to valid clock edge e=v il ,g=v il ,l=v ih 10 ns t rlkh valid data ready low to valid clock edge e=v il ,g=v il ,l=v ih 10 ns figure 12. synchronous burst read (9.1.1.1 example) x-latency = 0 (m14-m11 = 0100), y-latency = 1 (m9 = 0), burst length = 4 (m2-m0 = 001), burst type = sequential (m7 = 1), valid clock edge = rising (m6 = 1) ai03698 k (1) for set up signals and timings see synchronous burst read 8.1.1.1 14 13 12 11 10 9 dq0-dqx tqvkh tkhqx q0 q1 q2 q3 q0 q1 setup (1) burst read q0 to q3 burst read wraps if device remains selected (e = v il )
33/53 M58LW064a, M58LW064b figure 13. synchronous burst read (8.1.1.1 example) x-latency = 8 (m14-m11 = 0010), y-latency = 1 (m9 = 0), burst length = 1 (m2-m0 = 100), burst type = any (m7 = 0 or 1), valid clock edge = rising (m6 = 1) ai03256 dq0-dqx (1) a1-a22 (1) l e g k valid tkhax tqvkh 10 9 8 7 6 5 4 3 2 1 0 tkhll tllkh telll tavll tkhlx tehqx tehqz tghqx tghqz tglkh setup (1) a1 is not used (don't care) in x32 organization (2) dq0-dq15 in x16 or dq0-dq31 in x32 organization output
M58LW064a, M58LW064b 34/53 figure 14. synchronous burst read - continuous - valid data ready output valid data ready = valid low during valid clock edge (m8 = 0) figure 15. synchronous burst pipeline read (8.1.1.1 example) x-latency = 8 (m14-m11 = 0010), y-latency = 1 (m9 = 0), burst length = 1 (m2-m0 = 100), burst type = any (m7 = 0 or 1), valid clock edge = rising (m6 = 1) ai03696 k (1) v = valid output; nv = not valid output. (2) r is an open drain output with an internal pull up resistor of 1m w. the internal timing of r follows dq. an external resistor, typically 300k w for a single memory on the r bus, should be used to give a data valid set up time required to recognize valid data is evailable on the next valid clock edge. output (1) v v nv nv v v tblkh r v (2) ai03695 valid clock edges outputs addresses 12345678910111213141516171819 q0 q1 q2 q3 q0 q1 q2 q3 not valid 8 8 2nd address latch 1st address latch
35/53 M58LW064a, M58LW064b figure 16. synchronous burst read - burst address advance ai03697 k (1) valid clock edge '9' is valid and outputs q0. (2) b goes low before valid clock edge '10' and output increments to q1. (3) b goes high before valid clock edge '12' and output remains q1. 14 13 12 11 10 9 outputs q0 q1 (1) tblkh tbhkh (2) (3) b
M58LW064a, M58LW064b 36/53 table 26. asynchronous write and latch enable controlled write (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v, v dd = 1.8v to v dd ) symbol parameter test conditio n min max unit t avlh address valid to latch enable high 10 ns t avwh address valid to write enable high e=v il 50 ns t dvwh data input valid to write enable high e=v il 50 ns t elwl chip enable low to write enable low 0 ns t lhax latch enable high to address transition 3 ns t lllh latch enable low to latch enable high 10 ns t llwh latch enable low to write enable high 50 ns t qvrh output valid to reset/power down vdd 0 ns t qvvpl output valid to program/erase enable low 0 ns t rhhwh reset/power down vhh to write enable high 0 ns t vphwh program/erase enable high to write enable high 0 ns t whax write enable high to address transition e=v il 10 ns t whbl write enable high to read/busy low 90 ns t whdx write enable high to input transition e=v il 10 ns t wheh write enable high to chip enable high 0 ns t whgl write enable high to output enable low 35 ns t whwl write enable high to write enable low 30 ns t wlwh write enable low to write enable high e = v il 70 ns
37/53 M58LW064a, M58LW064b figure 17. asynchronous write ai03694 dq0-dq31 rb w rp a1-a22 e g input valid valid twheh valid tavwh twlwh telwl input valid sr v pp twhax twhwl twhdx tdvwh twhgl twhqv twhbl tvphwh tqvvpl tqvrh trhhw rp = v dd rp = v hh read status register write cycle write cycle
M58LW064a, M58LW064b 38/53 figure 18. asynchronous latch enabled controlled write ai03693 dq0-dqx w a1-a22 e g input valid valid tlllh valid tavlh telwl input valid sr tlhax twhdx tdvwh twhgl twhqv write cycle write cycle l twhax tllwh tavwh twheh twhwl twlwh
39/53 M58LW064a, M58LW064b table 27. reset, power-down and power-up (t a = 0 to 70 c, 40 to 85 c, v dd = 2.7v to 3.6v, v dd = 1.8v to v dd ) table 28. program, erase times and program erase endurance cycles (t a = 0 to 70 c; v dd = 2.7v to 3.6v; v ddq =1.7v to 1.9v) symbol parameter min max unit t phel reset/power-down high to chip enable low 50 m s t phqv reset/power-down high to output valid 10 m s t phwl reset/power-down high to write enable low 50 m s t plph reset/power-down low to reset/power-down high 500 ns t plrh reset/power-down low to ready high 22 m s t pur power-up to read 10 m s t puw power-up to write 10 m s t vdhel supply voltages high to chip enable low 50 ms t vdhph supply voltages high to reset/power-down high 1 m s t vdhwl supply voltages high to write enable low 50 ms parameters M58LW064a/b unit min max typ typical after 100k w/e cycles uniform block (1mb) erase 1.5 0.75 0.75 sec chip program 54 54 sec write buffer 192 192 m s program suspend latency time 10 3 m s erase suspend latency time 30 10 m s program/erase cycles (per block) 100,000 cycles
M58LW064a, M58LW064b 40/53 figure 19. reset, power-down and power-up ac waveform ai03692 tphqv rp tplph rp tplph reset during read mode reset during program/erase tplrh tphwl tphel rp tplph tplrh tphwl tphel reset recovery to read reset abort recovery abort power down recovery rp v dd ,v ddq e tphr, tpkw tvdhph power-up tvdhel tvdhwl reset during power up
41/53 M58LW064a, M58LW064b figure 20. write buffer program flowchart and pseudo code write to buffer e8h command, block address ai03635 start read status register no b7=1 write buffer data, start address yes x=n yes no end no write to buffer timeout write word or byte count, block address yes x=0 write next buffer data, device address x=x+1 program buffer to flash confirm d0h read status register no b7 = 1 yes full status check (optional) try again later
M58LW064a, M58LW064b 42/53 figure 21. program suspend & resume flowchart and pseudo code write 70h command ai00612 read status register yes no b7=1 yes no b4=1 program continues write ffh command pes instruction: write b0h command (memory enters read register state after the pes instruction) do: read status register (e or g must be toggled) while b7 = 1 if b4 = 0, program completed (at this point the memory will accept only the rd or per instruction) rd instruction: write ffh command one or more data reads from another block write d0h command per instruction: write d0h command to resume erasure if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). read data from another block start write b0h command program complete write ffh command read data
43/53 M58LW064a, M58LW064b figure 22. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 20h command ai00613b start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error ee instruction: write 20h command write block address (a12-a17) & command d0h (memory enters read status state after the ee instruction) do: read status register (e or g must be toggled) if ee instruction given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: error handler if b4, b5 = 1, command sequence error: error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: error handler
M58LW064a, M58LW064b 44/53 figure 23. erase suspend & resume flowchart and pseudo code write 70h command ai00615 read status register yes no b7=1 yes no b6=1 program continues write ffh command pes instruction: write b0h command (memory enters read register state after the pes instruction) do: read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed (at this point the memory wich accept only the rd or per instruction) rd instruction: write ffh command one o more data reads from another block write d0h command read data from another block or program start write b0h command erase complete write ffh command read data pg instruction: write 40h command write address & data per instruction: write d0h command to resume erasure if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued).
45/53 M58LW064a, M58LW064b figure 24. command interface and program erase controller flowchart (a) note: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-down or if v dd falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. ai03618 read signature yes no 90h read status yes 70h no clear status yes 50h no program buffer load yes e8h no erase set-up yes 20h no erase command error yes ffh wait for command write (1) read status read array yes d0h no a b no c cfi query yes 98h no
M58LW064a, M58LW064b 46/53 figure 25. command interface and program erase controller flowchart (b) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b erase yes ready (2) no a b0h no read status yes ready (2) no erase suspend yes d0h read array yes erase suspended read status (read status) yes no (erase resume) no read status 90h no read signature yes 98h no cfi query yes e8h no program buffer load yes c ai03618
47/53 M58LW064a, M58LW064b figure 26. command interface and program erase controller flowchart (c) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b program yes ready (2) no c b0h no read status yes ready (2) no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618
M58LW064a, M58LW064b 48/53 table 29. ordering information scheme devices are shipped from the factory with the memory content bits erased to '1'. for a list of available options (configuration, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: M58LW064a 150 n 1 t device type m58 architecture l = multi-bit cell, burst mode, page mode operating voltage w=v dd = 2.7v to 3.6v; v ddq = 1.8 to v dd device function 064a = 64 mbit (x16), equal block, boot block 064b = 64 mbit (x16/x32), equal block, boot block speed 150 = 150 ns package nf = tsop56: 14 x 20 mm nh = tsop86 type ii t = pqfp80 za = lbga64 temperature range 1=0to70 c 6=40to85 c optio n t = tape & reel packing
49/53 M58LW064a, M58LW064b table 30. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 13.90 14.10 0.5472 0.5551 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n40 40 cp 0.10 0.0039 figure 27. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
M58LW064a, M58LW064b 50/53 table 31. tsop86 type ii, package mechanical data symbol mm inch typ min max typ min max a 1.200 0.0472 a1 0.050 0.0020 a2 0.950 1.150 0.0374 0.0453 b 0.220 0.170 0.300 0.0087 0.0067 0.0118 c 0.145 0.0057 d 22.220 22.120 22.320 0.8748 0.8709 0.8787 e 11.760 11.560 11.960 0.4630 0.4551 0.4709 e1 10.160 10.060 10.260 0.4000 0.3961 0.4039 e 0.500 0.0197 l 0.450 0.750 0.0177 0.0295 a 0 8 0 8 n86 86 cp 0.100 0.0039 figure 28. tsop86 type ii, package outline drawing is not to scale. tsop-e n 1 cp a l a1 a n/2 d e b e1 e c a2
51/53 M58LW064a, M58LW064b figure 29. pqfp80 - 80 lead plastic quad flat pack, package outline drawing is not to scale. tqfp nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 table 32. pqfp80 - 80 lead plastic quad flat pack, package mechanical data symbol mm inches typ min max typ min max a 3.40 0.1339 a1 0.25 0.0098 a2 2.80 2.55 3.05 0.1102 0.1004 0.1201 b 0.30 0.45 0.0118 0.0177 c 0.11 0.23 0.0043 0.0091 d 23.90 0.9409 d1 20.00 0.7874 e 0.80 0.0315 e 17.90 0.7047 e1 14.00 0.5512 l 0.88 0.73 1.03 0.0346 0.0287 0.0406 a 3.5 0 7 3.5 0 7 n80 80 nd 24 24 ne 16 16 cp 0.250 0.0098
M58LW064a, M58LW064b 52/53 figure 30. lbga54 - 6 x 8 balls, 1 mm pitch, package outline drawing is not to scale. d1 d e1 e eb se sd a2 a1 a bga-z11 ddd fe fd ball oa1o table 33. lbga54 - 6 x 8 balls, 1 mm pitch, package mechanical data symbol mm inch typ min max typ min max a 1.090 0.980 1.200 0.0429 0.0386 0.0472 a1 0.290 0.220 0.360 0.0114 0.0087 0.0142 a2 0.800 0.760 0.840 0.0315 0.0299 0.0331 b 0.430 0.300 0.560 0.0169 0.0118 0.0220 d 10.000 9.800 10.200 0.3937 0.3858 0.4016 d1 7.000 0.2756 ddd 0.150 0.0059 e 1.000 0.925 1.075 0.0394 0.0364 0.0423 e 13.000 12.800 13.200 0.5118 0.5039 0.5197 e1 7.000 0.2756 fd 3.000 0.1181 fe 1.500 0.0591 sd 0.500 0.0197 se 0.500 0.0197
53/53 M58LW064a, M58LW064b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

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