View MAX8594_978857.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX8594/MAX8594a complete power-manage- ment chips for low-cost personal digital assistants (pdas) operates from a 1-cell lithium-ion (li+) or 3-cell nimh battery. they include all regulators, outputs, and voltage monitors necessary for small portable devices while requiring a bare minimum of external compo- nents. featured are three linear regulators, a boost dc- dc converter for lcd bias, an efficient 4mhz buck dc-dc converter for core power, a microprocessor (?) reset output, and low-battery shutdown in a 0.8mm high thin qfn package. the cor1 buck dc-dc converter supplies a pin-selec- table output at 400ma. all linear regulators feature pmos pass elements for efficient low-dropout opera- tion. a main ldo supplies 3.3v at 500ma. a secure- digital (sd) card slot output supplies 3.3v at 500ma, and a cor2 ldo supplies 1.8v at 50ma. each output has its own logic-controlled enable. for other output voltage combinations, contact maxim. an lcd bias boost dc-dc converter features an on- board mosfet and true shutdown when off. this means that during shutdown, input power is disconnect- ed from the inductor so the boost output falls to 0v rather than remaining one diode drop below the input voltage. a ? reset output clears 20ms (typ) after the cor1 out- put achieves regulation to ensure an orderly start. in addition, the cor1 regulator is not started until the 3.3v main output is in regulation. also included are a 1% accurate reference and low-battery monitor. thermal shutdown protects the die from overheating. the MAX8594/MAX8594a operate from a 3.1v to a 5.5v supply voltage and consume 46? no-load supply cur- rent. they are packaged in a tiny, 4mm x 4mm, 24-pin thin qfn capable of dissipating 1.67w. the devices are specified for operation from -40? to +85?. applications pdas organizers cellular and cordless phones mp3 players handheld devices features ? minimum external components ? efficient step-down dc-dc powers cpu core ? 1v/1.3v selectable core voltage, 400ma (MAX8594) ? 1.3v/1.8v selectable core voltage, 400ma (MAX8594a) ? main ldo 3.3v, 500ma ? sd card output 3.3v, 500ma ? second core ldo 1.8v, 50ma ? high-efficiency lcd boost ? lcd 0v true shutdown when off ? 46? quiescent current MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ________________________________________________________________ maxim integrated products 1 ordering information main in gnd sdig rs enc2 lxl lfb 3.3v, 500ma sd card slot to in enl lcd 15v lcd to main sw ensd on off on off on off on off on off 3.3v, 500ma main v in ref cor1 1.3v or 1.8v (MAX8594a) 1v or 1.3v (MAX8594) 400ma cor1 lxc pgnd cv 1.8v/1.3v 1.3v/1v enc1 1.8v, 50ma cor2 cor2 to main lbo lbi dbo to main dbi pv enm sdig cor2 cor1 main MAX8594 MAX8594a t ypical operating circuit 19-3349; rev 2; 4/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. true shutdown is a trademark of maxim integrated products, inc. part temp range pin-package MAX8594etg -40 c to +85 c 24 thi n qfn - e p * 4m m x 4m m ( t2444- 4) MAX8594aetg -40 c to +85 c 24 thi n qfn - e p * 4m m x 4m m ( t2444- 4) pin configuration appears at end of the data sheet. * ep = exposed pad.
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, pv, ensd, enc1, enc2, enl, rs , sdig, lbi, dbi to gnd ...................................................-0.3v to +6v lxl to gnd ............................................................-0.3v to +30v main, cor1, cor2, ref, lfb, cv, enm, lbo , dbo, lxc, sw to gnd......................................-0.3v to (v in + 0.3v) pv to in..................................................................-0.3v to +0.3v pgnd to gnd .......................................................-0.3v to +0.3v current into lxl..........................................................300ma rms current out of sw .......................................................300ma rms current into lxc .........................................................400ma rms output short-circuit duration.....................................continuous continuous power dissipation (t a = +70?) 24-pin thin qfn package (derate 20.8mw/? above +70?) .................................1.67w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = v cv = 4.0v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units general in, pv voltage range 3.1 5.5 v v dbi = v in , v in falling 2.950 3.0 3.050 v in complete shutdown threshold v dbi = v in , v in rising 3.135 3.3 3.525 v v dbi falling 1.234 1.25 1.263 v dbi complete shutdown threshold v dbi rising 1.306 1.375 1.478 v v lbi rising 1.234 1.25 1.263 v lbi lbo threshold v lbi falling 1.103 1.125 1.140 v v lbi = v in , v in falling 3.262 3.33 3.366 v in lbo threshold v lbi = v in , v in rising 3.625 3.7 3.744 v preset mode, v in = 2.9v v in - 0.3 dbi input dual mode ? threshold adj mode, v in = 2.9v v in - 1.2 v preset mode, v in = 3.2v v in - 0.3 lbi input dual-mode threshold with respect to in adj mode, v in = 3.2v v in - 1.2 v dbi complete shutdown input program range v in falling 3.0 5.5 v dbi input bias current v dbi = 1.25v -50 +50 na lbi input bias current v lbi = 1.25v -50 +50 na shutdown (dbi remains on, ref off), v in = v pv = v dbi = v lbi = 2.7v 2 10 all off (ref on) 30 55 in, pv operating current all on; lxl, lxc not switching 130 180 ? main on, no load 46 75 main on, no load, cor1 on, lxc not switching 80 110 in operating current al l on excep t lc d , v e n l = 0v , lx l and lx c not sw i tchi ng 115 160 ? dual mode is a trademark of maxim integrated products, inc.
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = v cv = 4.0v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units ldos main, sdig soft-start time 300 600 1200 ? main output voltage i load = 100? to 300ma, v in = 3.6v to 5.5v 3.218 3.3 3.383 v main current limit 550 800 1200 ma i load = 1ma 1 i load = 300ma 210 330 main dropout voltage i load = 500ma 350 595 mv sdig output voltage i load = 100? to 200ma, v in = 3.6v to 5.5v 3.218 3.3 3.383 v sdig current limit 525 718 900 ma i load = 1ma 0.75 i load = 200ma 170 300 sdig dropout voltage i load = 500ma 525 1010 mv sdig reverse leakage current v sdig = 5.5v, v ensd = v in = 0v 7 15 ? cor2 output voltage i load = 100? to 50ma, v in = 3.6v to 5.5v 1.755 1.8 1.845 v cor2 current limit 65 98 150 ma cor1 pwm buck cv = high (MAX8594a) 1.743 1.8 1.855 cv = high (MAX8594) or cv = low (MAX8594a) 1.259 1.3 1.340 cor1 output voltage accuracy cv = low (MAX8594) 0.972 1 1.023 v i lxc = -180ma 0.70 1.34 p-channel on-resistance i lxc = -180ma, v pv = 3.1v 0.8 1.58 ? i lxc = 180ma 0.25 0.46 n-channel on-resistance i lxc = 180ma, v pv = 3.1v 0.30 0.53 ? p-channel current-limit threshold -0.500 -0.75 -0.925 a n-channel current-limit threshold -0.50 -0.72 -0.92 a t on(min) 0.1 minimum on- and off-times t off(min) 0.1 ? lxc leakage current v lxc = 0v, v enc1 = 0v -10 +0.1 +10 ? ref and reset output ref voltage accuracy i ref = 0.1? 1.236 1.25 1.264 v ref line regulation 3.1v < v in < 5.5v, i ref = 0.1? 0.1 3 mv ref load regulation 0.1? < i ref < 10? 1 3 mv cv = low (MAX8594a), cv = low or cv = high (MAX8594) 88.00 90 93.25 rs deassert threshold for cor1 rising (note 1) cv = high (MAX8594a) 67.0 69 72.7 %
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = v cv = 4.0v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units cv = low or cv = high (MAX8594), cv = low (MAX8594a) 80 rs assert threshold cv = high (MAX8594a) 62.5 % rs deassert delay 10 20 30 ms rs assert delay 50mv overdrive 5 ? lcd lxl voltage range 28 v lxl current limit l1 = 10? 195 235 275 ma lxl on-resistance 1.7 ? lxl leakage current v lxl = 28v 0.2 2 ? maximum lxl on-time 2 3 4 ? v lfb > 1.1v 0.8 1 1.2 minimum lxl off-time v lfb < 0.8v (soft-start) 3.9 5 6.0 ? lfb feedback threshold 1.229 1.25 1.270 v lfb input bias current v lfb = 1.3v 5 50 na sw off-leakage current v sw = 0v, v pv = 5.5v, v enl = 0v 0.01 1 ? sw pmos on-resistance 1 1.5 ? sw pmos peak current limit 700 ma sw pmos average current limit 300 ma soft-start time c sw = 1? 0.13 ms logic en_, cv input low level v in = 3.1v to 5.5v 0.35 v en_, cv input high level v in = 3.1v to 5.5v 1.4 v en_, cv input leakage current 0.01 1 ? rs , lbo , dbo output low level sinking 1ma, v in = 2.5v 0.02 0.1 v dbo output low level sinking 100?, v in = 1.0v 0.02 0.1 v rs , lbo , dbo output high leakage v out = 5.5v, v in = 5.5v 1 ? thermal protection thermal-shutdown temperature rising temperature +160 ? thermal-shutdown hysteresis 15 ?
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas _______________________________________________________________________________________ 5 electrical characteristics (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = 4.0v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter conditions min typ max units general in, pv voltage range 3.1 5.5 v v dbi = v in , v in falling 2.93 3.06 v in complete shutdown threshold v dbi = v in , v in rising 3.135 3.525 v v dbi falling 1.228 1.264 v dbi complete shutdown threshold v dbi rising 1.306 1.478 v v lbi rising 1.228 1.264 v lbi lbo threshold v lbi falling 1.103 1.140 v v lbi = v in , v in falling 3.248 3.366 v in lbo threshold v lbi = v in , v in rising 3.609 3.744 v preset mode, v in = 2.9v v in - 0.3 dbi input dual-mode threshold adj mode, v in = 2.9v v in - 1.25 v preset mode, v in = 3.2v v in - 0.3 lbi input dual-mode threshold with respect to in adj mode, v in = 3.2v v in - 1.25 v dbi complete shutdown input program range v in falling 3.0 5.5 v dbi input bias current v dbi = 1.25v -50 +50 na lbi input bias current v lbi = 1.25v -50 +50 na shutdown (dbi remains on, ref off), v in = v pv = v dbi = v lbi = 2.7v 10 all off (ref on) 55 in, pv operating current all on, lxl, lxc not switching 180 ? main on, no load 75 main on, no load, cor1 on, lxc not switching 110 in operating current all on except lcd, v enl = 0v, lxl and lxc not switching 160 ? ldos main, sdig soft-start time ramp ilim from 0% to 100% 300 1200 ? main output voltage i load = 100? to 300ma, v in = 3.6v to 5.5v 3.209 3.383 v main current limit 550 1230 ma i load = 300ma 330 main dropout voltage i load = 500ma 595 mv
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 6 _______________________________________________________________________________________ parameter conditions min typ max units sdig output voltage i load = 100? to 200ma, v in = 3.6v to 5.5v 3.218 3.383 v sdig current limit 485 900 ma i load = 200ma 300 sdig dropout voltage i load = 500ma 1250 mv sdig reverse leakage current v sdig = 5.5v, v ensd = v in = 0v 15 ? cor2 output voltage i load = 100? to 50ma, v in = 3.6v to 5.5v 1.750 1.845 v cor2 current limit 60 150 ma cor1 pwm buck cv = high (MAX8594a) 1.743 1.855 cv = high (MAX8594) or cv = low (MAX8594a) 1.255 1.340 cor1 output voltage accuracy cv = low (MAX8594) 0.969 1.023 v i lxc = -180ma 1.34 p-channel on-resistance i lxc = -180ma, v pv = 3.1v 1.58 ? i lxc = 180ma 0.46 n-channel on-resistance i lxc = 180ma, v pv = 3.1v 0.53 ? p-channel current-limit threshold -0.460 -0.925 a n-channel current-limit threshold -0.46 -0.92 a lxc leakage current v pv = 5.5v, v lxc = 0v or v pv , v enc1 = 0v -10 +10 ? ref and reset output ref voltage accuracy i ref = 0.1? 1.229 1.264 v ref line regulation 3.1v < v < 5.5v, i ref = 0.1? 3 mv ref load regulation 0.1? < i ref < 10? 3 mv cv = low or cv = high (MAX8594), cv = low (MAX8594a) 88.00 93.25 rs deassert threshold for cor1 rising (note 1) cv = high (MAX8594a) 67.0 72.7 % rs deassert delay 10 30 ms lcd lxl voltage range 28 v lxl current limit l1 = 10? 180 280 ma lxl leakage current v lxl = 28v 2 ? maximum lxl on-time 2 4 ? v lfb > 1.1v 0.8 1.2 minimum lxl off-time v lfb < 0.8v (soft-start) 3.9 6.0 ? lfb feedback threshold 1.223 1.270 v lfb input bias current v lfb = 1.3v 50 na sw off-leakage current v sw = 0v, v pv = 5.5v, v enl = 0v 1 ? sw pmos on-resistance 1.5 ? electrical characteristics (continued) (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = 4.0v, t a = -40? to +85? , unless otherwise noted.) (note 2)
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas _______________________________________________________________________________________ 7 parameter conditions min typ max units logic en_, cv input low level v in = 3.1v to 5.5v 0.35 v en_, cv input high level v in = 3.1v to 5.5v 1.4 v en_, cv input leakage current 1 ? rs , lbo , dbo output low level sinking 1ma, v in = 2.5v 0.1 v dbo output low level sinking 100?, v in = 1.0v 0.1 v rs , lbo , dbo output high leakage v out = 5.5v, v in = 5.5v 1 ? electrical characteristics (continued) (v in = v pv = v ensd = v enc2 = v enl = v enm = v enc1 = v dbi = v lbi = 4.0v, t a = -40? to +85? , unless otherwise noted.) (note 2) note 1: the reset trip point tracks the cor1 voltage. for example, a minimum reset spec does not occur with a maximum cor1 spec, and a minimum cor1 spec does not occur with a maximum reset spec. note 2: specifications to -40? are guaranteed by design, not production tested. t ypical operating characteristics (circuit of figure 2, v in = 4v, t a = +25?, unless otherwise noted.) main dropout voltage vs. load current MAX8594/MAX8594a toc01 load current (ma) dropout voltage (mv) 500 400 300 200 100 50 100 150 200 250 300 350 400 450 500 0 0 600 100 200 300 400 500 600 700 800 0 sdig dropout voltage vs. load current MAX8594/MAX8594a toc02 load current (ma) dropout voltage (mv) 500 400 300 200 100 0600 1.50 2.00 1.75 2.75 2.50 2.25 3.25 3.00 3.50 0300 400 100 200 500 600 700 800 900 main output voltage vs. load current MAX8594/MAX8594a toc03 load current (ma) output voltage (v)
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 2, v in = 4v, t a = +25?, unless otherwise noted.) 1.50 2.00 1.75 2.50 2.25 3.25 3.00 2.75 3.50 0 200 100 300 400 500 600 700 sdig output voltage vs. load current MAX8594/MAX8594a toc04 load current (ma) output votlage (v) 1.8 1.7 1.9 0.9 300 200 100 0400 cor1 output voltage vs. load current MAX8594/MAX8594a toc05 load current (ma) output voltage (v) 1.6 1.4 1.3 1.5 1.2 1.1 1.0 cor2 output voltage vs. load current MAX8594/MAX8594a toc06 load current (ma) output voltage (v) 80 60 40 20 1.62 1.64 1.66 1.68 1.70 1.72 1.74 1.76 1.78 1.80 1.82 1.60 0 100 load-transient main MAX8594/MAX8594a toc07 100 s/div v main i out 100ma/div 50mv/div ac-coupled 0 load-transient cor1 MAX8594/MAX8594a toc08 40 s/div v cor1 i out 100ma/div 20mv/div ac-coupled 0 input current vs. input voltage MAX8594/MAX8594a toc09 input voltage (v) input current ( a) 5 4 3 2 1 10 20 30 40 50 60 0 06 v in falling v in rising
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (circuit of figure 2, v in = 4v, t a = +25?, unless otherwise noted.) rs and output timing MAX8594/MAX8594a toc10 20ms/div v cor1 v in v main v rs 5v/div 2v/div 5v/div 1v/div 0 0 0 0 40 55 50 45 60 65 70 75 80 85 90 02 1345 lcd efficiency vs. load current MAX8594/MAX8594a toc11 load current (ma) efficiency (%) v lcd = 18v v lcd = 15v lcd output voltage vs. load current MAX8594/MAX8594a toc12 load current (ma) output voltage (v) 10 8 6 4 2 17.0 17.2 17.4 17.6 17.8 18.0 18.2 16.8 012 5.0 4.5 4.0 17.97 17.98 17.99 18.00 18.01 18.02 18.03 18.04 17.96 3.5 5.5 lcd output voltage vs. input voltage MAX8594/MAX8594a toc13 input voltage (v) output voltage (v) lcd switching waveforms MAX8594/MAX8594a toc14 4 s/div i lx v in v lcd v lx 20mv/div ac-coupled 50mv/div ac-coupled 20v/div 200ma/div sdig response to ensd MAX8594/MAX8594a toc15 200 s/div v ensd v sdig 1v/div 2v/div i load = 100ma
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 10 ______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 2, v in = 4v, t a = +25?, unless otherwise noted.) lcd response to enl MAX8594/MAX8594a toc16 400 s/div v enl v lcd 5v/div 2v/div lcd boost soft-start sw turn-on main response to enm MAX8594/MAX8594a toc17 200 s/div v enm v main 1v/div 2v/div i load = 100ma cor1 response to enc1 MAX8594/MAX8594a toc18 40 s/div v enc1 v cor1 i lxc 500mv/div 0 200ma/div 2v/div r load = 10 ? for rs response, see rs and cor1 response to enc1 rs and cor1 response to enc1 MAX8594/MAX8594a toc19 10ms/div v enc1 v cor1 v rs i lxc 1v/div 5v/div 200ma/div 2v/div r load = 10 ? cor2 response to enc2 MAX8594/MAX8594a toc20 200 s/div v enc2 v cor2 1v/div 2v/div cor1 efficiency vs. load current with 1v output MAX8594/MAX8594a toc21 load current (ma) efficiency (%) 100 10 1 45 50 55 60 65 70 75 80 85 90 40 0.1 1000 v in = 3.6v v in = 4v v in = 5v MAX8594
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 11 t ypical operating characteristics (continued) (circuit of figure 2, v in = 4v, t a = +25?, unless otherwise noted.) cor1 efficiency vs. load current with 1.3v output MAX8594/MAX8594a toc22 load current (ma) efficiency (%) 100 10 1 45 50 55 60 65 70 75 80 85 90 40 0.1 1000 v in = 3.6v v in = 4v v in = 5v cor1 efficiency vs. load current with 1.8v output MAX8594/MAX8594a toc22a load current (ma) efficiency (%) 100 10 1 55 60 65 70 75 80 85 90 95 100 50 0.1 1000 v in = 3.6v v in = 4v v in = 5v light-load switching cor1 MAX8594/MAX8594a toc23 1 s/div v cor1 v lxc i lxc 50mv/div ac-coupled 200ma/div 5v/div 0 i load = 20ma heavy-load switching cor1 MAX8594/MAX8594a toc24 200ns/div v cor1 v lxc i lxc 5v/div 0 200ma/div 50mv/div ac-coupled i load = 200ma cor1 response to cv MAX8594/MAX8594a toc25 40 s/div v cor1 v cv 0 2v/div 500mv/div 1.3v/1.8v 1v/1.3v
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 12 ______________________________________________________________________________________ pin description pin name function 1 sdig 3.3v, 500ma ldo output for secure-digital card slot. sdig has reverse current protection so sdig can be biased when no power is present at in. sdig output turns off when v in is below the dbi threshold, ensd goes low, or main is out of regulation. when sdig turns off, the output is discharged at a rate depending on the load and the internal feedback resistors (typically 1.3m ? ). 2 in input voltage to the MAX8594/MAX8594a. bypass in to gnd with a 1? ceramic capacitor. 3 rs reset output. rs is an active-low, open-drain output that goes high impedance 20ms (typ) after cor1 is in regulation. cor1 does not turn on until main is in regulation. if main falls out of regulation, cor1 turns off and rs goes low. if main is still in regulation, then rs goes low when v in is below the dbi threshold. rs goes low when enc1 is low. 4 lbo low-battery detector open-drain output. lbo is an active-low, open-drain output that goes high impedance when v in is greater than both the dbi and lbi thresholds. lbo goes low when v in falls below the lbi threshold. 5 dbo dead-battery detector open-drain output. when v in is below the dbi threshold, both dbo and lbo go low, all outputs shut down, and the MAX8594/MAX8594a enter the lowest possible quiescent- current state. once this occurs, main does not turn back on until both v in exceeds the dbi threshold and enm = high. dbo is an active-low, open-drain output that goes high impedance when v in exceeds the dbi threshold. 6 dbi dead-battery detector. dbi remains active at all times. if dbi = in, the dbi threshold is 3.0v when in is falling and 3.3v when rising. the dbi threshold can also be adjusted to other values by connecting dbi to a resistor voltage-divider. also see the dbo description. 7 lbi low-battery detector. if lbi = in, the lbi threshold is 3.33v when in is falling and 3.7v when rising. the lbi threshold can also be adjusted to other values by connecting lbi to a resistor voltage- divider. also see the lbo description. 8 cv s el ects 1v or 1.3v c or1 outp ut v ol tag e for m ax 8 594, and 1.3v or 1.8v c o r1 for m ax 8594a. d r i ve c v hi g h or connect to in for a 1.3v c or1 outp ut ( 1.8v c or1 for m ax 8594a) . d r i ve c v l ow or connect to gn d for a 1v c or1 outp ut ( 1.3v c or1 for m ax 8594a) . 9 enm enable input for main. no other outputs turn on until main is in regulation. if main is pulled out of regulation, all other outputs turn off and rs goes low. main cannot be activated when v in is below the dbi threshold. 10 gnd ground 11 ref 1.25v 1% reference. bypass ref with a 0.1? capacitor to gnd. ref is enabled when v in is greater than the dbi threshold. ref is off when v in is below the dbi threshold. 12 lfb lcd feedback input. connect lfb to a resistor-divider network between the lcd output and gnd. the feedback threshold is 1.25v. lcd turns off when v in is below the dbi threshold, when enl goes low, or when main is out of regulation. when off, the lcd output is discharged at a rate depending on the load and the external feedback resistors (typically 2.4m ? ). 13 enl enable input for lcd (boost regulator). drive enl high to activate the lcd boost. drive enl low to shut down the lcd output. the lcd converter cannot be activated when v in is below the dbi threshold or before main is in regulation. 14 lxl lcd boost switch. connect lxl to a boost inductor and schottky diode. see figure 1.
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 13 pin description (continued) pin name function 15 sw lcd true-shutdown switch output. sw is the power source for the lcd boost inductor. sw turns on when enl is high. for best efficiency, bypass sw with a 4.7? capacitor to gnd. sw is disconnected from pv when lcd is shut down. 16 pv power input for cor1 buck converter and lcd true-shutdown switch. connect in to pv. 17 pgnd power ground 18 lxc cor1 switching node. connect lxc to the cor1 inductor. see figure 1. 19 enc1 enable input for primary core buck converter (cor1). drive enc1 high to turn on cor1 and low to turn off. cor1 cannot be activated if v in is below the dbi threshold or before main is in regulation. 20 ensd enable input for secure digital card (sdig). drive ensd low to turn off sdig and high to turn on. sdig cannot be activated when v in is below the dbi threshold or before main is in regulation. 21 cor1 feedback sense input for cor1 output. cor1 turns off when v in is below the dbi threshold, when enc1 goes low, or when main is out of regulation. when off, the output is discharged by lxc through an internal 1m ? (typ) resistor. 22 enc2 enable input for secondary core ldo (cor2). drive enc2 high to turn on cor2 and low to turn off. cor2 cannot be activated when v in is below the dbi threshold or before main is in regulation. cor2 can be activated when v in is greater than the dbi threshold and main is in regulation. 23 cor2 1.8v, 50ma ldo output for secondary core. cor2 turns off when v in is below the dbi threshold, when enc2 goes low, or when main is out of regulation. the cor2 output is discharged at a rate depending on the load and the internal feedback resistors (typically 700k ? ). 24 main 3.3v, 500ma ldo output for main supply. main output turns off when v in is below the dbi threshold or when enm goes low. when off, the output is discharged at a rate depending on the load and the internal feedback resistors (1.3m ? typ). ep exposed pad. connect to ground for enhanced power dissipation.
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 14 ______________________________________________________________________________________ main in c1 1 f gnd sdig rs enc2 lxl lfb 3.3v, 500ma sd card slot to in enl lcd 15v lcd to main sw ensd on off on off on off on off on off 3.3v, 500ma main power input c7 4.7 f c8 1 f c9 47pf l1 10 h murata lqh32c c2 4.7 f c3 4.7 f c4 2.2 f c6 2.2 f r1 2.2m ? r2 200k ? ref c10 0.1 f cor1 1.3v or 1.8v (MAX8594a) 1v or 1.3v (MAX8594) 400ma cor1 lxc pgnd l2 2.2 h cv 1.8v/1.3v 1.3v/1v c5 0 f enc1 1.8v, 50ma cor2 cor2 to main lbo lbi dbo to main dbi pv enm r8 1m ? r7 1m ? r6 1m ? dc usb 1 f 1 f 1 f ac adapter input 4.15v to 7v usb input 4.15v to 6v batt gnd sdig cor2 cor1 main li-ion battery MAX8594 MAX8594a max8601 en usel isel 500ma 100ma charge control die thermal control logic pok chg flt figure 1. typical application circuit with charger
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 15 main in c1 1 f sdig enc2 3.3v, 500ma sd card slot to in fb mainok lcd boost 20ms after cor1 ok lcd off switch ensd on off on off on off on off 3.3v, 500ma main power input c2 4.7 f c3 4.7 f c4 2.2 f c6 2.2 f cor1 lxc pgnd l2 2.2 h cv 1.8v/1.3v 1.3v/1v c5 0 f enc1 1.8v, 50ma cor2 cor2 pv enm MAX8594 MAX8594a ldo control ldo control ldo control pwm buck 1.3v or 1.8v (MAX8594a) 1v or 1.3v (MAX8594) 400ma cor1 enl lcd to main on off to main to main r8 1m ? r7 1m ? r6 1m ? lbo rs dbo gnd lxl lfb lcd 15v sw to pv c7 4.7 f c8 1 f c9 47pf l1 10 h murata lqh32c r1 2.2m ? r2 200k ? ref lbi in to in to in dbi c10 0.1 f ref figure 2. block diagram
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 16 ______________________________________________________________________________________ detailed description cor1 step-down dc-dc converter the cor1 regulator is a proprietary hysteretic pwm control step-down converter that supplies up to 400ma. the output voltage is set to either 1v or 1.3v by cv for the MAX8594 and 1.3v or 1.8v for the MAX8594a. under moderate to heavy loading, cor1 operates in a low-noise pwm mode with constant frequency and modulated pulse width. switching harmonics generated by fixed-frequency operation are consistent and easily filtered. with light loads (<30ma), cor1 operates in an efficiency-enhanced idle mode during which the con- verter switches only as needed to service the load. linear regulators power for main logic, a sd card slot, and codec are provided by three ldos: main?rovides 3.3v at a guaranteed 500ma with a typical current limit of 800ma. sdig?rovides 3.3v at a guaranteed 500ma for sd cards with a typical current limit of 718ma. cor2?rovides 1.8v at a guaranteed 50ma for a codec core with a typical current limit of 98ma. note that it may not be possible to draw the full rated current of main and sdig at all operating input volt- ages due to the dropout limitations of those regulators. the typical dropout resistance of the main regulator is 0.7 ? (350mv drop at 500ma), and the typical dropout resistance of the sdig regulator is 0.85 ? (525mv drop at 500ma). all voltage outputs have separate enable inputs (enm, enl, ensd, enc1, and enc2); however, no other out- put turns on until main is in regulation. main cannot be activated until v in exceeds the dbi threshold. when sdig is turned off, reverse current is blocked so the sdig output can be biased with an external source when no power is present at in. leakage current is typ- ically 3? with 3.3v at sdig. lcd dc-dc boost the MAX8594/MAX8594a include a low-current, high- voltage boost dc-dc converter for lcd bias. this circuit can output up to 28v and is adjustable with either an ana- log or pwm control signal using external components. sw provides an input-power disconnect for the lcd when enl is low (off). the input-power disconnect function is ideal for applications that require the output voltage to fall to 0v in shutdown (true shutdown). if true shutdown is not required, the sw switch can be bypassed by connecting the boost inductor directly to pv and removing the bypass cap on sw (c7 in figure 1). system sleep all regulated outputs turn off when v dbi < 1.25v (or v in = 3.0v if dbi = in, figure 1). the MAX8594/MAX8594a resume normal operation when v dbi >1.375v (or v in = 3.3v if dbi = in, figure 1). reset output ( rs ) reset rs asserts when cor1 falls 20% below its set level (38% for 1.8v setting in the MAX8594a). rs is an open-drain, active-low output. connect a pullup resistor from rs to the logic supply of the gate receiving the reset signal. rs deasserts a minimum of 10ms after the cor1 output is in regulation. upon application of valid input power, the main output activates first (if enm = high) followed by other outputs (if en_ = high). power and output sequencing are shown in figure 3. idle mode is a trademark of maxim integrated products, inc. figure 3. power sequence for rising and falling input voltage. note that v in thresholds are for lbi and dbi connected to v in . other thresholds can be set with resistors. v in 3.3v main rs lbo dbo v in = 3.7v v in = 3.33v v in = 3.0v v in = 3.3v cor1 main at 90% 20ms rs deassert delay cor1 at 90% main at 86%
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 17 power sequencing as v in increases from 0v, sequencing is as follows: 1) the dbi comparator is always on. dbo , lbo , and rs are pulled low at approximately v in = 0.7v. main, sdig, cor1, cor2, and lcd are off. 2) when v in rises above the dbi threshold (3.3v if dbi = in), dbo goes high impedance immediately and the part turns on. the main ldo turns on if enm = high. 3) when the main output reaches 90% of its nominal voltage, or 2.97v, all other regulators turn on if they are enabled. 4) rs goes high impedance 20ms after cor1 reach- es 90% of its nominal voltage (69% when 1.8v set- ting in the MAX8594a is used). 5) when v in rises above the lbi threshold (3.7v if lbi = in), lbo goes high impedance. as in decreases, sequencing is as follows: 1) when v in falls to the lbo threshold (3.33v if lbi = in), lbo is pulled to gnd. 2) if v in falls to the dbi threshold (3.0v if lbi = in) before the main output falls to 2.838v, dbo and rs go low, all regulators turn off, and the part is shut down. 3) if the main output falls below 86% of its nominal voltage (2.838v) before in reaches the dbi thresh- old (3.0v if dbi = in), rs is pulled to gnd and all other outputs turn off, but main remains on (in dropout) and dbo remains high until in falls to the dbi threshold. applications information cor1 buck output cor1 inductor a 2.2? inductor with a saturation current of at least 500ma is recommended. for lower load currents, the inductor current rating may be reduced. for maximum efficiency, the inductor? dc resistance should be as low as possible. note that core materials differ among manufacturers and inductor types, resulting in varia- tions in efficiency. cor1 capacitors ceramic input and output capacitors are recommend- ed. for best stability over a wide temperature range, use capacitors with an x5r or x7r dielectric due to their low esr and low temperature coefficient. the cor1 output capacitor c6 (figure 1) is required to keep the output voltage ripple small; 2.2? is recom- mended for most applications. due to the pulsating nature of input current in a buck converter, a low-esr input capacitor is required for input voltage filtering and to minimize interference with other circuits. the impedance of the input capacitor, c5 (figure 1), should be kept very low at the switching frequency. a minimum value of 4.7? is recommended at pv for most applications. the input capacitor can be increased to further improve input filtering. ldo output capacitors (main, sdig, cor2) capacitors are required at each ldo output of the MAX8594/MAX8594a for stable operation over the full load and temperature range. see figure 1 for recom- mended capacitor values for each output. to reduce noise and improve load-transient response, larger out- put capacitors up to 10? can be used. surface-mount ceramic capacitors have very low esr and are com- monly available in values up to 10?. x7r and x5r dielectrics are recommended. note that some ceramic dielectrics, such as z5u and y5v, exhibit large capaci- tance and esr variation with temperature and require larger than the recommended values to maintain stabil- ity overtemperature. setting lbi and dbi the dbi and lbi inputs monitor input voltage (usually a battery) and trigger the dbo and lbo outputs. with lbi and dbi connected to in, the lbi and dbi thresh- olds are internally set. for a rising input voltage, dbo goes high when v in exceeds 3.3v and lbo goes high when v in exceeds 3.7v. for a falling input voltage, lbo goes low when v in falls below 3.3v and dbo goes low when v in falls below 3.0v (see also the electrical characteristics table and figure 3). alternatively, the lbi and dbi thresholds can be set with external resis- tors as shown in figures 4 and 5.
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 18 ______________________________________________________________________________________ in figure 4, one three-resistor-divider can set both dbi and lbi according to the following equations (shown for setting falling thresholds). choose the lower resistor of the divider chain (r5 in figure 4) to be between 100k ? and 250k ? . the equations for the two upper resistor- dividers as a function of each (falling) threshold are: where v dbfall and v lbfall are the desired falling thresholds to trigger the dbo and lbo outputs, respectively. once those thresholds are selected, the rising dbi and lbi thresholds are: alternately, lbi and dbi can be set with separate resis- tor-dividers. the resistor calculation is simpler and the two settings do not interact, but one more resistor is needed and battery drain is slightly higher due to the extra resistor load. choose the lower resistor of each divider chain (r7 and r9 in figure 5) to be between 100k ? and 250k ? . the equations for upper resistor- dividers as a function of each (falling) threshold are: where v dbfall and v lbfall are the desired falling thresholds to trigger the dbo and lbo outputs, respectively. once those thresholds are selected, the rising dbi and lbi thresholds are: note that the low-battery threshold should not be set below the dead-battery threshold because both dbo vx rr r lbrise = + 125 89 9 . vx rr r dbrise = + 1 375 67 7 . rrx v lbfall 89 1 125 1 =? ? ? ? ? ? ? . rrx v dbfall 67 125 1 =? ? ? ? ? ? ? . vx rrr r lbrise = ++ 125 345 5 . vx rrr rr dbrise = ++ + 1 375 345 45 . rrx xv xv lbfall dbfall 45 125 1 125 1 =? . . rrx v x v lbfall dbfall 35 1 125 1 125 =? ? ? ? ? ? ? . . figure 4. setting the dbi and lbi threshold with three external resistors MAX8594 MAX8594a in r3 r4 r5 dbi (1.25v falling, 1.375v rising) lbi (1.125v falling, 1.25v rising) figure 5. setting the dbi and lbi thresholds with four resistors MAX8594 MAX8594a in r6 r8 r7 r9 dbi (1.25v falling, 1.375v rising) lbi (1.125v falling, 1.25v rising)
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 19 and lbo are automatically driven low and the part is shut down when the dbi threshold is crossed (going low). lcd boost output lcd inductor the lcd boost is designed to operate with a wide range of inductor values (4.7? to 150?). smaller inductance values typically offer smaller size for a given series resistance or saturation current. smaller values cause lx to switch more frequently for a given load and can reduce efficiency at low load currents. larger values reduce switching losses due to less fre- quent switching for a given load, but higher dc resis- tance can reduce efficiency. note that for inductors larger than 43?, the peak inductor current does not reach 250ma before the lxl maximum on-time (3?) expires. this reduces output current but may be benefi- cial for light-load efficiency. a 10? inductor provides a good balance and works well for most applications. the inductor? saturation current rating should be greater than the peak switching current (250ma). lcd diode schottky diodes rated at 250ma or more, such as the mbr0530 or nihon ep05q03l, are recommended. the diode reverse-breakdown voltage rating must be greater than the lcd output voltage. lcd capacitors for most applications, use a ceramic 1f output capacitor. this typically provides a peak-to-peak output ripple of 30mv. in addition, bypass in with 1? and sw with 4.7? ceramic capacitors. an lcd feed-forward capacitor, connected from the output to lfb, improves stability over a wide range of battery voltages. a 47pf capacitor is sufficient for most applications; however, the optimum value is affected by pc board layout. setting lcd voltage adjust the output voltage by connecting a voltage- divider from the lcd output to lfb (see figure 1). select r2 between 10k ? and 200k ? . calculate r1 with the following equation: where v lfb = 1.25v and v out can range from v in to 28v. the input bias current of lfb is typically only 5na, allowing large-value resistors to be used. for less than 1% error, the current through r2 should be greater than 100 times the feedback input bias current (i lfb ). lcd adjustment the lcd boost output can be digitally adjusted by either a dac or pwm signal. dac adjustment adding a dac and a resistor, r d , to the divider circuit (figure 6) provides dac adjustment of v out . ensure that v out(max) does not exceed the lcd panel rating. the output voltage (v out ) as a function of the dac voltage (v dout ) is calculated using the following formula: vx r r vxr r out dout d =+ ? ? ? ? ? ? ? ? ? ? ? ? + ? () 125 1 1 2 125 1 . . rrx v v out lfb 12 1 =? ? ? ? ? ? ? figure 6. adjusting the output voltage with a dac max5365 MAX8594 MAX8594a dac av dd v dout r1 r2 r d v in v out i 1 i 2 i d control error amp simplified dc-dc converter v ref 1.25v
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas 20 ______________________________________________________________________________________ using pwm signals many ?s have the ability to create pwm outputs. these are digital outputs, based on either 16-bit or 8-bit counters, with a programmable duty cycle. in many applications, they are suitable for adjusting the output of the MAX8594/MAX8594a as seen in figure 7. the circuit consists of the pwm source, capacitor c11, and resistors r d and r w . to analyze the transfer func- tion of the pwm circuit, it is easiest to first simplify it to its thevenin equivalent. the thevenin voltage is calcu- lated using the following formula: where d is the duty cycle of the pwm signal, v oh is the pwm output high level (often 3.3v), and v ol is the pwm output low level (usually 0v). for cmos logic, this equation simplifies to: v thev = d x v dd where v dd is the logic-high output voltage of the pwm output. the thevenin impedance is the sum of resistors r w and r d : r thev = r d + r w the output voltage (v out ) as a function of the pwm average voltage (v thev ) is: when using the pwm adjustment method, r d isolates the capacitor from the feedback loop of the MAX8594/MAX8594a. the cutoff frequency of the low- pass filter is defined as: the cutoff frequency should be at least two decades below the pwm frequency to minimize the induced ac ripple at the output. an important consideration is the turn-on transient cre- ated by the initial charge on filter capacitor c11. this capacitor forms a time constant with r thev , causing the output to initialize at a higher than intended voltage. this overshoot is minimized by scaling r d as high as possible compared to r1 and r2. alternatively, the ? can briefly keep the lcd disabled until the pwm volt- age has had time to stabilize. pc board layout and grounding careful pc board layout is important for minimizing ground bounce and noise. keep the MAX8594/ MAX8594a? ground pin and the ground leads of the input and output capacitors less than 0.2in (5mm) apart. in addition, keep all connections to lfb, cor1, lxc, and lxl as short as possible. in particular, exter- nal feedback resistors should be as close to lfb as possible. to minimize output voltage ripple and to max- imize output power and efficiency, use a ground plane and solder pgnd and exposed pad directly to the ground plane. refer to the MAX8594 evaluation kit for a layout example. thermal considerations in most applications, the circuit is located on a multilay- er board and full use of the four or more layers is recom- mended. for heat dissipation, connect the exposed backside pad of the thin qfn package to a large ground plane, preferably on a surface of the board that receives good airflow. typical applications use multiple ground planes to minimize thermal resistance. avoid large ac currents through the ground plane. f xxr xc c thev = 1 2 11 vx r r vxr r out thev thev =+ ? ? ? ? ? ? ? ? ? ? ? ? + ? () 125 1 1 2 125 1 . . vdxv dxv thev oh ol = () +? () 1 figure 7. pwm-controlled lcd bias sw lxl lcd 15v c7 4.7 f c8 1 f c9 47pf r1 2.2m ? r2 200k ? r d r w connection for pwm-controlled lcd bias c11 lfb
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas ______________________________________________________________________________________ 21 24 main 23 cor2 22 enc2 21 cor1 20 ensd 19 enc1 7 lbi 8 cv 9 enm 10 gnd 11 ref 12 lfb MAX8594 MAX8594a 3 rs 2 in 1 sdig 4 lbo 5 dbo 6 dbi 16 pv 17 pgnd 18 lxc 15 sw 14 lxl 13 enl top view thin qfn pin configuration chip information transistor count: 3436 process: bicmos
MAX8594/MAX8594a 5-output pmics with dc-dc core supply for low-cost pdas maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

▲Up To Search▲

Price & Availability of MAX8594

	To Download MAX8594 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .