4 megabit high speed cmos sram DPS128X32CV3/dps128x32bv3 description: the DPS128X32CV3/dps128x32bv3 ??versa-stack?? module is a revolutionary new high speed memory subsystem using dense-pac microsystems? ceramic stackable leadless chip carriers (slcc) mounted on a co-fired ceramic substrate. it offers 4 megabits of sram in a package envelope of 1.090 x 1.090 x 0.252 inches. the DPS128X32CV3/dps128x32bv3 contains four individual 128k x 8 srams, packaged in their own hermetically sealed slccs making the module suitable for commercial, industrial and military applications. by using slccs, the ??versa-stack?? family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or hybrid techniques. the dps128x32bv3 has one active low chip enable ( ce ) and while the DPS128X32CV3 an active low chip enable ( ce ) and an active high select line (sel). by using slccs, the ??versa-stack?? family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. features: organizations available: 128k x 32, 256k x 16, or 512k x 8 access times: 20*, 25, 30, 35, 45ns fully static operation - no clock or refresh required low power dissipation: 8.0mw (typ.) full standby 0.8w (typ.) operating (x8) single +5v power supply, 10% tolerance ttl compatible common data inputs and outputs low data retention current: 140 m a typ. (2.0v) 66-pin pga ??versa-stack?? package * commercial only. pin-out diagram note: sel applies to the DPS128X32CV3 only, no connect for the dps128x32bv3 version. pin names a0 - a16 address inputs i/o0 - i/o31 data input/output ce 0 - ce 3 low chip enables sel high chip enable we 0 - we 1 write enables oe output enable v dd power (+5v) v ss ground n.c. no connect functional block diagram this document contains information on a product that is currently released to production at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. 30a044-24 rev. f 1
DPS128X32CV3/dps128x32bv3 dense-pac microsystems, inc. recommended operating range 3 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd +0.3 v v il input low voltage -0.5 2 0.8 v t a operating temperature m -55 +25 +125 o c i -40 +25 +85 c 0 +25 +70 truth table mode sel ce w e oe i/o pin supply current not selected l x x x high-z standby not selected x h x x high-z standby d out disable h l h h high-z active read h l h l d out active write h l l x d in active h = high l = low x = don?t care note: sel applies to DPS128X32CV3 version only. dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -4.0ma 2.4 v v ol low voltage i ol =8.0ma 0.4 v absolute maximum ratings 3 symbol parameter value unit t stc storage temperature -65 to +150 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.5 to +7.0 c v i/o input/output voltage 1 -0.5 to v dd +0.5 v dc operating characteristics: over operating ranges symbol characteristics test conditions typ. (?) c i m unit min. max. min. max. min. max. i in input leakage current v in = 0v to v dd - -20 +20 -20 +20 -20 +20 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il - -10 +10 -10 +10 -10 +10 m a i cc operating supply current cycle=min., duty=100% i out = 0ma x8 175 230 245 265 ma x16 250 340 350 390 x32 400 560 560 640 i sb1 full standby supply current v in 3 v dd -0.2v or v in v ss +0.2v 1.6 20 20 40 ma i sb2 standby current (ttl) ce = v ih 100 120 140 140 ma i dr3 data retention supply current (3v) v dr = 3v, ce 3 v dr -0.2v, (or sel 0.2v, v in 3 v dd -0.2v or v in +0.2v) 0.28 1.60 2.40 8.00 ma i dr2 data retention supply current (2v) v dr = 2v, ce 3 v dr -0.2v, (or sel 0.2v, v in 3 v dd -0.2v or v in +0.2v) 0.14 1.00 1.60 7.20 ma v ol output low voltage i out = 8.0ma - 0.4 0.4 0.4 v v oh output high voltage i out = -4.0ma - 2.4 2.4 2.4 v ? typical measurements made at +25 o c, cycle = min., v dd = 5.0v. capacitance 4 : t a = 25 c, f = 1.0mhz symbol parameter max. unit condition c adr address input 50 pf v in 2 = 0v c ce chip enable 20 c sel active high chip select 50 c we write enable 25 c oe output enable 50 c i/o data input/output 20 note: c sel applies to DPS128X32CV3 version only. 30a044-24 rev. f 2
dense-pac microsystems, inc. DPS128X32CV3/dps128x32bv3 data retention waveform: sel controlled. (applies to DPS128X32CV3 only) data retention waveform: ce controlled. v dd 4.5v sel v dr2 0.4v 0v sel -0.2v v dd 4.5v 2.3v v dr1 ce 0v ce 3 v dd -0.2v data retention ac characteristics 8 symbol parameter test conditions min. typ. max. unit v dr v dd for data retention ce 3 v dr -0.2v, (sel 3 v dr -0.2v, or v in v dr -0.2v or v in 0.2v) 2.0 - - v v cdr chip disable to data retention time see data retention waveform 0 - - ns t r operation recovery time see data retention waveform 5 - - ms note: test conditions in parenthesis apply to DPS128X32CV3 version only. 30a044-24 rev. f 3
DPS128X32CV3/dps128x32bv3 dense-pac microsystems, inc. ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 20ns* 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 1 t rc read cycle time 20 25 30 35 45 ns 2 t aa address access time 20 25 30 35 45 ns 3 t co1 ce to output valid 20 25 30 35 45 ns 4 t co2 sel to output valid 20 25 30 35 45 ns 5 t oe output enable to output valid 8 10 15 20 25 ns 6 t lz1 ce to output in low-z 4, 5 3 3 3 3 3 ns 7 t lz2 sel to output in low-z 4, 5 3 3 3 3 3 ns 8 t olz output enable to output in low-z 4, 5 0 0 0 0 0 ns 9 t hz1 ce to output in high-z 4, 5 10 12 15 20 25 ns 10 t hz2 sel to output in high-z 4, 5 10 12 15 20 25 ns 11 t ohz output enable to output in high-z 4, 5 8 10 15 20 25 ns 12 t oh output hold from address change 3 3 3 3 3 ns * available in commercial only. note: t co2 , t lz2 and t hz2 apply to DPS128X32CV3 version only. ac operating conditions and characteristics - write cycle 6, 7 : over operating ranges no. symbol parameter 20ns* 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 13 t wc write cycle time 20 25 30 35 45 ns 14 t aw address valid to end of write 15 20 25 30 40 ns 15 t cw chip enable to end of write 15 20 25 30 40 ns 16 t as address set-up time ** 0 0 0 0 0 ns 17 t wp write pulse width 15 20 25 30 35 ns 18 t wr write recovery time 0 0 0 0 0 ns 19 t whz write enable to output in high-z 4, 5 8 10 12 15 20 ns 20 t dw data to write time overlap 12 15 15 20 25 ns 21 t dh data hold from write time 0 0 0 0 0 ns 22 t ow output active from end of write 3 3 3 3 3 ns * available in commercial only. ** valid for both read and write cycles. +5v 255 w 480 w c l * d out figure 1. output load * including probe and jig capacitance. output load load c l parameters measured 1 30pf except t lz1 , t lz2 , t hz1 , t hz2 , t ohz , t olz , and t whz 2 5pf t lz1 , t lz2 , t hz1 , t hz2 , t ohz , t olz , and t whz note: t lz2 and t hz2 apply to DPS128X32CV3 version only. ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns input and output timing reference levels 1.5v 30a044-24 rev. f 4
dense-pac microsystems, inc. DPS128X32CV3/dps128x32bv3 read cycle address ce sel oe data i/o write cycle 1: ce controlled. 8 address ce we data in data out 30a044-24 rev. f 5
DPS128X32CV3/dps128x32bv3 dense-pac microsystems, inc. write cycle 3: we controlled. oe is low. 8, 9 address ce we data in data out write cycle 2: we controlled. oe is high. 8, 9 address ce we data in data out 30a044-24 rev. f 6
dense-pac microsystems, inc. DPS128X32CV3/dps128x32bv3 ordering information mechanical drawing dense-pac microsystems, inc. 7321 lincoln way u garden grove, california 92841-1428 (714) 898-0007 u (800) 642-4477 (outside ca) u fax: (714) 897-1772 notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. 8. sel timing is the same as ce timing (valid for DPS128X32CV3 only). the waveform is inverted. 9. ce and we can initiate and terminate write cycle. 30a044-24 rev. f 7
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