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HT2201 cmos 1k 2-wire serial eeprom block diagram pin assignment pin description pin name i/o description sda i/o serial data inputs/output scl i serial clock data input vss negative power supply, ground vcc positive power supply rev. 1.20 1 january 6, 2006 features operating voltage: 2.2v~5.5v low power consumption operation: 5ma max. standby: 4 a max. internal organization: 128 8 2-wire serial interface write cycle time: 5ms max. automatic erase-before-write operation write operation with built-in timer 40-year data retention 10 6 erase/write cycles per word industrial temperature range ( 40 cto+85 c) 4-pin sip, sot-25 package general description the HT2201 is a 1k-bit serial read/write non-volatile memory device using the cmos floating gate process. its 1024 bits of memory are organized into 128 words and each word is 8 bits. the device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. the HT2201 is guaranteed for 1 million erase/write cycles and 40-year data retention.

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absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage .............................v ss 0.3v to v cc +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta = 40 c~85 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.2 5.5 v i cc1 operating current 5v read at 100khz 2ma i cc2 operating current 5v write at 100khz 5ma v il input low voltage 1 0.3v cc v v ih input high voltage 0.7v cc v cc +0.5 v v ol output low voltage 2.4v i ol =2.1ma 0.4 v i li input leakage current 5v v in =0 or v cc 1 a i lo output leakage current 5v v out =0 or v cc 1 a i stb1 standby current 5v v in =0 or v cc 4 a i stb2 standby current 2.4v v in =0 or v cc 3 a c in input capacitance (see note) f=1mhz 25 c 6pf c out output capacitance (see note) f=1mhz 25 c 8pf note: these parameters are periodically sampled but not 100% tested HT2201 rev. 1.20 2 january 6, 2006
a.c. characteristics ta = 40 c~85 c symbol parameter remark standard mode* v cc =5v 10% unit min. max. min. max. f sk clock frequency 100 400 khz t high clock high time 4000 600 ns t low clock low time 4700 1200 ns t r sda and scl rise time note 1000 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the first clock pulse is generated 4000 600 ns t su:sta start condition setup time only relevant for repeated start condition 4000 600 ns t hd:dat data input hold time 0 0 ns t su:dat data input setup time 200 100 ns t su:sto stop condition setup time 4000 600 ns t aa output valid from clock 3500 900 ns t buf bus free time time in which the bus must be free before a new transmission can start 4700 1200 ns t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns t wr write cycle time 5 5ms note: these parameters are periodically sampled but not 100% tested * the standard mode means v cc =2.2v to 5.5v for relative timing, refer to timing diagrams HT2201 rev. 1.20 3 january 6, 2006
HT2201 rev. 1.20 4 january 6, 2006 functional description serial clock (scl) the scl input is used for positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda) the sda pin is bidirectional for serial data transfer. the pin is open-drain driven and may be wired-or with any number of other open-drain or open collector devices. memory organization HT2201, 1k-bit serial eeprom internally organized with 128 8-bit words, the HT2201 requires an 8-bit data word address for ran - dom word addressing. device operations clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in data line while the clock line is high will be interpreted as a start or stop condition. start condition a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (re- fer to start and stop definition timing diagram). acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has re - ceived each word. this happens during the ninth clock cycle. device addressing the HT2201 requires an 8-bit device address word fol - lowing a start condition to enable the chip for a read or write operation. the device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the device address). this is common to all the eeprom device. the next three bits are fixed to zeros. the 8th bit of device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. write operations byte write a write operation requires an 8-bit data word address following the device address word and acknowledg - ment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the addressing de - vice, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle to the non-volatile memory. all inputs are disabled during this write cycle and eeprom will not respond until the write is completed (refer to byte write timing). acknowledge polling to maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write com- mand have been sent. if the device is still busy imple- menting its write cycle, then no ack will be returned. the master can send the next read/write command when the ack signal has finally been received. read operations the HT2201 supports three read operations, namely, current address read, random address read and se - quential read. during read operation execution, the read/write select bit should be set to 1 .
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HT2201 rev. 1.20 5 january 6, 2006 current address read the internal data word address counter maintains the last address accessed during the last read or write op - eration, incremented by one. this address stays valid between operations as long as the chip power is main - tained. the address roll over during read from the last byte of the last memory page to the first byte of the first page. the address roll over during write from the last byte of the current page to the first byte of the same page. once the device address with the read/write se - lect bit set to one is clocked in and acknowledged by the eeprom, the current address data word is seri - ally clocked out. the microcontroller should respond a no ack (high) signal and following stop condition (re - fer to current read timing). random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start con - dition. the microcontroller now initiates a current ad - dress read by sending a device address with the read/write select bit high. the eeprom acknowl - edges the device address and serially clocks out the data word. the microcontroller should respond with a no ack signal (high) followed by a stop condition. (refer to random read timing). sequential read sequential reads are initiated by either a current ad - dress read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the sequential read operation is terminated when the microcontroller responds with a no ack sig - nal (high) followed by a stop condition. # ) " / % $ ) % $
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timing diagrams note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. HT2201 rev. 1.20 6 january 6, 2006 ' ) * * 9 : 7
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package information 4-pin sip outline dimensions symbol dimensions in mil min. nom. max. a 203 208 b 141 146 c 543 583 d13 17 e 148 152 f48 52 g27 30 h59 63 HT2201 rev. 1.20 7 january 6, 2006
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sot-25 outline dimensions symbol dimensions in mm min. nom. max. a1 1.3 a1 0.1 a2 0.7 0.9 b 0.35 0.5 c 0.1 0.25 d 2.7 3.1 e 1.4 1.8 e 1.9 h 2.6 3 l 0.37 1 9 HT2201 rev. 1.20 8 january 6, 2006 * !
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product tape and reel specifications reel dimensions sot-25 symbol description dimensions in mm a reel outer diameter 178 1 b reel inner diameter 62 1 c spindle hole diameter 13 0.2 d key slit width 2.5 0.25 t1 space between flange 8.4+1.5 t2 reel thickness 11.4+1.5 HT2201 rev. 1.20 9 january 6, 2006
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carrier tape dimensions sot-25 symbol description dimensions in mm w carrier tape width 8 0.3 p cavity pitch 4 e perforation position 1.75 f cavity to perforation (width direction) 3.5 0.05 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.1 p0 perforation pitch 4 p1 cavity to perforation (length direction) 2 a0 cavity length 3.15 b0 cavity width 3.2 k0 cavity depth 1.4 t carrier tape thickness 0.2 0.03 c cover tape width 5.3 HT2201 rev. 1.20 10 january 6, 2006 " ) " " 1 ! ; 0 1 & 1
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HT2201 rev. 1.20 11 january 6, 2006 copyright
2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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