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rev 0.5 / jun. 2006 1 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash document title 256mbit (32mx8bit / 16mx 16bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. apr. 04. 2005 preliminary 0.1 1) change ac parameter 2) change 256mb package type. - wsop package is changed to usop package. - figure & dimension are changed. jul. 07. 2005 preliminary 0.2 1 ) correct the test conditions (dc characteristics table) 2 ) change ac conditions table 3 ) add tww parameter ( tww = 100ns, min) - texts & figures are added. - tww is added in ac timing characteristics table. 4) edit copy back program operation step 5) edit system interface using ce don?t care figures. 6) correct address cycle map. 7) change nop (table 11) aug. 08. 2005 preliminary tcry(1.8v) before 50+tr(r/b#) after 60+tr(r/b#) test conditions ( i cc1) test conditions ( i li, i lo ) before t rc =50ns, ce#= v il , i out =0ma vin=vout=0 to 3.6v after t rc (1.8v=60ns, 3.3v=50ns) ce#= v il , i out =0ma vin=vout=0 to vcc (max) main array spare array before 1 2 after 2 3
rev 0.5 / jun. 2006 2 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash revision history - continued - revision no. history draft date remark 0.2 8) correct pkg dimension (tsop, usop pkg) 9) change vil parameter (max.) 10) change ac parameter aug. 08. 2005 preliminary 0.3 1) correct usop figure. nov. 07. 2005 preliminary 0.4 1) correct figure 32. feb. 06. 2006 preliminary 0.5 1) add ecc algorithm. (1bit/512bytes) 2) delet preliminary. 3) change ac parameter 4) correct read id naming jun. 20. 2006 cp before 0.050 after 0.100 1.8v 3.3v before 0.2xvcc 0.2xvcc after 0.4 0.8 toh trp trea before 15 30 35 after 10 25 30 tr (1.8v) tcry (1.8v) tcry (3.3v) before 12 50+tr(r/b#) (4) 50+tr(r/b#) (4) after 15 80+tr(r/b#) (4) 60+tr(r/b#) (4) twhr before 60 ns after 50 ns
rev 0.5 / jun. 2006 3 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27usxx561a - 1.8v device: vcc = 1.7 to 1.95v : hy27ssxx561a memory cell array = (512+16) bytes x 32 pages x 2,048 blocks = (256+8) words x 32 pages x 2,048 blocks page size - x8 device : (512 + 16 spare) bytes : hy27(u/s)s08561a - x16 device: (256 + 8 spare) words : hy27(u/s)s16561a block size - x8 device: (16k + 512 spare) bytes - x16 device: (8k + 256 spare) words page read / program - random access: 3.3v: 12us (max.) 1.8v: 15us (max.) - sequential access: 3.3v: 50ns (min.) 1.8v: 60ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering fast block erase - block erase time: 2ms (typ.) status register electronic signature - 1st cycle : manufacturer code - 2nd cycle: device code chip enable don't care - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles (with 1bit/512byte ecc) - 10 years data retention package - hy27(u/s)s(08/16)561a-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27(u/s)s(08/16)561a-t (lead) - hy27(u/s)s(08/16)561a-tp (lead free) - hy27(u/s)s(08/16)561a-s(p) : 48-pin usop1 (12 x 17 x 0.65 mm) - hy27(u/s)s(08/16)561a-s (lead) - hy27(u/s)s(08/16)561a-sp (lead free) - hy27(u/s)s(08/16)561a-f(p) : 63-ball fbga (9 x 11 x 1.0 mm) - hy27(u/s)s(08/16)561a-f (lead) - hy27(u/s)s(08/16)561a-fp (lead free)
rev 0.5 / jun. 2006 4 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 1. summary description the hynix hy27(u/s)s(08/16)561a series is a 32mx8bit with spare 8mx16 bit capacity. the device is offered in 1.8v vcc power supply and in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 2048 blocks, composed by 32 pages cons isting in two nand structures of 16 series connected flash cells. a program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce , we , ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp input pin. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multi- ple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of the hy27(u/s)s(08/16)561a extended reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. the chip could be offered with the ce don?t care function. this function allows the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not st op the read operation. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. this device includes also extra features like otp/unique id area, block lock mechanism, automatic read at power up, read id2 extension. the hynix hy27(u/s)s(08/16)561a series is available in 48 - tsop1 12 x 20 mm , 48 - usop1 12 x 17 mm, fbga 9 x 11 mm. 1.1 product list part number orization vcc range package HY27SS08561A x8 1.70 - 1.95 volt 63fbga / 48tsop1 / 48usop1 hy27ss16561a x16 hy27us08561a x8 2.7v - 3.6 volt hy27us16561a x16
rev 0.5 / jun. 2006 5 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 9&& 966 35( :3 &/( $/( 5( :( &( ,2a,2 ,2a,2[2qo\ 5% figure1: logic diagram io15 - io8 data input / outputs (x16 only) io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection pre power-on read enable, lock unlock table 1: signal names
rev 0.5 / jun. 2006 6 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 8623 [ figure 2. 48tsop1 contac tions, x8 and x16 device figure 3. 48usop1 contactions, x8 and x16 device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk 8623 [
rev 0.5 / jun. 2006 7 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 1& 1& 1& 1& 1& 1& 1& 1& &/( $/( 9vv 9vv 9vv 9ff 9ff 1& 1& 1& :3 5( &( :( 5% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 35( 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 1& 1& 1& 1& 1& 1& 1& 1& &/( $/( 9vv 9vv 9vv 9ff 9ff 1& 1& 1& :3 5( &( :( 5% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 35( ,2 1& 1& 1& 1& 1& ,2 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 figure 4. 63fbga contactions, x8 device (top view through package) figure 5. 63fbga contactions, x16 device (top view through package)
rev 0.5 / jun. 2006 8 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 1 .2 pin description pin name description io0-io7 io8-io15(1) data inputs/outputs the io pins allow to input comma nd, address and data and to outp ut data during read / program operations. the inputs are latched on th e rising edge of write enable (we ). the i/o buffer float to high-z when the device is desele cted or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of th e device. when the device is busy ce low does not deselect the memory. we write enable this input acts as clock to latch command, addre ss and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protection against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection pre to enable and disable the lock mechanism and power on auto read. when pre is a logic high, block lock mode and power-on auto-read mode ar e enabled, and when pre is a logic low, block lock mode and power-on auto-read mode are disa bled. power-on auto-read mode is available only on 3.3v device. not using lock mechanism & power-on auto -read, connect it v ss or leave it nc. table 2: pin description note: 1. for x16 version only 2. a 0.1uf capacitor should be connected between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widt hs must be sufficient to carry the currents required during program and erase operations.
rev 0.5 / jun. 2006 9 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a9 a10 a11 a12 a13 a14 a15 a16 3rd cycle a17 a18 a19 a20 a21 a22 a23 a24 table 3: address cycle map(x8) note: 1. a8 is set to low or high by the 00h or 01h command. io0 io1 io2 io3 io4 io5 io6 io7 io8-io15 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 l (1) 2nd cycle a9 a10 a11 a12 a13 a14 a15 a16 l (1) 3rd cycle a17 a18 a19 a20 a21 a22 a23 a24 l (1) table 4: address cycle map(x16) note: 1. l must be set to low. function 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy read 1 00h /01 h -- read 2 50h - - read id 90h - - reset ffh - - yes page program 80h 10h - copy back pgm 00h 8ah (10h) block erase 60h d0h - read status register 70h - - yes lock block 2ah lock tight 2ch unlock (start area) 23h unlock (end area) 24h read lock status 7ah table 5: command set
rev 0.5 / jun. 2006 10 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash cle ale ce we re wp mode h l l rising h x read mode command input l h l rising h x address input(3 cycles) h l l rising h h write mode command input l h l rising h h address input(3 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 6: mode selection note: 1. with the ce high during latency time does not stop the read operation
rev 0.5 / jun. 2006 11 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 7 and table 12 for details of the timings requirements. command codes are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.2 address input. address input bus operation allows the in sertion of the memory address. three bus cycles are required to input the addresses for the 256mbit devices. addresses are accepted with chip enable low, addr ess latch enable high, com- mand latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protec t pin must be high. see figure 8 and table 12 for details of the timings requirements. addresses are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.3 data input. data input bus operation allows to feed to the device the data to be programm ed. the data insertion is serially and timed by the write enable cycles. data are accepted only wi th chip enable low, addre ss latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 9 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the me mory array and to check the st atus register content, the lock status and the id data. data can be serially shifted ou t toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figures 10 to 14 and table 12 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev 0.5 / jun. 2006 12 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 3. device operation 3.1 page read. upon initial device power up, the device defaults to read1 mo de. this operation is also in itiated by writing 00h to the command register along with followed by the three address input cycles. once the command is latched, it does not need to be written for the following page read operation. three types of operations are available: random read, serial page read and sequential row read. the random read mode is enabled when the page addre ss is changed. the 528 bytes (x8 device) or 264 word (x16 device) of data within the sele cted page are transferred to the data regist ers in less than access random read time tr (12us). the system controller can detect the completion of th is data transfer tr (12us) by analyzing the output of r/b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially puls- ing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. after the data of last column address is clocked out, the next page is automati cally selected for sequential row read. waiting tr again allows reading the selected page. the sequ ential row read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. writing the read2 command user may selectively access the spare area of bytes 512 to 527. addresses a0 to a3 set the start- ing address of the spare area while addresses a4 to a7 are ignored. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 command (00h/01h) is needed to move the pointer back to the main area. figure_12 to 15 show typical sequence and timings for each read operation. devices with automatic read of page0 at power up can be provided on request. 3.2 page program. the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 (x8 device), in a single page program cycle. the number of consecutive partial page pro- gramming operations within the same pa ge without an intervening erase operation must not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes (x8 devi ce) or 264 word (x16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to figure_29, 30. the data-loading sequence begins by in putting the serial data input command (80h), followed by the three address input cycles and then serial data loading. the page prog ram confirm command (10h) star ts the programming process. writing 10h alone without previously ente ring the serial data will not initiate the programming process. the internal program erase controller automatically executes the algori thms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit (i/o 6) of th e status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked figure_16. the internal write verify detects only errors for "1"s th at are not successfully programmed to "0"s. the command reg- ister remains in read status comman d mode until another valid command is written to the command register.
rev 0.5 / jun. 2006 13 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 3.3 block erase. the erase operation is done on a block (16k byte) basis. it consists of an erase setup command (60h), a block address loading and an erase confirm command (d0h). the erase confirm command (d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setu p followed by execution com- mand ensures that memory contents are not accidentally erased due to external noise conditions. the block address loading is accomplished in two to thr ee cycles depending on the device density. only block addresses (a14 to a24) are needed while a9 to a13 is ignored. at the rising edge of we after the erase confirm command input, the internal program erase controller handles erase and erase-verify. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure_18 details the sequence. 3.4 copy-back program. the copy-back program is provided to quickly and efficientl y rewrite data stored in one page within the plane to another page within the same plane without using an external memory. si nce the time-consuming sequential-reading and its reloading cycles are removed, the system performanc e is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back program is a sequenti al execution of page-read without burst-reading cycle and copying-program with the address of destination page. a no rmal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. as soon as the device returns to ready state, page-copy data-input command (8ah) with the address cycles of destination page followed may be written. the program confirm command (10h) is not needed to actually begin the programming operation. for backward-compati- bility, issuing program confirm comma nd during copy-back does not affe ct correct device operation. copy-back program operation is allowed only within the same memory plane. once the co py-back program is finished, any additional partial page programming into the copied pages is prohibited be fore erase. plane address must be the same between source and target page "when there is a program-failure at copy-back operatio n, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit e rror due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 17 shows the command sequ ence for the copy-back operation .the copy back program operation requires three steps: - 1 . t h e s o u r c e p a g e m u s t b e r e a d u s i n g t h e re a d a c o m m a n d ( o n e b u s w r i t e c y c l e t o s e t u p t h e c o m m a n d a n d t h e n 3 bus cycles to input the source page address.) this operation copies all 264 words/ 528 bytes from the page into the page buffer. - 2. when the device returns to the ready state (ready/busy high), the seco nd bus write cycle of the command is given with the 3cycles to inpu t the target page address. a24 must be th e same for the source and target pages. - 3. then the confirm command is is sued to start the p/e/r controller.
rev 0.5 / jun. 2006 14 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or eras e operation is completed successfully. after writing 70h command to the com- mand register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle. 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. two read cycles sequentially output the manufacturer code (adh ), the device code. the com- mand register remains in read id mode until further co mmands are issued to it. fi gure 19 shows the operation sequence, while tables 13, 14 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the st atus register is cleared to value e0h when wp is high. refer to table 12 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst afte r the reset command is written. refer to figure 25.
rev 0.5 / jun. 2006 15 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 4. other features 4.1 data protection & power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions whenever vcc is below about 1.1v(1.8v device), 2v(3.3v device). wp pin pro- vides hardware protection and is recommended to be kept at vil during power-up and power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 26. the two-step command sequence for program/erase provides additional software protection. if the power is dropped during the ready read/write/erase operation, power protection function may not guaranteed the data. power protection function is only available during the power on/off sequence. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back, cache program and ra ndom read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it re turns to high when the internal controller has finished the operation. the pin is an open-drain dr iver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig 27). its valu e can be determined by the following guidance. 4.3 lock block feature in high state of pre pin, block lock mode and power on auto read are enabled, otherwise it is regarded as nand flash without pre pin. block lock mode is enabled while pre pin state is high, which is to offer protec tion features for nand flash data. the block lock mode is divided into unlock , lock, lock-tight operation. consecutive blocks protects data allows those blocks to be locked or lock-tighten with no latency. this block lock scheme offers two levels of protection. the first allows software control (command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control (wp low pulse input method) before lock ing can be changed that is useful for protecting infrequently changed code blocks. the followings summarized the locking functionality. - all blocks are in a locked state on power-up . unlock sequence can unlock the locked blocks. - the lock-tight command locks blocks and prevents from being unlocked. lock-tight stat e can be returned to lock state only by hardware control(wp low pulse input). 1. block lock operation 1) lock - command sequence: lock bloc k command (2ah). see fig. 20. - all blocks default to locked by power-up and hardware control (wp low pulse input) - partial block lock is not available; lock block operation is based on all block unit - unlocked blocks can be locked by using the lock block command, and a lo ck block?s status can be changed to unlock or lock-tight using the appropriate commands - on the program or erase operation in locked or lock-tighten block, busy state holds 1~10us(tlbsy)
rev 0.5 / jun. 2006 16 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 2) unlock - command sequence: unlock block command (23h) + star t block address + command (24h) + end block address. see fig. 21. - unlocked blocks can be programmed or erased. - an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate sequence of commands. - only one consecutive area can be released to unlock st ate from lock state; unlockin g multi area is not available. - start block address must be nearer to the logica l lsb (least significant bit) than end block address. - one block is selected for unlocking block when start block address is same as end block address. 3) lock-tight - command sequence: lock-tight block command (2ch). see fig. 22. - lock-tighten blocks offer the user an additional level of wr ite protection beyond that of a regular lock block. a block that is lock-tighten can?t have its state change d by software control, only by hardware control (wp low pulse input); unlocking multi area is not available - only locked blocks can be lo ck-tighten by lock-tight command. - on the program or erase operation in locked or lock-tighten block, busy state holds 1~10us(tlbsy) 4) lock block boundaries after unlock command issuing - if start block address = 0000h and end bloc k address = ffffh , the device is all unlocked - if start block address = end block address = ffffh , the device is all locked except for the last block - if start block address = end block address = 0000h , the device is all locked except for the first block 2. block lock status read block lock status can be read on a block basis to find ou t whether designated block is available to be programmed or erased. after writing 7ah command to the command register and block address to be chec ked, a read cycle outputs the content of the block lock status register to the i/o pins on the falling edge of ce or re , whichever occurs last. re or ce does not need to be toggled for updated status. block lo ck status read is prohibited while the device is busy state. refer to table 16 for specific status register definitions. the command regist er remains in block lock status read mode until further commands are issued to it. in high state of pre pin, write protection status ca n be checked by block lock status read (7ah) while in low state by status read (70h). 4.4 power-on auto-read the device is designed to offer automa tic reading of the first page without command and address input sequence dur- ing power-on. an internal voltage detector enables auto-page read functi ons when vcc reaches about 1.8v. pre pin controls activa- tion of auto-page read function. auto-page read function is enabled only when pre pin is lo gic high state. serial access may be done after power-on without latency. power-on auto read mode is available only on 3.3v device.
rev 0.5 / jun. 2006 17 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash parameter symbol min typ max unit valid block number n vb 2008 2048 blocks table 6: valid blocks number note: 1. the 1st block is guaranteed to be a valid bl ock up to 1k cycles without ecc. (1bit/512bytes) symbol parameter value unit 1.8v 3.3v t a ambient operating temperature (commercial temperature range) 0 to 70 0 to 70 ambient operating temperature (extended temperature range) -25 to 85 -25 to 85 ambient operating temperature (industrial temperature range) -40 to 85 -40 to 85 t bias temperature under bias -50 to 125 -50 to 125 t stg storage temperature -65 to 150 -65 to 150 v io (2) input or output voltage -0.6 to 2.7 -0.6 to 4.6 v vcc supply voltage -0.6 to 2.7 -0.6 to 4.6 v table 7: absolute maximum ratings note: 1. except for the rating ?operating temperature range?, stresses above those listed in the table ?absolute maximum ratings? may cause perm anent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tr ansition and for less than 20ns during transitions.
rev 0.5 / jun. 2006 18 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( 35( $a$ figure 6: block diagram
rev 0.5 / jun. 2006 19 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash parameter symbol test conditions 1.8volt 3.3volt unit min typ max min typ max operating current sequential read i cc1 t rc (1.8v=60ns, 3.3v=50ns) ce =v il , i out =0ma -815-1020ma program i cc2 - - 8 15 - 10 20 ma erase i cc3 - - 8 15 - 10 20 ma stand-by current (ttl) i cc4 ce =v ih , pre=wp =0v/vcc --1 - 1ma stand-by current (cmos) i cc5 ce =vcc-0.2, pre=wp =0v/vcc - 10 50 - 10 50 ua input leakage current i li v in= 0 to vcc (max) - - 10 -- 10 ua output leakage current i lo v out =0 to vcc (max) - - 10 -- 10 ua input high voltage v ih - vcc-0.4 - vcc+0. 3 2- vcc+0. 3 v input low voltage v il - -0.3 - 0.4 -0.3 - 0.8 v output high voltage level v oh i oh =-100ua vcc-0.1 - - - - - v i oh =-400ua - - - 2.4 - - v output low voltage level v ol i ol =100ua - - 0.1 - - - v i ol =2.1ma - - - - - 0.4 v output low current (r/ b ) i ol (r/b ) v ol =0.2v 3 4 - - - - ma v ol =0.4v - - - 8 10 - ma table 8: dc and operating characteristics parameter value 1.8volt 3.3volt input pulse levels 0v to vcc 0.4v to 2.4v input rise and fall times 5ns 5ns input and output timing levels vcc / 2 1.5v output load (1.7v - 1.95volt & 2.7v - 3.3v) 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf output load (3.0v - 3.6v) 1 ttl gate and cl=100pf table 9: ac conditions
rev 0.5 / jun. 2006 20 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf table 10: pin capacita nce (ta=25c, f=1.0mhz) parameter symbol min typ max unit program time t prog - 200 500 us dummy busy time for the lock or lock-tight block t lbsy -510us number of partial program cycles in the same page main array nop - - 2 cycles spare array nop - - 3 cycles block erase time t bers -23ms table 11: program / erase characteristics
rev 0.5 / jun. 2006 21 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash parameter symbol 1.8volt 3.3volt unit min max min max cle setup time t cls 00ns cle hold time t clh 10 10 ns ce setup time t cs 00ns ce hold time t ch 10 10 ns we pulse width t wp 40 25 (1) ns ale setup time t als 00ns ale hold time t alh 10 10 ns data setup time t ds 20 20 ns data hold time t dh 10 10 ns write cycle time t wc 60 50 ns we high hold time t wh 20 15 ns data transfer from cell to register t r 15 12 us ale to re delay (id read) t ar 10 10 ns cle to re delay t clr 10 10 ns ready to re low t rr 20 20 ns re pulse width t rp 40 25 ns we high to busy t wb 100 100 ns read cycle time t rc 60 50 ns re access time t rea 35 30 ns re high to output high z t rhz 30 30 ns ce high to output high z t chz 20 20 ns re or ce high to output hold t oh 10 10 ns re high hold time t reh 20 15 ns output high z to re low t ir 00ns ce access time t cea 45 45 ns we high to re low t whr 50 50 ns last re high to busy (at sequential read) t rb 100 100 ns ce high to ready (in case of interception by ce at read) t cry 80+tr(r/b#) (4) 60+tr(r/b#) (4) ns ce high hold time (at the last serial read) (3) t ceh 100 100 ns device resetting time (read / program / erase) t rst 5/10/500 (2) 5/10/500 (2) us write protection time t ww (5) 100 100 ns table 12: ac timing characteristics note: 1. if t cs is less than 10ns t wp must be minimum 35ns, otherwise, t wp may be minimum 25ns. 2. if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5us 3. to break the sequential read cycle, ce must be held for longer time than tceh. 4. the time to ready depends on the value of the pull-up resistor tied r/b pin.ting time. 5. program / erase enable operation : wp high to we high. program / erase disable operation : wp low to we high
rev 0.5 / jun. 2006 22 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash io page program block erase read coding 0 pass / fail pass / fail na pass: ?0? fail: ?1? 1na na na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na - 3na na na - 4na na na - 5 ready/busy ready/busy ready/busy active: ?0? idle: ?1? 6 ready/busy ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect protected: ?0? not protected: ?1? table 13: status register coding device identifier cycle description 1st manufacturer code 2nd device identifier table 14: device identifier coding part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) hy27us08561a 3.3v x8 adh 75h hy27us16561a 3.3v x16 adh 55h HY27SS08561A 1.8v x8 adh 35h hy27ss16561a 1.8v x16 adh 45h table 15: read id data table
rev 0.5 / jun. 2006 23 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash figure 7: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2a w'+ w'6 w$/6 w$/+ w&/+ w&+ table 16: lock status code
rev 0.5 / jun. 2006 24 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash w&/6 w&6 w:& w:& vw$gg w:3 w:3 w:3 w:+ w:+ w$/6 w$/6 w$/6 w$/+ w$/+ w$/+ w'6 w'6 w'6 w'+ w'+ w'+ qg$gg ug$gg &/( &( :( $/( ,2a figure 8: address latch cycle
rev 0.5 / jun. 2006 25 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w:+ w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( figure 10: sequential out cycle after read (cle=l, we =h, ale=l) notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t cea t rea t rp t rea t rhz* t rhz* dout dout dout t chz* t oh t oh t rea t reh t rc t rr ce re r/b i/ox figure 9. in put data latch cycle
rev 0.5 / jun. 2006 26 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash figure 11: status read cycle t cls t clr t clh t cs t ch t wp t whr t cea t ds t rea t chz t rhz 70h status output t dh t ir ce we i/o 0-7 cle re cle ce we ale re i/o 0~7 r/b twc tceh tchz tcry trhz trc tr tar twb trp 00h or 01h col. add 1 row add 1 row add 2 dout n dout n+1 dout n+2 dout 527 trb column address page(row) address busy figure 12: read1 operation (read one page)
rev 0.5 / jun. 2006 27 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash cle ce we ale re i/o 0~7 r/b 00h or 01h col. add 1 row add 1 row add 2 dout n dout n+1 dout n+2 busy column address row address trp trc tr twb tar tchz figure 13: read1 operation intercepted by ce cle ce we ale re i/o0~7 r/b tr tar twb trr 50h col. add 1 row add 1 row add 2 dout 511+m dout 527 m address a0-a3: valid address a4-a7: dont care selected row 512 16 start address m figure 14: read2 operation (read one page)
rev 0.5 / jun. 2006 28 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash cle ce we ale re i/o0~7 r/b 00h col. add1 row add1 row add2 dout n dout n+1 dout 527 dout 0 dout 1 dout 527 m n output m+1 output busy busy ready figure 15: sequential row read operation within a block
rev 0.5 / jun. 2006 29 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash figure 16: page program operation cle ale ce re r/b i/ox we twc 80h col. add1 serial data input command column address row address read status command program command i/oo=0 successful program i/oo=1 error in program 1upto512byte serial input row add1 row add2 din n din m 10h 70h i/oo twc twc twb tprog
rev 0.5 / jun. 2006 30 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash twc twb tr tprog i/o0 70h 8ah row add1 row add2 col. add1 row add1 row add2 col. add1 00h column address row address column address row address read status command busy busy i/o0=0 successful program i/o1=1 error in program copy-back data input command 10h write cycle no more cle ce we ale re i/o 0~7 r/b figure 17 : copy back program
rev 0.5 / jun. 2006 31 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash w:& &/( &( :( $/( 5( ,2 a 5% w:% w%(56 %86< k ,2 'k 5rzdgg 5rzdgg k $xwr%orfn(udvh6hwxs&rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 3djh5rz$gguhvv figure 18: block erase op eration (erase one block) k &/( &( :( $/( 5( ,2a k w5($ w$5 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k k figure 19: read id operation
rev 0.5 / jun. 2006 32 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash $k /rfn&rppdqg :3 &/( &( :( ,2[ figure 20: lock command :3 &/( &( :( $/( ,2[ k 8qrfn&rppdqg 6wduw%orfn$gguhvvf\fohv 8qorfn&rppdqg (qg%orfn $gguhvvf\fohv k $gg $gg $gg $gg figure 21: unlock command sequence
rev 0.5 / jun. 2006 33 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash :3 &/( &( :( ,2[ &k /rfnwljkw&rppdqg figure 22: lock tight command :3 &/( $/( &( :( ,2[ 5( $k $gg $gg 'rxw 5hdg%orfn/rfn vwdwxv&rppdqg %orfn$gguhvvf\foh w:+5 %orfn/rfn6wdwxv figure 23: lock st atus read timing
rev 0.5 / jun. 2006 34 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 9 9ff :( &( $/( &/( 5% 35( w5 5( ,2[ 'dwd 'dwd 'dwd 'dwd2xwsxw /dvw 'dwd figure 24: automatic power at power on ffh t rst we ale cle re io7:0 r/b figure 25: reset operation
rev 0.5 / jun. 2006 35 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash :3 :( 9ff xv w 9 7+ figure 26: power on / off timing vth = 1.5 volt for 1.8 volt supply devices; 2.5 volt for 3.3 volt supply devices
rev 0.5 / jun. 2006 36 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash 5sydoxhjxlghqfh 5splq zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) )lj5syvwuwi 5syvlexv\ 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 wu wi 9 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 27: ready/busy pin electrical specifications
rev 0.5 / jun. 2006 37 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash figure 28: lock/unlock fsm flow cart ['hylfhv $uhd$ k $uhd% k $uhd& k %\whv %\whv %\whv $%& 3rlqwhu kkk 3djh%xiihu ['hylfhv $uhd$ k $uhd& k %\whv %\whv $& 3rlqwhu kk 3djh%xiihu figure 29: pointer operations
rev 0.5 / jun. 2006 38 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k $5($$ $5($% $5($& ,2 ,2 ,2 $uhdv$%&fdqehsurjudpphgghshqglqjrqkrzpxfkgdwdlvl qsxw6xevhtxhqwkfrppdqgvfdqehrplwwhg $uhdv%&fdqehsurjudpphgghshqglqjrqkrzpxfkgdwdlvlqsx w7khkfrppdqgpxvwehuhlvvxhgehiruhhdfksurjudp 2qo\$uhdv&fdqehsurjudpphg6xevhtxhqwkfrppdqgfdqehr plwwhg figure 30: pointer operations for porgramming
rev 0.5 / jun. 2006 39 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash system interface using ce don?t care to simplify system interface, ce may be inactive during data loading or sequential data-reading as shown below. so, it is possible to connect nand flash to a microprocess or. the only function that was removed from standard nand flash to make ce don?t care read operation was disabling of the automatic sequential read function. jsl hsl pvv? jl ~l _w? xw? z????gh??uozj????p k???gp???? k???gp???? jlg???n?t???? figure 31: program operation with ce don?t-care. ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh w5 k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo figure 32: read operation with ce don?t-care.
rev 0.5 / jun. 2006 40 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transi stor. the devices are supplied with al l the locations inside valid blocks erased(ffh).the bad block information is written prior to shipping. any block where the 6th byte/ 1st word in the spare area of the 1st or 2nd page (if the 1st page is bad) does not contain ffh is a bad block. the bad block informa- tion must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is reco mmended to create a bad block table fol- lowing the flowchart shown in figure 33. the 1st block, whic h is placed on 00h block addr ess is guaranteed to be a valid block. block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.the copy back program command can be used to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 17 for the recommended procedure to follow if an error occurs during an operation. operation recommended procedure erase block replacement program block replacement or ecc (with 1bit/512byte) read ecc (with 1bit/512byte) table 17: block failure <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh figure 33: bad block management flowchart
rev 0.5 / jun. 2006 41 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 34~37) :: w k k :( ,2[ :3 5% k k w :: :( ,2[ :3 5% figure 34: enable programming figure 35: disable programming
rev 0.5 / jun. 2006 42 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 36: enable erasing figure 37: disable erasing
rev 0.5 / jun. 2006 43 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash table 18: 48pin-tsop1, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 figure 38: 48pin-tsop1, 12 x 20mm, package outline ' $ ',( $ h % / . ( ( & &3 $
rev 0.5 / jun. 2006 44 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash symbol millimeters min typ max a 0.650 a1 0 0.050 0.080 a2 0.470 0.520 0.570 b 0.130 0.160 0.230 c 0.065 0.100 0.175 c 1 0.450 0.650 0.750 cp 0.100 d 16.900 17.000 17.100 d1 11.910 12.000 12.120 e 15.300 15.400 15.500 e0.500 alpha 0 8 table 19: 48 p in-usop1 , 12 x 17mm , packa g e mechanical data figure 39. 48pin-us op1, 12 x 17mm, package outline $ $ $ & ' ( & h % $qjoh doskd ' . &3
rev 0.5 / jun. 2006 45 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash symbol millimeters min typ max a 0.80 0.90 1.00 a1 0.25 0.30 0.35 a2 0.55 0.60 0.65 b 0.40 0.45 0.50 d 8.90 9.00 9.10 d1 4.00 d2 7.20 e 10.90 11.00 11.10 e1 5.60 e2 8.80 e0.80 fd 2.50 fd1 0.90 fe 2.70 fe1 1.10 sd 0.40 se 0.40 ' ' 6' )' )' $ $ $ 6( )( )( ( ( %$//3$ ( h h ggg h e ' figure 40. 63ball-fbga, pakage outline note : drawing is not to scale. table 20: 63ball-fbga, pakage mechanical data
rev 0.5 / jun. 2006 46 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash marking information - tsop1/usop packag marking example tsop1 / usop k o r h y 2 7 x s x x 5 6 x a x x x x y w w x x - hynix - ko r - hy27xsxx56xa xxxx h y: hynix 27: nand flash x: power supply s: classification xx: bit o rganization 56: density x: mode a : version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix sym bol : o rigin c ountry : u(2.7v~3.6v), l(2.7v), s(1.8v) : single level c ell+ single d ie+ sm all b lock : 08(x8), 16(x16) : 256mbit : 1(1nce & 1r/nb; sequential row read enable) 2(1nce & 1r/nb; sequential row read disable) : 2nd generation : t(48-tsop1), s(48-usop) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) m(-30 ~85 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part num ber
rev 0.5 / jun. 2006 47 hy27us(08/16)561a series hy27ss(08/16)561a series 256mbit (32mx8bit / 16 mx16bit) nand flash marking information - fbga packag marking example fbga k o r h y 2 7 x s x x 5 6 x a x x x x y w w x x - hynix - kor - hy27xsxx56xa xxxx hy: hynix 27: nand flash x: power supply s: classification xx: bit organization 56: density x: mode a: version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u(2.7v~3.6v), l(2.7v), s(1.8v) : single level cell+ single die+ sm all block : 08(x8), 16(x16) : 256mbit : 1(1nce & 1r/nb; sequential row read enable) 2(1nce & 1r/nb; sequential row read disable) : 2nd generation : f(63fbga) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) m(-30 ~85 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part num ber

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