uc2909 uc3909 description the uc3909 family of switchmode lead-acid battery chargers accurately controls lead acid battery charging with a highly efficient average current mode control loop. this chip combines charge state logic with average cur- rent pwm control circuitry. charge state logic commands current or voltage control depending on the charge state. the chip includes undervoltage lockout circuitry to insure sufficient supply voltage is present before output switching starts. additional circuit blocks include a differential current sense amplifier, a 1.5% voltage reference, a C3.9mv/c thermistor linearization circuit, voltage and current error amplifiers, a pwm oscillator, a pwm com- parator, a pwm latch, charge state decode bits, and a 100ma open collec- tor output driver. switchmode lead-acid battery charger features accurate and efficient control of battery charging average current mode control from trickle to overcharge resistor programmable charge currents thermistor interface tracks battery requirements over temperature output status bits report on four internal charge states undervoltage lockout monitors vcc and vref 1/99 block diagram udg-95007-1 pin numbers refer to j, n, dw packages.
2 uc2909 uc3909 dil-20, (top view) j or n, dw packages absolute maximum ratings supply voltage (vcc), out, stat0, stat1 . . . . . . . . . . . 40v output current sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1a cs+, cs- . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 to vcc (note 1) remaining pin voltages. . . . . . . . . . . . . . . . . . . . . . -0.3v to 9v storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . -55c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c all currents are positive into, negative out of the specified ter- minal. consult packaging section of databook for thermal limi- tations and considerations of packages. note 1: voltages more negative than -0.4v can be tolerated if current is limited to 50ma. connection diagrams electrical characteristics: unless otherwise stated these specifications apply for t a = C40c to +85c for uc2909; 0c to +70c for uc3909; c t = 330pf, r set = 11.5k, r10 = 10k, r thm = 10k, v cc = 15v, output no load, r stat0 = r stat1 = 10k, chgenb = ovctap = vlogic, t a = t j . parameter test conditions min typ max units current sense amp (csa) section v id = cs+ C csC dc gain csC = 0, cs+ = -50mv; cs+ = C250mv 4.90 5 5.10 v/v cs+ = 0, csC = 50mv; csC- = 250mv 4.90 5 5.10 v/v v offset (v cso C v cao ) cs+ = csC = 2.3v, cao = caC 15 mv cmrr v cm = C0.25 to vcc C 2, 8.8 < vcc < 14 50 db v cm = C0.25 to vcc, 14 < vcc < 35 50 db v ol v id = C550mv, C0.25v < vcm < vccC2, i o = 500 m a 0.3 0.6 v v oh v id = +700mv, C0.25v < vcm < vccC2, i o = C250 m a 5.2 5.7 6.2 v output source current v id = +700mv, cso = 4v C1 C0.5 ma output sink current v id = C550mv, cso = 1v 3 4.5 ma 3db bandwidth v id = 90mv, v cm = 0v 200 khz lcc-28, plcc-28 (top view) l, q packages
3 uc2909 uc3909 electrical characteristics: unless otherwise stated these specifications apply for t a = C40c to +85c for uc2909; 0c to +70c for uc3909; c t = 330pf, r set = 11.5k, r10 = 10k, r thm = 10k, v cc = 15v, output no load, r stat0 = r stat1 = 10k, chgenb = ovctap = vlogic, t a = t j . parameter test conditions min typ max units current error amplifier (cea) section i b 8.8v < vcc < 35v, v chgenb = v logic 0.1 0.8 m a v io (note 2) 8.8v < vcc < 35v, cao = caC 10 mv a vo 1v < vao < 4v 60 90 db gbw t j = 25c, f = 100khz 1 1.5 mhz v ol i o = 250 m a 0.4 0.6 v v oh i o = C5ma 4.5 5 v output source current cao = 4v C25 C12 ma output sink current cao = 1v 2 3 ma i ca C, i trck_control v chgenb = gnd 8.5 10 11.5 m a voltage amplifier (cea) section i b total bias current; regulating level 0.1 1 m a v io (note 2) 8.8v < vcc < 35v, vcm = 2.3v, vao = vaC 1.2 mv a vo 1v < cao < 4v 60 90 db gbw t j = 25c, f = 100khz 0.25 0.5 mhz v ol i o = 500 m a 0.4 0.6 v v oh i o = C500 m a 4.75 5 5.25 v output source current cao = 4v C2 C1 ma output sink current cao = 1v 2 2.5 ma vao leakage: high impedance state v chgenb = gnd, stat0 = 0 & stat1 = 0, vao = 2.3v C1 1 m a pulse width modulator section maximum duty cycle cao = 0.6v 90 95 100 % modulator gain cao = 2.5v, 3.2v 63 71 80 %/v osc peak 3v osc valley 1v oscillator section frequency 8.8v < vcc < 35v 198 220 242 khz thermistor derived reference section v id = v rthm C v r10 initial accuracy, vao (rthm = 10k) v id = 0, r10 = rthm =10k (note 3) 2.2655 2.3 2.3345 v v id = 0, r10 = rthm =10k, C40c t a < 0c (note 3) 2.254 2.3 2.346 v line regulation v cc = 8.8v to 35v 3 10 mv vao rthm = 138k, r10 = 10k 2.458 2.495 2.532 v rthm = 138k, r10 = 10k, -40c t a < 0c 2.445 2.495 2.545 v rthm = 33.63k, r10 = 10k 2.362 2.398 2.434 v rthm = 33.63k, r10 = 10k, -40c t a < 0c 2.350 2.398 2.446 v rthm = 1.014k, r10 = 10k 2.035 2.066 2.097 v rthm = 1.014k, r10 = 10k, -40c t a < 0c 2.025 2.066 2.107 v charge enable comparator section (cec) threshold voltage as a function of vaC 0.99 1 1.01 v/v input bias current chgenb = 2.3v C0.5 C0.1 m a
4 uc2909 uc3909 electrical characteristics: unless otherwise stated these specifications apply for t a = C40c to +85c for uc2909; 0c to +70c for uc3909; c t = 330pf, r set = 11.5k, r10 = 10k, r thm = 10k, v cc = 15v, output no load, r stat0 = r stat1 = 10k, chgenb = ovctap = vlogic, t a = t j . parameter test conditions min typ max units voltage sense comparator section (vsc) threshold voltage stat0 = 0, stat1 = 0, function of v ref 0.945 0.95 0.955 v/v stat0 = 1, stat1 = 0, function of v ref 0.895 0.9 0.905 v/v over charge taper current comparator section (octic) threshold voltage function of 2.3v ref, ca- = cao 0.99 1 1.01 v/v input bias current ovctap = 2.3v C0.5 C0.1 m a logic 5v reference section (vlogic) vlogic vcc = 15v 4.875 5.0 5.125 v line regulation 8.8v < v cc < 35v 3 15 mv load regulation 0 < i o < 10ma 3 15 mv reference comparator turn-on threshold 4.3 4.8 v short circuit current v ref = 0v 30 50 80 ma output stage section i sink continuous 50 ma i peak 100 ma v ol i o =50ma 1 1.3 v leakage current v out =35v 25 m a stat0 & stat1 open collector outputs section maximum sink current v out = 8.8v 6 10 ma saturation voltage i out = 5ma 0.1 0.45 v leakage current v out = 35v 25 m a statlv open collector outputs section maximum sink current v out = 5v 2.5 5 ma saturation voltage i out = 2ma 0.1 0.45 v leakage current v out = 5v 3 m a uvlo section turn-on threshold 6.8 7.8 8.8 v hysteresis 100 300 500 mv i cc section i cc (run) (see fig. 1) 13 19 ma i cc (off) vcc = 6.5v 2 ma note 2 : vio is measured prior to packaging with internal probe pad. note 3 : thermistor initial accuracy is measured and trimmed with respect to vao; vao = vaC. caC : the inverting input to the current error amplifier. cao : the output of the current error amplifier which is internally clamped to approximately 4v. it is internally connected to the inverting input of the pwm comparator. csC, cs+ : the inverting and non-inverting inputs to the current sense amplifier. this amplifier has a fixed gain of five and a common-mode voltage range of from C250mv to +vcc. cso : the output of the current sense amplifier which is internally clamped to approximately 5.7v. chgenb : the input to a comparator that detects when battery voltage is low and places the charger in a trickle charge state. the charge enable comparator makes the output of the voltage error amplifier a high impedance while forcing a fixed 10 m a into caC to set the trickle charge current. pin descriptions
5 uc2909 uc3909 gnd : the reference point for the internal reference, all thresholds, and the return for the remainder of the de- vice. the output sink transistor is wired directly to this pin. ovctap : the overcharge current taper pin detects when the output current has tapered to the float thresh- old in the overcharge state. osc : the oscillator ramp pin which has a capacitor (c t ) to ground. the ramp oscillates between approximately 1.0v to 3.0v and the frequency is approximated by: frequency cr tset = 1 12 . out : the output of the pwm driver which consists of an open collector output transistor with 100ma sink capabil- ity. r10 : input used to establish a differential voltage corre- sponding to the temperature of the thermistor. connect a 10k resistor to ground from this point. rset : a resistor to ground programs the oscillator charge current and the trickle control current for the oscil- lator ramp. the oscillator charge current is approximately 175 . r set . the trickle control current (i trck_control ) is approxi- mately 0115 . r set . rthm : a 10k thermistor is connected to ground and is thermally connected to the battery. the resistance will vary exponentially over temperature and its change is used to vary the internal 2.3v reference by C3.9mv/c. the recommended thermistor for this function is part number l1005-5744-103-d1, keystone carbon com- pany, st. marys, pa. stat0 : this open collector pin is the first decode bit used to decode the charge states. stat1 : this open collector pin is the second decode bit used to decode the charge states. statlv : this bit is high when the charger is in the float state. vaC : the inverting input to the voltage error amplifier. vao : the output of the voltage error amplifier. the up- per output clamp voltage of this amplifier is 5v. vcc : the input voltage to the chip. the chip is opera- tional between 7.5v and 40v and should be bypassed with a 1 m f capacitor. a typical i cc vs. temperature is shown in figure 1. vlogic : the precision reference voltage. it should be bypassed with a 0.1 m f capacitor. charge state decode chart stat0 and stat1 are open collector outputs. the out- put is approximately 0.2v for a logic 0. stat1 stat0 trickle charge 0 0 bulk charge 0 1 over charge 1 0 float charge 1 1 pin descriptions (cont.) figure 1. i cc vs. temperature.
6 uc2909 uc3909 application information a block diagram of the uc3909 is shown on the first page, while a typical application circuit is shown in fig- ure 2. the circuit in figure 2 requires a dc input voltage between 12v and 40v. the uc3909 uses a voltage control loop with average current limiting to precisely control the charge rate of a lead-acid battery. the small increase in complexity of average current limiting is offset by the relative simplicity of the control loop design. control loop current sense amplifier this amplifier measures the voltage across the sense re- sistor rs with a fixed gain of five and an offset voltage of 2.3v. this voltage is proportional to the battery current. the most positive voltage end of rs is connected to cs- ensuring the correct polarity going into the pwm com- parator. cso = 2.3v when there is zero battery current. rs is chosen by dividing 350mv by the maximum allow- able load current. a smaller value for rs can be chosen to reduce power dissipation. maximum charge current, ibulk, is set by knowing the maximum voltage error amplifier output, v oh = 5v, the maximum allowable drop across rs, and setting the re- sistors rg1 and rg2 such that; (1) rg rg v vlogic ca v vv v v rs rs rs 1 2 55 523 5 27 185 = = = = CC C. . .2 irs bulk the maximum allowable drop across rs is specified to limit the maximum swing at cso to approximately 2.0v to keep the cso amplifier output from saturating. no charge/load current: v cso = 2.3v, max charge/load current: v max(cso) = 2.3vC2.0v = 0.3v voltage error amplifier: the voltage error amplifier (vea) senses the battery voltage and compares it to the 2.3v C 3.9mv/c thermis- tor generated reference. its output becomes the current command signal and is summed with the current sense amplifier output. a 5.0v voltage error amplifier upper clamp limits maximum load current. during the trickle charge state, the voltage amplifier output is opened (high impedance output) by the charge enable comparator. a trickle bias current is summed into the caC input which sets the maximum trickle charge current. the vea, v oh = 5v clamp saturates the voltage loop and consequently limits the charge current as stated in equation 1. during the trickle bias state the maximum allowable charge current (itc) is similarly determined: (2) itc irg rs trick control = _ 1 5 i trck_control is the fixed control current into caC. i trck_control is 10 m a when r set = 11.5k. see rset pin description for equation. current error amplifier the current error amplifier (ca) compares the output of the current sense amplifier to the output of the voltage error amplifier. the output of the ca forces a pwm duty cycle which results in the correct average battery current. with integral compensation, the ca will have a very high dc current gain, resulting in effectively no average dc current error. for stability purposes, the high frequency gain of the ca must be designed such that the magni- tude of the down slope of the ca output signal is less than or equal to the magnitude of the up slope of the pwm ramp. charge algorithm refer to figure 3 in uc3906 data sheet in the data book. a) trickle charge state stat0 = stat1 = statlv = logic 0 when chgnb is less than vref (2.3v C 3.9mv/c), statlv is forced low. this decreases the sense voltage divider ratio, forcing the battery to overcharge (voc). (3) () voc vref rs rs rs rs rs rs = ++ () () || 123 4 34 || during the trickle charge state, the output of the voltage error amplifier is high impedance. the trickle control cur- rent is directed into the caC pin setting the maximum trickle charge current. the trickle charge current is de- fined in equation 2. b) bulk charge state stat1 = statlv = logic 0, stat0 = logic 1 as the battery charges, the uc3909 will transition from trickle to bulk charge when chgenb becomes greater than 2.3v. the transition equation is (4) vt vref rs rs rs rs rs rs rs = ++ + (||) (||) 1234 234 statlv is still driven low.
7 uc2909 uc3909 udg-95008-1 application information (cont.) figure 2. typical application circuit pin numbers refer to j, n, dw packages.
8 uc2909 uc3909 during the bulk charge state, the voltage error amplifier is now operational and is commanding maximum charge current (i bulk ) set by equation 1. the voltage loop at- tempts to force the battery to voc. c) overcharge state stat0 = statlv = logic 0, stat1 = logic 1 the battery voltage surpasses 95% of voc indicating the uc3909 is in its overcharge state. during the overcharge charge state, the voltage loop be- comes stable and the charge current begins to taper off. as the charge current tapers off, the voltage at cso in- creases toward its null point of 2.3v. the center connec- tion of the two resistors between cso and vlogic sets the overcurrent taper threshold (ovctap). knowing the desired overcharge terminate current (i oct ), the resistors r ovc1 and r ovc2 can be calculated by choosing a value of r ovc2 and using the following equation: (5) () rirsr ovc oct ovc 12 18518 = . d) float state stat0 = stat1 = statlv = logic 1 the battery charge current tapers below its ovctap threshold, and forces statlv high increasing the volt- age sense divider ratio. the voltage loop now forces the battery charger to regulate at its float state voltage (v f ). (6) () () vv rs rs rs rs fref = ++ 123 3 if the load drains the battery to less than 90% of v f , the charger goes back to the bulk charge state, state 1. off line applications for off line charge applications, either figure 3 or figure 4 can be used as a baseline. figure 3 has the advan- tage of high frequency operation resulting in a small iso- lation transformer. figure 4 is a simpler design, but at the expense of larger magnetics. application information (cont.) figure 3. off line charger with primary side pwm udg-95009
9 uc2909 uc3909 figure 4. isolated off line charger application information (cont.) unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 ? fax (603) 424-3460 udg-95010
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