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asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 1 - general description the AK5356 is a low voltage 20bit a/d converter for digital audio system. the AK5356 also includes microphone amplifier and analog input pga, making it suitable for microphone applications or low - input signal levels. as digital power supply of the AK5356 corresponds to 1.8v, the interface with microprocessor can operate at low voltage. the AK5356 is housed in a space - saving 28 - pin qfn package. features 1. mic block mic power pre - amplifier (+13db / +18db / +28db / +33db) 2. 20bit 2ch adc 2 - input stereo selector analog input pga: +28db ~ - 52db, mute s/(n+d): 84db dr, s/n: 89db monaural mixing digital hpf for dc - offset cancellation (fc=3.4hz@fs=44.1khz) 3. 3 - wire serial control i/f 4. master cloc k: 256fs/384fs 5. audio data format: msb first, 2 ? s compliment 16/20bit msb justified or 16/20bit i 2 s compatible 6. power supply voltage avdd: 2.0 ~ 3.3v mvdd: 2.4 ~ 3.3v dvdd: 1.8 ~ 3.3v 7. power supply current mic block: 3.4ma ipga+adc: 6ma 8 . ta = - 4 0 ~ 85 c 9. package: 28pin qfn low power 20 - bit adc with mic - amp & pga AK5356
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 2 - sdto mclk lrck bclk prer dvss dvdd pdn csn cclk cdti audio i/f controller control register i/f prel mic power supply power management adc mvdd rin pmadc pre - amp lin pmmic mvs s mrf avss avdd vcom mvcm micl mpwr micr figure 1 . AK5356 block diagram
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 3 - n ordering guide AK5356vn - 40 ~ +85 c 28pin qfn (0.5mm pitch) akd5356 evaluation board for AK5356 n pin layout top view 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 9 10 11 12 13 14 16 17 18 19 20 21 avdd avss sdto mrf lin mpwr mvss mvdd micr preor micl preol prenl prel prer prenr lrck cdti cclk csn pdn rin vcom dvss dvdd bclk mclk 15 mvcm
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 4 - pin/function no. pin name i/o function 1 rin i rch line input pin 2 vcom o adc common voltage output pin 3 avdd - analog power supply pin, +2.5v 4 avss - analog ground pin 5 dvss - digital ground pin 6 dvdd - digital power supply pin, +2.5v 7 sdto o audio serial data output pin 8 bclk i audio serial data clock pin 9 mclk i master clock input pin 10 lrck i input/output channel clock pin 11 cdti i control data input pin 12 cclk i control clock input pin 13 csn i chip select pin 14 pdn i reset & power down pin ? l ? : reset & power down, ? h ? : normal operation 15 micl i lch mic input pin 16 preol o lch pre - amp output pin 17 prenl i lch pre - amp negative input pin 18 prel i lch pre - amp positive input pi n 19 prer i rch pre - amp positive input pin 20 prenr i rch pre - amp negative input pin 21 preor o rch pre - amp output pin 22 micr i rch mic input pin 23 mvdd - mic block power supply pin, +2.7v 24 mvss - mic block ground pin 25 mvcm o mic block common voltage output pin 26 mrf o mic power supply ripple filter pin 27 mpwr o mic power supply pin 28 lin i lch line input pin note: all digital input pins should not be left floating.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 5 - a bsolute maximum ratings (avss, dvss, mvss= 0v ; note 1 ) parameter symbol min max units power supply analog mic digital | dvss ? avss | ( note 2 ) | mvss ? avss | ( note 2 ) avdd mvdd dvdd d gnd1 d gnd2 - 0.3 - 0.3 - 0.3 - - 4.6 4.6 4.6 0.3 0.3 v v v v v input current (any pin except supplies) iin - 10 ma analog input voltage ( note 3 ) ( note 4 ) vina1 vina2 - 0.3 - 0.3 avdd+0.3 mvdd+0.3 v v digital input voltage ( note 5 ) vind - 0.3 dvdd+0.3 v ambient temperature (power applied) ta - 40 85 c storage temperature tstg - 65 150 c note 1 . all voltages with respect to ground. note 2 . avss, dvss and mv ss must be connected to the same analog ground plane. note 3 . micl, micr, lin and rin pins note 4 . prel, prer, prenl and prenr pins note 5 . mclk, bclk, lrck, csn, cclk, cdti and pdn pins warning : operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss, mvss =0v ; note 1 ) parameter sym bol min typ max units power supply analog mic digital avdd mvdd dvdd 2.0 2.4 1.8 2.5 2.7 2.5 3.3 3.3 avdd v v v note 1 . all voltages with respect to ground warning: akm assumes no responsibility for the usage beyond the condi tions in this data sheet.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 6 - analog characteristics ( ta=25 c ; avdd, dvdd = 2.5 v , mvdd=2.7v; avss, dvss, mvss=0v; fs=4 4.1k hz ; signal frequency =1khz ; measurement frequency=10hz ~ 20khz; unless otherwise specified) parameter min typ max units pre - amp char acteristics: positive input pin ( note 6 ) 50 100 200 k w input resistance negative input pin ( note 7 ) 100 190 400 w gain error (+13db, +18db, +28db, +33db) - 1.5 0 +1.5 db maximum output voltage(gain=+13 db,+18db,+28db,+33db) (thd+n 0.1%) ( note 8 ) - 3 - 1.5 dbv gain = +33db 54 60 db gain = +28db - 65 - db gain = +18db - 74 - db s/(n+d) (vout = - 29.2dbv) gain = +13db - 78 - db gain = +33db - 91 - 86 dbv gain = +28db - - 96 - dbv gain = +18db - - 105 - dbv output noise voltage (no input, rg = 600 w , a - weighted) gain = +13db - - 109 - dbv interchannel gain mismatch (gain = +13db, +18db, +28db, +33db) 0.5 db gain = +33db 75 90 db interchannel isolation gain = +2 8db, +18db, +13db - 100 - db load resistance 5 k w load capacitance 10 pf gain = +33db - 46 - db gain = +28db - 52 - db gain = +18db - 64 - db power supply rejection ( note 9 ) gain = +13db - 73 - db mic power charac teristics: output voltage (no load) ( note 10 ) 2.05 2.16 2.27 v output power supply current 1 ma ipga characteristics: input resistance (lin, rin, micl, micr pins) 6.3 9 15 k w step size +28db ~ - 8db - 8db ~ - 16db - 16db ~ - 32db - 32db ~ - 40db - 40db ~ - 52db 0.1 0.1 0.1 - - 0.5 1 2 2 4 1 2 4 - - db db db db db adc characteristics: ( note 11 ) resolution 20 bits input voltage ( note 12 ) 1.35 1.5 1.65 vpp ipga = 0db 74 84 db s/(n+d) ( - 0.5dbfs i nput) ipga= +28db - 70 - db ipga = 0db 82 89 db d - range ( - 60dbfs input, a - weighted) ipga= +28db - 79 - db ipga = 0db 82 89 db s/n (a - weighted) ipga= +28db - 79 - db ipga = 0db 90 100 db interchannel isolation ( note 13 ) ipga= +28db - 75 - db ipga = 0db 0.5 db interchannel gain mismatch ipga= +28db - 0.5 - db
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 7 - parameter min typ max units power supplies power supply voltage: normal operation (pdn = ? h ? ) ( note 14 ) mvdd ( note 15 ) avdd+dvdd power - down mode ( pdn= ? l ? ) ( note 16 ) mvdd + avdd + dvdd 3.4 6 10 5 9 100 ma ma m a note 6 . prel and prer pins note 7 . prenl and prenr pin s . gain of pre - amp is +33db. input resistance of pre - amp is changed by gain. gain = +13db: 1.9k w (typ), gain = +18db: 1.1k w (typ), gain = +28db: 340 w (typ) note 8 . a maximum output voltage is the value whi ch fills ? thd+n 0.1% ? . it is almost in proportion to mvdd voltage. - 1.5dbv = 2.38vpp = (mvdd x 0.88)vpp (typ) note 9 . psr is applied to mvdd with 1khz, 50mvpp. note 10 . output voltage is proportional to mvdd voltage and it is typically (mvdd x 0.8) v. note 11 . adc is input from micl/micr or lin/rin and it measures included in ipga. internal hpf cancels the offset of ipga and adc. note 12 . analog input voltage (full - scale voltage: ipga = 0db) is proportional to avdd voltage. ipga = adc = (0.6 x avdd) vpp (typ) note 13 . this value is interchannel isolation between lin and rin or between micl and micr. note 14 . all blocks in the AK5356 are powered - up. (pmmic=pmadc= ? 1 ? ) note 15 . mpwr pin supplies 0ma. note 16 . in case of power - down mode, all digital input pins including clocks pins (mclk, bclk and lrck) are held at dvdd or dvss . pdn pin is held at dvss.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 8 - filter characteristics ( ta= 25 c ; avdd =2.0 ~ 3.3v , dvdd= 1.8 ~ 3.3 v , mvdd=2.4 ~ 3.3 v , fs=4 4.1k hz ) parameter symbol min typ max units adc digital filter (lpf): passband ( note 17 ) 0.1db - 1.0db - 3.0db pb 0 20.0 21.1 17.4 khz khz khz stopband ( note 17 ) sb 27.0 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay ( note 18 ) gd 17.0 1/fs group delay distortion d gd 0 m s adc digital filter (hpf): frequency response ( note 17 ) - 3db - 0.5db - 0.1db fr 3.4 10 22 hz hz hz note 17 . the passband and stopband freq uencies scale with fs (sampling frequency). for example , pb=0.454 x fs (@ - 1.0db). note 18 . the calculated delay time caused by digital filtering. this time from the input of an analog signal to setting the 20bit data of both channe ls to the output register of the adc and includes the group delay of the hpf. dc characteristics ( ta= 25 c ; avdd=2.0 ~ 3.3 v , dvdd=1.8 ~ 3.3v, mvdd=2.4 ~ 3.3 v ) parameter symbol min typ max units high - level input voltage low - level input voltage vih vil 75 % dvdd - - - - 25 % dvdd v v high - level output voltage iout = - 80 m a low - level output voltage iout = 80 m a voh vol dvdd - 0.4 - - - - 0.4 v v input leakage current iin - - 10 m a
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 9 - switching characteristics ( ta= 25 c ; avdd = 2.0 ~ 3.3 v , dvdd=1.8 ~ 3.3 v ; c l =2 0pf ) parameter symbol min t yp max units master clock timing (mclk) 256fs: frequency pulse width low pulse width high 384fs: frequency p ulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 2.048 28 28 3.072 23 23 11.2896 16.9344 12.8 19.2 mhz ns ns mhz ns ns lrck timing frequency duty cycle fs duty 8 45 44.1 50 55 khz % serial interface timing bclk period bclk pulse width low pulse width high bclk ? ? to lrck edge lrck to sdto (msb) ( note 19 ) bclk ? ? to sdto tblk tblkl tblkh tblr tdlr tdss 312.5 130 130 - tblkh+50 tblkl - 50 80 80 ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ? h ? time csn ? ? to cclk ? - ? cclk ? - ? to csn ? - ? tcck tcckl tcckh tcds tcdh tcsw tcss t csh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns power - down & reset timing pdn pulse width pdn ? - ? to sdto delay ( note 20 ) tpw tpwv 150 4128 n s 1/fs note 19 . except f or i 2 s mode. note 20 . this is the number of lrck rising after pdn pin is pulled high.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 10 - n timing diagram mclk 1/fclk tclkh tclkl vih vil lrck 1/fs vih vil bclk tblk vih vil tblkh tblkl figure 2 . clock timing vih lrck vil vih bclk tblr vil tdlr tdss sdto 50%dvdd d19 (msb) figure 3 . audio data output timing (audio i/f = no.0) csn tcss tcckl vih vil cclk vih vil cdti tcds vih vil op2 op1 tcckh tcdh op0 a4 figure 4 . write command input timing
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 11 - csn vih vil cclk vih vil cdti vih vil d2 d1 tcsh d0 tcsw d3 figure 5 . write data input timing pdn sdto vil tpwv tpw 50%dvdd figure 6 . power down & reset timing
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 12 - operation overview n system clock the clocks required to operate are mclk ( 256fs/384fs), lrck ( fs) and bclk ( 32fs, 40fs ~ ). the master clock (mclk) should be s ynchronized with lrck. the phase between these clocks does not matter. the frequency of mclk can be input at 256fs or 384fs. when the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling frequency. all external cloc ks (mclk, bclk and lrck) should always be present whenever the adc is in operation. if these clocks are not provided, the AK5356 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of register s. if the external clocks are not present, the AK5356 should be placed in power - down mode. n audio data i/f format the sdto, bclk and lrck pins are connected to an external controller. the audio data format has two modes, msb - first and 2 ? s compliment. t he data format is set using the dif bit. sdto is latched by a falling edge of bclk. no. dif bit sdto (adc) lrck bclk 16bit msb justified lch: ? h ? , rch: ? l ? = 32fs 0 0 20bit msb justified lch: ? h ? , rch: ? l ? 3 40fs default 16bit i 2 s compatible lc h: ? l ? , rch: ? h ? = 32fs 1 1 20bit i 2 s compatible lch: ? l ? , rch: ? h ? 3 40fs table 1 . audio data format lrck bclk( i :64fs) sdto(o) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 19 1 18 0 19 18 8 7 6 0 19 19:msb, 0:lsb lch data rch data 8 7 6 bclk( i :32fs) sdto (o) 0 1 2 12 10 11 13 3 0 1 2 18 8 18 11 10 17 9 14 17 3 3 7 5 6 4 19 19 15 8 10 9 7 5 6 4 19 11 9 11 9 10 12 15 0 13 14 1 19 19 figure 7 . audio data timing (no.0)
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 13 - lrck(i) bclk( i :64fs) sdto(o) 0 1 2 19 17 18 20 31 0 1 2 19 17 18 20 31 0 1 19 1 19 4 3 1 lch data rch data 4 3 18 2 21 18 3 3 2 0 0 21 bclk( i :32fs) sdto (o) 0 1 2 11 9 10 12 15 0 1 2 19 9 19 19:msb, 0:lsb 12 11 18 10 13 18 3 3 8 6 7 5 4 4 14 9 11 10 8 6 7 5 4 12 8 11 9 10 12 15 0 13 14 8 1 figure 8 . audio data timing (no.1) n digital high pass filter the AK5356 has a digital high pass filter (hpf) to cancel dc - offset in both the ipga and adc. the cut - off frequency of the hpf is 3.4hz at fs=44.1khz. this cut - off frequency s cales with the sampling frequency (fs). and the hpf can select on/off by hpf bit.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 14 - n mic block 1. pre-amp the pre - amp is non - inverting amplifier and internally biased to mvcm voltage with 100k w (typ.). gain of the pre - amp can select +13db, +18db, +28 db or +33db by preg1 - 0 bits. pre - amp gain value of l/r channels change by zero crossing detection or timeout independently. timeout cycle is fixed to 2048/fs (=46.8ms @ fs = 44.1khz). zero crossing detection is done by ipga block. when pmadc bit is ? 0 ? , g ain of pre - amp changes immediately. an external capacitor is needed to cancel dc gain. the cut - off frequency is determined by an internal resistor (ri) and an external capacitor (c1). pre - amp prel pin prer pin - + rf ri + c1 to micl/micr pins figure 9 . pre-am p 2. power supply for mic the power supply for microphone device is supplied from mpwr pin. the output voltage is typically 2.16v(= 0.8 x mvdd at mvdd=2.7v). mpwr pin can supply the current up to 1ma. when pmmic bit is ? 0 ? , the output current is not supp lied.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 15 - n system reset the AK5356 is placed in the power - down mode by bringing pdn pin ? l ? . the control registers are also reset at the same time. this reset should always be done after power - up. an analog initialization cycle starts after exiting the p ower - down mode. the output data sdto becomes available after 4128 cycles of lrck clocks. during initialization, the adc digital data outputs of both channels are forced to a 2 ? s complement ? 0 ? . the adc outputs settle to the data corresponding to the input signal at the end of initialization (settling time equals the group delay time approximately.). as a normal initialization cycle may not be executed, nothing writes at address 01h during initialization cycle after exiting power - down by pdn pin. the clocks may be stopped. 4128/fs pdn pin power supply adc internal state control register external clocks ain sdto pd pdn pin may be ? l ? at power - up. init - 1 normal gd gd gd (1) ? 0 ? data (3) ? 0 ? data (2) pm (1) idle noise normal init - 2 normal inhibit normal (4) 4128/fs init - 1 write to register (5) figure 10 . power - up / power - down timing example pd: power - down state. adc is output ? 0 ? . pm: power - down state by power management bit. adc is output ? 0 ? . init - 1: initialization cycle of adc in it - 2: initializing all control registers. inhibit: inhibits writing to all control registers. note: see ? register definitions ? about the condition of each register. (1). digital output corresponding to the analog input is delayed by the group delay amount (gd). output signal gradually comes to settle to input signal during a group delay. (2). if the analog signal does not be input, digital outputs have the offset to op - amp of input and some offset error of a internal. (3). adc output data is ? 0 ? at p ower - down. (4). when the external clocks (mclk, bclk and lrck) are stopped, the AK5356 should be placed in the power - down state. (5). when external clocks are not supplied, inhibits writing to all control registes.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 16 - n timing of control register the int ernal registers are written by the 3 - wire m p interface pins: csn, cclk, cdti. these data are included by chip address (2bit, the AK5356 is fixed to ? 10 ? .), read/write (1bit), address (msb - first, 5bit) and control data (msb - first, 8bit). a side of transmitt ed data is output to each bit by ? ? of cclk, a side of receiving data is input by ? - ? of cclk. writing of data becomes effective by ? - ? of csn. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ? l ? . cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1 - c0: chip address (fixed to ? 10 ? ) r/w: read/write (fixed to ? 1 ? ; write only ) a4 - a0: register address d7 - d0: control data figure 11 . control data timing
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 17 - n register map addr register name d7 d6 d5 d4 d 3 d2 d1 d0 00h input select 0 preg1 preg0 hpf rin micr lin micl 01h power management control 0 0 0 0 0 0 pmadc pmmic 02h mode control mono1 mono0 ztm1 ztm0 0 0 dif 0 03h ipga control zeip ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 all registers are re set at pdn = ? l ? , then inhibits writing to all registers. for address from 04h to 1fh, data must not be written. unused bits must contain a ? 0 ? value. n register definition input select addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h input select 0 pr eg1 preg0 hpf rin micr lin micl default 0 1 0 0 0 1 0 1 preg1 - 0: select gain of pre - amp 00: +13db 01: +18db 10: +28db (default) 11: +33db pre - amp gain value of l/r channels change by zero crossing detection or timeout independently. timeout cycle is f ixed to 2048/fs (=46.8ms @ fs = 44.1khz). zero crossing detection is done by ipga block. when pmadc bit is ? 0 ? , gain of pre - amp changes immediately. hpf: select on/off of the digital hpf (0: on, 1: off) r in: select on/off of rch line input (0: o ff, 1: on) micr: select on/off of rch mic input (0: off, 1: on) lin: select on/off of lch line input (0: off, 1: on) micl: select on/off of lch mic input (0: off, 1: on) power management control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management control 0 0 0 0 0 0 pmadc pmmic default 0 0 0 0 0 0 1 1 pmadc: power management of ipga and adc 0: power off 1: power on (default) pmmic: power management of mic block (pre - amp, mic power and mvcm) 0: power off 1: power on (defaul t) when pdn pin goes ? l ? , all circuit in the AK5356 can be powered - down in no relation to pmadc and pmmic bits. when pmadc and pmmic bits go ? 0 ? , all circuit in the AK5356 can be also powered - down. however, the contents of control registers are held. exc ept the case of pmadc=pmmic= ? 0 ? or pdn pin = ? l ? , mclk, bclk and lrck should not be stopped.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 18 - mode control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h mode control mono1 mono0 ztm1 ztm0 0 0 dif 0 default 0 0 1 1 0 0 0 0 mono1 - 0: monaural mixing 00 : stereo (default) 01: (l+r)/2 10: ll 11: rr adc hpf lch rch adc hpf + x 0.5 lch rch selector selector sw1 sw2 figure 12 . monaural mixing block mode sw1 sw2 mono1 mono0 stereo recording lch rch 0 0 monaural recording stereo input (l+r)/2 (l+r)/2 0 1 monaural reco rding lch input lch lch 1 0 monaural recording rch input rch rch 1 1 table 2 . monaural mode setting ztm1 - 0: setting of zero crossing timeout for ipga 00: 256/fs 01: 512/fs 10: 1024/fs 11: 2048/fs (default) dif: select digital in terface format no. dif bit sdto (adc) lrck bclk 16bit msb justified lch: ? h ? , rch: ? l ? = 32fs 0 0 20bit msb justified lch: ? h ? , rch: ? l ? 3 40fs default 16bit i 2 s compatible lch: ? l ? , rch: ? h ? = 32fs 1 1 20bit i 2 s compatible lch: ? l ? , rch: ? h ? 3 40fs table 3 . audio data format
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 19 - input analog pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input analog pga control zeip ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 default 0 28h zeip: select ipga zero cros sing operation 0: disable (default) 1: enable writing to ipga value at zeip = ? 1 ? , ipga value of l/r channels changes by zero crossing detection or timeout independently. in the timeout cycle, it is possible to set in ztm1 - 0 bit. when ztm1 - 0 is ? 11 ? , timeo ut cycle is 2048/fs = 46.4ms (@fs=44.khz). when zeip is ? 0 ? , ipga changes immediately . ipga 6 - 0: input analog pga, 97 levels; 00h=mute on/off of zero crossing detection can be controlled by zeip bit. data gain(db) step level 60h +28.0 5fh +27.5 5eh +27.0 28h +0.0 27h - 0.5 19h - 7.5 18h - 8.0 0.5db 73 17h - 9.0 16h - 10.0 11h - 15.0 10h - 16.0 1db 8 0fh - 18.0 0eh - 20.0 05h - 38.0 04h - 40.0 2db 12 03h - 44.0 02h - 48.0 01h - 52.0 4db 3 00h mute 1 table 4 . input gain setting [ writing to ipga register at zeip = ? 1 ? continuously ] when writing control register continuously, the change of ipga should be written after zero crossing timeout. if ipga is changed by writing to control register before zero crossing detection, ipga value of l/r channels may not give a difference level.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 20 - system design figure 13 shows the system connection diagram. an evaluation board [AK5356] is available wh ich demonstrates the application circuit, optimum layout, power supply arrangement and measurement results. 21 20 19 18 17 16 15 lin 28 27 26 25 24 23 22 rin 1 2 3 4 5 6 7 vcom avss dvss dvdd sdto mpwr mrf mvdd micr bclk 8 9 10 11 12 13 14 cdti mclk lrck cclk pdn preol micl top view csn mvcm mvss avdd prenl prel prer prenr preor micro controller audio controller 2.2 c1 + 2.0 ~ 3.3v analog power supply 1.8 ~ 3.3v digital power supply + c2 c1 c2 c1 + 1 + 4.7 c1 47 + c1 c2 + 6.8k 6.8k + 47 4.7 + c2 + 47 mic device 0.33 0.33 2.4 ~ 3.3v analog power supply c1: 0.1 m c2: 10 m figure 13 . system connection diagram example note: electrolytic capacitor value of vcom dep ends on low frequency noise of supply voltage.
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 21 - package 28pin qfn (unit: mm) 0.25 0.10 5.0 0.10 5.2 0.20 5.0 0.10 0.2 + 0.10 - 0.20 5.2 0.20 0.50 0.22 0.05 28 22 1 8 21 0.05 m 21 15 14 8 7 1 22 45 45 0.21 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 0.05 7 14 15 4 - c0.6 0.60 0.10 28 note) the part of black at four corners on reverse side must not be soldered and must be open. n package & lead frame material package molding compound: epoxy lead frame material : cu lead frame surface treatment: solder plate (pb free)
asahi kasei [ AK5356] ms0171 - e - 00 2002/08 - 22 - marking 5356 xxxx 1 xxxx : date code identifier (4 digits) i m portant notice these products and their specifications are subject to change without noti ce. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of expo rt pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no res ponsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications i n medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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