1 www.semtech.com high-performance products revision 1/november 14, 2001 an1006 DESIGNING with 10k and 100k ecl / pecl devices DESIGNING with 10k and 100k ecl / pecl devices the basic differences between 10k and 100k de- vices are circuit stability and performance with varia- tion in supply voltage and ambient temperature. 100k ecl parts are both temperature and voltage compensated and 10k ecl parts are only voltage compensated. ecl is used to obtain the required circuit speed and provide the circuit features necessary to optimize high-speed system design. the problem caused by mixing 10k ecl and 100k ecl logics is illustrated in figures 1 & 2. 10k output levels and input threshold vary with tem- perature, whereas 100k output levels and input threshold remain essentially constant over supply voltage and temperature change. this means that the noise margins vary with the temperature, even if the temperatures of the driving and receiving cir- cuits track. perhaps the worse-case is shown in figure 2, which illustrates 100k driving 10k. at t a = 75 c, the high margins are seen to be less than 100 mv. clearly this would not represent accept- able dc margins in any real systems. if the use of 10k ecl in a 100k system is unavoid- able, it is recommended that all interfacing be done differentially. this is illustrated in figure 3, which is applicable in either direction. also if the operating ambient temperature for all the ecl devices is un- der control, this type of connection is allowed. for ecl/pecl output termination techniques refer to application note an1003. 10k/100k ecl/pecl devices high state margins 10k 100k 10k v oh (m in) 100k v il (max) low state margins 10k 100k 100k v ih (min) -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 010 20 30 40 50 60 70 80 input / output levels (v) t a - ambient temperature ( o c) 10k ecl driving 100k ecl figure 1 10k v ol (max) t a - ambient temperature ( o c) figure 2 high state margins 100k 10k 100k v ol (max) low state margins 100k 10k 1 0 k v ih (min) -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 010 20 30 40 50 60 70 80 input / output levels (v) 100k ecl driving 10k ecl 10k v ol (max) 100k v oh (min) figure 3 interfacing 10k and 100k -2v -2v differential line receiver
2 www.semtech.com high-performance products revision 1/november 14, 2001 an1006 logic 1 = v oh min - v ih min = - 980 - (-1130) = 150 mv logic 0 = v il max ? v ol max = - 1480 - (- 1630) = 150 mv nm for 100k at ta = 25c are: logic 1 = v oh min ? v ih min = -1025 - (-1165) = 140 mv logic 0 = v il max - v ol max = -1475 - (-1620) = 145 mv noise margin noise margin is a dc voltage specification that measures the immunity of a circuit to adverse op- erating conditions. this is defined as the differ- ence between the worst-case input logic level (vihmin or vilmax) and the worst-case output logic level (vohmin or volmax). noise margins, nm, for 10k at t a = 25c are: division headquarters 10021 willow creek road san diego, ca 92131 phone: (858) 695-1808 fax: (858) 695-2633 marketing group 1111 comstock street santa clara, ca 95054 phone: (408) 566-8776 fax: (408) 727-8994 semtech corporation high-performance products division contact information
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