1 ? multiplexed data acquisit ion system considerations a practical multip lexer application figure 1 illustrates a practical data acquisition system hookup using an analog multiplexer, a monolithic sample- and-hold and an a/d converter. the ha-242x and ha-53xx sample-and-holds are particularly good choices for this type application because they eliminate the need for a separate high impedance, high slew rate buffer amplifier. their acquisition time is consistent with cmos multiplexer settling times and most available a/d conversion times. errors, after initial adjustment, are consis tent with up to 12 bit absolute accuracy over a wide temperature range. a. accuracy dc error sources include: 1. multiplexer: a. input offset = r source x l s(off) b. output offset = r (on) x [l d(on) + i bias (s/h) ] 2. sample-and-hold a. input offset voltage b. charge injection; sample-to-hold offset c. gain error during ?hold? d. drift during hold 3. a/d converter: a. linearity b. gain drift c. offset drift items 1(a) and (b), and 2(d) be come significant only at very high temperatures. 2(a) and (b) are initially adjusted out with the offset adjustment pot on the s/h. 2(c) is usually adjusted out by a/d gain adjustment, but could also be removed by a voltage divider feedback on the s/ h to give a slightly greater than unity gain during ?sample? . after initial adjustments, typical s/h errors are less than 0.5mv over 0 o c to +75 o c. note that after adjustment, there may be an appreciable offset at the s/h output when switching from sample to hold. this is not a problem, since accuracy is required only during ?hold?, and the system is adjusted for this. the largest system errors are usually 3(b) and (c) due to drifts with temperature and time . if two multiplexer channels can be dedicated for stable (+) and (-) reference voltage inputs, then the data processor can continuously calibrate the system, effectively removing all errors, except 1(a) and 3(a) which are usually negligible. - + hi-506a/508a/1818a offset adj mux address - + a/d converter ha-2420 c h 1000pf parlene ? data out data ready start sample/hold analog in t 3 t 2 t 1 mux address sample/hold control a/d start a/d data ready +15v 100k figure 1. timing diagram application note august 2002 an1033 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 b. timing the timing diagram in figure 1 indicates the necessary system delays for each multiplexer address: t 1 is the combined acquisition time for the multiplexer and s/h. t 2 is the short interval required for the sample-to-hold transient to settle. t 3 is the a/d conversion time. the following table indicates minimum recommended timing for 10 volt input range for acquisition/settling times to 1/2 lsb accuracy: the multiplexer, by itself, requires about 2 s and 9 s settling to 10 bit and 12 bit accuracy, respectively; but fortunately this can be concurrent with s/h acquisition time. this is longer than would be predicted by the r on c d time constant; probably because of internal distributed capacitance, a rather long period is required to traverse the last few millivolts towards the final value. it should be noted that im pedance conditions at the multiplexer inputs can affect the necessary acquisition time. at the instant the multiplexer switches from one channel to a new one, there is appreciable current pulled through the new channel input in order to charge c d from its old level to its new level. this can cause ringing on signal lines, or glitches at signal conditioning amplifie r outputs which require longer periods to settle. it is best for signal conditioning amplifiers to be wideband types, such as the ha -5170, so that their high frequency output impedance is low and recovery from load transients is fast, even though the signal to be measured is very low bandwidth. the t 1 and t 2 times could be eliminated by alternating two s/h circuits, acquiring a new signal on the second while a/d conversion is taking place. the two s/h circuits would have inputs connected together, and outputs alternately connected to the a/d by an analog switch. total time, then, would be t 3 plus the analog switch settling time. if the mux input channels are sequentially switched, each channel will be sampled at a rate of: samples per second, where n is the number of channels. the frequency spectra of the in put signals must then be no higher than . in many systems, however, each channel carries a different maximum frequency of interest, and it may be desirable to depart from simple sequentia l scanning. qu ickly varying signals, for example, could be addressed several times during a scanning period. c. adding channels for more than sixteen channel s, several multiplexers may be tied together at the outputs, and addressed in parallel, but with only one ?enabled? at a time. the mux output offset will be increased, since i d (off or on) is additive. also, output capacitance, c d , is additive, creating increased access times. these errors can be minimized in large systems by having several tiered levels of multiplexing; where the outputs of a number of muxs are individually connected to the inputs of another mux. d. differential multiplexing when low level analog signals must be conducted over a distance, it is generally better, from a noise pickup standpoint, to use a balanced transmission line carrying signals which are differential with respect to ground. a differential multiplexer is used for this purpose, as shown in figure 2. two sample-and-hold circuits plus an op amp form a high impedance differential sample-and-hold with gain. at gains greater than 4, the minimum sampling time (t 1 in previous example) must be increased proportionately to gain to allow for overdamped settling characteristics. when handling low level, or high impedance signals, consideration should be given to adding signal conditioning amplifiers at the signal sources, since this can often produce less troublesome, more ac curate, lower cost systems. minimum recommended timing for 10 volt v in t 1 t 2 10 bit: 6 s1 s 12 bit: 12 s2 s fs 1 nt 1 t 2 t 3 ++ () -------------------------------------------- = fs 2 ------- - figure 2. differential multiplexer - + + - - + + - - + ha-2600 ha-2420 ha-2420 r 3 r 1 r 2 r 1 s/h r 3 r 4 r 4 ( ( ( ( gain = 1+ 2r 1 r 2 r 4 r 3 address hi-507a/509a/1828a control application note 1033
3 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com e. demultiplexing since the switches in a cmos mux conduct equally well in either direction, it is perfectly feasible to use it as a single input-selected multiple output s witch. figure 3 illustrates its use as a demultiplexer, with capacitors to hold the output signal between samples. when the address lines are synchronous with the address of the original multiplexer, the output lines will create the original inputs, except level changes will be in steps. overvoltage protection is not effective with signals injected at the normal mux output, so an external network should be added, if necessary. a more accurate demultiplexer could be constructed using the ha-2420/2425 sample-and -hold for each channel, connecting inputs together and sampling each channel sequentially. - + de-mux?d out address (synch?d with original mux) - + figure 3. demultiplexer multiplexed data in application note 1033
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