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1 ps8951a 03/06/08 description pi6cua878 pll clock driver is developed for registered ddr2 dimm applications with 1.8v operation and differential data input and output levels. the device is a zero delay buffer that distributes a differential clock input pair (clk, clk) to eleven differential pairs of clock outputs which includes feedback clock (y[0:9], y[0:9]; fbout, fbout). the clock outputs are controlled by clk/clk, fbout, fbout, the lvcmos inputs (oe, os) and the analog power input (av dd ). when oe is low, all the outputs except for fbout, fbout, are disabled while the internal pll continues to maintain its locked-in frequency. os is a program pin that must be tied to gnd or v dd. when os is high, oe will function as described above. when os is low, oe has no effect on y7/y7, they are free running. when av dd is grounded, the pll is turned off and bypassed for test purposes. when clk/clk are logic low, the device will enter a low power mode. an input logic detection circuit will detect the logic low level and perform a low power state where all y[0:9], y[0:9]; fbout, fbout, and pll are off. the pi6cua878 is a high performance, low skew, and low jitter pll clock driver, and is also able to track spread spectrum clock- ing (ssc) for reduced emi. features ? pll clock distribution for ddr2 dimm applications. ? distributes one differential clock input pair to eleven differ- ential clock output pairs. ? differential inputs (clk, clk) and (fbin, fbin) ? input oe/os: lvcmos ? differential outputs (y[0:9], y[0:9] and (fbout, fbout) ? external feedback pins (fbin, fbin) are used to synchronize the outputs to the clock input. ? operates at av dd = 1.8v for core circuit and internal pll, and v ddq = 1.8v for differential output drivers ? available packages (pb-free & green): ? 52-ball vfbga (nf) ? pi6cua878 is for ddr2-800/667/533/400 applications pi6cua878 pll clock driver for 1.8v ddr2 mem o ry pin con guration 123456 a y1 y0 y0 y5 y5 y6 b y1 gnd gnd gnd gnd y6 c y2 gnd nb nb gnd y7 d y2 vddq vddq vddq os y7 e ck vddq nb nb vddq fbin f ck vddq nb nb oe fbin g agnd vddq vddq vddq vddq fbout h avdd gnd nb nb gnd fbout j y3 gnd gnd gnd gnd y8 k y3 y4 y4 y9 y9 y8 08-0043
2 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory y0 y0 y1 av dd os oe y1 y2 y2 y3 y3 y4 y4 y5 y5 y6 y6 y7 y7 y8 y8 y9 y9 fbout fbout pll ck ck fbin fbin 10k - 100k ohm ld* or oe ld*, os or oe pll bypass * the logic detect (ld) powers down the device when a logic low is applied to both ck and ck. powerdown control & test logic ld* block diagram 08-0043
3 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory pinout table pin name characteristics description agnd ground analog ground av dd 1.8v nominal analog power ck differential input clock input with a (10k - 100k ) pulldown resistor ck differential input complementary clock input with a (10k - 100k ) pulldown resistor fbin differential input complementary feedback clock input fbin differential input feedback clock input fbout differential output complementary feedback clock output fbout differential output feedback clock output oe lvcmos input output enable (async.) os lvcmos input output select (tied to gnd or v ddq ) gnd ground ground v ddq 1.8v nominal logic and output power y[0:9] differential outputs clock outputs y[0:9] differential outputs complementary clock outputs nb no ball function table inputs outputs pll state av dd oe os ck ck y y fbout fbout gnd h x l h l h l h bypass/off gnd h x h l h l h l bypass/off gnd l h l h l(z) (1) l(z) (1) l h bypass/off gnd l l h l l(z) (1) , y7 active l(z) (1) , y7 active h l bypass/off 1.8v (nom) l h l h l(z) (1) l(z) (1) lhon 1.8v (nom) l l h l l(z) (1) , y7 active l(z) (1) , y7 active hlon 1.8v (nom) h x l h l h l h on 1.8v (nom) h x h l h l h l on 1.8v (nom) x x l l l(z) (1) l(z) (1) l(z) (1) l(z) (1) off 1.8v (nom) x x h h reserved notes: 1. l (z) means the outputs are disabled to a low state meeting the i odl limit on dc speci cation 08-0043
4 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory dc speci cations recommended operating con di tions symbol parameter min. typ. max. units v ddq output supply voltage 1.7 1.8 1.9 v av dd supply voltage (4) v ddq v il low-level input voltage (5) oe, os, ck, ck 0.35 x v ddq v ih high-level input voltage (5) oe, os, ck, ck 0.65 x v ddq i oh high-level output current, see fig 2 - -9 ma i ol low-level output current, see fig. 2 - 9 v ix input differential-pair crossing voltage (v ddq /2) -0.15 (v ddq /2) +0.15 v in input voltage level -0.3 v ddq +0.3 v v id input differential voltage, see fig 9 (5) dc 0.3 v ddq +0.4 ac 0.6 v ddq +0.4 t a operating free air temperature 0 70 oc notes: 4. the pll is turned off and bypassed for test purposes when av dd is grounded. during this test mode, v ddq remains within the recommended operating conditions and no timing parameters are guaranteed. 5. v id is the magnitude of the difference between the input level on ck and the input level on ck, see figure 9 for de t nition. the ck and ck, v ih and v il limits are used to de t ne the dc low and high levels for the logic detect state. absolute maximum ratings (over operating free-air temperature range) symbol parameter min. max. units v ddq , a vdd i/o supply voltage range and analog /core supply voltage range -0.5 2.5 v v i input voltage range (2, 3) -0.5 v ddq +0.5 v o output voltage range (2, 3) -0.5 v ddq +0.5 i ik input clamp current -50 50 ma i ok output clamp current -50 50 i o continuous output current -50 50 i o(pwr) continuous current through each v ddq or gnd -100 100 t stg storage temperature -65 150 oc notes: 1. stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. 08-0043
5 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory dc speci cations param- eter description test condition av dd , v ddq min. typ. max. units v ik all inputs i i = -18ma 1.7v 1.2 v v oh high output voltage i oh = -100a 1.7 to 1.9v v ddq -0.2 i oh = -9ma 1.7 1.1 i odl output disabled low current oe = l, v odl = 100mv 1.7v 100 a v od output differential voltage, the magnitude of the difference between the true and complimentary outputs, see t g. 9 for dimentions 0.6 v i i ck, ck v i = v ddq or gnd 1.9v 250 a oe, os, fbin, fbin v i = v ddq or gnd 10 i ddld static supply current, i ddq + i add ck and ck = l 500 i dd dynamic supply current, i ddq + i add , see note 6 for cpd calcula- tion ck and ck = 410 mhz, all outputs are open (not connected to a pcb) 300 ma ci ck, ck v i = v ddq or gnd 1.8v 23 pf fbin, fbin v i = v ddq or gnd 2 3 ci(?) ck, ck v i = v ddq or gnd 0.25 fbin, fbin v i = v ddq or gnd 0.25 notes: 6. total i dd = i ddq + i add = f ck *c pd *v ddq , solving for c pd = (i ddq + i add )/(f ck *v ddq ) where f ck is the input fre quen cy, v ddq is the power supply and c pd is the power dissipation capacitance. timing requirements (over recommended operating free-air temperature) symbol description av dd , v ddq = 1.8v 0.1v units min. max. f ck operation clock frequency (7, 9) 125 410 mhz application clock frequency (7, 9) 160 410 t l stabilization time (10) f ck = 160 - 410 mhz 6 s t dc input clock duty cycle 40 60 % t off device power down (10) 8ns notes: 7. the pll is able to handle spread spectrum induced skew. 8. operating clock frequency indicates a range over which the pll is able to lock, but in which it is not required to meet the other timing parameters. (used for low-speed debug). 9. application clock frequency indicates a range over which the pll must meet all timing parameters. 10. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal after power up . during normal operation, the stabilization time is also the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal when ck and ck go to a logic low state, enter the power-down mode and later return to active ope ration. ck and ck maybe left ? oating after they have been driven low for one complete clock cycle. 08-0043
6 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory ac speci cations switching char ac ter is tics over rec om mend ed operating free-air temperature range (unless oth er wise noted) (15) parameter description diagram f ck (mhz) av dd , v ddq = 1.8v 0.1v units min. nom. max. ten oe to and y/y see fig 11 8 ns tdis oe to and y/y see fig 11 8 tjit(cc+) cycle-to-cycle jitter see fig 4 04 0 ps tjit(cc-) 0 -40 t(?) static phase offset (11) see fig 5 -50 50 t(?)dyn dynamic phase offset see fig 10 -50 50 tsk(o) output clock skew see fig 6 40 tjit(per) period jitter (12) see fig 7 -40 40 tjit(hper) half period jitter (12) see fig 8 160 to 270 -75 75 half period jitter (12) see fig 8 271 to 350 -50 50 t(su) | tjit(per) | + | t(?)dyn | + tsk(o) (see note 17) 271 to 410 80 t(h) | t(?)dyn | + tsk(o) (see note 17) 271 to 410 60 slr(i) input clock slew rate see fig 9 1 2.5 4 v/ns output enable (oe) see fig 9 0.5 slr(o) output clock slew rate (14, 16) see fig 1, 9 1.5 2.5 3 v ox output differential-pair cross voltage (13) see fig 2 (v ddq /2) -0.1 (v ddq / 2) +0.1 v the pll on the pi6cua878 is capable of meeting all the above test parameters while supporting ssc synthesirers with the following parameters: ssc modulation frequency 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % pi6cua878 pll design should target the values below to minimize the scc induced skew: pll loop bandwidth 2.0 mhz notes: 11. static phase offset does not include jitter 12. period jitter and half-period jitter speci t cations are separate speci t cations that must be met independently of each other. 13. vox speci t ed at the dram clock input or the test load. 14. to eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input ck, ck and feedback clock input fbin, fbin are recommended to be nearly equal. the 2.5v/ns slew rates are shown as a recommended target. compliance with these nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered ddr2 dimm application. 15. there are two terminations that are used with the above ac tests. the load/board in figure 2 is used to measure the input and output differen- tial-pair cross-voltage only. the load/board in figure 3 is used to measure all other tests. for con sis ten cy, equal length cables should be used. 16. the output slew rate is determined from ibis model load shown in figure 1. it is measured single-ended. 17. in the frequency range of 271 mhz to 410 mhz, the minimum and maximum values for tjit(per) and (t(?)dyn and the minimum value for tsk(o) must not exceed the corresponding minimum and maximum values of the 160 mhz to 270 mhz range and sum of the speci t ed values for | tjit(per) |, | t(?)dyn | and tsk(o) must meet the requirement for t(su) and the sum of the speci t ed values for | t(?)dyn | adn tsk(o) must meet the requirment for t(h). 08-0043
7 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory v dd pi6cu878 gnd v ck v ck v dd/2 r = 60 r = 60 figure 2. output load test circuit 1 figure 1. ibis model output load gnd v dd z = 120ohm z= 60ohm z= 60ohm v tt r = 1mohm c= 1pf scope l= 2.97" l= 2.97" gnd gnd c = 10pf c = 10pf v tt r = 1mohm c= 1pf note : v tt = gnd pi6cu878 figure 3. output load test circuit 2 ?v dd /2 v dd /2 ?v dd /2 ?v dd /2 c = 10pf r = 10 r = 10 z= 60 z= 60 z= 50 z= 50 c = 10pf v tt r = 50 r = 50 scope l= 2.97" l= 2.97" v tt note: v tt = gnd pi6cu878 08-0043
8 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory figure 4. cycle-to-cycle jitter figure 5. static phase off set figure 6. output skew fbin fbin ck ck t ( ) n t ( ) n+1 t = 1 n=n t ( ) n n (n is a large number of samples) t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 t cycle n yx,fbout yx,fbout t sk(o) yx yx yx, fbout yx, fbout 08-0043
9 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory figure 7. period jitter (fo = average input frequency measured at ck/ck) figure 8. half-period jitter figure 9. input and output slew rates clock inputs and outputs,oe v id, v od t f(i), t f(o) 80% 20% t r(i), t r(o) 80% 20% slrr (i/o) = v 80% ? v 20% tr (i/o) slrf (i/o) = v 80% ? v 20% tf (i/o) yx, fbout yx, fbout yx, fbout yx, fbout t cycle n f o 1 t jit(per) = t cycle n f o 1 yx, fbout yx, fbout t half period n t n+1 half period f o 1 t jit(hper) = t half period n 2*f o 1 08-0043
10 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory ck ck fbin fbin ssc off ssc on t (?) t (?)dyn t (?)dyn ssc off ssc on t (?) t (?)dyn t (?)dyn figure 10. dynamic phase offset figure 11. time delay between output enable (oe) and clock output (y, y) oe y/y y y 50% v dd 50% v dd t dis 50% v dd 50% v dd t en oe y y 08-0043
11 ps8951a 03/06/08 pi6cua878 pll clock driver for 1.8v ddr2 memory packaging mechanical: 52-pin vfbga (nf) description: 52-ball, very thin pro le fine pitch ball grid array, vfbga package code: nf document control no. pd - 2017 revision: a date: 03/09/05 notes: 1) controlling dimensions in millimeters 2) ref: jedec mo-225b/ba pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com ordering information ordering code packaging code package type PI6CUA878NFE nf pb-free & green, 52-ball vfbga notes: 1. thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ pericom semiconductor corporation ? 1-800-435-2336 ? http://www.pericom.com 08-0043

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