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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD5300 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 2.7 v to 5.5 v, 140 a, rail-to-rail output 8-bit dac in an sot-23 functional block diagram power-on reset dac register input control logic AD5300 v dd gnd v out sync sclk din 8-bit dac ref (+) ref (? output buffer power-down control logic resistor network features single 8-bit dac 6-lead sot-23 and 8-lead soic packages micropower operation: 140 a @ 5 v power-down to 200 na @ 5 v, 50 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design reference derived from power supply power-on-reset to zero volts three power-down functions low power serial interface with schmitt-triggered inputs on-chip output buffer amplifier, rail-to-rail operation sync interrupt facility applications portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the AD5300 is a single, 8-bit buffered voltage out dac that operates from a single 2.7 v to 5.5 v supply consuming 115 a at 3 v. its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the AD5300 utilizes a versatile three-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi?, qspi?, microwire? and dsp interface standards. the reference for AD5300 is derived from the power supply inputs and thus gives the widest dynamic output range. the part incorporates a power-on-reset circuit that ensures that the dac output powers up to zero volts and remains there until a valid write takes place to the device. the part contains a power-down feature that reduces the current consumption of the device to 200 na at 5 v and provides software selectable output loads while in power-down mode. the part is put into power-down mode over the serial interface. the low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment. the power consumption is 0.7 mw at 5 v reducing to 1 w in power-down mode. the AD5300 is one of a family of pin-compatible dacs. the ad5310 is the 10-bit version and the ad5320 is the 12-bit version. the AD5300/ad5310/ad5320 are available in 6-lead sot-23 packages and 8-lead soic packages. product highlights 1. available in 6-lead sot-23 and 8-lead soic packages. 2. low power, single supply operation. this part operates from a single 2.7 v to 5.5 v supply and typically consumes 0.35 mw at 3 v and 0.7 mw at 5 v, making it ideal for battery pow- ered applications. 3. the on-chip output buffer amplifier allows the output of the dac to swing rail-to-rail with a slew rate of 1 v/ s. 4. reference derived from the power supply. 5. high speed serial interface with clock speeds up to 30 mhz. designed for very low power consumption. the interface only powers up during a write cycle. 6. power-down capability. when powered down the dac typically consumes 50 na at 3 v and 200 na at 5 v. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. * patent pending; protected by u.s. patent no. 5684481.
C2C rev. b AD5300?pecifications (v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 500 pf to gnd; all specifications t min to t max unless otherwise noted.) b version 1 parameter min typ max unit conditions/comments static performance 2 resolution 8 bits relative accuracy 1 lsb see figure 2. differential nonlinearity 0.25 lsb guaranteed monotonic by design. see figure 3. zero code error +0.5 +3.5 lsb all zeros loaded to dac register. see figure 6. full-scale error C0.5 C3.5 lsb all ones loaded to dac register. see figure 6. gain error 1.25 % of fsr zero code error drift C20 v/ c gain temperature coefficient C5 ppm of fsr/ c output characteristics 3 output voltage range 0 v dd v output voltage settling time 4 6 s 1/4 scale to 3/4 scale change (40 hex to c0 hex). r l = 2 k ? ; 0 pf < c l < 500 pf. see figure 16. slew rate 1 v/ s capacitive load stability 470 pf r l = 1000 pf r l = 2 k ? digital-to-analog glitch impulse 20 nv-s 1 lsb change around major carry. see figure 19. digital feedthrough 0.5 nv-s dc output impedance 1 ? short circuit current 50 ma v dd = 5 v 20 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode. v dd = 5 v 5 s coming out of power-down mode. v dd = 3 v logic inputs 3 input current 1 a v inl , input low voltage 0.8 v v dd = 5 v v inl , input low voltage 0.6 v v dd = 3 v v inh , input high voltage 2.4 v v dd = 5 v v inh , input high voltage 2.1 v v dd = 3 v pin capacitance 3 pf power requirements v dd 2.7 5.5 v i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 140 250 av ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 115 200 av ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.2 1 av ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 0.05 1 av ih = v dd and v il = gnd power efficiency i out /i dd 93 % i load = 2 ma. v dd = 5 v notes 1 temperature ranges are as follows: b version: C40 c to +105 c. 2 linearity calculated using a reduced code range of 4 to 251. output unloaded. 3 guaranteed by design and characterization, not production tested. specifications subject to change without notice.
AD5300 C3C rev. b timing characteristics 1, 2 limit at t min , t max parameter v dd = 2.7 v to 3.6 v v dd = 3.6 v to 5.5 v unit conditions/comments t 1 3 50 33 ns min sclk cycle time t 2 13 13 ns min sclk high time t 3 22.5 13 ns min sclk low time t 4 13 13 ns min sync to sclk falling edge setup time t 5 5 5 ns min data setup time t 6 4.5 4.5 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising edge t 8 50 33 ns min minimum sync high time notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 see figure 1. 3 maximum sclk frequency is 30 mhz at v dd = 3.6 v to 5.5 v and 20 mhz at v dd = 2.7 v to 3.6 v. specifications subject to change without notice. sclk sync din t 8 db15 db0 t 4 t 3 t 2 t 7 t 5 t 6 t 1 figure 1. serial write operation (v dd = 2.7 v to 5.5 v; all specifications t min to t max unless otherwise noted.) absolute maximum ratings * (t a = 25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v digital input voltage to gnd . . . . . . . C0.3 v to v dd + 0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature (t j max) . . . . . . . . . . . . . . . . . . 150 c sot-23 package power dissipation . . . . . . . . . . . . . . . . . . . (t j maxCt a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . 240 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c soic package power dissipation . . . . . . . . . . . . . . . . . . . (t j maxCt a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . 206 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . 44 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. ordering guide temperature branding package model range information option * AD5300brt C40 c to +105 c d2b rt-6 AD5300brm C40 c to +105 c d2b rm-8 * rt = sot-23; rm = soic. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD5300 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
AD5300 C4C rev. b pin configurations top view (not to scale) 6 5 4 1 2 3 v out gnd v dd sync sclk din AD5300 top view (not to scale) 8 7 6 5 1 2 3 4 nc AD5300 sync v out gnd v dd sclk din nc nc = no connect sot-23 soic pin function descriptions sot-23 pin numbers pin no. mnemonic function 1v out analog output voltage from dac. the output amplifier has rail-to-rail operation. 2 gnd ground reference point for all circuitry on the part. 3v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and v dd should be decoupled to gnd. 4 din serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 5 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. 6 sync level triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the fall- ing edges of the following clocks. the dac is updated following the 16th clock cycle unless sync is taken high before this edge in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac.
AD5300 C5C rev. b terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer func- tion. a typical inl vs. code plot can be seen in figure 2. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 3. zero-code error zero-code error is a measure of the output error when zero code (00 hex) is loaded to the dac register. ideally the output should be 0 v. the zero-code error is always positive in the AD5300 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in lsbs. a plot of zero-code error vs. temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full-scale code (ff hex) is loaded to the dac register. ideally the output should be v dd C 1 lsb. full-scale error is expressed in lsbs. a plot of full-scale error vs. temperature can be seen in figure 6. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the dac transfer characteristic from ideal ex- pressed as a percent of the full-scale range. total unadjusted error total unadjusted error (tue) is a measure of the output error taking into account all the various errors. a typical tue vs. code plot can be seen in figure 4. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is chan ged by 1 lsb at the major carry transition (7f hex to 80 hex). see figure 19. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv secs and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
code inl error lsbs 1 0.5 1 0 50 250 100 150 200 0 0.5 inl @ 3v inl @ 5v t a = 25 c figure 2. typical inl plot temperature c error lsbs 1 0.5 1 40 0 120 40 80 0 0.5 max inl min inl max dnl min dnl v dd = 5v figure 5. inl error and dnl error vs. temperature i source/sink ma v out v 3 2 0 0 515 10 1 dac loaded with ff hex t a = 25 c dac loaded with 00 hex figure 8. source and sink current capability with v dd = 3 v code dnl error lsbs 0.5 0.4 0.5 050 250 100 150 200 0.1 0.2 0.3 0.4 0.3 0.1 0.2 0 t a = 25 c dnl @ 5v dnl @ 3v figure 3. typical dnl plot temperature c 3 2 3 40 120 04080 0 1 v dd = 5v error lsbs 2 1 zs error fs error figure 6. zero-scale error and full- scale error vs. temperature i source/sink ma v out v 5 4 0 0 515 10 3 2 1 dac loaded with 00 hex t a = 25 c dac loaded with ff hex figure 9. source and sink current capability with v dd = 5 v code tue lsbs 1.0 0.5 1.0 0 50 250 100 150 200 0 0.5 t a = 25 c tue @ 5v tue @ 3v figure 4. typical total unadjusted error plot 2500 2000 500 50 1500 1000 0 frequency 70 90 110 130 150 170 190 60 80 100 120 140 160 180 v dd = 3v v dd = 5v i dd a figure 7. i dd histogram with v dd = 3 v and v dd = 5 v code i dd a 500 400 0 0 50 250 100 150 200 300 200 100 v dd = 3v v dd = 5v figure 10. supply current vs. code AD5300 typical performance characteristics C6C rev. b
AD5300 C7C rev. b temperature c i dd a 0 40 80 040 300 100 50 120 v dd = 5v 150 200 250 figure 11. supply current vs. temperature v logic v 800 600 0 01 5 234 400 200 t a = 25 c v dd = 5v v dd = 3v i dd a figure 14. supply current vs. logic input voltage 2k load to v dd ch1 1v, ch 2 1v, time base = 20 s/div v dd v out ch1 ch2 figure 17. power-on reset to 0 v v dd v i dd a 300 250 0 2.7 3.2 5.2 3.7 4.2 4.7 200 150 100 50 figure 12. supply current vs. supply voltage v out clk ch1 1v, ch 2 5v, time base = 1 s/div ch1 ch 2 v dd = 5v full-scale code change 00 hex ff hex t a = 25 c output loaded with 2k and 200pf to gnd figure 15. full-scale settling time ch1 1v, ch 2 5v, time base = 5 s/div ch2 ch1 clk v out v dd = 5v figure 18. exiting power-down (7f hex loaded) v dd v 1.0 0.9 0 2.7 3.2 5.2 3.7 4.2 4.7 0.4 0.3 0.2 0.1 0.8 0.6 0.7 0.5 three state condition 40 c +25 c +105 c i dd a figure 13. power-down current vs. supply voltage v out clk v dd = 5v half-scale code change 40 hex c0 hex t a = 25 c output loaded with 2k and 200pf to gnd ch1 1v, ch2 5v, time base = 1 s/div ch 1 ch 2 figure 16. half-scale settling time v out v 500ns/div 2.54 2.46 2.50 2.48 2.52 loaded with 2k and 200pf to gnd code change: 80 hex to 7f hex figure 19. digital-to-analog glitch impulse
AD5300 C8C rev. b general description d/a section the AD5300 dac is fabricated on a cmos process. the archi- tecture consists of a string dac followed by an output buffer amplifier. since there is no reference input pin, the power supply (v dd ) acts as the reference. figure 20 shows a block diagram of the dac architecture. v dd v out gnd resistor string ref (+) ref ( ) output amplifier dac register figure 20. dac architecture since the input coding to the dac is straight binary, the ideal output voltage is given by: v out = v dd d 256 ? ? ? ? ? ? where d = decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 255. resistor string the resistor string section is shown in figure 21. it is simply a string of resistors, each of value r. the code loaded to the dac r r to output amplifier r r r figure 21. resistor string register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaran- teed monotonic. output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0 v to v dd . it is capable of driving a load of 2 k ? in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figures 8 and 9. the slew rate is 1 v/ s with a half-scale settling time of 4 s with the output loaded. serial interface the AD5300 has a three-wire serial interface ( sync , sclk and din), which is compatible with spi, qspi and microwire interface standards as well as most dsps. see figure 1 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 16-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the AD5300 compatible with high-speed dsps. on the sixteenth falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in dac register contents and/or a change in the mode of operation). at this stage, the sync line may be kept low or be brought high. in either case, it must be brought high for a mini- mum of 33 ns (v dd = 3.6 v to 5.5 v) or 50 ns (v dd = 2.7 v to 3.6 v) before the next write sequence so that a falling edge of sync can initiate the next write sequence. since the sync buffer draws more current when v in = 2.4 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part. as is mentioned above, however, it must be brought high again just before the next write sequence. input shift register the input shift register is 16 bits wide (see figure 22). the first two bits are dont cares. the next two are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). there is a more complete description of the various modes in the power-down modes section. the next eight bits are the data bits. these are trans- ferred to the dac register on the sixteenth falling edge of sclk. finally, the last four bits are dont cares. db0 (lsb) db15 (msb) 0 0 normal operation 011k to gnd 1 0 100k to gnd 1 1 three-state power-down modes data bits x x pd1pd0d7d6d5d4d3d2 d1d0 x x x x figure 22. input register contents
AD5300 C9C rev. b power-down circuitry resistor network v out resistor string dac amplifier figure 24. output stage during power-down the bias generator, the output amplifier, the resistor string and other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s for v dd = 3 v. see figure 18 for a plot. microprocessor interfacing AD5300 to adsp-2101/adsp-2103 interface figure 25 shows a serial interface between the AD5300 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, 16- bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. adsp-2101/ adsp-2103 * dt * additional pins omitted for clarity sync din sclk AD5300 * tfs sclk figure 25. AD5300 to adsp-2101/adsp-2103 interface db15 db0 sclk sync din db15 db0 valid write sequence, output updates on the 16 th falling edge invalid write sequence: sync high before 16 th falling edge figure 23. sync interrupt facility sync interrupt in a normal write sequence, the sync line is kept low for at least 16 falling edges of sclk and the dac is updated on the 16th falling edge. however, if sync is brought high before the 16th falling edge this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. ne ither an update of the dac register contents or a change in the operating mode occurssee figure 23. power-on-reset the AD5300 contains a power-on-reset circuit which controls the output voltage during power-up. the dac register is filled with zeros and the output voltage is 0 v. it remains there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the out- put of the dac while it is in the process of powering up. power-down modes the AD5300 contains four separate modes of operation. these modes are software-programmable by setting two bits (db13 and db12) in the control register. table i shows how the state of the bits corresponds to the mode of operation of the device. table i. modes of operation for the AD5300 db13 db12 operating mode 0 0 normal operation power-down modes 01 1 k ? to gnd 1 0 100 k ? to gnd 1 1 three-state when both bits are set to 0, the part works normally with its normal power consumption of 140 a at 5 v. however, for the three power-down modes, the supply current falls to 200 na at 5 v (50 na at 3 v). not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output imped ance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through a 1 k ? resis- tor, a 100 k ? resistor or it is left open-circuited (three-state). the output stage is illus trated in figure 24.
AD5300 C10C rev. b * additional pins omitted for clarity sync din AD5300 * sclk microwire * sk so cs figure 28. AD5300 to microwire interface applications using ref19x as a power supply for AD5300 because the supply current required by the AD5300 is extremely low, an alternative option is to use a ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) to supply the required voltage to the partsee figure 29. this is especially useful if your power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v (e.g., 15 v). the ref19x will output a steady supply voltage for the AD5300. if the low dropout ref195 is used, the current it needs to supply to the AD5300 is 140 a. this is with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k ? load on the dac output) is: 140 a + (5 v /5 k ? ) = 1.14 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 2.3 ppm (11.5 v) for the 1.14 ma current drawn from it. this corresponds to a 0.0006 lsb error. AD5300 three-wire serial interface sync sclk din 15v 5v 140 a v out = 0v to 5v ref195 figure 29. ref195 as power supply to AD5300 bipolar operation using the AD5300 the AD5300 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 30. the circuit below will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: v o = v dd d 256 ? ? ? ? ? ? r 1 + r 2 r 1 ? ? ? ? ? ? C v dd r 2 r 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? where d represents the input code in decimal (0C255). with v dd = 5 v, r 1 = r 2 = 10 k ? : v o = 10 d 256 ? ? ? ? ? ? C5 v this is an output voltage range of 5 v with 00 hex corresponding to a C5 v output and ff hex corresponding to a 5 v output. AD5300 to 68hc11/68l11 interface figure 26 shows a serial interface between the AD5300 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the AD5300, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct opera- tion of this interface are as follows: the 68hc11/68l11 should be configured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmit- ted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data to the AD5300, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac and pc7 is taken high at the end of this procedure. * additional pins omitted for clarity sync din AD5300 * sclk 68hc11/68l11 * sck mosi pc7 figure 26. AD5300 to 68hc11/68l11 interface AD5300 to 80c51/80l51 interface figure 27 shows a serial interface between the AD5300 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the AD5300, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case port line p3.3 is used. when data is to be transmit- ted to the AD5300, p3.3 is taken low. the 80c51/80l51 trans- mits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/ 80l51 outputs the serial data in a format which has the lsb first. the AD5300 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. * additional pins omitted for clarity sync din AD5300 * sclk 80c51/80l51 * txd rxd p3.3 figure 27. AD5300 to 80c51/80l51 interface AD5300 to microwire interface figure 28 shows an interface between the AD5300 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5300 on the rising edge of the sk.
AD5300 C11C rev. b 0.1 f v dd 10k power 10 f v dd sync sclk data AD5300 5v regulator v dd 10k v dd 10k v out din sync sclk gnd figure 32. AD5300 with an opto-isolated interface power supply bypassing and grounding when accuracy is important in a circuit it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the AD5300 should have separate analog and digital sections, each having its own area of the board. if the AD5300 is in a system where other devices require an agnd to dgnd connection, the connec- tion should be made at one point only. this ground point should be as close as possible to the AD5300. the power supply to the AD5300 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physi- cally as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series induc tance (esi), e.g., common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as pos- sible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a two-layer board. r2 = 10k +5v 5v ad820/ op295 three-wire serial interface +5v AD5300 10 f 0.1 f v dd v out r1 = 10k 5v figure 30. bipolar operation with the AD5300 two 8-bit AD5300s together make one 15-bit dac by using the configuration below in figure 31, it can be seen that one 15-bit dac can be made with two 8-bit AD5300s. because of the low supply current the AD5300 requires, the output of one dac may be directed into the supply pin of the second dac. the first dac has no problem sourcing the required 140 a of current for the second dac. since the AD5300 works on any supply voltage between 2.5 v and 5.5 v, the output of the first dac can be anywhere above 2.5 v. for a v dd of 5 v this allows the first dac to use half of its output range (2.5 v to 5 v), which gives 7-bit resolution on the output voltage. this output then becomes the supply and reference for the second dac. the second dac has 8-bit reso- lution on the output range, which gives an overall resolution for the system of 15 bits. a level-shifter is required to ensure that the logic input voltages do not exceed the supply voltage of the part. the microcontroller outputs 5 v signals which need to be level-shifted down to 2.5 v in the case of the second dac having a supply of only 2.5 v. 5v micro- controller v out = 2.5v to 5v level shifter v out = 0v to 5v 15-bit resolution sync sclk din v dd AD5300 AD5300 v dd sync sclk din figure 31. 15-bit dac using two AD5300s using AD5300 with an opto-isolated interface in process-control applications in industrial environments it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous common- mode voltages that may occur in the area where the dac is functioning. opto-isolators provide isolation in excess of 3 kv. because the AD5300 uses a three-wire serial logic interface, it requires only three opto-isolators to provide the required isola- tion (see figure 32). the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the AD5300.
AD5300 C12C rev. b outline dimensions dimensions shown in inches and (mm). c00471bC3C10/00 (rev. b) printed in u.s.a. 6-lead sot-23 (rt-6) 0.122 (3.10) 0.106 (2.70) pin 1 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) 8-lead soic (rm-8) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84)

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