easy gui browser chip AGB64LV01-QC amulet? easy gui browser chip is a special pur- pose microcontroller that is optimized to execute amulet? gui kernel and component based gui firm- ware. the chip is a combination lcd controller chip and a user interface chip. this chip eliminates the need for complex code to draw each pixel on an lcd. the chip renders gui pages containing graphic images, amulet widgets, and other ui ob- jects directly to the lcd. this lets your embedded micro do its job more efficiently. thus, the main application can run on a smaller processor with less ram and rom, and code development and main- tenance time is significantly reduced. the AGB64LV01-QC is an 80-pin fqfp asic with the following built in peripherals: lcd controller microprocessor uart timer spi master the easy gui browser chip has 13 dedicated output lines for lcd control of various size sub- vga displays. the chip is able to drive different size displays because the bias voltage, which determines the lcd driving voltage, is supplied from an external source. supply voltage: 3.3v + 10% applicable lcd duty: up to 1/256 (adjust- able in single increments) dedicated gui chip ? manages the gui, interacts with the user, and controls the lcd?frees up your micro! html-based gui creation? create and edit quickly using drag-and-drop html tools compiler included? converts from html, jpeg, and gif into small, quickly-executable amulet ?tml pages processor independent? easily interfaces to most microcontrollers (8/16/32-bit and dsps) replaces traditional gui library? no library porting, complex gui programming, or rtos required rs232 interface? up-to 115.2 kbps pin pin no. name no. name 1 iclk 2 gnd 3 xtal 4 /reset 5 /irq2 6 pixel_d7 7 pixel_d6 8 vcc 9 pixel_d5 10 pixel_d4 11 pixel_d3 12 pixel_d2 13 pixel_d1 14 gnd 15 pixel_d0 16 lcd_pwr 17 line_pulse 18 frame_clk 19 pixel_clk 20 gnd 21 frame_out 22 addr7 23 addr6 24 addr5 25 addr4 26 vcc 27 /we 28 data3 29 data2 30 data1 31 data0 32 gnd 33 sync 34 addr3 35 addr2 36 addr1 37 addr0 38 gnd 39 addr16 40 addr15 41 addr14 42 addr13 43 /oe 44 vcc 45 data7 46 data6 47 data5 48 data4 49 addr12 50 gnd 51 addr11 52 addr10 53 addr9 54 addr8 55 txd 56 gnd 57 rxd 58 /poc0 59 poc1 60 poc2 61 poc3 62 vcc 63 /poc4 64 /irq1 65 poc6 66 poc7 67 sclk 68 gnd 69 mosi 70 miso 71 /ss0 72 /ss1 73 /ss2 74 gnd 75 /ss3 76 /ss4 77 /ss5 78 /ss6 79 /ss7 80 vcc requires: 3.3v power supply serial flash (atmel, 1 megabit minimum) static ram (64k-byte minimum) clock/crystal (up to 20 mhz)
pin description i = input o = output i/o = input and output p = power supply pin name type pin number description data7-data0 i/o 45-48, 11-13, 31 system data bus addr16-addr0 o 40-42, 49, 51-54, system address bus 22-25, 34-37, 39 we o 27 memory write enable (1=read 0=write) oe o 43 memory output enable (0=read 1=write) sync o 33 n/c reset i 4 system reset (active low) iclk i 1 system clock see diagram for connections xtal o 3 system clock irq2 i 5 interrupt request (active low) rxd i 57 uart receive data txd o 55 uart transmit data miso i 70 spi data in mosi o 69 spi data out ss0 o 71 spi flash select ss1-ss6 o 72-73, 75-78 extra slave selects ss7 o 79 system ram test status poc0 i 58 system power-up mode poc3 i 61 flash programming rate* poc6 i 65 system ram test poc4 i 63 touch panel calibration poc1-poc2 i 59-60 crystal selection* irq1 i 64 touch panel interrupt poc7 i 66 n/c sclk o 67 spi clock pixel_d7- o 6-7, 9-13, 15 lcd pixel data. this output bus transfers data pixel_d0 to be displayed on the lcd. users can specify the bus width to be either 1, 2, 4, or 8. pixel_clk o 19 pixel data shift clock (cl2). user can specify whether to clock data in on the rising or falling edge of pixel_clk. line_pulse o 17 pixel data latch signal (cl1). this output goes active for one clock period after all the serial data for the current line has been shifted to the lcd. polarity of this signal can be specified. frame_out o 21 frame signal (flm). lcd first frame synchronization. frame_clk o 18 lcd drive signal (m). lcd crystal polarization clock. lcd_pwr o 16 display control signal. lcd power (??on, ??off). vcc p 8, 26, 44, 62, 80 power supply pin gnd p 2, 14, 20, 32, 38, grounding pin 50, 56, 68, 74 19200 baud rate freq. poc line 1 2 3 10mhz 0 1 1 12mhz 0 1 0 16mhz 1 0 0 20mhz 0 0 0 115200 baud rate freq. poc line 1 2 3 10mhz 1 1 1 12mhz 0 1 1 16mhz 1 0 1 20mhz 0 0 1 *frequency setup table.
dc characteristics current vcc = + 3.3v +/-10%, gnd = 0, temp= -20 to +75c item symbol condition min typ max unit operating current icc 10mhz 10 ma operating current icc 10mhz reset 7 ma operating current icc 16mhz 16 ma operating current icc 16mhz reset 10 ma absolute maximum ratings item symbol value unit supply voltage vcc -0.3 to +6.5 v input voltage 3.3v vin 3.0 to 3.6 v operating temp. topr -20 to +75 ? storage temp. tstg -60 to +150 ? soldering lead temp. tsol 210 ? soldering 10 sec. dc characteristics for 3.3v item symbol min typ max unit ttl input input ?igh?voltage vih 2 v input ?ow?voltage vil 0.8 v input leakage current il -10 10 ? cmos input input ?igh?voltage vih .7 x vcc v input ?ow?voltage vil 0.3vcc v input leakage current il -10 10 ? ttl output output ?igh?voltage voh 2.45 v output ?ow?voltage vol 0.45 v cmos output output ?igh?voltage voh .7 x vcc v output ?ow?voltage vol 0.3vcc v operating frequency f_clk 10 16 20 mhz pull-up resistor (reset, rxd, 70k 108k 202k ohms poc7, irq, miso, iclk)
although there is only a single von-neuman cpu, the cpu features task specific opcodes, registers and memory segments for three very different types of tasks: graphics rendering, i/ o processing and general purpose computing. this architecture enables the gui kernel firmware to implement a highly efficient task scheduler. in addition, graphics and i/o tasks are implemented with a minimum of cpu cycles and code space. the line buffer is a parallel loaded shift register with a maximum capacity of 256 bytes. it is responsible for periodically burst fetching a block of pixel data for each raster line from the frame buffer. to minimize the burst period, the line buffer was implemented as a dual ported synchronous sram block capable of reading a single byte in a single cpu clock cycle. to minimize external pin and component count, only a single external memory bus is imple- mented. because both the cpu and line buffer require access to external memory, a memory interface unit is employed to resolve arbitration and to direct flow of data and ad- dress signals. the cpu also features a separate i/o bus linking the following on-chip peripherals to the cpu?s i/o task: an lcd raster controller, three timers, a uart, and an spi master with 8 slave selects. the lcd raster controller is a unique peripheral. it is responsible for converting the line buffer data to signals conforming to standard lcd interfaces. these include horizontal and vertical synchs as well as a serially shifted data stream of pixel data and a shift clock. detailed description
interface information, by manufacturer/model seiko optrex denistron nanya hantronix pixtech signal g4 /g8 dmf50081 pm0149 lmbgax032x dm3224-1 fe524m1 pixel_clk cl2 cp cl2(scp) cp2 cp dclk pixel_d0 d3 d3 d0 d3 d3 d4 pixel_d1 d2 d2 d1 d2 d2 d3 pixel_d2 d1 d1 d2 d1 d1 d2 pixel_d3 d0 d0 d3 d0 d0 d1 line_pulse cl1 lp cl1(lp) cp1 load hsync frame_out flm flm flm s frame ysync frame_clk m m m lcd_pwr disp off disp off ble dispoff don lcd interface timing diagrams the following timing diagrams assume: data width = 8-bits max. (adjustable in software) line_pulse = positive or negative - edge line pulse (adjustable in software) pixel_clk = positive or negative - edge pixel clock (adjustable in software) maxbyte = 4 bytes of data per line and with the following data in the line buffer: 20, 21, 22, 23 xtal pixel_clk active edge pixel_data 0 2 1 2 3 2 line_pulse frame_out frame_clk lcd characteristic settings within the compiler let you specify different displays either by manufacturer or by size (up to 1/4 vga resolution), frame frequency, and pixel clock.
spi interface timing diagram /ss0 sclk mosi miso spi interface serial interface architecture minimum 1m-bit (264 bytes/page * 512 pages) one 264-byte sram data buffer ttl i/o description amulet? easy gui browser chip supports an atmel flash memory device (part # at45db011b-sc) for data storage of ?tml pages. the flash memory device must be organized with a minimum of 512 pages of 264 bytes each, plus one sram data buffer of 264 bytes. the flash is enabled through a chip select pin (/cs) and accessed via a three-wire serial interface consisting of a serial input (si), serial output (so), and a serial clock (sck). device operation the flash device is controlled by instructions from the amulet easy gui browser chip. the list of instructions which amulet uses to interface to the flash are as follows: main memory page read (52h) main memory page to buffer transfer (53h), buffer write (84h) buffer to main memory page program (83h) status register (57h). if you decide to use a flash device other than the recommended atmel part, the device must support the five instructions above. please check the atmel datasheet for more information on the atmel flash device.
t cyc cpu write clk t ad t ah addr t ds0 t dh0 data t ws t wh /we cpu read clk t ad t ah addr t ds1 t dh1 data there are two subsystems that access memory: the cpu and the display line buffer. the timing for each subsystem is detailed below. cpu memory access timing the cpu performs both read and write accesses to memory. in either case, all timing parameters for cpu accesses are relative to the falling edge of clk. all input signals are sampled at the falling edge of clk and all output signals transition after some delay relative to the falling edge of clk. input hold times are the amount of time after the falling edge of clk that a signal must remain stable. output hold times are the minimum delay that the signal will remain stable after the falling edge of clk. label description value units t ad address delay 10 ns t ah address hold 5 ns t ds1 read data setup 5 ns t dh1 read data hold 0 ns label description value units t ad address delay 10 ns t ah address hold 5 ns t ds0 write data delay 10 ns t dh0 write data hold 5 ns t ws write enable delay 8 ns t wh write enable hold 3 ns
line buffer memory access timing the line buffer only performs read accesses to memory. timing parameters for line buffer reads are relative to both edges of clk. all input signals are sampled at the rising edge of clk and all output signals transition after some delay relative to the falling edge of clk. input hold times are the amount of time after the rising of clk that a signal must remain stable. output hold times are the minimum delay that the signal will remain stable after the falling edge of clk. label description value units t ad address delay 10 ns t ah address hold 5 ns t ds2 read data setup 5 ns t dh2 read data hold 5 ns t cyc linebuffer read clk t ad t ah addr t ds2 t dh2 data iclk xtal clock clock options clock oscillator
chip mechanicals 80 pqfp (14x20x2.7mm), 3.2mm fp
www.amulettechnologies.com amulet technologies, llc 275 saratoga avenue, suite 230 santa clara, ca 95050 (408) 244-0363 ?001 amulet technologies. u.s. and foreign patents pending. easy gui and ?tml are trademarks of amulet technologies. sample application
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