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? semiconductor components industries, llc, 2005 may, 2005 ? rev. 2 1 publication order number: NBC124XXEVB/d NBC124XXEVB/d nbc12429/12430/12439 evaluation board prepared by: casey stys device description the nbc124xx ? series are high ? speed, programmable pll ? based clock synthesizers. a crystal (or an external frequency source for the 12430 or 12439) provides a reference frequency to the internal pll. this reference frequency is multiplied by a vco to a desired frequency by a ratio of integers. the vco frequency is sent to the n ? output divider, where it can be configured to various division ratios and then drive a pair of differential (lv)pecl outputs. board description the nbc12429/430/439 evaluation board provides a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of all three nbc124xx clock generators. this user?s manual provides detailed information on board contents, layout and its use. it should be used in conjunction with a device data sheet: nbc12429, nbc12430 or nbc12439. (www.onsemi.com) the nbc12429/430/439 evaluation board is equipped with a plcc ? 28 surface mount socket. board features ? accommodates all three nbc12429/430/439 clock generators ? supports use of 10 mhz to 20 mhz through ? hole or surface mount crystal ? incorporates dip switch controlled m and n logic pins are programmed on board, minimizing excess cabling ? p_load is push ? button or externally controlled ? serial input interfaces are accessed externally via sma connectors ? convenient and compact board layout ? 3.3 v or 5 v split ? power supply operation ? lvpecl/pecl differential output signals are monitored via sma connectors figure 1. evaluation board manual http://onsemi.com
NBC124XXEVB/d http://onsemi.com 2 figure 2. evaluation board (top view) figure 3. evaluation board (bottom view)
NBC124XXEVB/d http://onsemi.com 3 lab set ? up procedure power supply connections and output termination each device has a positive supply pin, v cc , and a negative supply pin, gnd. v tt is the termination supply for the pecl outputs, only. power supply terminal connectors, v cc , v tt and gnd are provided in the upper right corner of the board. the (lv)pecl f out outputs must be externally dc terminated, off the evaluation board. a ?split? or dual power supply technique can be used to take advantage of terminating the (lv)pecl outputs into 50 of an oscilloscope or a frequency counter. since v tt = v cc ? 2 v, offsetting v cc by +2 v yields v tt = 0 v or ground. the v tt terminal connects to the isolated sma connector ground plane, and is not to be confused with the device ground pin. (see and8020 for more information on terminating ecl) figure 4. ?split? or dual power supply connections +3.3v dual power supplies v cc gnd v tt +2.0 v +1.3 v ? + ? + f out power red ? vcc yellow ? vtt black ? gnd on semiconductor nbc12429/30/39 evaluation board 10338 f out digitial oscilloscope or frequency counter vcc ? 8 vcc 12439 j11 j10 test m[0] m[0] m[1] m[1] m[2] m[2] m[3] m[3] m[4] m[4] m[5] m[5] m[6] m[6] m[7] m[7] m[8] m[8] m[0] m[0] m[1] m[1] sw3 sw4 trigger 50 50 v cc = +2.0 v v tt = 0 v gnd = ? 1.3 v figure 5. ?split? or dual power supply connections table 1. ?split? power supply configuration device power supply ?spilt? power supply pin connector color v cc red v cc = +2.0 v yellow v tt = v cc ? 2 v = 0 v gnd black gnd = ? 1.3 v (or ?3.0 v) board layout the evaluation board is constructed with getek material and is designed to minimize noise, achieve high bandwidth and minimize crosstalk. sma connectors are provided for signal access. serial clock, serial data, serial load and test have sma connector provisions, if the application requires them.
NBC124XXEVB/d http://onsemi.com 4 the nbc124xx evaluation board is equipped with dip switches, used to manipulate the static levels of the m and n pins. the off (open = ?0?) condition of the dip switch asserts a logic low on the assigned pin, and the on (closed = ?1?) condition asserts a logic high by way of the device?s internal pull ? up resistor. layer stack l1 signal l2 sma ground l3 v cc (positive power supply) l4 signal/device ground (negative power supply) lab set ? up and measurement procedure getting started ? equipment used ? agilent signal generator #33250a for fref_ext on 12430 and 12439 ? tektronix tds8000 oscilloscope or frequency counter ? agilent #6624a dc power supply ? digital voltmeter ? matched high ? speed cables with sma connectors in order to get started and demonstrate the nbc124xx, perform the following test set ? up sequence: to monitor the f out outputs on an oscilloscope or frequency counter (with internal 50 termination impedance), the power supply needs to be dc offset: 1. connect a ?split? power supply to the evaluation board. (see figures 4 and 5) connect v cc banana jack to +2.0 v connect v tt banana jack to sma_gnd = 0 v connect gnd banana jack to ? 1.3 v for 3.3 v operation; or ?3.0 v for 5 v operation 2. ensure the oscilloscope is triggered properly and has 50 termination to ground. the board does not provide 50 source termination resistors. two oscilloscope trigger methods are from f out (using ?t? connector) or directly from f out . 3. connect the (lv)pecl f out /f out outputs to the oscilloscope with matched cables. the outputs are terminated with 50 to v tt (v cc ? 2.0 v) = 0 v = ground internal to the oscilloscope. 4. determine if a crystal (xtal) or an external reference (fref_ext) will be used. see table 2 a) for cyrstal use on the 12429 or 12430, use a crystal; no jumpers are need. for the 12439, [m7] switch (pin 15) is set to high, use a crystal. b)for external reference use, on the 12430 or 12439, force a logic low on xtal_sel to choose an external reference frequency. provide a clock input from a signal generator (10 ? 20 mhz) into fref_ext. 5. set the programmable m and n pin switches accordingly to achieve the desired function table logic input levels. 6. set the oe pin to a logic high (and pwr_dwn to a logic low on the 12439). fref_ext sma j1 12430 ? fref_ext 12439 ? pwr_down 12430 ? xtal_sel 12439 ? fref_ext v cc gnd figure 6. programmable jumpers for device selection and operating options (pins 2 and 3, plcc ? 28) pin 2 pin 3 jmp1 jmp2 jmp3 jmp4 table 2. programmable jumper selection for pins 2 and 3 (plcc28) 12430 12439 xtal fref_ext xtal fref_ext pwr_down no jumper use crystal jmp2 and jmp4 use sma j1 pin 15 (m7/xtal_sel ? high) no jumpers use crystals pin 15 (m7/xtal_sel ? low) jmp3 use sma j1 jmp1 switch 1 ? h ? 16 ? l ? 1
NBC124XXEVB/d http://onsemi.com 5 evaluation board features by pin the nbc12429/430/439 evaluation board was designed to accommodate the test and evaluation of all three nbc12429/430/439 clock generators. detailed board features by device pin are described below: crystal (xtal1 and xtal2) either a through ? hole or surface mount crystal can be used. xt al1 and xtal2 have equal length board traces to sma connectors available to directly interface to the crystal input pins (with an external signal source) when a zero resistor (or short) is placed on the board trace at the crystal pins. otherwise, these board traces and connectors are open and not connected to the crystal pins and have no impedance affect on the crystal pins. m and n the m and n pins are programmed by the dip switches. the input logic levels can be monitored by observing the status of the appropriate led. the m and n device pins have internal pull ? up resistors. the nbc124xx evaluation board was designed to take advantage of this attribute. when the m or n switch is in the logic high position, the input pin ?floats? to a logic high owing to the pull ? up resistor and the led is turned on simply for a visual indicator. a logic high voltage is not forced on the pin. in the low position, the switch forces the m or n pin to the negative power supply rail, a logic low. an led power supply jumper, j11, is provided to disable the leds (current). measuring only the device power supply current is then possible. p_load the p_load pin ?floats? to a logic high by means of the internal pull ? up resistor and can be controlled manually with the momentary push ? button switch, which is normally open. depressing and releasing p_load forces a logic low ? high ? low signal on the p_load pin, latching the m and n logic levels. p ? load also has a board trace to an sma connector for external control. fref_ext ? external reference frequency on the 12430 and 12439, an external reference signal can be forced into fref_ext via sma j1. the xt al_sel pin must set to a logic low. there is no 50 resistor on this node. if a signal generator requiring output termination is used to drive fref_ext, a 50 resistor can be added, from the board trace or sma conductor to the sma ground. f out and f out the f out and f out pecl outputs have equal length board traces with sma connectors, j8 and j9. matched cables can connect to an oscilloscope or frequency counter. serial and test pins s_clock, s_data, s_load and test pins have board traces connected to sma connectors j7, j6, j5 and j10 for external control. there are no 50 resistors on this nodes. if a signal sources requiring output termination are used to drive s_clock, s_data and s_load, 50 resistors can be added, from the board trace or sma conductor to the sma ground. power_down ? (nbc12439) the power down function on the nbc12439 can be carried out manually by setting switch 1 a with the condition described in table 2 and observing the f out pins; 1 or 16. oe the output enable function is carried out manually with the oe switch and observing the f out pins.
NBC124XXEVB/d http://onsemi.com 6 table 3. nbc12429 pin description pin # pin # open pin 28 ? plcc 32 ? tqfp pin name i/o open pin default type function 1 4 pll_vcc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 5 pll_vcc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 2 6 nc no connect 3 7 nc no connect 4 8 xtal1 input analog crystal oscillator interface 5 9 xtal2 input analog crystal oscillator interface 6 10 oe input h cmos/ttl active high output enable. the enable is synchronous to the output clock to eliminate the possibility of runt pulses on the f out outputs. 7 11 p_load input h cmos/ttl parallel configuration control input. this pin loads the configuration latches with the contents of the parallel in- puts. the latches will be transparent when the signal is low; therefore, the parallel data must be stable on the low ? to ? high transition of p_load for proper operation. 8 12 m0 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. m0 is the lsb. 9 13 m1 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 10 14 m2 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 11 15 m3 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 16 nc h no connect 12 17 m4 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 13 18 m5 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 14 19 m6 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 15 20 m7 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 16 21 m8 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. m8 is the msb. 17 22 n0 input h cmos/ttl output divider input. used to configure the output divider modules. sampled on the low ? to ? high transition of p_load. 18 23 n1 input h cmos/ttl output divider input. used to configure the output divider modules. sampled on the low ? to ? high transition of p_load. 24 nc no connect 19 25 gnd supply supply ground negative power supply (gnd) 20 26 test output cmos/ttl test and device diagnostics output; function is determined by serial configuration bits t[2:0]. 21 27 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 28 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 22 29 gnd supply supply ground negative power supply (gnd) 23 30 f out output pecl differential clock output 24 31 f out output pecl differential clock output 25 32 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 26 1 s_clock input l cmos/ttl clock input to the serial configuration shift registers 27 2 s_data input l cmos/ttl data input to the serial configuration shift registers 28 3 s_load input l cmos/ttl load input, which latches the contents of the shift, regis- ters. the latches will be transparent when this signal is high; thus, the data must be stable on the high ? to ? low transition of s_load for proper operation.
NBC124XXEVB/d http://onsemi.com 7 table 4. nbc12430 pin description pin open pin 28 ? plcc 32 ? tqfp pin name i/o open pin default type function 1 4 pll_vcc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 5 pll_vcc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 2 6 fref_ext input l external pll reference frequency 3 7 xtal_sel input h selects between the crystal and the fref_ext source for the pll 4 8 xtal1 input analog crystal oscillator interface 5 9 xtal2 input analog crystal oscillator interface 6 10 oe input h cmos/ttl active high output enable. the enable is synchronous to the output clock to eliminate the possibility of runt pulses on the f out outputs. 7 11 p_load input h cmos/ttl parallel configuration control input. this pin loads the con- figuration latches with the contents of the parallel inputs. the latches will be transparent when the signal is low; there- fore, the parallel data must be stable on the low ? to ? high transition of p_load for proper operation. 8 12 m0 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. m0 is the lsb. 9 13 m1 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 10 14 m2 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 11 15 m3 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 16 nc h no connect 12 17 m4 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 13 18 m5 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 14 19 m6 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 15 20 m7 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 16 21 m8 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. m8 is the msb. 17 22 n0 input h cmos/ttl output divider input. used to configure the output divider modules. sampled on the low ? to ? high transition of p_load. 18 23 n1 input h cmos/ttl output divider input. used to configure the output divider modules. sampled on the low ? to ? high transition of p_load. 24 nc no connect 19 25 gnd supply supply ground negative power supply (gnd) 20 26 test output cmos/ttl test and device diagnostics output; function is determined by serial configuration bits t[2:0]. 21 27 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 28 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 22 29 gnd supply supply ground negative power supply (gnd) 23 30 f out output pecl differential clock output 24 31 f out output pecl differential clock output 25 32 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 26 1 s_clock input l cmos/ttl clock input to the serial configuration shift registers 27 2 s_data input l cmos/ttl data input to the serial configuration shift registers 28 3 s_load input l cmos/ttl load input, which latches the contents of the shift, registers. the latches will be transparent when this signal is high; thus, the data must be stable on the high ? to ? low transition of s_load for proper operation.
NBC124XXEVB/d http://onsemi.com 8 table 5. nbc12439 pin description pin # pin # open pin 28 ? plcc 32 ? tqfp pin name i/o open pin default type function 1 4 pll_vcc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 5 pll_v cc supply supply v cc positive supply for the pll and is connected to +3.3 v or +5.0 v. 2 6 pwr_do wn input l forces the f out outputs to synchronously reduce its fre- quency by a factor of 16 3 7 fref_ext input l external pll reference frequency 4 8 xtal1 input analog crystal oscillator interface 5 9 xtal2 input analog crystal oscillator interface 6 10 oe input h cmos/ttl active high output enable. the enable is synchronous to the output clock to eliminate the possibility of runt pulses on the f out outputs. 7 11 p_load input h cmos/ttl parallel configuration control input. this pin loads the configuration latches with the contents of the parallel inputs. the latches will be transparent when the signal is low; therefore, the parallel data must be stable on the low ? to ? high transition of p_load for proper operation. 8 12 m0 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. m0 is the lsb. 9 13 m1 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 10 14 m2 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 11 15 m3 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 16 nc h no connect 12 17 m4 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 13 18 m5 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 14 19 m6 input h cmos/ttl used to configure the pll loop divider. sampled on the low ? to ? high transition of p_load. 15 20 xtal_sel input h cmos/ttl selects between the crystal and the fref_ext source for the pll 16 21 nc no connect 17 22 n0 input h cmos/ttl output divider input. used to configure the output divider modulus. sampled on the low ? to ? high transition of p_load. 18 23 n1 input h cmos/ttl output divider input. used to configure the output divider modulus. sampled on the low ? to ? high transition of p_load. 24 nc no connect 19 25 gnd supply supply ground negative power supply (gnd) 20 26 test output cmos/ttl test and device diagnostics output; function is determined by serial configuration bits t[2:0]. 21 27 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 28 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 22 29 gnd supply supply ground negative power supply (gnd) 23 30 f out output pecl differential clock output 24 31 f out output pecl differential clock output 25 32 v cc supply supply v cc positive supply for the internal logic and output buffers, and is connected to +3.3 v or +5.0 v. 26 1 s_clock input l cmos/ttl clock input to the serial configuration shift registers 27 2 s_data input l cmos/ttl data input to the serial configuration shift registers 28 3 s_load input l cmos/ttl load input, which latches the contents of the shift, regis- ters. the latches will be transparent when this signal is high; thus, the data must be stable on the high ? to ? low transition of s_load for proper operation.
NBC124XXEVB/d http://onsemi.com 9 table 6. nbc12429/ 12430/ 12439 package pin description pkg pin # pkg pin # 28 ? plcc 12429 12430 12439 32 ? lqfp 12429 12430 12439 1 vcc ? pll vcc ? pll vcc ? pll 1 sclock sclock sclock 2 nc fref_ext pwr_down 2 sdata sdata sdata 3 nc xtal_sel fref_ext 3 sload sload sload 4 xtal1 xtal1 xtal1 4 vcc_pll vcc_pll vcc_pll 5 xtal2 xtal2 xtal2 5 vcc_pll vcc_pll vcc_pll 6 oe oe oe 6 nc fref_ext pwr_down 7 p_load p_load p_load 7 nc xtal_sel fref_ext 8 m0 m0 m0 8 xtal1 xtal1 xtal1 9 m1 m1 m1 9 xtal2 xtal2 xtal2 10 m2 m2 m2 10 oe oe oe 11 m3 m3 m3 11 p_load p_load p_load 12 m4 m4 m4 12 m0 m0 m0 13 m5 m5 m5 13 m1 m1 m1 14 m6 m6 m6 14 m2 m2 m2 15 m7 m7 xtal_sel 15 m3 m3 m2 16 m8 m8 nc 16 nc nc nc 17 n0 n0 n0 17 m4 m4 m4 18 n1 n1 n1 18 m5 m5 m5 19 gnd gnd gnd 19 m6 m6 m6 20 test test test 20 m7 m7 xtal_sel 21 v cc v cc v cc 21 m8 m8 nc 22 gnd gnd gnd 22 n0 n0 n0 23 f out f out f out 23 n1 n1 n1 24 f out f out f out 24 nc nc nc 25 v cc v cc v cc 25 gnd gnd gnd 26 sclock sclock sclock 26 test test test 27 sdata sdata sdata 27 v cc v cc v cc 28 sload sload sload 28 v cc v cc v cc 29 gnd gnd gnd 30 f out f out f out 31 f out f out f out 32 v cc v cc v cc
NBC124XXEVB/d http://onsemi.com 10 table 7. bill of material component description digikey # qty vendor pn connector sma jack, edge mount, johnson comp inc. #142 ? 0701 ? 801 j502 ? nd 4 142 ? 0701 ? 801 capacitor chip, 0.010 f, 0805, avx #08055c103kat2a 478 ? 1383 ? 1 ? nd 7 08055c103kat2a capacitor chip, 0.1 f, 0805, panasonic #ecj ? 2yb1h104k pcc1840ct ? nd 2 ecj ? 2yb1h104k capacitor chip, 22 f, tant ?d?, kemet, t494d226k016as 399 ? 1782 ? 1 ? nd 3 t494d226k016as header double row, male, sullens, #ptc18daan s2012 ? 18 ? nd 1 ptc18daan resistor chip, 330 , 0805, panasonic #erj ? 6geyj331v p330act ? nd 11 erj ? 6geyj331v resistor chip, 13.3 , 0805, panasonic #erj ? 6enf13r3v p13.3cct ? nd 1 erj ? 6enf13r3v switch spst, gull, sealed, grayhill #90hbw02p gh1291 ? nd 1 90hbw02p switch spdt, toggle, 4 stations, grayhill #76stc04 3 76stc04 switch spst, momentary, push button, omron #b3s ? 1002 sw416 ? nd 1 b3s ? 1002 led diffused, amber, lumex #ssl ? lx2573ad 67 ? 1045 ? nd 2 ssl ? lx2573ad led diffused, green, lumex #ssl ? lx2573gd 67 ? 1046 ? nd 9 ssl ? lx2573gd pin recepicle (for through ? hole crystal), mill ? max #m0462 ? 0 ? 15 ? 15 ? 11 ? 14 ? 04 ? 0 2 crystal 16.000 mhz, series through ? hole, ecliptek #ecx ? 6142 ? 16.000m surface mount, ecliptek #ecx ? 6143 ? 16.000m 1 ecx ? 6142 ? 16.000m ecx ? 6143 ? 16.000m
NBC124XXEVB/d http://onsemi.com 11 11338.sch ? 1 ? thu feb 06 07:08:11 2003
NBC124XXEVB/d http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NBC124XXEVB/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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