PM7339 pmc-sierra,inc. quad cell delineation block device s/uni?-cdb pmc-2000367 (r4) proprietary and confidential to pmc - sierra, inc., and for its customers ? internal use ? copyright pmc - sierra, inc. 2001 features quad cell delineation block operating up to a maximum rate of 52 mbit/s. provides a utopia level 2- compatible atm-phy interface. implements the physical layer convergence protocol (plcp) for ds1 transmission systems according to the atm forum user network interface specification and ansi ta-tsy- 000773, ta-tsy-000772, and e1 transmission systems according to the etsi 300-269 and etsi 300-270. supports smds plcp and atm direct mapping into various rate transmission systems in the following formats: e1 (2.048 mbit/s) in crc-4 and pcm30; t1 (1.544 mbit/s) in esf and sf; arbitrary cell rate (up to 52 mbit/s) with atm direct mapping only. uses the pmc-sierra pm4341 t1xc, pm4344 tquad, pm6341 e1xc, and pm6344 equad t1 and e1 framer/line interface chips for ds-1 and e1 applications. provides programmable pseudo- random test pattern generation, detection and analysis features. provides performance monitoring counters suitable for accumulation periods of up to 1 second. receiver section provides plcp frame synchronization, path overhead extraction and cell extraction for ds1 and e1 plcp formatted streams. provides a 50 mhz 8-bit wide or 16-bit wide utopia fifo buffer in the receive path with parity support, and multi-phy (level 2) control signals. provides atm framing using cell delineation. atm cell delineation may optionally be disabled to allow all cell bytes to pass regardless of cell delineation status. provides cell descrambling, header check sequence (hcs) error detection, idle cell filtering, header descrambling (for use with ppp packets), and accumulates the number of received idle cells, the number of received cells written to the fifo and the number of hcs errors. provides a four cell fifo for rate decoupling between the line, and a higher layer processing entity. fifo latency may be reduced by changing the number of operational cell fifos. provides programmable pseudo- random test-sequence detection and analysis features. transmitter section provides a 50 mhz 8-bit wide or 16-bit wide utopia fifo buffer in the transmit path with parity support and multi-phy (level 2) control signals. provides optional atm cell scrambling, header scrambling (for use with ppp packets), hcs generation/insertion, programmable idle cell insertion, diagnostics features and accumulates transmitted cells read from the fifo. cppm plcp/cell perf. monitor prgd ber tester rxcp_50 rx cell processor tpohins[4:1] tpoh[4:1] tiohm[4:1] ticlk[4:1] tpohclk[4:1] tpohfp[4:1] ref8ki lcd [4:1] rpoh [4:1] rpohfp [4:1] rpohclk [4:1] frmstat [4:1] tclk[4:1] tdato[4:1] tohm[4:1] jtag test access port tdo tck tdi tms trstb d [7:0] intb a [10:0] rstb ale csb wrb rdb microprocessor interface splt transmit atm and plcp framer txcp_50 tx cell processor txff tx 4 cell fifo rxff rx 4 cell fifo atm/splr receive atm and plcp framer rclk[4:1] rdati[4:1] rohm[4:1] dtca[4:1] tca rca rsoc rprty rdat[15:0] d r c a [ 4 : 1 ] tdat[15:0] tprty tsoc tadr[4:0] tenb tfclk phy_adr[2:0] atm8 rfclk renb radr[4:0] system i/f block diagram
head office: pmc-sierra, inc. 8555 baxter place burnaby, b.c. v5a 4v7 canada tel: 604.415.6000 fax: 604.415.6200 quad cell delineation block device to order documentation, send email to: document@pmc-sierra.com or contact the head office, attn: document coordinator all product documentation is available on our web site at: http://www.pmc-sierra.com for corporate information, send email to: info@pmc-sierra.com pmc-2000367 (r4) ? copyright pmc-sierra, inc. 2001. all rights reserved. s/uni is a registered trademark of pmc-sierra, inc. proprietary and confidential to pmc-sierra, inc., and for its customers ? internal use PM7339 s/uni ? -cdb provides a four cell fifo for rate decoupling between the line and a higher layer processing entity. fifo latency may be reduced by changing the number of operational cell fifos. provides an 8 khz reference input for locking the transmit plcp frame rate to an externally applied frame reference. provides programmable pseudo- random test sequence generation (up to 2 32 -1 bit length sequences conforming to itu-t o.151 standards). diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10 -1 to 10 -7 . loopback features provides for diagnostic loopbacks and line loopbacks. general provides an 8-bit microprocessor interface for configuration, control and status monitoring. provides a standard five signal p1149.1 jtag test port for boundary scan board test purposes. low power 3.3 v cmos technology with 5 v tolerant inputs. available in a high density 256-pin sbga package (27 mm x 27 mm). applications atm switches, multiplexers, and routers. smds switches, multiplexers and routers. dslam. integrated access devices (iad). typical application 8 port xdsl card xdsl modem xdsl modem xdsl modem xdsl modem atm switch core switch fabric pm7322 rcmp-800 egress device utopia bus xdsl modem xdsl modem xdsl modem xdsl modem PM7339 s/uni-cdb oc-3 line cards pm5346 s/uni-lite pm7348 s/uni- dual pm5347 s/uni-plus access side uplink side PM7339 s/uni-cdb utopia bus atm based dslam equipment
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