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| Datasheet File OCR Text: |
| loop filter disable lock detect phase freq detector pecl vcso vcxo monitor frequency divider microprocessor frequency divider input frequency frequency select ! " # $%& &'((&) *&*+, -&+,$ . / 0 123&23&(-24 %#567 ) / 8!9.:.09.:;:.#"<- #!%# ,! ) '((& '((& 6&=- *&1*- /9 9 5 / >? @=? 9 5 / ><6? @-? $+ / 4 >-+, >*&*+, $ -+, *&*+, " / 4 > ! > ! $ $ 5 .# 9 %(a ab'((&) c 4 %$ $ ,) " # $9 / 7 $ % 14(4*4*!46 8!9 ) / * : / ,: -& *&* + + -&(- *&6'- +, +, " " 1*- 11- ( ( 0 0 d"8 ! <<< <<< 1--&-( <<< 5 . # 6 6- $ -- a * 0 5 @.<6 + e <* 0; 7 , , # $ 9 , f f $ &9 $ $ 1 = , f f / g, h / &9 h 7 <1i(& 9 <* 7 $ , 7 1 ,= $4 '((& , '''&-16* , $ '((& & 9 / #! ,/ 7 1c ,<1i(& 9 2" # $9 / 7 $2 $, g / <* / , & 0 3 4 $ , 7 '((& j ( & 9 <* / , j6 g . //. $ , & (- + b@(-? + b@(-? + + <1&i- + <1&'* + + + <&i + <&=- + c 4 %1( () &(* 6i.-1 ! 1& 9 4 c5<(-*<5! -&'&(&1&( &1 ,k 1 = d"8 " # $%) 1 d"8 $" # $%) ( : % ) : /212, ,, & /22, , & * % ) .+l g / , ,, 4 ,7 m&*+ ,n*&+ *&*g m&-+ ,n6&-+ -g &" $ $7 / g / 3 , & 6 <<<< / - 8 8 ' c8: c , = : 7 %" ) # /> 7 , /22> , 7 , 9 %) i 9 $ %) 1 8 8 11 # & f o > $# $ f 1o > , $# $%: !3 ,+,,) 1( 8 8 1* 8 8 16 c8: c , 1- + -+, *&*+, 1' '&*- %&(-) *&1 %&1-) 1=&= %&=) (&*( %&) (&-6 %&1) (-&6 %1&) 1&=* %&') 1&=* %&') 1&1 %&6) %) < / ' i & b16? 1'? 6 ' & bm1*? 9 <* , 7 7h , g &8 !08 , , , & 9 <* 7 , / , , , /&9 // , 7g & 9 <* $7 , 4 , , 7 , g , & &i %&*-) 1=&= %&=) 1i&- %&=-) (&-6 %&1) 1&i1 %&=-) *&6 %&1() i&-* %&*=-) %) 9 %? ) 9 , , , g , <* 3 $&9 $ 1a $ 7 &9 $ ,, , $ 7 $ , << / , , << & 0 / $ 7 , / , , g 4 ,7 g, 3 , / %!:), / ,/ , /&+" $ <7,$ , %k) , / ,<, g , %:) !:< 7 $ / , , / g & !: g / , , , , , , & 0 / , $< , , , 7 , , :4 , ,k % >1- 4 > 1) , $ , , 7 , & 9 k !: , , 7 , 7$/ & , 9 , $ 1&- &(--f , 1 9 CS-300-dfc-p2xxp2 622.08 mhz in 622.08 mhz out CS-300-dfc-p2xxp2 622.08 mhz in 622.08 mhz out CS-300-dfc-p2xxp2 622.08 mhz in 622.08 mhz out CS-300-dfc-p2xxp2 622.08 mhz in 622.08 mhz out input frequency input select 0)'((& k)'''&-16* 1)'((& " / / " 1 : 0 0 1p9 '((& '((& k 1p9 '''&-16* '((& 0 , , , 73 , ,. & 9 h 7 / <*&# ,, 7 $ , # $& loop filter disable lock detect phase freq detector vcxo monitor frequency divider microprocessor frequency divider pecl vcso + q %# ) %(4=41-) %i) %1') q q loop filter disable lock detect phase freq detector pecl vcso vcxo monitor frequency divider microprocessor frequency divider input frequency frequency select %1) - - 0 , , , 73 , ,. &9 h 7 / <*&# ,, 7 $ , # $& +" / $ , / 7$ r1#4&1# , 1# ,7 $ & 1p; , g 7 s ! " #$ ! % & '() * '()+ , # #$ - " .+/ (p $, <* s "00 " " 1 ## " #$ + *p" $ 4 $ (, s 0 $ ""! 0 "2 % % % % ## " #$ + 0 "23 " % ! 3 " # + 6p; <*s 2 4 0 % " " # " #$ !+ 5 4 0 % # ! & + -p; $ $ <* s " 5 " 4 6 " ! "% "" + 5# 2 - " ""! 0! " 7 "#0 + 2 # 0! $ + % ! "% ""! - %! # # ! ""! + 83 0 9 ' ' : 0" 4 ; $ ! < = CS-300-dfc-p2xxp2 622.08 mhz in 622.08 mhz out " $ ! > > ?" @ > 4 5 " $ ! - = - - " $ + $" # $ ,9 a9/ # $ 07g q " , 7 , $ 7 & , $" # $ ,1 a9/ # $ 07g # $ $ ll 7& q" , 7 , $ 7 & " , $ $ 7 / $ $& <*<: < (ll ( $+ / >-+,@.<-a >*&*+,@.<-a # $<1 ,'1 9/ # $ 07g q $ 7 g 7 $ < , , & 9$ > & ! 9 5 / > @= ><6 @- note: the primary input frequency must be less than secondary input frequency. q0 7 7 / , & %%%+- + 0 1& 9 1(& 1 1*& 1-& 9 1'&*6 b 1i&66 c (& 1 (&161' (&6 9 ((&(1=1 b ('& (=& 9 (i&6i1( b *(&=' ( *=&-' (9 *& (b 66&6*6* :1 66&=*' : -1&6 :9 '1&66 :b '-&-*' :c ==&=' d1 =&1(- d =&'6*( db (&i66 dc 11(& >1 116& > 1(-& >9 1*i&('6 >b 1--&-( '1 1-'&(- ' 1'1&1*( '9 1''&'(' 'b 1'=&**1' 1 1'&6= '((& 1 '(-& '66&-*1* 9 '''&-16* b ''i&1(1 a1 ''i&*('' a 'i&-'i( a9 =1&i6' 1 =1i&=*66 ===&' 9 8 ," # ee " # , # , '(6&=6 c '(=&*(i' * *11&6 & '=(&1'(= ab =6&1(- d& =6&(- d* ''i&'6( a& 'i*&6* ac |
Price & Availability of CS-300
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