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vga/svga/xga digital data serial transmitter features 1 chip transmitter for serial transmission of 18bit color vga/svga/xga picture on chip differential cable driver ttl/cmos compatible interface support 1 pixel/shiftclock mode & 2 pixel/shiftclock mode +3.3v single power supply low power consumption 80pin plastic qfp package (body size: 14mm 14mm) block digagram & pin out ?1 e97913a1z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXB1451Q 80 pin qfp (plastic) v ee t blu1 (3) blu1 (2) blu1 (1) blu1 (0) grn1 (5) grn1 (4) grn1 (3) grn1 (2) v cc t v ee t grn1 (1) grn1 (0) red1 (5) red1 (4) red1 (3) red1 (2) red1 (1) red1 (0) v cc t lpfb lpfa v ee s v ee a v cc a testsb v cc e sdatan sdatap v ee e refreq idle v cc t red0 (0) red0 (1) red0 (2) red0 (3) red0 (4) red0 (5) v ee t v cc t blu0 (0) blu0 (1) blu0 (2) v ee g v cc g blu0 (3) blu0 (4) blu0 (5) v ee t v cc t grn0 (0) grn0 (1) grn0 (2) grn0 (3) grn0 (4) grn0 (5) v ee g v cc g v ee t v ee g testdt panel1 panel0 ckmode cntl3 cntl2 cntl1 v cc g v cc t v ee t sftclk hsync vsync v ee g v cc g cntl0 blu1 (5) blu1 (4) v cc t 10 11 21 30 1 encoder pll parallel to serial converter cable driver 40 39 38 37 36 35 34 31 32 33 22 23 24 25 26 27 28 29 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 48 49 50 51 52 53 54 55 56 57 58 59 60 41 42 43 44 45 46 47 fig. 1. block diagram & pin out
2 CXB1451Q pin list power/ground pin name v cc t v ee t v cc g v ee g v cc e v ee e v cc a v ee a v ee s 10, 20, 30, 40, 48, 70, 80 1, 11, 21, 31, 41, 71 25, 32, 69, 76 26, 33, 68, 75 54 51 56 57 58 ttl power surpply , should be connected to 3.3v 5% ttl ground, connected to 0v logical core power surpply, connected to 3.3v 5% logical core ground, connected to 0v serial driver power surpply, connected to 3.3v 5% serial driver ground, connected to 0v analog power surpply, connected to 3.3v 5% analog ground, connected to 0v analog substrate, connected to 0v pin number descriptions digital signals pin name sftclk red1 (5 to 0) grn1 (5 to 0) blu1 (5 to 0) red0 (5 to 0) grn0 (5 to 0) blu0 (5 to 0) hsync vsync cntl (3 to 0) panel (1, 0) ckmode idle sdatap/n refreq 72 14, 15, 16, 17, 18, 19 6, 7, 8, 9, 12, 13 78, 79, 2, 3, 4, 5 42, 43, 44, 45, 46, 47 34, 35, 36, 37, 38, 39 22, 23, 24, 27, 28, 29 73 74 65, 66, 67, 77 62, 63 64 49 52, 53 50 ttl in ttl in ttl in ttl in ttl in ttl in ttl in ttl in ttl in tx ttl out shift clock, for the data fetch at rising or falling edge pixel data input in 1 pixcel/sftclk mode 2nd pixel data input in 2 pixel/sftclk mode ignored in 1 pixcel/sftclk mode 1st pixel data input in 2 pixel/sftclk mode hsync data vsync data control data panel mode select switch clock mode select switch idle mode select switch serial output & refclk request input refclk request detect flag pin number type descriptions special pin name 55, 61 59, 60 sftclk polarity / test function control external loop filter pin number descriptions testsb/dt lpfa/b
3 CXB1451Q equivalent i/o circuit 300 6k 6k v cc t ttl-in v ee t v cc g v ee g 3k v cc t ttl-out v ee t (a) ttl input equivalent circuit (b) ttl output equivalent circuit v cc a lpfa lpfb v ee a v cc e sdatap sdatan v ee e (c) lpfa/b equivalent circuit (d) sdatap/n equivalent circuit v cc a testdt v ee a v cc g v ee g v cc t testsb v ee t v cc g v ee g (e) testdt equivalent circuit (f) testsb equivalent circuit
4 CXB1451Q electrical characteristics tab. 1. absolute maximum rating description power supply voltage ttl dc input voltage ttl output current (high) ttl output current (low) serial output pin voltage ambient temperature storage temperature v cc v i _t i oh _t i ol _t vsdout ta tstg 0.3 0.5 20 0 0.5 55 65 4 5.5 0 20 v cc + 0.5 70 150 v v ma ' ma v c c under bias symbol min. typ. max. unit comments tab. 2. recommended operating conditions description power supply voltage (include v cc t5) ambient temperature v cc ta 3.135 0 3.3 3.465 70 v c symbol min. typ. max. unit comments tab. 3. dc characteristics (under the recommended conditons. see tab. 2) description input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) output high voltage (ttl) output low voltage (ttl) output high current (sdata) output low current (sdata) input high voltage (sdata) input low voltage (sdata) supply current v ih _t v il _t i ih _t i il _t v oh _t v ol _t i oh _sd i ol _sd v ih _sd v il _sd i cc 2 0.5 400 2.3 0.1 14.7 v cc 0.6 165 175 0 16 215 225 5.5 0.8 20 0.4 +0.1 17.3 v cc 0.7 265 275 v v a a v v ma ma v v ma ma v in = v cc v in = 0 i oh = 0.2ma i ol = 4ma see fig. 2 common mode voltage xga, outputs open svga/vga, outputs open symbol min. typ. max. unit conditions
5 CXB1451Q v cc a/g/e/t v ee a/g/e/t v cc CXB1451Q a 52 53 55 61 a fig. 2. i oh _sd and i ol _sd dc measurement tab. 4. ac characteristics (under the recommended conditons. see tab. 5) description input ttl rise time input ttl fall time sftclk frequency sftclk duty factor pixel/sync/cntl setup to sftclk pixel/sync/cntl hold to sftclk sdata rise time sdata fall time clock mode assert time clock mode deassert time idle mode assert time idle mode deassert time pll lockin time tir tir fsftclk dsftclk tsetup thold tor tof taclk tdclk taidle tdidle tlockin 0.7 0.7 20.0 10.0 38.0 19.0 60.0 30.0 40 4.0 1.0 25.0 12.5 40.0 20.0 65.0 32.5 130 10 150 350 0.1 4.8 4.8 28.0 14.0 48.0 24.0 68.0 34.0 60 400 400 ns ns mhz mhz mhz mhz mhz mhz % ns ns ps ps ns ns ns ns ms 0.8v to 2.0v 2.0v to 0.8v vga, 1 pixel/sftclk mode vga, 2 pixel/sftclk mode svga, 1 pixel/sftclk mode svga, 2 pixel/sftclk mode xga, 1 pixel/sftclk mode xga, 2 pixel/sftclk mode vth = 1.4v xga 1 pixel/sftclk mode @65mhz see fig. 4 20 to 80%, c l = 2pf see fig. 3 symbol min. typ. max. unit conditions v cc a/g/e/t v ee a/g/e/t v cc CXB1451Q 52 53 fet probe sampling oscillo- scope 72 ttl clock 51 51 100 fig. 3. sdata waveform measurement
6 CXB1451Q timing chart tif setup/hold time is refered from fall edge in testsb/dt = gnd or open rise edge in testsb/dt=v cc tir v ih _t vth v il _t dsftclk/fsftclk 1/fsftclk 2.0v 0.8v sftclk redxx grnxx bluxx h/vsync cntlx v ih _t v il _t thold tsetup 2.0v 0.8v tif tir fig. 5. serial output timing 100% 0% tor 80% 20% tof sdatap sdatan fig. 6. refclk request timing sdatap sdatan refrq signal from cxb1452q refreq tdclk taclk nrz data reference clock fig. 7. idle mode timing idle sdatap sdatan tdidle nrz data taidle fig. 4. ttl input timing
7 CXB1451Q operation mode CXB1451Q supports 3 panel mode and 2 clock mode switched by the panel (1, 0) and ckmode pin according to the tab. 5 & 6. the supporting clock rate are summarized in tab. 7. these pins are open high ttl inputs. tab. 5. panel mode select panel1 l l h h l h l h vga (640 480) 18bit color svga (800 600) 18bit color xga (1024 768) 18bit color not supported panel0 supporting panel size & color tab. 6. clock mode select ckmode l h 2 pixel/shiftclock (2ppc) 1 pixel/shiftclock (1ppc) supporting clock mode tab. 7. operation mode panel mode vga svga xga 1 pixel/sftclk 2 pixel/sftclk 1 pixel/sftclk 2 pixel/sftclk 1 pixel/sftclk 2 pixel/sftclk 18bit 18bit 18bit 18bit 18bit 18bit 25mhz 12.5mhz 40mhz 20mhz 65mhz 32.5mhz 25mhz 25mhz 40mhz 40mhz 65mhz 65mhz 600mbps 600mbps 960mbps 960mbps 1560mbps 1560mbps clock mode color shift clock dot clock serial rate testsb/testdt pins select the trigger edge of sftclk and test mode according to tab. 8. tab. 8. sftclk polarity & test mode testdt gnd open v cc fabricator reserved test mode testsb gnd sdatap = h sdatan = l sdatap = l sdatan = h open v cc idle pin disable differential signal transmission from sdatap/n pins. it's open high ttl input. transmission is disabled when idle = high. transmitter operation trigger = falling edge trigger = rising edge
8 CXB1451Q applications CXB1451Q gvif transmitter is applied to the digital rgb signal transmittion for p/c with lcd monitor video on demand system monitoring system graphical controller projector digital tv monitor with gvif receiver, cxb1452q. red0/grn0/blu0 are active in 2pixel/shiftclock mode only CXB1451Q gvif transmitter stp or twin axial cxb1452q gvif receiver red1 (5 to 0) grn1 (5 to 0) blu1 (5 to 0) red0 (5 to 0) grn0 (5 to 0) blu0 (5 to 0) sync/cntl shiftclock 6 6 6 6 6 6 6 pll serial to parallel converter cable equalizer decoder 6 6 6 6 6 6 6 encoder parallel to serial converter cable driver pll red1 (5 to 0) grn1 (5 to 0) blu1 (5 to 0) red0 (5 to 0) grn0 (5 to 0) blu0 (5 to 0) sync/cntl shiftclock
9 CXB1451Q application cicuit (a) select sftclk polarity according to tab. 8 select panel resolution according to tab. 5 330 sw1 on : transmit data off : idle (1) chip resistor (1%) (2) chip capacitor (3) formed by the printed circuit pattern (l = 0.5 to 1.0mm/w = 0.5 to 1.0mm) 51 (1) 51 (1) 0.1 (2) 1.5k (1) 1.5k (1) 680p (2) 0.1 (2) 0.1 to 0.4n (3) 0.1 to 0.4n (3) 0.1 to 0.4n (3) v cc 0.1 to 0.4n (3) e 1k sw0 sw2 330 sw3 330 e t t t e e e t t e 0.1 (2) 0.1 (2) t 543210 msb lsb blue data sftclk hsync vsync de 543210 msb lsb green data 543210 msb lsb red data t 0.1 (2) e 0.1 (2) t e t 0.1 (2) differential cable connector v ee t blu1 (3) blu1 (2) blu1 (1) blu1 (0) grn1 (5) grn1 (4) grn1 (3) grn1 (2) v cc t v ee t grn1 (1) grn1 (0) red1 (5) red1 (4) red1 (3) red1 (2) red1 (1) red1 (0) v cc t lpfb lpfa v ee s v ee a v cc a testsb v cc e sdatan sdatap v ee e refreq idle v cc t red0 (0) red0 (1) red0 (2) red0 (3) red0 (4) red0 (5) v ee t v cc t blu0 (0) blu0 (1) blu0 (2) v ee g v cc g blu0 (3) blu0 (4) blu0 (5) v ee t v cc t grn0 (0) grn0 (1) grn0 (2) grn0 (3) grn0 (4) grn0 (5) v ee g v cc g v ee t v ee g testdt panel1 panel0 ckmode cntl3 cntl2 cntl1 v cc g v cc t v ee t sftclk hsync vsync v ee g v cc g cntl0 blu1 (5) blu1 (4) v cc t 48 49 50 51 52 53 54 55 56 57 58 59 60 10 11 21 30 1 41 42 43 44 45 46 47 40 39 38 37 36 35 34 31 32 33 22 23 24 25 26 27 28 29 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 78 79 80 33 16v 0.01 (2) 77 clock mode: 1 pixel/sftclk (1ppc) picture sync: h/v sync & de color depth: 18bit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXB1451Q application cicuit (b) select sftclk polarity according to tab. 8 select panel resolution according to tab. 5 330 sw1 on : transmit data off : idle (1) chip resistor (1%) (2) chip capacitor (3) formed by the printed circuit pattern (l = 0.5 to 1.0mm/w = 0.5 to 1.0mm) 51 (1) 51 (1) 0.1 (2) 1.5k (1) 1.5k (1) 680p (2) 0.1 (2) 0.1 to 0.4n (3) 0.1 to 0.4n (3) 0.1 to 0.4n (3) v cc 0.1 to 0.4n (3) e 0.01 (2) 1k sw0 sw2 330 sw3 330 e t t e e e t t e 0.1 (2) 0.1 (2) t 3210 msb lsb even blue data sftclk enable 3210 msb lsb even green data 32 1 0 msb lsb even red data t 0.1 (2) e 0.1 (2) t e t 0.1 (2) differential cable connector 33 16v 32 1 0 msb lsb odd blue data 32 1 0 msb lsb odd green data 32 1 0 msb lsb odd red data odd pixel transmission order of the pixel even pixel v ee t blu1 (3) blu1 (2) blu1 (1) blu1 (0) grn1 (5) grn1 (4) grn1 (3) grn1 (2) v cc t v ee t grn1 (1) grn1 (0) red1 (5) red1 (4) red1 (3) red1 (2) red1 (1) red1 (0) v cc t lpfb lpfa v ee s v ee a v cc a testsb v cc e sdatan sdatap v ee e refreq idle v cc t red0 (0) red0 (1) red0 (2) red0 (3) red0 (4) red0 (5) v ee t v cc t blu0 (0) blu0 (1) blu0 (2) v ee g v cc g blu0 (3) blu0 (4) blu0 (5) v ee t v cc t grn0 (0) grn0 (1) grn0 (2) grn0 (3) grn0 (4) grn0 (5) v ee g v cc g v ee t v ee g testdt panel1 panel0 ckmode cntl3 cntl2 cntl1 v cc g v cc t v ee t sftclk hsync vsync v ee g v cc g cntl0 blu1 (5) blu1 (4) v cc t 48 49 50 51 52 53 54 55 56 57 58 59 60 10 11 21 30 1 41 42 43 44 45 46 47 40 39 38 37 36 35 34 31 32 33 22 23 24 25 26 27 28 29 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 70 69 68 63 64 65 66 61 62 71 72 73 74 75 76 78 79 80 67 77 clock mode: 2 pixel/sftclk picture sync: enable only color depth: 12bit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXB1451Q recommended printed circuit board structure aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa l1: cu plate (18m) + solder coat l2: cu plate (36m) i1: adhesive sheet (0.3mm 0.09mm) i2: fiber-glass epoxy core (0.8mm) l3: cu plate (36m) i3: adhesive sheet (0.3mm) l4: cu plate (18m) + solder coat recommended printed circuit board pattern sdatap/sdatan pins to the connector path w = 0.50mm (z0 = 50 ? ) other path w = 0.25mm power and special signal routing example aa aa aa a a a a testdt panel1 panel0 ckmode cntl3 cntl2 cntl1 v ee g v cc g v cc t v ee t sftclk hsync vsync v ee g v cc g cntl0 blu1 (5) blu1 (4) v cc t v ee t blu1 (3) blu1 (2) blu1 (1) blu1 (0) grn1 (5) grn1 (4) grn1 (3) grn1 (2) v cc t v ee t grn1 (1) grn1 (0) red1 (5) red1 (4) red1 (3) red1 (2) red1 (1) red1 (0) v cc t v cc t grn0 (0) grn0 (1) grn0 (2) grn0 (3) grn0 (4) grn0 (5) v ee g v cc g v ee t v cc t blu0 (0) blu0 (1) blu0 (2) v ee g v cc g blu0 (3) blu0 (4) blu0 (5) v ee t lpfb lpfa v ee s v ee a v cc a testsb v cc e sdatan sdatap v ee e refreq idle v cc t red0 (0) red0 (1) red0 (2) red0 (3) red0 (4) red0 (5) v ee t 40 21 80 61 60 41 20 1 g g g e e eg g e e g g e g e g g t ttt tttt l2 doesn't have plane in this area 0.5mm through hole to the gnd plane (l2) through hole to the v cc e/v cc g plane (l3) through hole to the v cc t plane (l3) chip capacitor chip resistor e t aa g
12 CXB1451Q 40.1820ns 40.6820ns 41.1820ns ch. 1 = 100.0mvolts/div timebase = 100ps/div offset = 92.00mvolts delay = 40.6820ns center 32.50mhz span 10.00mhz ref lvl 0dbm vbw 100khz swp 50.0ms d atten 10db rl 0dbm 10db/ rbw 100khz 1.56gb/s sdatap output waveform xga 2ppc mode 32.5mhz sftclk jitter tolerance: example power spectrum available for transmission
13 CXB1451Q package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin 42 / copper alloy qfp-80p-l03 p-qfp80-14x14-0.65 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 ?0.1 + 0.4 b 0? to 10? 0.5 0.2 0.1 ?0.1 + 0.15 (15.0) 1.5 ?0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.24 0.1 0.65 b = 0.3 ?0.1 ( 0.3 ) (0.127) + 0.15 0.127 ?0.05 + 0.1 detail a : solder a solder plating sony corporation lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. kokubu ass'y sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin 42 / copper alloy qfp-80p-l03 p-qfp80-14x14-0.65 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 0.1 + 0.4 b 0 ? to 10 ? 0.5 0.2 0.1 0.1 + 0.15 (15.0) 1.5 0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.24 0.1 0.65 b = 0.3 0.1 ( 0.3 ) (0.127) + 0.15 0.127 0.05 + 0.1 detail a : solder a solder plating

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