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? semiconductor components industries, llc, 2001 march, 2001 rev. 4 1 publication order number: cs52313/d cs5231-3 500 ma, 3.3 v linear regulator with auxiliary control the cs52313 combines a threeterminal linear regulator with circuitry controlling an external pfet transistor thus managing two input supplies. the part provides a 3.3 v regulated output either from the main 5.0 v supply or a 3.3 v auxiliary that switches on when the 5.0 v supply is not present. this delivers constant, uninterrupted power to the load. the cs52313 meets intel's ainstantly availableo power requirements which follows from the aadvanced configuration and power interfaceo (acpi) standards developed by intel, microsoft and toshiba. the cs52313 linear regulator provides a fixed 3.3 v output at 500 ma with an overall accuracy of 2.0%. the internal npnpnp composite pass transistor provides a low dropout voltage and requires less supply current than a straight pnp design. full protection with both current limit and thermal shutdown is provided. designed for low reverse current, the ic prevents excessive current from flowing from v out to either v in or ground when the regulator input voltage is lower than the output voltage. the cs52313 can be used to provide power to an asic on a pci network interface card (nic). when the system enters a sleep state and the 5.0 v input drops below 4.4 v, the auxdrv control signal on the cs52313 is activated turning on the external pfet. this switches the supply source from the 5.0 v input to the 3.3 v input through the pfet, guaranteeing a constant 3.3 v output to the asic that is aglitch free.o the cs52313 is available in two package types: the 5lead d 2 pa k (to263) package and the 8lead soic 4leadfused (df) package. other applications include desktop computers, power supplies with multiple input sources and pcmcia/pci interface cards. features ? linear regulator 3.3 v 2.0% output voltage 3.0 ma quiescent current @ 500 ma fast transient response current limit protection thermal shutdown with hysteresis 450 m a reverse output current ? system power management auxiliary supply control aglitch freeo transition between two supplies ? internally fused leads in so8 package http://onsemi.com pin connections and marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information cs52313gdp5 d 2 pak* 50 units/rail cs52313gdpr5 d 2 pak* 750 tape & reel cs52313gdf8 so8 95 units/rail cs52313gdfr8 so8 2500 tape & reel so8 df suffix case 751 pin 1. no connect 2. v in 3. gnd 4. v out 5. auxdrv tab = gnd d 2 pak 5pin dp suffix case 936f cs52313 awlyww 1 1 5 v out v in 1 5231 alyw3 8 gnd gnd gnd gnd auxdrv nc 1 8 so8 d 2 pak 5pin * 5pin
cs52313 http://onsemi.com 2 thermal shutdown v in gnd 10 k w error amp current limit shutdown auxdrv internal bias v out figure 1. block diagram - + - + bandgap reference 50 k w v in uv comparator v ref absolute maximum ratings* rating value unit maximum operating junction temperature 150 c storage temperature range 65 to +150 c lead temperature soldering: reflow: (smd styles only) (note 1.) 230 peak c esd damage threshold (human body model) 2.0 kv 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. absolute maximum ratings pin name pin symbol v max v min i source i sink ic power input v in 14 v 0.3 v 100 ma internally limited output voltage v out 6.0 v 0.3 v internally limited 100 ma auxiliary drive output auxdrv 14 v 0.3 v 10 ma 50 ma ic ground gnd n/a n/a n/a n/a
cs52313 http://onsemi.com 3 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 v v cc < 6.0 v; c out 10 m f with esr < 1.0 w , i out = 10 ma; unless otherwise specified.) characteristic test conditions min typ max unit linear regulator output voltage 10 ma < i out < 500 ma. 3.234 ( 2%) 3.3 3.366 (+ 2%) v line regulation i out = 10ma; v in = 4.75 v to 6.0 v 1.0 5.0 mv load regulation v in = 5.0 v; i out = 10 ma to 500 ma 5.0 15 mv ground current i out = 10 ma i out = 500 ma 2.0 3.0 3.0 6.0 ma ma reverse current v in = 0 v, v out = 3.3 v 0.45 1.0 ma current limit 0 v < v out < 3.2 v 0.55 0.85 1.2 a thermal shutdown note 2. 150 180 210 c thermal shutdown hysteresis note 2. 25 c auxiliary drive upper v in threshold increase v in until regulator turns on and auxdrv drives high 4.35 4.5 4.65 v lower v in threshold decrease v in until regulator turns off and auxdrv drives low 4.25 4.4 4.55 v v in threshold hysteresis 75 100 125 mv output low voltage i auxdrv = 100 m a, 1.0 v < v in < 4.5 v 0.1 0.4 v output low peak voltage increase v in from 0v to 1.0 v. record peak auxdrv output voltage 0.65 0.9 v auxdrv current limit v auxdrv = 1.0 v; v in = 4.0 v 0.5 6.0 25 ma response time step v in from 5.0 v to 4.0 v, measure time for v auxdrv to drive low. note 1.0 10 m s pullup/down resistance v in = 0 v and v in > 4.7 v. 5.0 10 25 k w 2. guaranteed by design, not 100% production tested. thermal shutdown is 100% functionally tested at wafer probe. package pin description package lead # d 2 pak 5pin so8 lead symbol function 1 1 nc no connection. 2 4 v in input voltage. 3, tab 2, 3, 6, 7 gnd ground and ic substrate connection. 4 5 v out regulated output voltage. 5 8 auxdrv output used to control an auxiliary supply voltage. this lead is driven low if v in is less than 4.5 v, and is otherwise pulled up to v in through an internal 10 k w resistor.
cs52313 http://onsemi.com 4 typical performance characteristics figure 2. output voltage vs. junction temperature junction temperature ( c) 3.302 3.300 3.298 120 0 3.296 output voltage (v) 100 80 60 40 20 i out (a) 0 load regulation (mv) 0.2 1.2 1.0 0.8 0.6 0.4 0.2 0 0.4 figure 3. line regulation vs. i out over temperature i out (a) 0.8 0.0 load regulation (mv) 0.2 0.6 0.4 0.2 0.0 0.4 figure 4. load regulation vs. i out over temperature 125 c junction temperature ( c) 380 0 reverse current ( m a) 20 370 360 40 60 80 100 120 figure 5. reverse current vs. junction temperature figure 6. v out vs. i out over junction temperature figure 7. v in thresholds vs. junction temperature 1.0 1.2 i out (a) 0.0 v out (v) 0.2 3 2 1 0 0.4 0.6 0.8 1.0 junction temperature ( c) 4.52 4.50 4.48 4.46 120 0 4.38 v in threshold voltage (v) 100 80 60 40 20 4.44 4.42 4.40 v in turnon threshold v in turnoff threshold 27 c 0 c 125 c 27 c 0 c i out = 10 ma i out = 500 ma 27 c 125 c 0 c 140 390
cs52313 http://onsemi.com 5 figure 8. ground current vs. load current capacitance esr ( w ) 1000 6.0 0 10 capacitance ( m f) 5.0 4.0 3.0 2.0 1.0 100 figure 9. region of stable operation temperature ( c) 4.4 0 4.0 current limit (ma) 40 20 4.2 60 figure 10. auxdrv current limit vs. junction temperature load current (a) 0.0 ground current (ma) 0.2 2.2 2.0 1.8 1.6 0.4 t j = 0 c i gnd @ 0 c 2.4 2.6 4.6 4.8 5.0 80 100 120 140 time, 5.0 m s per division 3.2 10 v out 500 figure 11. transient response 3.3 3.4 i out (ma ) t j = 27 c i gnd @ 27 c t j = 125 c i gnd @ 125 c c in = 33 m f c out = 33 m f v in = 5.00 v stable region t j = 25 c 7.0 figure 12. application circuit 5.0 v pci c1 33 m f v in gnd auxdrv v out 3.3 v v aux c1 33 m f c3 33 m f m1 asic v dd * indicates pfet body diode cs52313
cs52313 http://onsemi.com 6 application information theory of operation the cs52313 is a fixed 3.3 v linear regulator that contains an auxiliary drive control feature. when v in is greater than the typical 4.5 v threshold, the ic functions as a linear regulator. it provides up to 500 ma of current to a load through a composite pnpnpn pass transistor. an output capacitor greater than 10 m f with equivalent series resistance less than 1.0 w is required for compensation. more information is provided in the stability considerations section. the cs52313 provides an auxiliary drive feature that allows a load to remain powered even if the v in supply for the ic is absent. an external pchannel fet is the only additional component required to implement this function if an auxiliary power supply is available. the pfet gate is connected to the auxdrv lead. the pfet drain is connected to the auxiliary power supply, and the pfet source is connected to the load. the polarity of this connection is very important, since the pfet body diode will be connected between the load and the auxiliary supply. if the pfet is connected with its drain to the load and its source to the supply, the body diode will be forwardbiased if the auxiliary supply is turned off. this will result in the linear regulator providing current to everything on the auxiliary supply rail. the auxdrv lead is internally connected to a 10 k w resistor and to a saturating npn transistor that acts as a switch. if the v in supply is off, the auxdrv output will connect the pfet gate to ground through the 10 k w resistor, and the pfet will conduct current to the load. as the v in supply begins to rise, the auxdrv lead will also rise until it reaches a typical voltage of about 650 mv. the npn transistor connected to the auxdrv lead will saturate at this point, and the gate of the pfet will be pulled down to a typical voltage of about 100 mv. the pfet will continue to conduct current to the load. the v in supply voltage will continue to rise, but the linear regulator output is disabled until v in reaches a typical threshold of 4.5 v. during this time, the load continues to be powered by the auxiliary driver. once the 4.5 v v in threshold is reached, the saturating npn connected to the auxdrv lead turns off. the onchip 10 k w pullup resistor will pull the pfet gate up to v in , thus turning the pfet off. the linear regulator turns on at the same time. an external compensation capacitor is required for the linear regulator to be stable, and this capacitance also serves as a charge reservoir to minimize any aglitchingo that might result during the supply changeover. hysteresis is present in the auxdrv circuitry, requiring v in to drop by 100 mv (typical) after the linear regulator is providing power to the load before the auxdrv circuitry can be reenabled. figure 13. initial powerup, v aux not present r out = 8.8 i out = startup 375 ma v in v out v auxdrv figure 14. powerup, v aux = 3.3 v. note the aoscillatory performanceo as the linear regulator changes the v out node. i out r ds(on) 130 mv i out = 375 ma v aux = 3.30 v v in v out v auxdrv figure 15. powerdown, v aux = 3.3 v. again, note v = i r ds(on) 130 mv i out = 375 ma v aux = 3.30 v in v out v auxdrv
cs52313 http://onsemi.com 7 figure 16. powerup, v aux = 3.135 v. the aoscillatory performanceo mode lasts longer because the difference between v aux and 3.3 is greater i out = 375 ma v aux = 3.135 v v in v out v auxdrv figure 17. powerdown, v aux = 3.135 v. the difference in voltage is now i out r ds(on) plus the difference in supply voltages (3.3 v aux ) i out = 375 ma v aux = 3.135 v in v out v auxdrv figure 18. powerup, v aux = 3.465 v. i out r ds(on) is compensated by higher value of v aux i out = 375 ma v aux = 3.465 v in v out v auxdrv figure 19. powerdown, v aux = 3.465 v i out = 375 ma v aux = 3.465 v in v out v auxdrv stability considerations the output capacitor helps determine three main characteristics of a linear regulator: startup, transient response and stability. startup is affected because the output capacitor must be charged. at initial startup, the v in supply may not be present, and the output capacitor will be charged through the pfet. the pfet will initially provide current to the load through its body diode. the diode will act as a voltage follower until sufficient voltage is present to turn the fet on. since most commercial power supplies have a fairly low ramp rate, charging through the body diode should effectively limit inrush current to the capacitor. during normal operation, transient load current requirements will be satisfied from the charge stored in the output capacitor until either the linear regulator or the auxiliary supply can respond. larger values of capacitance will improve transient response, but will also cost more. a linear regulator will respond within microseconds, where an external power supply may take milliseconds to react. the output capacitance will provide the difference in current until this occurs. the result will be an instantaneous voltage change at the output. this change is the product of the current change and the capacitor esr: v out i load esr this limitation directly affects load regulation. capacitor esr must be minimized if output voltage must be maintained within tight tolerances. in such a case, it is often advisable to use a parallel network of different types of capacitors. for example, electrolytic capacitors provide high charge storage capacity in a small size, while tantalum capacitors have low esr. the parallel combination will result in a high capacity, low esr network. it is also important to physically locate the capacitance network close to the load, and to connect the network to the load with wide pc board traces to minimize the metal resistance.
cs52313 http://onsemi.com 8 the cs52313 has been carefully designed to be stable for output capacitances greater than 10 m f with equivalent series resistance less than 1.0 w . while careful board layout is important, the user should have a stable system if these constraints are met. a graph showing the region of stability for the cs52313 is included in the atypical performance characteristicso section of this datasheet. input capacitors and the v in thresholds a capacitor placed on the v in pin will help to improve transient response. during a load transient, the input capacitor serves as a charge areservoir,o providing the needed extra current until the external power supply can respond. one of the consequences of providing this current is an instantaneous voltage drop at v in due to capacitor esr. the magnitude of the voltage change is again the product of the current change and the capacitor esr. it is very important to consider the maximum current step that can exist in the system. if the change in current is large enough, it is possible that the instantaneous voltage drop on v in will exceed the v in threshold hysteresis, and the ic will enter a mode of operation resembling an oscillation. as the part turns on, the output current i out will increase, reaching current limit during initial charging. increasing i out results in a drop at v in such that the shutdown threshold is reached. the part will turn off, and the load current will decrease. as i out decreases, v in will rise and the part will turn on, starting the cycle all over again. this oscillatory operation is most likely at initial startup when the output capacitance is not charged, and in cases where the rampup of the v in supply is slow. it may also occur during the power transition when the regulator turns on and the pfet turns off. a 15 m s delay exists between turnon of the regulator and the auxdrv pin pulling the gate of the pfet high. this delay prevents achattero during the power transitions. during this interval, the linear regulator will attempt to regulate the output voltage as 3.3 v. if the output voltage is significantly below 3.3 v, the ic will go into current limit while trying to raise v out . it is a shortlived phenomenon and is mentioned here to alert the user that the condition can exist. it is typically not a problem in applications. careful choice of the pfet switch with respect to r ds(on) will minimize the voltage drop which the output must charge through to return to a regulated state. more information is provided in the section on choosing the pfet switch. if required, using a few capacitors in parallel to increase the bulk charge storage and reduce the esr should give better performance than using a single input capacitor. short, straight connections between the power supply and v in lead along with careful layout of the pc board ground plane will reduce parasitic inductance effects. wide v in and v out traces will reduce resistive voltage drops. choosing the pfet switch the choice of the external pfet switch is based on two main considerations. first, the pfet should have a very low turnon threshold. choosing a switch transistor with v gs(on) 1.0 v will ensure the pfet will be fully enhanced with only 3.3 v of gate drive voltage. second, the switch transistor should be chosen to have a low r ds(on) to minimize the voltage drop due to current flow in the switch. the formula for calculating the maximum allowable onresistance is r ds(on)max v aux(min) v out(min) 1.5 i out(max) where v aux(min) is the minimum value of the auxiliary supply voltage, v out(min) is the minimum allowable output voltage, i out(max) is the maximum output current and 1.5 is a afudge factoro to account for increases in r ds(on) due to temperature. output voltage sensing it is not possible to remotely sense the output voltage of the cs52313 since the feedback path to the error amplifier is not externally available. it is important to minimize voltage drops due to metal resistance of high current pc board traces. such voltage drops can occur in both the supply traces and the return traces. the following board layout practices will help to minimize output voltage errors: ? always place the linear regulator as close to both load and output capacitors as possible. ? always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. ? connect the load to ground through the widest possible traces. ? connect the ic ground to the load ground trace at the point where it connects to the load. current limit the cs52313 has internal current limit protection. output current is limited to a typical value of 850 ma, even under output short circuit conditions. if the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition. the ic does not contain circuitry to report this fault. thermal shutdown the cs52313 has internal temperature monitoring circuitry. the output is disabled if junction temperature of the ic reaches 180 c. thermal hysteresis is typically 25 c and allows the ic to recover from a thermal fault without the need for an external reset signal. the monitoring circuitry is located near the composite pnpnpn output transistor, since this transistor is responsible for most of the onchip power dissipation. the combination of current limit and thermal shutdown will protect the ic from nearly any fault condition.
cs52313 http://onsemi.com 9 reverse current protection during normal system operation, the auxiliary drive circuitry will maintain voltage on the v out pin when v in is absent. ic reliability and system efficiency are improved by limiting the amount of reverse current that flows from v out to ground and from v out to v in . current flows from v out to ground through the feedback resistor divider that sets up the output voltage this resistor can range in value from 6.0 k w to about 10 k w , and roughly 500 m a will flow in the typical case. current flow from v out to v in will be limited to leakage current after the ic shuts down. onchip rc time constants are such that the output transistor should be turned off well before v in drops below the v out voltage. calculating power dissipation and heatsink requirements most linear regulators operate under conditions that result in high onchip power dissipation. this results in high junction temperatures. since the ic has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. some heatsinking will usually be required. thermal characteristics of an ic depend on four parameters: ambient temperature (t a in c), power dissipation (p d in watts), thermal resistance from the die to the ambient air ( q ja in c per watt) and junction temperature (t j in c). the maximum junction temperature is calculated from the formula below: t j(max) t a(max) ( ja p d(max) ) maximum ambient temperature and power dissipation are determined by the design, while q ja is dependent on the package manufacturer. the maximum junction temperature for operation of the cs52313 within specification is 150 c. the maximum power dissipation of a linear regulator is given as p d(max) (v in(max) v out(min) ) (i load(max) v in(max) ) i gnd(max) where i gnd(max) is the ic bias current. it is possible to change the effective value of q ja by adding a heatsink to the design. a heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. each material in the path of heat flow has its own characteristic thermal resistance, all measured in c per watt. the thermal resistances are summed to determine the total thermal resistance between the die junction and air. there are three components of interest: junctiontocase thermal resistance ( q jc ), casetoheatsink thermal resistance ( q cs ) and heatsinktoair thermal resistance ( q sa ). the resulting equation for junctiontoair thermal resistance is ja jc cs sa the value of q jc both packages of the cs52313 are provided in the packaging information section of this data sheet. the value of q cs can be considered zero, since heat is conducted out of the d 2 pak package by the ic leads and the tab, and out of the soic package by its ic leads that are soldered directly to the pc board. modification of q sa is the primary means of thermal management. for surface mount components, this means modifying the amount of trace metal that connects to the ic. the thermal capacity of pc board traces is dependent on how much copper area is used, whether or not the ic is in direct contact with the metal, whether or not the metal surface is coated with some type of sealant, and whether or not there is airflow across the pc board. the chart provided below s hows heatsinking capability of a square, single sided copper pc board trace. the area is given in square millimeters, and it is assumed there is no airflow across the pc board. figure 20. thermal resistance capability of copper pc board metal traces pc board trace area (mm 2 ) 70 0 thermal resistance, cw 2000 50 60 40 30 20 10 0 4000 6000 typical d 2 pak pc board heatsink design a typical design of the pc board surface area needed for the d 2 pak package is shown on page 11. calculations were made assuming v in(max) = 5.25 v, v out(min) = 3.266 v, i out(max) = 500 ma, i gnd(max) = 5.0 ma and t a = 70 c. p d (5.25 v 3.266 v) 0.5 a (5.25 v)(0.005 a) 1018 mw maximum temperature rise t t j(max) t a 150 c 70 c 80 c ja (worst case) t p d 80 c 1.018 w 78.56 c w
cs52313 http://onsemi.com 10 first, we determine the need for heatsinking. if we assume the maximum q ja = 50 c/w for the d 2 pak, the maximum temperature rise is found to be t p d ja 1.018 w 50 c w 50.9 c this is less than the maximum specified operating junction temperature of 125 c, and no heatsinking is required. since the d 2 pak has a large tab, mounting this part to the pc board by soldering both tab and leads will provide superior performance with no pc board area penalty. typical 8 lead fused lead soic design we first determine the need for a heat sink for the 8 lead soic package at a load of 500 ma. using the dissipation from the d 2 pak example of 1018 mw and the q ja of the soic package of 110 c/w gives a temperature rise of 112 c. adding this to an ambient temperature of 70 c gives 182 c junction temperature. this is an excessive temperature rise but it can be reduced by adding additional cooling in the form of added surface area of copper on the pcb. using the relationship of maximum temperature rise of t ja t j(max) t a 150 c 70 c 80 c we calculate the thermal resistance allowed from junction to air: ja (worst case) t ja p d 80 c 1.018 w 79.6 c w the thermal resistance from the die to the leads (case) is 25 c/w. subtracting these two numbers gives the allowable thermal resistance from case to ambient: ca ja jc 79.6 c w 25 c w 54.6 c w the thermal resistance of this copper area will be 54.6 c/w. we now look at figure 20 and find the pcb trace area that will be less than 54.5 c/w. examination shows that 750 mm 2 of copper will provide cooling for this part. this would be the soic part with the center 4 ground leads soldered to pads in the center of a copper area about 27 mm 27 mm. a lower dissipation or the addition of airflow could result in a smaller required surface area. description the cs52313 application circuit has been implemented as shown in the following pages. the schematic, bill of materials and printed circuit board artwork can be used to build the circuit. the design is very simple and consists of two capacitors, a pchannel fet and the cs52313. five turret pins are provided for connection of supplies, meters, oscilloscope probes and loads. the cs52313 power supply management solution is implemented in an area less than 1.5 square inches. due to the simplicity of the design, output current must be derated if the cs52313 is operated at v in voltages greater than 7.0 v. figure 21 provides the derating curve on a maximum power dissipation if heatsink is added. operating at higher power dissipation without cs52313 heatsink may result in a thermal shutdown condition. figure 21. demo board output current derating vs. v in v in (volts) 5 i out (ma) 6 500 600 400 300 200 100 0 7891011121314 the v in connection the v in connection is denoted as such on the pc board. the maximum input voltage to the ic is 14 v before damage to the ic is possible. however, the specification range for the ic is 4.75 v < v in < 6.0 v. the gnd connection the gnd connection ties the ic power return to two turret pins. the extra turret pin provides for connection of multiple instrument grounds to the demonstration board. the auxdrv connection the auxdrv lead of the cs52313 is connected to the gate of the external pfet. this connection is also brought to a turret pin to allow easy connection of an oscilloscope probe for viewing the auxdrv waveforms. the v aux connection the v aux turret pin provides a connection point between an external 3.3 v supply and the pfet drain. the v out connection the v out connection is tied to the v out lead of the cs52313 and the pfet source. this point provides a convenient point at which some type of lead may be applied. figure 22. application circuit schematic tp5 tp6 auxdrv tp1 tp2 tp3 tp4 v aux +3.3 v c2 q1 u1 v out v in gnd auxdrv cs52313 v in gnd c1
cs52313 http://onsemi.com 11 pc board layout artwork the pc board is a single layer copper design. the layout artwork is reproduced at actual size below. figure 23. top copper layer figure 24. top silk screen layer 2o 1.8o 2o 1.8o v in 5.0 v gnd gnd v out 3.3 v aux 3.3 v aux.drv test description the startup and supply transition waveforms shown in figures 13 through 19 were obtained using the application circuit board with a resistive load of 8.8 w . this provides a dc load of 375 ma when the regulated output voltage is 3.3 v. a standard 2.0 a bench supply was used to provide power to the application circuit. the transient response waveforms shown in the typical performance characteristics section were obtained by switching a 6.3 w resistor across the output. temperature performance the graph below shows thermal performance for the cs52313 across the normal operating output current range. figure 25. package temperature vs. load current (v in = 5.0 v, t a = 23 c) load current (ma) 55 0 package temperature (c) 50 45 50 40 35 30 25 20 100 150 200 250 300 350 400 450 500 pfet r ds(on) performance the graph provided below show typical r ds(on) performance for the pfet. the data is provided as v ds vs i out for different values of v aux . figure 26. pfet v ds vs. i out i out (ma) 140 0 v ds (mv) 100 100 120 80 60 40 20 0 200 300 400 500 160 v aux = 3.135 v v aux = 3.300 v v aux = 3.465 v applications circuit bill of materials refdes description part number manufacturer contact information c1, c2 33 m f, 16 v tantalum capacitors tajd336k016 avx corp www.avxcorp.com 18434489411 q1 pchannel fet transistor mgsf1p02elt1 on semiconductor http://onsemi.com u1 linear regulator with auxiliary cs52313dps on semiconductor http://onsemi.com t1t6 turret pins 40f6023 newark electronics www.newark.com 18004639275
cs52313 http://onsemi.com 12 package dimensions d 2 pak 5pin dp suffix case 936f01 issue o t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.035 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.090 0.110 2.29 2.79 g 0.067 bsc 1.70 bsc h 0.098 0.108 2.49 2.74 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions b and m. 4. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) max. b n a k m e c seating plane f h j d 5 pl g t m 0.13 (0.005) m b 12345 so8 df suffix case 75106 issue t seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.19 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeter. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10 package thermal data parameter d 2 pak 5pin so8 unit r q jc typical 2.5 25 c/w r q ja typical 1050* 110 c/w *depending on thermal properties of substrate. r q ja = r q jc + r q ca .
cs52313 http://onsemi.com 13 notes
cs52313 http://onsemi.com 14 notes
cs52313 http://onsemi.com 15 notes
cs52313 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs52313/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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