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data sheet 100985a june 2, 2000 advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. note(s): the tx monitor is only used with the 100-pin cx2833i-3x. tpos tneg tclk encoder tais pulse shaper e3mode line driver pdb data mux rloop endecdis lloop lbo xoe tlinep tlinem/n decoder rpos rneg rclk rlos tclk clock/ data recovery pdata pdata/ ndata ndata datclk p n receiver tx monitor alos rlinep rlinem/n tmonp tmonm txmon tmontst refclk reqh liu #1 liu #2 liu #3 CX28331/cx28332/cx28333 single/dual/triple e3/ds3/sts-1 line interface unit the cx28333 is a three-channel, e3/ds3/sts-1 fully-integrated line interface unit (liu). it is configured via external pins and does not need a microprocessor interface. each channel has an independent equalizer on the receive side requiring no user configuration. also, each channel has a programmable transmit pulse shaper that can be set to ensure that the cross-connect pulse mask requirement is met for transmit cable length up to 450 feet. the cx28332 is a dual-channel, and the CX28331 is a single-channel liu with performance identical to the cx28333. the cx28333 gives the user new economies of scale in concentrator applications where three ds3 or sts-1 channels are concentrated into a single sts-3 channel. by including three independent transceivers on a chip, significant external components are eliminated, with the exception of 1:1 coupling transformers, termination resistors, and supply bypass capacitors. note: in this document, "i" is used to represent the number of channels: i = 1 (CX28331), i = 2 (cx28332), and i = 3 (cx28333). functional block diagram distinguishing features ? can be used as a data transceiver over a maximum of 900 feet of type 734/728 coaxial cable or equivalent in an on-premise environment programmable pulse filtering to meet cross-connect pulse masks ( ansi t1.102-1993 ) meets jitter specifications of bellcore gr499, gr253, and tbr24 (with external jat). large input dynamic range alarms for coding violation and loss of signal full diagnostic loopback capability uses a minimum of external components compatible with itu-t g.703, g.823 independent power down mode per channel easily interfaced to the ds3/e3 framer ic (cx28342/3/4/6/8 and cn8330) selectable b3zs/hdb3 encoding/decoding superior input receiver sensitivity (< 25 mv) transmit monitor inputs (cx2833i-3x series only) physical characteristics 80- and 100-pin etqfp package single 3.3 v power supply 1 w maximum power dissipation (cx28333) ?40 c to +85 c temperature range 5 v-tolerant pins ttl digital pins applications digital cross-connect systems routers atm switches channelized line aggregation units test equipment channel service units multiplexers
100985a conexant ? 2000, conexant systems, inc. all rights reserved. information in this document is provided in connection with conexant systems, inc. (?conexant?) products. these materials are provided by conexant as a service to its customers and may be used for informational purposes only. conexant assumes no responsibility for errors or omissions in these materials. conexant may make changes to specifications and product descriptions at any time, without notice. conexant makes no commitment to update the information and shall have no responsibility whatsoever fo r conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in conexant?s terms and conditions of sale for such products, conexant assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of conexant products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. conexant further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. conexant products are not intended for use in medical, lifesaving or life sustaining applications. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: conexant?, the conexant c symbol, and ?what?s next in communications technologies??. product names or services listed in this publication are for identification purposes only, and may be trademark s of third parties. third-party brands and names are the property of their respective owners. for additional disclaimer information, please consult conexant?s legal information posted at www.conexant.com , which is incorporated by reference. reader response: conexant strives to produce quality documentation and welcomes your feedback. please send comments and suggestions to tech.pubs@conexant.com . for technical questions, contact your local conexant sales office or field applications engineer. cx28333evm ch2 ch3 cx28333 nrztx data and clk in loss of signal code violation clock input control tx b3zs/hdb3 analog out rx b3zs/hdb3 analog in nrzrx data and clk out nrztx data and clk in nrzrx data and clk out nrztx data and clk in nrzrx data and clk out ch1 ch2 ch3 ch1 tx b3zs/hdb3 analog out rx b3zs/hdb3 analog in tx b3zs/hdb3 analog out rx b3zs/hdb3 analog in l i n e s i d e f r a m e r s i d e 100985_002
100985a conexant ordering information revision history model number package description operating temperature CX28331-1x 80-pin etqfp single-channel liu ? 40 c to +85 c cx28332-1x 80-pin etqfp dual-channel liu ? 40 c to +85 c cx28333-1x 80-pin etqfp triple-channel liu ? 40 c to +85 c CX28331-3x 100-pin etqfp single channel with transmit monitoring ? 40 c to +85 c cx28332-3x 100-pin etqfp dual channel with transmit monitoring ? 40 c to +85 c cx28333-3x 100-pin etqfp triple channel with transmit monitoring ? 40 c to +85 c revision level date description a ? may 5, 2000 initial release
100985a conexant
100985a conexant v table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 ami b3zs/hdb3 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.2 pulse shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3 line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.1 transmit pulse mask templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.4 alarm indication signal (ais) generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5 transmit monitor block (cx2833i-3x only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.6 jitter generation (intrinsic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.1 receive sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.2 agc/vga block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.3 receive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.4 the pll clock recovery circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.5 loss of signal (los) detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.6 b3zs/hdb3 decoder with bipolar violation detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.7 data squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4.1 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.5 additional CX28331/cx28332/cx28333 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.1 bias generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.2 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.3 loopback multiplexers (muxes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.6 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
table of contents CX28331/cx28332/cx28333 single/dual/triple e3/ds3/sts-1 line interface unit vi conexant 100985a 2.7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.7.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.8 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 3.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pcb design considerations for CX28331/cx28332/cx28333 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 power supply and ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.2 impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.3 other passive parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.4 ibis models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.5 recommended vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 appendix a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 applicable standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 appendix b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1 evaluation module schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1
CX28331/cx28332/cx28333 list of figures single/dual/triple e3/ds3/sts-1 line interface unit 100985a conexant vii list of figures figure 1-1. CX28331-1x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 figure 1-2. cx28332-1x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 figure 1-3. cx28333-1x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 figure 1-4. CX28331-3x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 figure 1-5. cx28332-3x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 figure 1-6. cx28333-3x pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 figure 2-1. typical application of single cx2833i channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 2-2. pulse shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 2-3. pulse measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-4. transmit pulse mask for ds3 rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 figure 2-5. transmit pulse mask for sts-1 rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 2-6. transmit pulse mask for e3 rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 figure 2-7. ais signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 figure 2-8. minimum jitter tolerance requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 4 figure 2-9. maximum jitter transfer curve requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 figure 2-10. cx2833i-1x mechanical drawing (80-pin) ? dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 figure 2-11. cx2833i-3x mechanical drawing (100-pin) ? dimensions . . . . . . . . . . . . . . . . . . . . . . . . 2-18 figure 2-12. timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 figure 3-1. typical cx28333 connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 figure b-1. recommended schematic for the cx2833i-1x device . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 figure b-2. recommended schematic for the cx2833i-3x device (1 of 2) . . . . . . . . . . . . . . . . . . . . . . b-3 figure b-3. recommended schematic for the cx2833i-3x device (2 of 2) . . . . . . . . . . . . . . . . . . . . . . b-4
list of figures CX28331/cx28332/cx28333 single/dual/triple e3/ds3/sts-1 line interface unit viii conexant 100985a
CX28331/cx28332/cx28333 list of tables single/dual/triple e3/ds3/sts-1 line interface unit 100985a conexant ix list of tables table 1-1. CX28331/cx28332/cx28333 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 table 1-2. cx2833i-3x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 table 2-1. ds3 transmit template specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 table 2-2. sts-1 transmit template specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 table 2-4. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 0 table 2-5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 table 2-6. ac characteristics (logic timing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
list of tables CX28331/cx28332/cx28333 single/dual/triple e3/ds3/sts-1 line interface unit x conexant 100985a
100985a conexant 1-1 1 1.0 pin description 1.1 pin assignments figures 1-1 (CX28331-1x), 1-2 (cx28332-1x), and 1-3 (cx28333-1x) illustrate pin assignments for the 80-pin exposed thin quad flat package (etqfp). see table 1-1 for the cx2833i-1x pin descriptions. figures 1-4 (CX28331-3x), 1-5 (cx28332-3x), and 1-6 (cx28333-3x) illustrate pin assignments for the 100-pin etqfp. the 100-pin package adds more functionality, supporting new features such as transmit monitoring and transmit monitoring status testing. see table 1-2 for the cx2833i-3x pin descriptions. the input/output (i/o) column is coded as follows: i = input o = output i/o = bidirectional p = power note: all digital inputs and outputs contain 75 k ? pull-down resistors. when a channel is disabled (i.e., the pdx pin is tied low or not connected), all receive and transmit analog circuitry powers down. analog inputs (rline) are ignored and analog outputs (tline) are high impedance. digital inputs of a powered-down channel are still active, but ignored. overall noise on the device can be lowered by not driving the digital inputs of a powered-down channel. note: when power is disconnected from the device, tline pins are low impedance to ground if driven by more than one forward-bias diode voltage (0.7 v) below ground. additionally, driving tline, a forward-bias diode voltage above the vgg pin, creates a low impedance path from the tline pin to the vgg pin. otherwise, the tline pins are high impedance.
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-2 conexant 100985a figure 1-1. CX28331-1x pin diagram CX28331-1x 76 77 78 79 80 nc gpd reset vgg rbias 71 72 73 74 75 nc nc dvddio nc nc 66 67 68 69 70 nc nc nc nc nc 61 62 63 64 65 nc nc nc nc nc 56 57 58 59 60 lloop rloop pd endecdis dvddc 51 52 53 54 55 tais rlos rclk rpos/rnrz rneg/rlcv 46 47 48 49 50 reqh refclk tclk tpos/tnrz tneg/nc 41 42 43 44 45 dvssc nc e3mode lbo xoe 5 4 3 2 1 10 9 8 7 6 15 14 13 12 11 20 19 18 17 16 25 24 23 22 21 nc vss nc nc vdd 30 29 28 27 26 nc nc dvssio nc nc 35 34 33 32 31 nc nc nc nc nc 40 39 38 37 36 nc nc nc nc nc rvss rlinen rlinep rvdd vdd nc nc vss tvdd tlinen tlinep tvss vss vdd nc nc vss nc vdd nc 100985_003
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-3 figure 1-2. cx28332-1x pin diagram cx28332-1x 76 77 78 79 80 pd1 gpd reset vgg rbias 71 72 73 74 75 xoe1 lbo1 dvddio lloop1 rloop1 66 67 68 69 70 rlos1 rclk1 rpos1/rnrz1 rneg1/rlcv1 reqh1 61 62 63 64 65 tais1 tclk1 tpos1/tnrz1 tneg1/nc1 refclk1 56 57 58 59 60 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc e3mode endecdis dvddc 51 52 53 54 55 46 47 48 49 50 41 42 43 44 45 dvssc nc 5 4 3 2 1 10 9 8 7 6 15 14 13 12 11 20 19 18 17 16 25 24 23 22 21 pd2 rvss2 rline2n rline2p rvdd2 30 29 28 27 26 xoe2 lbo2 dvssio lloop2 rloop2 35 34 33 32 31 rlos2 rclk2 rpos2/rnrz2 rneg2/rlcv2 reqh2 40 39 38 37 36 tais2 tneg2/nc2 tpos2/tnrz2 tclk2 refclk2 tvdd2 tline2n tline2p tvss2 vss nc nc vdd vdd nc nc vss tvss1 tvdd1 tline1n tline1p rvss1 rline1p rvdd1 rline1n 100985_004
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-4 conexant 100985a figure 1-3. cx28333-1x pin diagram cx28333-1x 76 77 78 79 80 pd1 gpd reset vgg rbias 71 72 73 74 75 xoe1 lbo1 dvddio lloop1 rloop1 66 67 68 69 70 rlos1 rclk1 rpos1/rnrz1 rneg1/rlcv1 reqh1 61 62 63 64 65 tais1 tclk1 tpos1/tnrz1 tneg1/nc1 refclk1 56 57 58 59 60 lloop2 rloop2 pd2 endecdis dvddc 51 52 53 54 55 tais2 rlos2 rclk2 rpos2/rnrz2 rneg2/rlcv2 46 47 48 49 50 reqh2 refclk2 tclk2 tpos2/tnrz2 tneg2/nc2 41 42 43 44 45 dvssc e3mode nc lbo2 xoe2 5 4 3 2 1 10 9 8 7 6 15 14 13 12 11 20 19 18 17 16 25 24 23 22 21 pd3 rvss3 rline3n rline3p rvdd3 30 29 28 27 26 xoe3 lbo3 dvssio lloop3 rloop3 35 34 33 32 31 rlos3 rclk3 rpos3/rnrz3 rneg3/rlcv3 reqh3 40 39 38 37 36 tais3 tneg3/nc3 tpos3/tnrz3 tclk3 refclk3 rvss2 rline2n rline2p rvdd2 tvdd3 tline3n tline3p tvss3 tvdd2 tline2n tline2p tvss2 tvss1 tvdd1 tline1n tline1p rvss1 rline1p rvdd1 rline1n 100985_005
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-5 table 1-1. cx2833i-1x pin definitions (1 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x coaxial line pins 14 ?? rlinep ch1 positive receive data i differential inputs for each channel from its respective receive coax line. the rx expects balanced differential inputs, usually achieved using a 1:1 transformer. the inputs are internally dc biased to 1.9 v. ? 66rline1p 15 ?? rlinen ch1 negative receive data i ? 77rline1n ? 22 14 rline2p ch2 positive receive data i ? 23 15 rline2n ch2 negative receive data i ?? 22 rline3p ch3 positive receive data i ?? 23 rline3n ch3 negative receive data i 10 ?? tlinep ch1 positive transmit data o differential, coax-driver balanced outputs for pulse-shaped ami b3zs/hdb3 encoded waveforms for each channel. these pins should be connected to the primary side of the 1:1 transformer through two backmatch resistors (see appendix b ). ? 2 2 tline1p 11 ?? tlinen ch1 negative transmit data o ? 33tline1n ? 18 10 tline2p ch2 positive transmit data o ? 19 11 tline2n ch2 negative transmit data o ?? 18 tline3p ch3 positive transmit data o ?? 19 tline3n ch3 negative transmit data o
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-6 conexant 100985a digital data pins 54 ?? rpos/ rnrz ch1 receive positive rail or nrz data o resynchronized receive data intended to be strobed out by the corresponding rclk. when endecdis = 1, these outputs are positive and negative ami data (rpos and rneg). when endecdis = 0, these outputs are decoded nrz data (rnrz) and line code violation (rlcv). a line code violation is indicated when rlcv = 1. see notes on the endecdis pin in the control signals section. ? 68 68 rpos1/ rnrz1 55 ?? rneg/ rlcv ch1 receive negative rail or line code violation o ? 69 69 rneg1/ rlcv1 ? 33 54 rpos2/ rnrz2 ch2 receive positive rail or nrz data o ? 32 55 rneg2/ rlcv2 ch2 receive negative rail or line code violation o ?? 33 rpos3/ rnrz3 ch3 receive positive rail or nrz data o ?? 32 rneg3/ rlcv3 ch3 receive negative rail or line code violation o 53 ?? rclk receive clock ch1 o recovered clock for each channel receiver, intended for strobing the corresponding rdat into the following framer or logic. ? 67 67 rclk1 ? 34 53 rclk2 receive clock ch2 o ?? 34 rclk3 receive clock ch3 o 49 ?? tpos/ tnrz ch1 transmit positive rail or nrz data i synchronized transmit data intended to be strobed in by the corresponding tclk. when endecdis = 1, these inputs are expected to be positive and negative ami data (tpos and tneg). when endecdis = 0, these inputs are expected to be uncoded nrz data (tnrz) and no connects (nc). see notes on the endecdis pin in the control signals section. ? 63 63 tpos1/ tnrz1 48 ?? tneg/ nc ch1 transmit negative rail or no connect data i ? 64 64 tneg1/ nc1 ? 38 49 tpos2/ tnrz2 ch2 transmit positive or nrz data i ? 37 48 tneg2/ nc2 ch2 transmit negative rail or no connect data i ?? 38 tpos3/ tnrz3 ch3 transmit positive or nrz data i ?? 37 tneg3/ nc3 ch3 transmit negative rail or no connect data i table 1-1. cx2833i-1x pin definitions (2 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-7 50 ?? tclk transmit clock ch1 i transmit bit clock input for strobing with transmit data into the cx2833i. ? 62 62 tclk1 ? 39 50 tclk2 transmit clock ch2 i ?? 39 tclk3 transmit clock ch3 i 52 ?? rlos loss of signal ch1 o loss of signal (los) indication for each channel, as determined by insufficient pulse density. signal loss detected when rlos = 1. an los will be asserted when 175 75 0s occur in a row and deasserted when the pulse density is between 28% and 33% (ds3/sts-1) (i.e., a 1s density). ? 66 66 rlos1 ? 35 52 rlos2 loss of signal ch2 o ?? 35 rlos3 loss of signal ch3 o control signals 59 59 59 endecdis encoder/decoder disable (for all channels) i 1 = dual rail pulse coded data format. input transmit data pins tpos, tnrz, tneg and nc are interpreted as tpos and tneg (encoded positive and negative rail data). output receive data pins rpos and rnrz, and rneg and rlcv are interpreted as rpos and rneg, with rpos having a positive pulse in place of every positive ami pulse and rneg having a negative pulse in place of every negative ami pulse. 0 = nrz format. transmit data pins tpos and tneg are interpreted as tnrz and nc (not connected). receive data pins rpos and rneg are interpreted as rnrz and rlcv. in this mode, all line code violations are reported as active high on rlcv. 51 ?? tais transmit ch1 ais mode enable i transmission of alarm indication signal (ais) for a given channel. replace transmit data with ais signal. the ami form of ais supported is alternating 1s. (+1, -1, +1, -1, +1, ...) looping takes precedence over ais. 1 = ais mode enabled 0 = ais mode disabled ? 61 61 tais1 ? 40 51 tais2 transmit ch2 ais mode enable i ?? 40 tais3 transmit ch3 ais mode enable i table 1-1. cx2833i-1x pin definitions (3 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-8 conexant 100985a 43 43 43 e3mode e3mode i when the pin is set to high, it enables the e3 mode on all channels, instead of the ds3/sts-1 mode. this also changes the pulse shaper to e3 mode and overrides all lbo pins. it also changes the encoder/decoder from b3zs mode to hdb3 mode. 1 = e3 mode 0 = ds3/sts-1 mode 44 ?? lbo transmit line ch1 build-out mode i line build-out mode per channel, based on the length of cable on the transmit side of the cross-connect block. this bit is overridden and the pulse shaper is disabled (no pulse shaping) if e3mode = 1. 1 = inserts line build-out into the transmit channel. usually used when the transmit cable is less than 350 feet in length. 0 = line build-out bypassed (not inserted). usually used when the transmit cable is greater than 350 feet in length. ? 72 72 lbo1 ? 29 44 lbo2 transmit line ch2 build-out mode i ?? 29 lbo3 transmit line ch3 build-out mode i 56 ?? lloop local loopback enable ch1 i local loopback enable per channel. the transmit data is looped back immediately from the encoder to the decoder in place of the received data. 1 = local loopback enabled 0 = local loopback disabled ? 74 74 lloop1 ? 27 56 lloop2 local loopback enable ch2 i ?? 27 lloop3 local loopback enable ch3 i 57 ?? rloop remote loopback enable ch1 i remote loopback enable per channel. the receive data, retimed after clock recovery, is looped back into the ami generator in place of the transmit data. 1 = remote loopback enabled 0 = remote loopback disabled ? 75 75 rloop1 ? 26 57 rloop2 remote loopback enable ch2 i ?? 26 rloop3 remote loopback enable ch3 i 45 ?? xoe transmit output enable ch1 i transmit output enable per channel. 1 = transmit line output driver enabled 0 = transmit output driver set to high impedance state ? 71 71 xoe1 ? 30 45 xoe2 transmit output enable ch2 i ?? 30 xoe3 transmit output enable ch3 i table 1-1. cx2833i-1x pin definitions (4 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-9 46 ?? reqh ch1 receive high eq gain enable i the equalizer in the cx2833i has two gain settings. the higher gain setting is designed to optimally equalize a nominally-shaped (meets the pulse template), pulse-driven ds3 or sts-1 waveform that is driven through 0 ? 900 feet of cable. square-shaped pulses such as e3 or ds3-high require less high-frequency gain and should use the low eq gain setting. reqh = 1 high eq gain (ds3/sts-1 modes) reqh = 0 low eq gain (e3/ds3 square modes) ? 70 70 reqh1 ? 31 46 reqh2 ch2 receive high eq gain enable ?? 31 reqh3 ch3 receive high eq gain enable i power/ground 12 ?? tvdd tx power ch1 p power pins for transmit circuitry per channel (3.3 v). ? 4 4 tvdd1 ? 20 12 tvdd2 tx power ch2 p ?? 20 tvdd3 tx power ch3 p 9 ?? tvss tx ground ch1 p ground pins for transmit circuitry per channel. ? 1 1 tvss1 ? 17 9 tvss2 tx ground ch2 p ?? 17 tvss3 tx ground ch3 p 13 ?? rvdd rx power ch1 p power pins for receive circuitry per channel (3.3 v). connect to 3.3 v power. ? 5 5 rvdd1 ? 21 13 rvdd2 rx power ch2 p ?? 21 rvdd3 rx power ch3 p 16 ?? rvss rx ground ch1 p ground pins for receive circuitry per channel. connect to ground. ? 8 8 rvss1 ? 24 16 rvss2 rx ground ch2 p ?? 24 rvss3 rx ground ch3 p 60 60 60 dvddc digital core power p digital core power for all channels (3.3 v). 41 41 41 dvssc digital core ground p digital core ground for all channels. 79 79 79 vgg 5 v/3.3 v esd pin (1) p 5 v supply for 5 v-tolerant, digital pad esd diodes. no static power is drawn from pin. 73 73 73 dvddio digital i/o power p connect to 3.3 v digital power. 28 28 28 dvssio digital ground p digital ground. table 1-1. cx2833i-1x pin definitions (5 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-10 conexant 100985a 4, 5, 20, 21 12, 13 ? vdd power p connect to 3.3 v power. 1, 8, 17, 24 9, 16 ? vss ground p connect to ground. miscellaneous 58 ?? pd power down for ch1 i power down transceiver channel 0 = power down channel (off) 1 = channel active (on) note: a special power-down mode exists when all three pdbs are set low. this special mode shuts off the entire chip (including biasing). this is useful for static idd testing. ? 76 76 pd1 ? 25 58 pd2 power down for ch2 i ?? 25 pd3 power down for ch3 i 47 ?? refclk reference clock for ch1 i reference clock from off-chip. this clock should be set to one of the following: e3 rate (34.368 mhz) ds3 rate (44.736 mhz) sts-1 rate (51.84 mhz) the clock rate should correspond to the mode of operation that has been chosen for the channel. ? 65 65 refclk1 ? 36 47 refclk2 reference clock for ch2 i ?? 36 refclk3 reference clock for ch3 i 80 80 80 rbias bias resistor o a 12.1 k ? 1% resistor tied from this pin to ground provides the current reference to the entire chip. (2) 78 78 78 reset reset i/o asynchronous reset (reset entire device). 77 77 77 gpd global power down i/o power down (static idd testing). 0 = power down disable 1 = power down active 2, 3, 6, 7, 18, 19, 22, 23, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 42, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76 10, 11, 14, 15, 42, 44 ? 58 42 nc no connect ? not connected. note(s): (1) this pin should be connected to 3.3 v in an all-3.3 v design. (2) placing a capacitor from this pin to ground may result in instabilities. 3. all digital input pins contain a 75 k ? pull-down resistor from input to dvss. table 1-1. cx2833i-1x pin definitions (6 of 6) pin # signal name description i/o/p notes CX28331-1x cx28332-1x cx28333-1x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-11 figure 1-4. CX28331-3x pin diagram 100985_015 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 dvddc endecdis pd rloop lloop rneg/rlcv rpos/rnrz rclk rlos nc nc nc tais tclk tpos/tnrz tneg/nc tlos refclk reqh xoe lbo tmontst e3mode nc dvssc vss rbias vgg reset gpd nc nc nc dvddio nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc nc nc nc vdd vdd nc nc vss tvss tmonp tlinep tlinem tmonm tvdd rvdd rlinep rlinem rvss vss nc nc nc nc vdd vdd nc nc vss nc nc nc dvssio nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc CX28331-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-12 conexant 100985a figure 1-5. cx28332-3x pin diagram 100985_016 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 dvddc endecdis nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc tmontst e3mode nc dvssc tvss1 rbias vgg reset gpd pd1 rloop1 lloop1 dvddio lbo1 xoe1 reqh1 nc nc nc rneg1/rlcv1 rpos1/rnrz1 rclk1 rlos1 refclk1 tlos1 tneg1/nc1 tpos1/tnrz1 tclk1 tais1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tmon1p tline1p tline1m tmon1m tvdd1 rvdd1 rline1p rline1m rvss1 vss nc nc nc nc vdd vdd nc nc vss tvss2 tmon2p tline2p tline2m tmon2m tvdd2 rvdd2 rline2p rline2m rvss2 pd2 rloop2 lloop2 dvssio lbo2 xoe2 reqh2 nc nc nc rneg2/rlcv2 rpos2/rnrz2 rclk2 rlos2 refclk2 tlos2 tneg2/nc2 tpos2/tnrz2 tclk2 tais2 nc cx28332-3x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-13 figure 1-6. cx28333-3x pin diagram 100985_006 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 dvddc endecdis pd2 rloop2 lloop2 rneg2 / rlcv2 rpos2 / rnrz2 rclk2 rlos2 nc nc nc tais2 tclk2 tpos2/tnrz2 tneg2/nc2 tlos2 refclk2 reqh2 xoe2 lbo2 tmontst e3mode nc dvssc tvss1 rbias vgg reset gpd pd1 rloop1 lloop1 dvddio lbo1 xoe1 reqh1 nc nc nc rneg1/rlcv1 rpos1/rnrz1 rclk1 rlos1 refclk1 tlos1 tneg1/nc1 tpos1/tnrz1 tclk1 tais1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tmon1p tline1p tline1m tmon1m tvdd1 rvdd1 rline1p rline1m rvss1 tvss2 tmon2p tline2p tline2m tmon2m tvdd2 rvdd2 rline2p rline2m rvss2 tvss3 tmon3p tline3p tline3m tmon3m tvdd3 rvdd3 rline3p rline3m rvss3 pd3 rloop3 lloop3 dvssio lbo3 xoe3 reqh3 nc nc nc rneg3/rlcv3 rpos3/rnrz3 rclk3 rlos3 refclk3 tlos3 tneg3/nc3 tpos3/tnrz3 tclk3 tais3 nc cx28333-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-14 conexant 100985a table 1-2. cx2833i-3x pin definitions (1 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x coaxial line pins 17 ?? rlinep ch1 positive receive data i differential inputs for each channel from its respective receive coax line. the rx expects balanced differential inputs, usually achieved using a 1:1 transformer. the inputs are internally dc biased to 1.9 v. ? 77rline1p 18 ?? rlinem ch1 negative receive data i ? 88rline1m ? 27 17 rline2p ch2 positive receive data i ? 28 18 rline2m ch2 negative receive data i ?? 27 rline3p ch3 positive receive data i ?? 28 rline3m ch3 negative receive data i 12 ?? tlinep ch1 positive transmit data o differential, coax-driver balanced outputs for pulse-shaped ami b3zs/hdb3 encoded waveforms for each channel. these pins should be connected to the primary side of the 1:1 transformer through two backmatch resistors (see appendix b ). ? 22tline1p 13 ?? tlinem ch1 negative transmit data o ? 33tline1m ? 22 12 tline2p ch2 positive transmit data o ? 23 13 tline2m ch2 negative transmit data o ?? 22 tline3p ch3 positive transmit data o ?? 23 tline3m ch3 negative transmit data o
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-15 digital data pins 69 ?? rpos/ rnrz ch1 receive positive rail or nrz data o resynchronized receive data intended to be strobed out by the corresponding rclk. when endecdis = 1, these outputs are positive and negative ami data (rpos and rneg). when endecdis = 0, these outputs are decoded nrz data (rnrz) and line code violation (rlcv). a line code violation is indicated when rlcv = 1. see notes on the endecdis pin in the control signals section. ? 84 84 rpos1/ rnrz1 70 ?? rneg/ rlcv ch1 receive negative rail or line code violation o ? 85 85 rneg1/ rlcv1 ? 41 69 rpos2/ rnrz2 ch2 receive positive rail or nrz data o ? 40 70 rneg2/ rlcv2 ch2 receive negative rail or line code violation o ?? 41 rpos3/ rnrz3 ch3 receive positive rail or nrz data o ?? 40 rneg3/ rlcv3 ch3 receive negative rail or line code violation o 68 ?? rclk receive clock ch1 o recovered clock for each channel receiver, intended for strobing the corresponding rdat into the following framer or logic. ? 83 83 rclk1 ? 42 68 rclk2 receive clock ch2 o ?? 42 rclk3 receive clock ch3 o table 1-2. cx2833i-3x pin definitions (2 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-16 conexant 100985a 61 ?? tpos/ tnrz ch1 transmit positive rail or nrz data i synchronized transmit data intended to be strobed in by the corresponding tclk. when endecdis = 1, these inputs are expected to be positive and negative ami data (tpos and tneg). when endecdis = 0, these inputs are expected to be uncoded nrz data (tnrz) and no connects (nc). see notes on the endecdis pin in the control signal section. ? 78 78 tpos1/ tnrz1 60 ?? tneg/ nc ch1 transmit negative rail or no connect data i ? 79 79 tneg1/ nc1 ? 47 61 tpos2/ tnrz2 ch2 transmit positive or nrz data i ? 46 60 tneg2/ nc2 ch2 transmit negative data or no connect data i ?? 47 tpos3/ tnrz3 ch3 transmit positive or nrz data i ?? 46 tneg3/nc3 ch3 transmit negative data or no connect data i 62 ?? tclk transmit clock ch1 i transmit bit clock input for strobing with transmit data into the cx2833i. ? 77 77 tclk1 ? 48 62 tclk2 transmit clock ch2 i ?? 48 tclk3 transmit clock ch3 i 67 ?? rlos loss of signal ch1 o loss of signal (los) indication for each channel, as determined by insufficient pulse density. signal loss detected when rlos = 1. an los will be asserted when 175 75 0s occur in a row and deasserted when the pulse density is between 28% and 33% (ds3/sts-1) (i.e., a 1s density). ? 82 82 rlos1 ? 43 67 rlos2 loss of signal ch2 o ?? 43 rlos3 loss of signal ch3 o table 1-2. cx2833i-3x pin definitions (3 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-17 control signals 74 74 74 endecdis encoder/decoder disable (for all channels) i 1 = dual rail pulse coded data format. input transmit data pins tpos, tnrz, tneg and nc are interpreted as tpos and tneg (encoded positive and negative rail data). output receive data pins rpos and rnrz, and rneg and rlcv are interpreted as rpos and rneg, with rpos having a positive pulse in place of every positive ami pulse and rneg having a negative pulse in place of every negative ami pulse. 0 = nrz format. transmit data pins tpos and tneg are interpreted as tnrz and nc (not connected). receive data pins rpos and rneg are interpreted as rnrz and rlcv. in this mode, all line code violations are reported as active high on rlcv. 63 ?? tais transmit ch1 ais mode enable i transmission of alarm indication signal (ais) for a given channel. replace transmit data with ais signal. the ami form of ais supported is alternating 1s. (+1, -1, +1, -1, +1, ...) looping takes precedence over ais. 1 = ais mode enabled 0 = ais mode disabled ? 76 76 tais1 ? 49 63 tais2 transmit ch2 ais mode enable i ?? 49 tais3 transmit ch3 ais mode enable ? 53 53 53 e3mode e3mode i when the pin is set to high, it enables the e3 mode on all channels, instead of the ds3/sts-1 mode. this also changes the pulse shaper to e3 mode and overrides all lbo pins. it also changes the encoder/decoder from b3zs mode to hdb3 mode. 1 = e3 mode 0 = ds3/sts-1 mode 55 ?? lbo transmit line ch1 build-out mode i line build-out mode per channel, based on the length of cable on the transmit side of the cross-connect block. this bit is overridden and the pulse shaper is disabled (no pulse shaping) if e3mode = 1. 1 = inserts line build-out into the transmit channel. usually used when the transmit cable is less than 350 feet in length. 0 = line build-out bypassed (not inserted). usually used when the transmit cable is greater than 350 feet in length. ? 91 91 lbo1 ? 34 55 lbo2 transmit line ch2 build-out mode i ?? 34 lbo3 transmit line ch3 build-out mode i table 1-2. cx2833i-3x pin definitions (4 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-18 conexant 100985a 71 ?? lloop local loopback enable ch1 i local loopback enable per channel. the transmit data is looped back immediately from the encoder to the decoder in place of the received data. 1 = local loopback enabled 0 = local loopback disabled ? 93 93 lloop1 ? 32 71 lloop2 local loopback enable ch2 i ?? 32 lloop3 local loopback enable ch3 i 72 ?? rloop remote loopback enable ch1 i remote loopback enable per channel. the receive data, retimed after clock recovery, is looped back into the ami generator in place of the transmit data. 1 = remote loopback enabled 0 = remote loopback disabled ? 94 94 rloop1 ? 31 72 rloop2 remote loopback enable ch2 i ?? 31 rloop3 remote loopback enable ch3 i 56 ?? xoe transmit output enable ch1 i transmit output enable per channel. 1 = transmit line output driver enabled 0 = transmit output driver set to high impedance state ? 90 90 xoe1 ? 35 56 xoe2 transmit output enable ch2 i ?? 35 xoe3 transmit output enable ch3 i 57 ?? reqh ch1 receive high eq gain enable i the equalizer in the cx2833i has two gain settings. the higher gain setting is designed to optimally equalize a nominally-shaped (meets the pulse template), pulse-driven ds3 or sts-1 waveform that is driven through 0 ? 900 feet of cable. square-shaped pulses such as e3 or ds3-high require less high-frequency gain and should use the low eq gain setting. reqh = 1 high eq gain (ds3/sts-1 modes) reqh = 0 low eq gain (e3/ds3 square modes) ? 89 89 reqh1 ? 36 57 reqh2 ch2 receive high eq gain enable i ?? 36 reqh3 ch3 receive high eq gain enable i power/ground 15 ?? tvdd tx power ch1 p power pins for transmit circuitry per channel (3.3 v). 55tvdd1 ? 25 15 tvdd2 tx power ch2 p ?? 25 tvdd3 tx power ch3 p table 1-2. cx2833i-3x pin definitions (5 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-19 10 ?? tvss tx ground ch1 p ground pins for transmit circuitry per channel. ? 100 100 tvss1 ? 20 10 tvss2 tx ground ch2 p ?? 20 tvss3 tx ground ch3 p 16 ?? rvdd rx power ch1 p power pins for receive circuitry per channel (3.3 v). connect to 3.3 v power. ? 6 6 rvdd1 ? 26 16 rvdd2 rx power ch2 p ?? 26 rvdd3 rx power ch3 p 19 ?? rvss rx ground ch1 p ground pins for receive circuitry per channel. connect to ground. ? 9 9 rvss1 ? 29 19 rvss2 rx ground ch2 p ?? 29 rvss3 rx ground ch3 p 75 75 75 dvddc digital core power p digital core power for all channels (3.3 v). 51 51 51 dvssc digital core ground p digital core ground for all channels. 98 98 98 vgg 5 v/3.3 v esd pin (1) p 5 v supply for 5 v-tolerant, digital pad esd diodes. no static power is drawn from pin. 92 92 92 dvddio digital i/o power p connect to 3.3 v digital power. 33 33 33 dvssio digital ground p digital ground. 5, 6, 25, 26 15, 16 ? vdd power p connect to 3.3 v power. 9, 20, 29, 100 10, 19 ? vss ground p connect to ground. miscellaneous 73 ?? pd power down for ch1 i power down transceiver channel 0 = power down channel (off) 1 = channel active (on) note: a special power-down mode exists when all three pdbs are set low. this special mode shuts off the entire chip (including biasing). this is useful for static idd testing. ? 95 95 pd1 ? 30 73 pd2 power down for ch2 i ?? 30 pd3 power down for ch3 i table 1-2. cx2833i-3x pin definitions (6 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-20 conexant 100985a 58 ?? refclk reference clock for ch1 i reference clock from off-chip. this clock should be set to one of the following: e3 rate (34.368 mhz) ds3 rate (44.736 mhz) sts-1 rate (51.84 mhz) the clock rate should correspond to the mode of operation that has been chosen for the channel. ? 81 81 refclk1 ? 44 58 refclk2 reference clock for ch2 i ?? 44 refclk3 reference clock for ch3 i 99 80 99 rbias bias resistor o a 12.1 k ? 1% resistor tied from this pin to ground provides the current reference to the entire chip. (2) 97 97 97 reset reset i/o asynchronous reset (reset entire device). 96 96 96 gpd global power down i/o power down (static idd testing). 0 = power down disable 1 = power down active 11 ?? tmonp ch1 positive input i transmit monitor input pins are normally tied to their respective transmit line outputs, i.e., (tmon1p ? tline1p and tmon1m ? tline1m). loss of signal outputs are active high when the monitor inputs detect no signal. the tx monitor test pin will assert all tlos outputs when tmontst is high. this is used to test board level functionality downstream from the tlos outputs. ? 11tmon1p 14 ?? tmonm ch1 negative input i ? 44tmon1m ? 21 11 tmon2p ch2 positive input i ? 24 14 tmon2m ch2 negative input i ?? 21 tmon3p ch3 positive input i ?? 24 tmon3m ch3 negative input i 59 ?? tlos tx loss of signal ch1 output o ? 80 80 tlos1 ? 45 59 tlos2 tx loss of signal ch2 output o ?? 45 tlos3 tx loss of signal ch3 output o 54 54 54 tmontst tx monitor test pin i table 1-2. cx2833i-3x pin definitions (7 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
CX28331/cx28332/cx28333 1.0 pin description single/dual/triple e3/ds3/sts-1 line interface unit 1.1 pin assignments 100985a conexant 1-21 1 ? 4, 7, 8, 21 ? 24, 27, 28, 30 ? 32, 34 ? 50, 52, 64 ? 66, 76 ? 91, 93 ? 95 11 ? 14, 17 ? 18, 37 ? 39, 50, 52, 55 ? 73, 86 ? 88 37, 38, 39, 50, 64, 65, 66, 86, 87, 88 52 no connect ? not connected. note(s): (1) this pin should be connected to 3.3 v in an all-3.3 v design. (2) placing a capacitor from this pin to ground may result in instabilities. 3. all digital input pins contain a 75 k ? pull-down resistor from input to dvss. table 1-2. cx2833i-3x pin definitions (8 of 8) pin # signal name description i/o/p notes CX28331-3x cx28332-3x cx28333-3x
1.0 pin description CX28331/cx28332/cx28333 1.1 pin assignments single/dual/triple e3/ds3/sts-1 line interface unit 1-22 conexant 100985a
100985a conexant 2-1 2 2.0 functional description 2.1 overview cx28333 is a triple e3/ds3/sts-1 line interface unit (liu). it is the physical layer interface between the data framer (or other terminal-side equipment) and the electrical cable used for data transmission. the cx28333 liu consists of three independent data transceivers that can operate over type 734/728 coaxial cable at the rates of 34.368 mbps (e3), 44.736 mbps (ds3), and 51.84 mbps (sts-1). the transmit side takes an nrz or already-encoded dual rail input and encodes it into ami b3zs (for ds3/sts-1) or hdb3 (for e3) analog waveforms to be transmitted over the coaxial cable. the receiver side takes in the attenuated and distorted analog receive signal and equalizes, slices, and resynchronizes the signal before decoding it to the nrz output or sending out a non-decoded dual rail. CX28331 and cx28332 are single- and dual-e3/ds3/sts-1 lius, respectively. in all respects, their performance and features are identical to the cx28333. the architecture of the cx2833i includes the following internal functions for each channel: transmitter: ? ami b3zs/hdb3 encoder pulse shaper line driver alarm indication signal (ais) insertion transmit monitor receiver: receive sensitivity automatic gain control (agc) receive equalizer clock recovery circuit loss of signal (los) detector b3zs/hdb3 decoder with bipolar violation detector data squelching
2.0 functional description CX28331/cx28332/cx28333 2.1 overview single/dual/triple e3/ds3/sts-1 line interface unit 2-2 conexant 100985a additional functions: bias generator power-on reset loopback muxes in addition, each channel has the ability to perform remote and local loopbacks. figure 2-1 illustrates a typical application using the cx2833i in a channel. external pins are provided to configure the various line rates and formats for each channel. the cx2833i is used as a data transceiver over a coaxial cable that is up to 900 feet long (or up to 450 feet from the dsx) in an on-premise environment within any public or private networks which use these data rates. figure 2-1. typical application of single cx2833i channel 0 ? 450 ft coax (type 734/728) dsx 0 ? 450 ft coax (type 734/728) dsx 0 ? 450 ft coax (type 734/728) 0 ? 450 ft coax (type 734/728) tx rx rx tx 100604_012
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.2 transmitter 100985a conexant 2-3 2.2 transmitter this section describes the detailed operation of the various blocks in the cx2833i transmitter. 2.2.1 ami b3zs/hdb3 encoder endecdis and the e3mode pins configure the encoder mode. when endecdis = 0, the encoder is receiving non-encoded nonreturn to zero (nrz) data on the tnrz (tpos) pin alone, and the nc (no connect) (tneg) pin is ignored. data is encoded into a representation of a three-level b3zs (e3mode = 0) or hdb3 (e3mode = 1) signal (conforming to the coding rules as specified in appendix a ) before going on to the pulse shaper in the form of two binary signals representing the positive and negative three-level pulses. when endecdis = 1, the encoder is disabled. the encoder passes already-encoded data over tpos (tnrz) and tneg (nc) to the pulse shaper. the transmit digital data is clocked into the chip via a rising tclk edge, which must be equal to the symbol rate (line rate). a small delay added to the data provides a certain amount of negative data hold time. 2.2.2 pulse shaper the pulse shaper converts the two digital (clocked) positive and negative pulses into a single analog three-level alternate mark inversion (ami) pulse. the pulses are in return to zero (rz) format, meaning that all positive and negative pulses have a duration of the first half of the symbol period. for the e3 rate (e3mode = 1), the ami pulse is a full-amplitude, square-shaped pulse with very little slope. figure 2-2. pulse shaper 100604_008 pulse shaper lbo e3 mode lbo = 0 lbo = 1 + pulse ? pulse line driver
2.0 functional description CX28331/cx28332/cx28333 2.2 transmitter single/dual/triple e3/ds3/sts-1 line interface unit 2-4 conexant 100985a for ds3/sts-1 rates, a pulse-shaper block is used to shape the transmit waveform and reduce its high-frequency energy content. this ensures that the transmit pulse template is met at the cross-connect block, which follows 0 ? 450 feet of transmit-side coaxial cable. 2.2.3 line driver the differential line driver takes the filtered transmit waveform, increases it to the proper level, and drives it into the transmit magnetics. the two external discrete back-matching resistors (36 ? ) aid in line matching. the driver is presented with an approximately 150 ? differential load. driver gain accounts for the 6 db gain loss in the back-matching resistors. figure 2-3 illustrates the pulse/power template measurement points for the various data rates. figure 2-3. pulse measurement points 0 ? 450 ft coax (type 734/728) dsx 0 ? 450 ft coax pulse/power template for e3 pulse/power template for ds3/sts-1 (type 734/728) dsx 0 ? 450 ft coax (type 734/728) 0 ? 450 ft coax (type 734/728) tx rx rx tx 100604_013
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.2 transmitter 100985a conexant 2-5 2.2.3.1 transmit pulse mask templates figure 2-4. transmit pulse mask for ds3 rates transmit pulse mask for sts-1 rates 1 0.5 0 0.5 1 1.5 normalized symbol time normalized pulse amplitude 1.2 1 0.8 0.6 0.4 0.2 0 0.2 100985_014 table 2-1. ds3 transmit template specifications time axis range (ui) normalized amplitude equation upper curve ? 0.85 t ? 0.68 0.03 ? 0.68 t 0.36 0.03 + 0.5 {1 + sin [(pi / 2)(1 + t / 0.34)]} 0.36 t 1.4 0.08 + 0.407 e ? 1.84(t ? 0.36) lower curve ? 0.85 t ? 0.36 ? 0.03 ? 0.36 t 0.36 ? 0.03 + 0.5{1 + sin[(pi / 2)(1 + t / 0.18)]} 0.36 t 1.4 0.03
2.0 functional description CX28331/cx28332/cx28333 2.2 transmitter single/dual/triple e3/ds3/sts-1 line interface unit 2-6 conexant 100985a figure 2-5. transmit pulse mask for sts-1 rates transmit pulse mask for sts-1 rates 1 0.5 0 0.5 1 1.5 normalized symbol time normalized pulse amplitude 1.2 1 0.8 0.6 0.4 0.2 0 0.2 100985_014 table 2-2. sts-1 transmit template specifications time axis range (t) normalized amplitude equation upper curve ? 0.85 t ? 0.68 0.03 ? 0.68 t 0.26 0.03 + 0.5{1 + sin[(pi / 2)(1 + t / 0.34)]} 0.26 t 1.4 0.1 + 0.61 e ? 2.4(t ? 0.26) lower curve ? 0.85 t ? 0.38 ? 0.03 ? 0.38 t 0.36 ? 0.03 + 0.5{1 + sin[(pi / 2)(1 + t / 0.18)]} 0.36 t 1.4 0.03
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.2 transmitter 100985a conexant 2-7 figure 2-6. transmit pulse mask for e3 rate 100985_007 17 ns 0.1 0.1 0.1 0.1 0.1 0.2 0.2 14.55 ns 8.65 ns 12.1 ns 24.5 ns 29.1 ns time volts normalized
2.0 functional description CX28331/cx28332/cx28333 2.2 transmitter single/dual/triple e3/ds3/sts-1 line interface unit 2-8 conexant 100985a 2.2.4 alarm indication signal (ais) generator when tais is asserted, an ais replaces the transmit data at tpos and tneg. the e3 type of ais signal (all 1s) is supported. in three-level signal form, this is a continuously alternating positive and negative pulse stream, as if the transmit data were a continuous string of logical 1s. figure 2-7 illustrates the ais signal. the tais pin has the same data latency as the tx data pins and can be used to replace single symbols within a data stream. when the encoder is disabled (endecdis = 1), the tais mode maintains the proper phase, based upon the polarity of the last 1 received. the ais signal follows the same path as the tx data during remote or local loopback. 2.2.5 transmit monitor block (cx2833i-3x only) the transmit monitor inputs (tmonp and tmonm) are designed to monitor the line driver outputs (tlinep and tlinem/n) for pulses and to assert a loss of signal (tlos) indicator when no output pulse has been detected for 32 tclk periods. after tlos is asserted, it will not deassert until a pulse is again detected. the transmit monitor is an independent function in which tmonp and tmonm must be externally connected to tlinep and tlinem/n, respectively. a special pin (tmontst) is available for testing board-level functionality downstream from the tlos outputs. when tmonst is high it will assert all tlos channel outputs. tlos outputs are active high when the monitor inputs do not detect a signal. figure 2-7. ais signal positive pulse negative pulse tlinep (output voltage) tlinen (output voltage) 8333_009
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.2 transmitter 100985a conexant 2-9 2.2.6 jitter generation (intrinsic) the cx2833i device meets the jitter generation requirements for various rates with large margins, with the condition that the input transmit clock (tclk) is jitter-free. data rates and jitter generation requirements are defined in the following documents: e3 rate ? etsi tbr24 , itu-t 9.823 ds3 rate ? bellcore telecardia gr499 , at&t accunet tr54014, itu-t 9.824 sts-1 rate ? bellcore telecardia gr253
2.0 functional description CX28331/cx28332/cx28333 2.3 receiver single/dual/triple e3/ds3/sts-1 line interface unit 2-10 conexant 100985a 2.3 receiver this section describes the detailed operation of the various blocks in the cx2833i receiver. 2.3.1 receive sensitivity the receiver recovers data from the coaxial cable that is attenuated due to the frequency-dependent characteristics of the cable. in addition, the receiver compensates for the flat loss (across all frequencies) in the various electrical components and the variation in transmitted signal power. the cx2833i device is able to recover data that has been attenuated by a maximum of 900 feet of coax having characteristics and attenuation consistent with ansi t1.102-1993 , annex c, figure c.2. this approximates the characteristics of at&t type 734/728 cable; almost the same attenuation characteristic is achieved by one-half the length of at&t type 735 cable. 2.3.2 agc/vga block the variable gain amplifier (vga) receives the ami input signal from the coaxial cable. the vga supplies flat gain (independent of frequency) to make up for various flat losses in the transmission channel and for loss at one-half the symbol rate that cannot be made up by the equalizer. the vga gain is controlled by a feedback loop which senses the amplitude of the equalizer output, acting to servo this amplitude for optimal slicing. 2.3.3 receive equalizer the receive equalizer receives the differential signal from a vga and acts to boost the high frequency content of the signal to reduce inter-symbol interference (isi) to the point that correct decisions can be made by the slicer with a minimum of jitter in the recovered data. the reqh pin is provided to allow lower amounts of equalization (shorter equivalent cable lengths) for cases where a square-shaped pulse (that does not meet the ds3/sts-1 standards) is transmitted to the receiver. a square-shaped input has a much larger high-frequency content and could have overshoots at the eq output high enough to cause bit errors. setting reqh = 0 will lower the gain and reduce the amount of overshoot.
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.3 receiver 100985a conexant 2-11 2.3.4 the pll clock recovery circuit the clock recovery circuit (rx pll) extracts the embedded clock from the sliced data and provides this clock and the retimed data to the decoder (data mode). upon startup (after the internal reset is deasserted), the rx pll uses a reference clock (refclk, running at the symbol rate) and a phase-frequency detector to lock to the correct data rate (reference mode). during reference mode, the data outputs are squelched (set to 0). the rx pll is kept in reference mode until a valid input is detected. 2.3.5 loss of signal (los) detector the receive loss of signal (rlos) is a digital function which monitors the retimed data from the clock recovery block. the ami data is checked for a continuous run of zeroes. when a continuous run of 128 1 consecutive zeroes occurs, the rlos signal is asserted. after the rlos signal is asserted, a 1s count is made on every block of 128 ami symbols. the rlos signal is deasserted when the 1s count within a block of 128 symbols is at least: b3zs: minimum 1s density = 39 1 count out of 128 (~30.5%) hdb3: minimum 1s density = 29 1 count out of 128 (~22.7%) the rlos detector will always monitor the cable-side rx inputs. the detector is not affected by the state of remote or local looping. 2.3.6 b3zs/hdb3 decoder with bipolar violation detector in the cx2833i device, when endecdis = 0 (encoder/decoder enabled), the decoder takes the output from the clock recovery circuit and decodes the data (hdb3 or b3zs) into a single retimed nrz data signal. the data signal is then sent out of the cx2833i over the rnrz (rpos) pin. any detected line code violations (lcv) are sent out over the corresponding rlcv (rneg) pin. the rlcv pin is asserted for one symbol period at the time the violation appears on the rx output pin (rnrz). the following shows data sequence criteria for lcv; violations are indicated in bold text. a valid bipolar pulse is indicated by a b. a bipolar violation (non-alternating positive or negative) pulse is indicated by a v. excessive zeros: 0, 0, 0, 0 (hdb3) or 0, 0, 0 (b3zs). these violations are passed on as 0 data on the rnrz pin. bipolar violation: b, 0, v (i.e., +1, 0, +1 or -1, 0, -1 for hdb3) b, v (b3zs and hdb3). these violations are passed on as 1 data on the rnrz pin. coding violation: 0, 0, v (hdb3) or 0, v (b3zs) with an even number of bs since the last valid 0 substitution v (follows coding rule). these violations are passed on as 0 data on the rnrz pin. the even/odd counter (used to count the number of bs between vs) will count a bipolar violation as a b. a coding violation or a valid 0 substitution resets the counter.
2.0 functional description CX28331/cx28332/cx28333 2.3 receiver single/dual/triple e3/ds3/sts-1 line interface unit 2-12 conexant 100985a when endecdis = 1, the decoder is disabled, and the retimed slicer outputs are sent out over rpos (rnrz) and rneg (rlcv) pins. these outputs are then decoded by the framer or other downstream device. line code violations are not detected in this mode of operation. the decoder is configurable for either: e3 mode using hdb3 coding (e3mode = 1) ds3/sts-1 mode using b3zs coding (e3mode = 0) the receiver digital data outputs are centered on the rising edge of rclk (see section 2.9 ). 2.3.7 data squelching a counter in the receiver keeps track of the number of consecutive symbol periods without a valid data pulse. when 128 or more 0s in a row are counted, the receiver assumes that it has lost the signal and resets itself to try and regain the signal. while the receiver is reacquiring the signal, the clock recovery block locks to the reference clock and the data squelching is achieved by forcing the data bits to zero. the data squelching is true in both nrz and dual rail mode. when the input signal has been properly amplified and equalized, the clock recovery pll will then switch to the incoming data.
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.4 jitter tolerance 100985a conexant 2-13 2.4 jitter tolerance the cx2833i receiver is able to tolerate a specified amount of high-frequency jitter in the received signal while providing error-free operation (generally defined as a bit error rate of less than 10 -9 ). the specifications (illustrated in figure 2-9 ) for jitter tolerance are discussed in the following documents: e3 rate ? itu-t g.823 and etsi tbr24 contain frequency masks for input jitter tolerance. note: to meet jitter transfer requirements for loop-timed operation, an external jitter attenuator is required. the jitter attenuator lessens jitter from the receive clock. ds3 rate ? itu-t g.823 and bellcore gr499 specify jitter tolerance frequency masks for category i and category ii interfaces. sts-1 rate ? bellcore gr253 specifies a jitter tolerance. it is noted that the sts-1 jitter tolerance differs from ds3 requirements only for category ii interfaces.
2.0 functional description CX28331/cx28332/cx28333 2.4 jitter tolerance single/dual/triple e3/ds3/sts-1 line interface unit 2-14 conexant 100985a figure 2-8. minimum jitter tolerance requirement ds3 / sts-1 rates 1.0 ui 0.1 ui 1.0 ui 10 ui 0.1 ui jitter frequency jitter frequency input jitter amplitude input jitter amplitude e3 rate sts-1 ds3 category i ds3 category ii 100 hz 1 khz 10 khz 100 khz 1 mhz 10 hz 100 hz 10 khz 100 khz 1 khz 100604_014
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.4 jitter tolerance 100985a conexant 2-15 2.4.1 jitter transfer the receiver must meet certain jitter transfer specifications between the input and output jitter as a function of frequency. these specifications are only intended to be met with the use of a jitter attenuator. because the cx2833i does not contain a jitter attenuator, one will have to be supplied externally. for reference purposes, the specifications are discussed in the following documents and shown in figure 2-9 . e3 rate ? assume the same as ds3. ds3 rate ? bellcore gr499, section 7.3.2 and figures 7-3, 7-4, and 7-5, defines and describes ds3 jitter transfer. sts-1 rate ? bellcore gr253, section 5.6.2.1, defines and describes jitter transfer for the sts-1 rate. figure 2-9. maximum jitter transfer curve requirement 0.1 db jitter frequency jitter gain ? 19.9 db sts-1 category ii ds3 category i ds3 category ii (note: all slopes are 20 db/decade) 10 hz 100 hz 1 khz 10 khz 100 khz 100985_012
2.0 functional description CX28331/cx28332/cx28333 2.5 additional cx2833i functions single/dual/triple e3/ds3/sts-1 line interface unit 2-16 conexant 100985a 2.5 additional cx2833i functions 2.5.1 bias generator to achieve good isolation between the channels, each channel utilizes an independent power and ground to both transmit and receive. additionally, each channel has its own band gap voltage reference. because only one external resistor for current generation exists, only one band gap voltage can be used. the band gap from ch1 has been chosen for this task. the 12.1 k ? external resistor from pin rbias to ground, is specified to have a tolerance of 1%. this helps to keep tighter control on power dissipation and circuit performance. note: capacitance should be kept to a minimum on the rbias pin. 2.5.2 power-on reset (por) a por function is provided in the cx2833i device to ensure all of the resettable digital logic and analog control lines are starting from a known state. this circuit uses a fixed rc timer (~1 s); additionally, 128 clocks from refclk are counted (after the rc timer has timed-out) before reset is deasserted, which begins timing after a minimum supply voltage is reached (see table 2-4 ). 2.5.3 loopback multiplexers (muxes) two loopback muxes per channel in the cx2833i allow for local loopback (terminal or framer side), remote loopback (cable side), or both (the ais signal follows the same path as the transmit data during loopback). the rlos signal monitors the rx cable inputs irrespective of any loopback. in remote loopback, set by asserting pin rloop high, the receive data (retimed after clock recovery but not decoded) loops back into the pulse shaper in place of the transmit data. additionally, this data sent out the rpos, rneg, and rclk pins. in local loopback, set by asserting pin lloop, the transmit data loops back immediately from the encoder output to the decoder input in place of the received data. additionally, this data is sent out the tlinep and tlinem/n pins.
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.6 mechanical specifications 100985a conexant 2-17 2.6 mechanical specifications figure 2-10. cx2833i-1x mechanical drawing (80-pin)?dimensions d 3 d 3 d d 1 d 1 d 2 d d 1 d 2 a l a 1 l 1 a 2 pin #1 ref. mark eb see detail b top detail b bottom c dim. a a 1 a 2 d d 1 d 2 d 3 l l 1 b c e coplanarity 0.05 0.95 15.75 13.90 0.45 0.09 1.20 max. 12.35 ref. 6.50 ref. 1.00 ref. 0.32 ref. 0.65 ref. 0.10 max. 0.15 1.05 16.25 14.10 0.75 0.20 0.002 0.040 0.620 0.547 0.018 0.004 0.047 max. 0.486 ref. 0.256 ref. 0.039 ref. 0.013 ref. 0.026 ref. 0.004 max. 0.006 0.041 0.640 0.555 0.030 0.008 ref. 80-pin etqfp (gp00-d537) millimeters inches min. max. min. max. 100985_008
2.0 functional description CX28331/cx28332/cx28333 2.6 mechanical specifications single/dual/triple e3/ds3/sts-1 line interface unit 2-18 conexant 100985a figure 2-11. cx2833i-3x mechanical drawing (100-pin) ? dimensions d 3 d 3 d d 1 d 1 d 2 d d 1 d 2 a l a 1 l 1 a 2 pin #1 ref. mark eb see detail b top detail b bottom c dim. a a 1 a 2 d d 1 d 2 d 3 l l 1 b e c coplanarity 0.05 0.95 15.75 13.90 0.45 0.09 1.20 max. 12.00 ref. 8.00 ref. 1.00 ref. 0.22 ref. 0.50 ref. 0.08 max. 0.15 1.05 16.25 14.10 0.75 0.20 0.002 0.004 0.620 0.547 0.018 0.004 0.047 max. 0.472 ref. 0.315 ref. 0.039 ref. 0.009 ref. 0.020 ref. 0.004 max. 0.006 0.041 0.640 0.555 0.006 0.008 ref. 100-pin etqfp (gp00-d543)mm millimeters inches min. max. min. max. 100985_008a
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.7 electrical characteristics 100985a conexant 2-19 2.7 electrical characteristics 2.7.1 absolute maximum ratings table 2-3. absolute maximum ratings symbol parameter min max unit dvddc/ rvdd/ tvdd/ vdd power supply voltage ? 0.3 6 v v i voltage on any signal pin ? 1.0 vgg + 0.3 v v t st storage temperature ? 40 125 c t vsol vapor phase soldering temperature (1 min.) ? 220 c ja thermal resistance (still air, socketed) ? 40 c / w ja thermal resistance (still air, soldered) ? 24 c / w jc ?? 7.40 c / w fit failures in time @ 89,000 device hours, temperature of 55 c, 0 failures. ? 313 fits note(s): 1. stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the other sections of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.0 functional description CX28331/cx28332/cx28333 2.7 electrical characteristics single/dual/triple e3/ds3/sts-1 line interface unit 2-20 conexant 100985a 2.7.2 recommended operating conditions table 2-4 specifies various operating conditions, power supplies, and the bias resistor. table 2-4. recommended operating conditions parameter conditions min nom max unit power supply voltage dvddc, rvdd, tvdd, vdd 3.135 3.3 3.465 v esd voltage (1) vgg 3.135 5 5.5 v power dissipation (cx28333) total chip ? 0.83 1.0 w power dissipation (cx28332) total chip ?? 0.8 w power dissipation (CX28331) total chip ?? .450 w external bias resistor pin rbias to gnd; 1% 11.98 12.1 12.22 k ? note(s): (1) with 5 v logic input, vgg should be tied to 5 v. with 3.3 v logic input, vgg should be tied to 3.3 v.
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.8 dc characteristics 100985a conexant 2-21 2.8 dc characteristics table 2-5. dc characteristics parameter conditions min nom max unit v ih high threshold digital inputs 2.0 ? vgg + 0.3 v v il low threshold digital inputs ? 0.3 ? 0.8 v v oh high threshold digital outputs, i oh = ? 4 ma 2.4 ?? v v ol low threshold digital outputs, i ol = 4 ma ?? 0.4 v i leak 0 v digital vin vgg ? 10 ? 200 a input capacitance ??? 10 pf load capacitance digital outputs ?? 15 pf note(s): 1. the digital inputs of cx2833i are ttl 5 v compliant. these inputs are diode protected to dvddio and dvssio pins. additionally, all of the cx2833i digital inputs contain 75 k ? pull-down resistors. 2. the digital outputs of cx2833i are also ttl 5 v compliant. however, these outputs will not drive to 5 v, nor will they accept 5 v external pull-ups. the output is dvddc (3.3 v).
2.0 functional description CX28331/cx28332/cx28333 2.9 ac characteristics single/dual/triple e3/ds3/sts-1 line interface unit 2-22 conexant 100985a 2.9 ac characteristics table 2-6. ac characteristics (logic timing) parameter conditions min nom max unit tosym, tisym rclk and tclk e3 ds-3 sts-1 ? 29.10 22.35 19.29 ? ns ns ns clock duty cycle towidth/tosym, rclk tiwidth/tisym, tclk tiwidth/tisym, refclk 45 40 40 ? 55 60 60 % % % todelay ??? 3ns tisetup tpos/tnrz, tneg, tais 4 ?? ns tihold tpos/tnrz, tneg, tais 0 ?? ns note(s): 1. the description applies to the ds3, e3, and sts-1 clock rates and other parameters such as pulse width, set-up time, hold time, and duty cycle. 2. the timing diagram, illustrated in figure 2-12 , describes the logical relationship between various clock and data signals, and parameter values.
CX28331/cx28332/cx28333 2.0 functional description single/dual/triple e3/ds3/sts-1 line interface unit 2.9 ac characteristics 100985a conexant 2-23 figure 2-12. timing diagram tclk tpos/tnrz, tneg, tais, tisym tisetup tihold data inputs don't care valid data tiwidth rclk rpos/rnrz, rneg/rlcv tosym todelay data outputs towidth don't care 100604_016
2.0 functional description CX28331/cx28332/cx28333 2.9 ac characteristics single/dual/triple e3/ds3/sts-1 line interface unit 2-24 conexant 100985a
100985a conexant 3-1 3 3.0 applications the CX28331/cx28332/cx28333 can be used in a variety of applications. figure 3-1 illustrates an example of three ds3 lines being terminated by the cx28333. the data and clock are extracted and passed on to the framer chip for further data manipulation and user interface. it is important to employ high-frequency design techniques for the printed board layout. 3.1 pcb design considerations for cx2833i the cx28333 device is a triple liu operating at frequencies up to 52.84 mhz. the high-speed nature of the device calls for a careful design of the pcb using this device. some design considerations are outlined below. 3.1.1 power supply and ground plane a unified power plane with properly placed capacitors of the correct size will mitigate most power rail-related voltage transients. a properly placed bulk capacitor, where the power enters the board, with noise-bypassing capacitors at the power pins on the integrated circuits should be adequate. the noise-bypassing capacitors must be able to supply all the switching current. ferrite beads are used with power rails to filter the high-frequency noise. for every design, noise frequencies and levels are different. therefore, whether beads are necessary, and the effective frequency where they should operate, is difficult to determine. it is a good idea to provision for ferrite beads on the boards. the board trace from the cx28333 power supply pin to the noise-bypassing capacitor should be minimized. additionally, ground connections from the ground plane to the cx28333 ground pins and the noise-bypassing capacitor ground pins should be minimized. a unified ground plane is the best way to minimize ground impedance. most of the ground noise is produced by the return currents and power supply transients during switching. this effect is minimized by reducing the ground plane impedance.
3.0 applications CX28331/cx28332/cx28333 3.1 pcb design considerations for cx2833i single/dual/triple e3/ds3/sts-1 line interface unit 3-2 conexant 100985a 3.1.2 impedance matching it is critical that traces around the transformers and matching resistors be kept to a minimum length and, in the following cases, the trace impedance be matched to 75 ? with a 10% tolerance: the impedance from the bnc connector to the transformer the impedance from the transformer to the matching resistors 3.1.3 other passive parts the reference design uses the pulse t3001 extended temperature range 1:1 transformer for the coupling of the bnc connector to the device. the ferrite beads used to decouple the receive- and transmit-vdd pins on all analog input vdd pins are type 2508056017y0 from fair-rite products corporation. the bulk capacitor used for where the power enters the board should be a tantulum ? type capacitor, the recommended value and type is a 220 f tantulum capacitor. 3.1.4 ibis models ibis (input/output buffer interface specification) models for the CX28331/cx28332/cx28333-1x and -3x are available from conexant ? s web site (www.conexant.com). 3.1.5 recommended vendors product: transformers product: ferrite beads america address: telo: fax: pulse corporate office 12220 world trade drive san diego, ca 92128 858-674-8100 858-674-8262 telo: web site: fair-rite products corp. p. o . b o x j one commercial row wallkill, ny 12589 914-895-2055 www.fair-rite.com northern asia telo: pulse 3f-4, no. 81, sec. 1 hsin tai wu road hsi-chih tapei hsien, taiwan r.o.c. 886-2-26980228 886-2-26980948 product: crystals northern europe telo: fax: pulse 1s2 huxley road the surrey research park guildford, surrey gu2 5re united kingdom 44-1483-401700 44-1483-401701 telo: fax: e-mail: web site: crystek corp. 12730 commonwealth drive fort myers, fl 33913 800-237-3061 941-561-1025 sales@crystek.com www.crystek.com
CX28331/cx28332/cx28333 3.0 applications single/dual/triple e3/ds3/sts-1 line interface unit 3.1 pcb design considerations for cx2833i 100985a conexant 3-3 figure 3-1. note(s): 1. all transformers are part number t3001 from pulse technology. see recommended vendors, section 3.1.5 . 2. tmonp and tmonm are only available on the cx2833i-3x device and are denoted by dotted lines. tx tpos tneg tclk tlinep tlinen rx rlinep rneg rlinen rpos rclk mode bias reset channel 1 cx28333 framer 37.4 w 37.4 w 31.6 w 31.6 w 0.01f 1:1 1:1 type 728, 734, 735 75 w type 728, 734, 735 75 w tx tpos tneg tclk tlinen rx rlinep rneg rlinen rpos rclk mode bias reset channel 2 tlinep tlinep tmonp tmonm tmonp tmonm tmonp tmonm framer 37.4 w 37.4 w 31.6 w 31.6 w 0.01f 1:1 1:1 type 728, 734, 735 75 w type 728, 734, 735 75 w tx tpos tneg tclk tlinen rx rlinep rneg rlinen rpos rclk mode bias reset channel 2 framer 37.4 w 37.4 w 31.6 w 31.6 w 0.01f 1:1 1:1 type 728, 734, 735 75 w type 728, 734, 735 75 w mode bias reset rbias 12.1k w mode/status pins 100985_009
3.0 applications CX28331/cx28332/cx28333 3.1 pcb design considerations for cx2833i single/dual/triple e3/ds3/sts-1 line interface unit 3-4 conexant 100985a
100985a conexant a-1 a appendix a a.1 applicable standards the applicable standards documents are as follows: ansi t1.102-1993 (ds3 and sts-1 standard) ansi t1.404a-1996 (ds3 metallic interface) itu recommendation g.703 (ds3 and e3 standard) itu recommendation g.823 and g.824 (jitter and wander) bellcore gr499 , issue 1, 12/89 (formerly tr-tsy-000499 ) (ds3 and sts-1 requirements) bellcore gr253 , issue 2, 12/91 (formerly ta-nwt-000253 ) (sts-1 requirements and jitter) bellcore tr-tsy-000191 , issue 1, 5/86 (ais and los) etsi tbr24 and tbr25 (e3 terminal equipment interface) etsi ets 300 686 and ets 300 687 (e3 standard) at&t technical reference tr54014 , may 1992 (accunet interface specification for ds-3 jitter only)
appendix a CX28331/cx28332/cx28333 a.1 applicable standards single/dual/triple e3/ds3/sts-1 line interface unit a-2 conexant 100985a
100985a conexant b-1 b appendix b b.1 evaluation module schematic
appendix b CX28331/cx28332/cx28333 b.1 evaluation module schematic single/dual/triple e3/ds3/sts-1 line interface unit b-2 conexant 100985a figure b-1. recommended schematic for the cx2833i-1x device position 7 reqh(1=enable equalization 0=disable) pin 2 e3mode 1=e3 mode is enabled 0=disabled pin 1 endecdis 1=dual rail pulse coded data format socket socket channel 3 receive channel 3 transmit channel 2 receive decoder and e3 selection channel 1 receive channel 1 transmit channel 2 transmit position 1 pdb powerdown (0=powerdown 1=active) position 2 rloop (1=remote lpbk enabled 0=disabled) position 3 lloop (1=local loop enabled 0=disabled) position 4 lbo (1=tx cable less than 250ft 0=greater than 250ft) position 5 xoe (1=transmitter enabled 0=disabled) position 6 tais (1=enable ais operation 0=disable) digital gnd bnc bnc bnc bnc bnc cc cc cc cc cc cc cc bnc cc analog gnd cc cc cc cc cc cc cc 2 pin dip switch setting seven position dip switch settings for all channels cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ch1_los ch2_los ch3_los 7 8 9 6 5 4 3 2 12 11 10 1 sw5 n1 t3001 pulse 1 2 34 5 6 l2 t3001 pulse 1 2 34 5 6 l3 1 2 34 5 6 t3001 pulse 6 5 4 3 2 1 l4 1 2 34 5 6 t3001 pulse 6 5 4 3 2 1 l5 1 2 34 5 6 t3001 pulse 1 2 34 5 6 l6 j2 j3 j4 j5 j6 r3 37.4 37.4 r4 r7 37.4 37.4 r8 0.01 c2 r11 37.4 0.01 c3 r12 37.4 j1 t3001 pulse 6 5 4 3 2 1 l1 1 23 4 4 3 2 1 sw4 j8 j9 j10 14 8 7 1 y1 2 1 cr3 c1 0.01 31.6 r1 r2 31.6 31.6 r5 31.6 r9 31.6 r10 l15 l7 l11 l10 c4 0.1 0.1 c5 r6 31.6 l13 l12 c6 0.1 0.1 c7 l14 c8 0.1 12.1k r13 cr1 12 cr2 sw9 c9 0.1 5 10 3 4 6 8 9 11 1 2 7 13 12 14 sw1 5 10 3 4 6 8 9 11 1 2 7 13 12 14 sw2 5 10 3 4 6 8 9 11 1 2 7 13 12 14 sw3 r14 402 402 r15 402 r16 1/4 42.2 r17 c10 0.1 l16 l17 c11 0.1 60 73 41 28 43 59 31 72 44 29 74 56 27 76 58 25 80 67 53 34 65 47 36 70 46 7 6 15 14 23 22 75 57 26 66 52 35 69 55 32 68 54 33 5 13 21 8 16 24 61 51 40 62 3 2 11 10 19 18 78 77 42 64 63 49 38 4 12 20 1 9 17 79 71 45 30 80 etqfp cx28333 50 48 39 37 u1 0.1 c12 c13 0.1 2 3 1 j7 tais3/tmuxa4 xoe3 lbo3 lloop3 pdb3 rloop3 +3_3v tais1/tmuxa2 xoe1 lbo1 lloop1 pdb1 rloop1 +3_3v rlos1 rlos2 rlos3 gnd nc out vcc +3_3v +3_3v +3_3v +3_3v +3_3v +3_3v +3_3v +5v tmuxio1 tmuxio2 pdb1 rloop1 lloop1 lbo1 xoe1 reqh1/tmuxdat rneg1/rlcv1 rpos1/rnrz1 rclk1 rlos1 refclk tneg1/nc1 tpos1/tnrz1 tclk1 tais1/tmuxa2 pdb2 rloop2 lloop2 rneg2/rlcv2 rpos2/rnrz2 rclk2 rlos2 tais2/tmuxa3 tpos2/tnrz2 refclk reqh2/tmuxa0 xoe2 lbo2 tmuxlat pdb3 rloop3 lloop3 lbo3 xoe3 reqh3/tmuxa1 rneg3/rlcv3 rpos3/rnrz3 rclk3 rlos3 refclk tpos3/tnrz3 tais3/tmuxa4 +3_3v +3_3v +3_3v +3_3v +3_3v rloop2 pdb2 lloop2 lbo2 xoe2 tais2/tmuxa3 e3mode endecdis endecdis e3mode reqh1/tmuxdat reqh2/tmuxa0 reqh3/tmuxa1 tmuxlat refclk +3_3v dvdd dvdd2 dvss dvss2 e3mode endecdis reqh3/tmuxa1 lbo1 lbo2 lbo3 lloop1 lloop2 lloop3 pdb1 pdb2 pdb3 rbias rclk1 rclk2 rclk3 refclk1 refclk2 refclk3 reqh1/tmuxdat reqh2/tmuxa0 rline1m rline1p rline2m rline2p rline3m rline3p rloop1 rloop2 rloop3 rlos1 rlos2 rlos3 rneg1/rlcv1 rneg2/rlcv2 rneg3/rlcv3 rpos1/rnrz1 rpos2/rnrz2 rpos3/rnrz3 rvdd1 rvdd2 rvdd3 rvss1 rvss2 rvss3 tais1/tmuxa2 tais2/tmuxa3 tais3/tmuxa4 tclk1 tline1m tline1p tline2m tline2p tline3m tline3p tmuxio1 tmuxio2 tmuxlat tneg1/nc1 tpos1/tnrz1 tpos2/tnrz2 tpos3/tnrz3 tvdd1 tvdd2 tvdd3 tvss1 tvss2 tvss3 vgg xoe1 xoe2 xoe3 tclk2 tneg2/nc2 tclk3 tneg3/nc3 tclk2 tneg2/nc2 tclk3 tneg3/nc3 +3_3v reqh2/tmuxa0 reqh3/tmuxa1 tais1/tmuxa2 tais2/tmuxa3 tais3/tmuxa4 reqh1/tmuxdat 100985_017
CX28331/cx28332/cx28333 appendix b single/dual/triple e3/ds3/sts-1 line interface unit b.1 evaluation module schematic 100985a conexant b-3 figure b-2. recommended schematic for the cx2833i-3x device (1 of 2) nc gnd out vcc socket ch1_rlos ch2_rlos ch3_rlos position 7 reqh# ( 0 =eq disable 1 = eq enable) position 5 xoe# ( 0 = tx disable 1 = tx enable) position 2 r loop# ( 0 = rlpbk disable 1 = rlpbk enable) position 3 lloop# ( 0 = lpbk disable 1 = lpbk enable) position 4 lbo# ( 0 = tx cable > 250ft 1 = tx cable < 250ft) position 6 t ais# ( 0 =tx ais disable 1 = tx ais enable) position 1 pdb# ( 0 = powerdown 1 = active) notes: seven position dip switch for all channels (sw1,2,3) cx28333 ds3/e3/sts-1 liu ch1_tlos ch2_tlos ch3_tlos pulse pulse pulse pulse pulse pulse 2,3,4 2,3,4 2,3,4 2,3,4 2,3,4 2,3,4 note: all capacitors are in microfarads reset device bt01-d 630- a cx 28333 (liu) w/jitter attenuator circuit conexant systems 9868 scranton road san diego,ca 92121 c 12 title size document number rev date: sheet of pd3 rloop3 e3mode endecdis refclk refclk rpos1/rnrz1 reqh1/tmuxdat tclk3 rlos3 lloop1 xoe1 tmuxio2 rclk1 lbo3 reqh3/tmuxa1 lloop3 tais3/ tmuxa4 lbo3 xoe3 pd2 rloop2 lloop2 lbo2 xoe2 tais2/tmuxa3 reqh2/tmuxa0 rneg1/rlcv1 rloop1 rclk3 reqh3/tmuxa1 reqh2/tmuxa0 rpos2/rnrz2 tais2/ tmuxa3 lbo2 e3mode tlos2 tmuxlat rneg2/rlcv2 rloop2 xoe2 tneg1/nc1 refclk tpos2/tnrz2 tneg2/nc2 xoe3 rclk2 tneg3/nc3 rloop3 tlos1 rpos3/rnrz3 tpos3/tnrz3 pd1 rlos1 refclk pd3 tmuxio1 rneg3/rlcv3 lloop2 tclk2 tais3/tm uxa4 lloop3 rlos2 tlos3 tpos1/tnrz1 tclk1 tais1/ tmuxa2 pd1 lbo1 reqh1/tmuxdat lloop1 tais1 /tmuxa2 rloop1 lbo1 xoe1 endecdis pd2 reqh1/tmuxdat reqh2/tmuxa0 reqh3/tmuxa1 tais1/tmuxa2 tais2/tmuxa3 tais3/tmuxa4 rlos1 rlos2 rlos3 tlos1 tlos3 tlos2 tmuxio1 tmuxlat tneg1/nc1 tpos1/tnrz1 rclk1 rneg1/rlcv1 rpos1/rnrz1 rloop1 lloop1 lbo1 xoe1 tais1/tmuxa2 reqh1/tmuxdat rloop3 refclk tclk3 tpos3/tnrz3 tneg3/nc3 rclk3 rpos3/rnrz3 rneg3/rlcv3 lloop3 lbo3 pd3 xoe3 tais3/tm uxa4 reqh3/tmuxa1 pd2 rloop2 lloop2 lbo2 xoe2 tais2/tm uxa3 reqh2/tmuxa0 e3mode tmuxio1 tmuxio2 pd1 tmuxlat tneg2/nc2 tpos2/tnrz2 tclk2 rclk2 rpos2/rnrz2 rneg2/rlcv2 tclk1 +3.3v +3.3v +5v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v l6 t3001 1 6 3 4 5 2 j5 channel 3 transmit 1 2 r17 42.2 l11 bead j1 channel 1 transmit 1 2 cr1 sw1 chn 1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 tmon1p tline1p tline1m tmon1m tvdd1 rvdd1 rline1p rline1m rvss1 tvss2 tmon2p tline2p tline2m tmon2m tvdd2 rvdd2 rline2p rline2m rvss2 tvss3 tmon3p tline3p tline3m tmon3m tvdd3 rvdd3 rline3p rline3m rvss3 pd3 rloop3 lloop3 dvssio lbo3 xoe3 reqh3 n/c1 n/c2 n/c3 rneg3/rlcv3 rpos3/rnrz3 rclk3 rlos3 refclk3 tlos3 tneg3/nc3 tpos3/tnrz3 tclk3 tais3 n/c4 dvssc nc11 e3mode tmontst lbo2 xoe2 reqh2 refclk2 tlos2 tneg2/nc2 tpos2/tnrz2 tclk2 tais2 n/c5 n/c6 n/c7 rlos2 rclk2 rpos2/rnrz2 rneg2/rlcv2 lloop2 rloop2 pd2 endecdis dvddc tais1 tclk1 tpos1/tnrz1 tneg1/nc1 tlos1 refclk1 rlos1 rclk1 rpos1/rnrz1 rneg1/rlcv1 n/c8 n/c9 n/c10 reqh1 xoe1 lbo1 dvddio lloop1 rloop1 pd1 gpd reset vgg rbais tvss1 cr2 r23 1k r3 37.4 sw2 chn 2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 j6 channel 3 receive 1 2 cr3 red led c3 0.01 jp6 1 2 l13 bead c9 0.1 jp7 1 2 1 j21 c8 0.1 c6 0.1 jp8 1 2 r9 31.6 sw9 1 4 2 3 r5 31.6 l10 bead l2 t3001 1 6 3 4 5 2 c5 0.1 l5 t3001 1 6 3 4 5 2 c13 .1 r10 31.6 r6 31.6 c4 0.1 r4 37.4 r22 1k r7 37.4 r36 1k l4 t3001 1 6 3 4 5 2 y1 44.736/34.368/51.256mhz +/- 2 0ppm 7 8 14 1 r25 1k jp9 1 2 jp10 1 2 l3 t3001 1 6 3 4 5 2 c10 0.1 jp11 1 2 r12 37.4 j3 channel 2 transmit 1 2 r18 0 sw4 1 2 4 3 r60 402 r52 0 r8 37.4 c1 0.01 j4 channel 2 receive 1 2 r1 31.6 r61 402 r62 402 l16 bead r13 12.1k cr60 r19 0 r53 0 r14 402 cr61 l14 bead c12 0.1 c11 0.1 r15 402 cr62 red led sw7 1 2 3 4 5 6 12 11 10 9 8 7 r16 402 r24 1k r11 37.4 l12 bead r2 31.6 l15 bead c7 0.1 c2 0.01 l17 bead j2 channel 1 receive 1 2 sw3 chn 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 r20 0 l1 t3001 1 6 3 4 5 2 1 j7 r21 0 sw10 1 4 2 3 100985_010
appendix b CX28331/cx28332/cx28333 b.1 evaluation module schematic single/dual/triple e3/ds3/sts-1 line interface unit b-4 conexant 100985a figure b-3. recommended schematic for the cx2833i-3x device (2 of 2) 25v + 1 square inch copper plane used for heat sink optional external 3.3v supply please remove jp3 when in use conexant conexant jitter jitter attenuator attenuator bt01-d 630- a cx 28333 (liu) w/jitter attenuator evualation module conexant systems 9868 scranton road san diego,ca 92121 c 22 title size document number rev date: sheet of reqh1/tmuxdat reqh2/tmuxa0 reqh3/tmuxa1 tais2/tmuxa3 tais3/tmuxa4 tais1/tmuxa2 pd1 lloop1 pd2 lloop2 lbo2 tais2/tmuxa3 pd3 lloop3 lbo3 reqh1/tmuxdat reqh3/tmuxa1 rloop1 e3mode xoe1 rloop2 xoe2 rloop3 xoe3 reqh2/tmuxa0 tmuxlat tmuxio1 tmuxio2 lbo1 tais1/tmuxa2 tdi vco1 vco1_cntrl vco1_cntrl djatclk1 vco2 vco2_cntrl vco3 vco3_cntrl vco2_cntrl djatclk2 djatclk3 vco3_cntrl channel3_status channel1_status tais3/tmuxa4 +5vsrc tmuxlat tneg1/nc1 rneg1/rlcv1 rclk1 tclk1 tpos1/tnrz1 tclk2 rpos1/rnrz1 rclk2 tpos2/tnrz2 rpos2/rnrz2 tneg2/nc2 rneg2/rlcv2 tclk3 rclk3 tpos3/tnrz3 rpos3/rnrz3 tneg3/nc3 rneg3/rlcv3 refclk djatclk1 djatclk2 djatpos2 djatpos1 djatneg1 djatneg2 djatclk3 djatpos3 djatneg3 channel2_status tdi rpos3/rnrz3 rpos2/rnrz2 djatneg2 rpos1/rnrz1 djatneg3 djatpos2 channel3_status djatpos3 tms djatneg1 djatpos1 channel2_status channel1_status vco1 tdo tck rclk3 djatclk2 djatclk1 rclk2 djatclk3 rneg2/rlcv2 rneg1/rlcv1 vco2 tck tdo tms rclk1 rneg3/rlcv3 vco3 pd1 rloop1 lloop1 lbo1 pd2 lloop2 lbo2 lloop3 lbo3 tais1/tmuxa2 xoe1 rloop2 xoe2 rloop3 xoe3 reqh1/tmuxdat tais3/ tmuxa4 tais2/ tmuxa3 tais1/ tmuxa2 reqh3/tmuxa1 reqh2/tmuxa0 tmuxlat pd3 e3mode tmuxio1 tmuxio2 reqh3/tmuxa1 reqh1/tmuxdat tais2/tmuxa3 reqh2/tmuxa0 tmuxlat tais3/ tmuxa4 tclk1 rpos1/rnrz1 tneg1/nc1 rneg1/rlcv1 tclk2 rclk2 tpos2/tnrz2 rpos2/rnrz2 tneg2/nc2 rneg2/rlcv2 tclk3 rclk3 tpos3/tnrz3 rpos3/rnrz3 tneg3/nc3 rneg3/rlcv3 refclk rclk1 tpos1/tnrz1 +3.3v +3.3v +3.3v +3.3v +5v +3.3v +3.3v +3.3v +3.3v y3 vco dijitck2 7 8 14 1 j23 black- banana - jack d14 diode j24 blue banana - jack y4 vco dijitck3 7 8 14 1 r34 1meg c26 10 jp2 header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 jp3 header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 jp1 header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 c20 0.1 j12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 c18 0.1 r40 330 c19 0.1 c21 220 1 j15 j20 12 34 56 78 910 r27 330 cr13 green led r28 330 r35 1meg c15 0.1 c22 10 c14 0.1 u2 lt1086 -3.3 1 3 2 gnd vin vout c24 0.1 c29 .1 u3 144 pin - tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 rpos3 rpos2 gnd_1 tdi nc/1 nc/2 nc/3 nc/4 nc/5 rpos1 nc/6 djatneg2 gnd_2 nc/7 djatneg3 djatpos2 gnd_3 status3 djatpos3 tms nc/8 nc/9 nc/10 vccio_1 djatneg1 djatpos1 status2 nc/11 nc/12 nc/13 nc/14 nc/15 gnd_4 nc/16 nc/17 nc/18 nc/19 nc/20 nc/21 nc/22 nc/23 nc/24 nc/25 nc/26 nc/27 nc/28 nc/29 nc/30 nc/31 vccio_2 vcci_1 gnd_5 nc/32 vco3 nc/33 nc/34 gnd_6 vcci_2 gnd_7 nc/35 nc/36 nc/37 nc/38 gnd_8 nc/39 nc/40 nc/41 nc/42 nc/43 nc/44 nc/45 nc/46 nc/73 nc/72 nc/71 gnd_10 tdo nc/70 nc/69 nc/68 nc/67 nc/66 nc/65 nc/64 nc/63 vccio_5 nc/62 nc/61 status1 vco1 nc/60 tck nc/59 nc/58 nc/57 gnd_9 nc/56 nc/55 nc/54 nc/53 nc/52 nc/51 nc/50 nc/49 vccio_4 nc/48 nc/47 vccio_3 vccio_7 rneg1 nc/89 rneg2 nc/88 nc/87 nc/86 djatck3 rclk2 gnd_15 djatck1 rclk1 rneg3 djatck2 vcci_4 gnd_14 gnd_13 rstn gnd_12 rclk3 gnd_11 vcci_3 nc/85 nc/84 nc/83 nc/82 nc/81 nc/80 nc/79 vccio_6 vco2 nc/78 nc/77 nc/76 nc/75 nc/74 c25 0.1 r38 1meg c28 .1 c23 0.1 r32 1meg r37 1meg c16 0.1 1 j14 j22 red - banana - jack r33 1meg j13 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 41 43 45 47 49 51 53 55 57 59 c27 .1 c17 0.1 r26 1meg y2 vco dijitck1 7 8 14 1 jp5 1 2 jp4 1 2 100985_011

further information: literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road, p.o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u.s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2 827 0181 fax: (852) 2 827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 4) 93 00 33 35 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p.o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371 1567 fax: (81 3) 5371 1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0 . 0 sa l es offi ces

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