View BR24C21FFJFV_1400391.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

br24c21 / br24c21f / br24c21fj / br24c21fv memory ics id rom for crt display br24c21 / br24c21f / br24c21fj / br24c21fv the br24c21 series are 1kbits serial eeproms and support ddc1 tm and ddc2 tm interfaces for plug & play displays. ! features 1) 128 x 8 bits serial eeprom 2) operating voltage range (2.5v 5.5v) 3) completely implements ddc1 tm / ddc2 tm interface for monitor identification transmit-only mode recovery mode bi-directional mode 4) page write function : 8 bytes 5) low current consumption active (at 5v) : 1.5ma (typ.) standby (at 5v) : 10 a (typ.) 6) data security write enable feature inhibit to write at low vcc 7) compact packages 8) high reliability fine pattern cmos technology 9) rewriting possible up to 100,000 times 10) data can be stored for ten years without corruption 11) noise filters at scl, sda and vclk pins ! ! ! ! absolute maximum ratings (ta=25 c) parameter symbol limits unit supply voltage ? 0.3 ~ + 6.5 v power disssipation mw storage temperature range ? 65 ~ + 125 c operating temperature range c terminal voltage ? v ? 40 ~ + 85 v cc ? 0.3 ~ v cc + 0.3 pd tstg topr ? 1 450(sop8) 800(dip8) ? 2 ? 2 450(sop-j8) ? 3 350(ssop-b8) ? 1 degradation is done at 8.0mw/ c for operation above 25 c. ? 2 degradation is done at 4.5mw/ c for operation above 25 c. ? 3 degradation is done at 3.5mw/ c for operation above 25 c. ! ! ! ! recommended operating conditions (ta=25 c) parameter symbol limits unit supply voltage v input voltage v in v v cc 0 ~ v cc 2.5 ~ 5.5
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics ! ! ! ! block diagram 1 n.c. n.c. 2 n.c. 3 gnd 4 v cc 8 vclk 7 6 scl sda 5 1kbits eeprom array control logic high voltage generator vcc level detecter 7bits 8bits ack stop start address decoder slave word address register 7bits data register ! ! ! ! pin assignment br24c21 br24c21f br24c21fj br24c21fv v cc n.c. vclk n.c. scl n.c. sda gnd 1234 5 6 7 8 ! ! ! ! pin descriptions 5 6 serial clock input for bi-directional mode 7 8 1 no connection 4 i / o pin no. scl n.c. gnd pin name function ? 2 no connection n.c. ? 3 no connection n.c. ? power supply v cc ? ? i clock input (transmit-only mode) write enable (bi-directional mode) vclk i ground (0v) sda i / o slave and word address, serial data input, serial data output ? an open drain output requires a pull-up resistor. ?
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics ! ! ! ! electrical characteristics (unless otherwise noted, ta= ? 40 85 c, v cc =2.5 5.5v) parameter symbol min. typ. max. unit conditions v ih1 ?? v v il1 ?? 0.3v cc v v ol ?? 0.4 v input leakage current i li ? 1 a scl, vclk, v in = 0v ~ v cc output leakage current i lo ? 1 ? 1 ? 1 a operating current i cc ? 3.0 ma standby current i sb ? ? 10 100 a 0.7v cc scl, sda scl, sda sda, i ol = 3.0ma v cc = 5.5v, f scl = 400khz sda, v out = 0v ~ v cc "high" input volatge1 "low" input volatge1 v ih2 ?? v v il2 ?? 0.8 v 2.0 vclk, v cc 4.0v vclk "high" input volatge2 "low" input volatge2 v il3 ?? 0.2v cc v vclk, v cc < 4.0v "low" input volatge3 "low" output volatge v cc = 5.5v, sda = scl = v cc , vclk = gnd ? 1 ? 1 transmit-only mode after the power is on, the br24c21, br24c21f, br24c21fj and br24c21fv are in standby state without providing the clock on the v clk pin. after the vclk pin is provided the clock, the device is switched from standby to transmit-only mode, and the operating current runs. bi-directional mode the br24c21, br24c21f, br24c21fj and br24c21fv are in standby state after each command is porformed. ! ! ! ! operating timing characteristics (unless otherwise noted, ta= ? 40 85 c, v cc =2.5 5.5v) parameter symbol fast-mode vcc = 2.5~5.5v standard-mode vcc = 2.5~5.5v unit f scl khz t high noise erase valid time (scl and sda) t i s data clock "high" time scl frequency s data clock "low" time t low s sda/scl rise time t r s sda/scl fall time t f s start condition hold time t hd : sta s start condition setup time t su : sta s input data hold time t hd : dat ns input data setup time t su : dat ns output data delay time (scl) t pd s stop condition setup time t su : sto s bus open time before start or transfer t buf s t wr min. ? 0.6 ? 1.3 ? ? 0.6 0.6 0 100 ? 0.6 1.3 ? typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 400 ? 0.1 ? 0.3 0.3 ? ? ? ? 0.9 ? ? 10 min. ? 4.0 ? 4.7 ? ? 4.0 4.7 0 250 ? 4.0 4.7 ? typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 100 ? t vhigh vclk "high" time s 0.6 ?? 4.0 ?? 0.1 ? 1.0 0.3 ? ? ? ? 3.5 output data delay time (vclk) t vpd s ? ? 1.0 ? ? 2.0 ? ? 10 ms internal write cycle time noise erase valid time (vclk) t vi s < transmit-only mode > vclk "low" time t vlow s transmit-only powerup time t vpu s vclk hold time t vhd s vclk setup time t vsu s ? 1.3 0 0.6 0 ? ? ? ? ? 0.1 ? ? ? ? ? 4.7 0 4.0 0 ? ? ? ? ? 0.1 ? ? mode transition time t vhz s ? ? 0.5 ? ? 1.0 ? ?
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics ! ! ! ! timing charts synchronous data timing t buf t pd t high t hd : sta t low t f t r scl start bit stop bit scl sda t su : dat t hd : dat t su : sto t hd : sta t su : sta sda (out) sda (in) fig.7 ? sda data is latched into the chip at the rising edge of the scl clock. ? output data toggles at the falling edge of the scl clock. write cycle timing ack d0 (n) t wr sda scl start condition stop condition write data fig.8 write enable timing fig.9 sda t vsu t vhd write command vclk scl start bit stop bit
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics ! ! ! ! circuit operation the br24c21, br24c21f, br24c21fj and br24c21fv operate in two modes, transmit-only mode and bi-directional mode. the devices operate in transmit-only mode when they will power up. in this mode, the devices transmit data on the sda pin with the vclk clock. this mode is continued by providing a valid high to low transition on the scl pin. the devices can be switched into bi-directional mode by providing a valid high to low transition on the scl pin. they begin to count the vclk clock at once. if the vclk counter reaches 128 clock without the command for bi-directional mode, the device revert to transmit-only mode. (recovery function) if the devices are received the command for bi- directional mode and respond with an acknowledge before the vclk counter reaches 128 clock, it is impossible to revert to transmit-only mode. (the way to switch bi-directional mode to transmit-only mode is that the power down again.) * when the power is on, the scl pin set to v cc (high level). (1) transmit-only mode ? after the power is on, the br24c21, br24c21f, br24c21fj and br24c21fv are in transmit-only mode. in this mode, the data can be output by providing the clock on the vclk pin. ? when the power is on, the scl pin set to v cc (high level). ? the state of sda is high-impedance during input of the first 9 clocks, and a data is output starting with the 10th rising clock edge on vclk. after the power is on, the output data is as follow 00h address data 01h address data 02h address data the address is incremented by one with every 9 clock of vclk. all address is output in this mode. when the counter reaches the last address, the next output data is 00h address data. ? in the mode, the null bit (high data) is output between the address data and the next address data. ? the read operation in transmit-only mode can be started after the power stabilized. fig.10 transmit-only mode 00h address data sda vclk scl v cc t vpu d3 d4 d5 d6 d7 1910 fig.11 null bit address n data address n+1 data null bit data=1 sda vclk d1 d0 d7 d6 t vpd t vhigh t vlow
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics (2) bi-directional mode 1) bi-directional mode and recovery function ? the br24c21, br24c21f, br24c21fj and br24c21fv can be switched from transmit-only mode to bi-directional mode by providing a valid high to low transition on the scl pin, and the state of sda is high-impedance. ? after a valid high to low transition on the scl pin, the br24c21, br24c21f, br24c21fj and br24c21fv begin to count the vclk clock. if the vclk counter reaches 128 clock without the command for bi-directional mode, the device revert to transmit-only mode. (recovery function) the vclk counter is reset by providing a valid high to low transition on the scl pin. after reversion to transmit-only mode, the devices begin to output a data with the 129th rising clock edge on vclk. the output data is 00h address data at the time. ? if the br24c21, br24c21f, br24c21fj and br24c21fv are switched from transmit-only mode and received the command for bi-directional mode and responds with an acknowledge, it is impossible to revert to transmit-only mode. (the only way to revert to transmit-only mode is that the power down again.) unless the input device code is ?1010?, the device responds no acknowledge. if the vclk counter reaches 128 clock afterward, it is possible to revert to transmit-only mode for recovery function. if the master generates a stop condition during the slave address input, it is possible to revert to transmit-only mode. ? when the devices are switched from transmit-only mode to bi-directional mode, the period of t vhz need to be held. fig.12 recovery mode address 00h sda t vhz vclk mode transmit-only bi-directional transition mode with possibility to return to transmit-only mode transmit-only scl d4 d5 d6 d7 129 128 127 3 2 14 fig.13 mode change sda t vhz vclk mode transmit-only bi-directional transition mode with possibility to return to transmit-only mode bi-directional parmanently scl r/w ack s1010 ??? 2n n < 128 1
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics 2) bi-directional mode start condition ? all commands are proceeded by the start condition, which is a high to low transition of sda when scl is high. ? the br24c21, br24c21f, br24c21fj and br24c21fv continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition ? all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. ? the stop condition initiates internal write cycle to write the data into memory array after write sequence. ? the stop condition is also used to place the device into the standby power mode after read sequence. ? a stop condition can only be issued after the transmitting device has released the bus. device addressing ? following a start condition, the master output the device address of the slave to be accessed. the most significant four bits of the slave address are the ?device type indentifier?, for the br24c21, br24c21f, br24c21fj and br24c21fv this is fixed as ?1010?. ? the next three bits of the slave address are don?t care. ? the last bit of the stream determines the operation to be performed. when set to ?1?, a read operation is selected ; when set to ?0?, a write operation is selected. r / w set to ?0? write (this bit also sets to ?0? for random read operation) r / w set to ?1? read ??? 1010 r / w ? don't care write protect function ? write enable (vclk) when using the br24c21, br24c21f, br24c21fj and br24c21fv in the bi-directional mode, the vclk pin can be used as a write enable pin. setting vclk high allows normal write operations, while setting vclk low prevents writing to any location in the array. changing vclk from high to low during the self-timed program operation will not halt programming of the device. setting vclk low allow the word address setting in random read.
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics acknowledge ? acknowledge is a software convention used to indicate successful data transfers. the master or the slave will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that the eight bits of data has been received. ? the br24c21, br24c21f, br24c21fj and br24c21fv will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the br24c21, br24c21f, br24c21fj and br24c21fv will respond with an acknowledge, after the receipt of each subsequent 8-bit word. ? in the read mode, the br24c21, br24c21f, br24c21fj and br24c21fv will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. ? if an acknowledge is detected, and no stop condition is generated by the master, the br24c21, br24c21f, br24c21fj, br24c21fv will continue to transmit the data. ? if an acknowledge is not detected, the br24c21, br24c21f, br24c21fj and br24c21fv will terminate further data transmissions and await a stop condition before returning to the standby mode. 189 scl sda sda start condition (start bit) acknowledge signal (ack signal) (from ? com) output data) ( ? com (ic output data) fig.14 acknowledge response from receiver 3) bi-directional mode command byte write sda line vclk s t a r t slave address 10 0 1 r / w w r i t e d7 data d0 a c k s t o p fig.15 byte write cycle timing a c k word address a c k wa 0 wa 6 ? don't care ? ? ? ? ? when the master generates a stop condition, the br24c21, br24c21f, br24c21fj and br24c21fv begin the internal write cycle to the nonvolatile array.
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics page w rite sda line vclk s t a r t slave address 10 0 1 ??? a c k r / w w r i t e word address(n) d7 data(n) d0 a c k fig.16 page write cycle timing wa 0 wa 6 ? data(n + 7) d0 a c k s t o p a c k ? don't care ? if the master transmits the next data instead of generating a stop condition in byte write cycle, the br24c21, br24c21f, br24c21fj and br24c21fv transfer from byte write cycle to page write cycle. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the high order five bits of the word address remains constant. if the master transmits more than eight words, prior to generating the stop condition, the address counter will ?roll over?, and the previous transmitted data will be overwritten. current read sda line s t a r t slave address 11 r / w a c k a c k data s t o p 00 ??? d7 d0 r e a d fig.17 current read cycle timing ? the br24c21, br24c21f, br24c21fj and br24c21fv contain an internal address counter which maintains the address of the last word accessed, incremented by one. if the last accessed address is address n in a read operation, the next read operation will access data from address n+1 and increment the current address counter. if the last accessed address is address n in a write operation, the next read operation will access data from address n. if the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides a single byte of data. at this point, the device discontinues transmission.
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics random read slave address sda line s t a r t 11 00 ??? r / w w r i t e fig.18 random read cycle timing s t o p a c k r e a d data(n) slave address s t a r t r / w a c k 11 00 ??? d7 d0 wa 0 word address(n) a c k wa 6 ? a c k ? random read operation allows the master to access any memory location. this operation involves a two-step process. first, the master issues a write command which includes the start condition and the slave address field (with r / w set to ?0?) followed by the address of the word to be read. this procedure sets the internal address counter of the br24c21, br24c21f, br24c21fj and br24c21fv to the desired address. after the word address acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address field with r / w the set to ?1?. the device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. if the master does not acknowledge the transmission but does generate the stop condition, at this point br24c21, br24c21f, br24c21fj and br24c21fv discontinue transmission. sequential read s t a r t slave address r / w a c k a c k a c k a c k r e a d data(n) data(n + x) sda line 11 00 ??? d7 d7 d0 d0 s t o p fig.19 sequential read cycle timing (current read) ? during the sequential read operation, the internal address counter of the br24c21, br24c21f, br24c21fj and br24c21fv automatically increments with each acknowledge received ensuring the data from address n will be followed with the data from n+1. for read operations, all bits of the address counter are incremented allowing the entire array to be read during a single operation. when the counter reaches the top of the array, it will ?roll over? to the bottom of the array and continue to transmit the data. ? the sequential read operation can be performed with both current read and random read.
br24c21 / br24c21f / br24c21fj / br24c21fv memory ics ! ! ! ! external dimension (units : mm) dip8 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~15 7.62 sop8 0.15 0.3min. 0.15 0.1 0.4 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.27 1.5 0.1 ssop-b8 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 sop-j8 0.1 0.45min. 0.42 0.1 4.9 0.2 85 4 123 1.27 76 0.2 0.1 0.175 6.0 0.3 3.9 0.2 1.375 0.1

▲Up To Search▲

Price & Availability of BR24C21FFJFV

	To Download BR24C21FFJFV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .