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hi-8282 pinconfiguration (topview) generaldescription thehi-8282isasilicongatecmosdeviceforinterfacing thearinc429serialdatabustoa16-bitparalleldatabus. tworeceiversandanindependenttransmitterare provided.thereceiverinputcircuitryandlogicare designedtomeetthearinc429specificationsforloading, leveldetection,timing,andprotocol.thetransmitter sectionprovidesthearinc429communicationprotocol. additionalinterfacecircuitrysuchastheholthi-8382is requiredtotranslatethe5voltlogicoutputstoarinc429 drivelevels. the16-bitparalleldatabusexchangesthe32-bitarinc datawordintw ostepswheneitherloadingthetransmitter orinterrogatingthereceivers.thedatabusinterfaceswith cmosandttl. timingofallthecircuitrybeginswiththemasterclockinput, clk.forarinc429applications,themasterclock frequencyis1mhz. eachindependentreceivermonitorsthedatastreamwitha samplingrate10timesthedatarate.thesamplingrateis softwareselectableateither1mhzor125khz.theresults ofaparitycheckareavailableasthe32ndarincbit.the hi-8282examinesthenullanddatatimingsandwillreject erroneouspatterns.forexample,witha125khzclock se lection,thedatafrequencymustbebetween10.4khz and15.6khz. thetransmitterhasafirstin,firstout(fifo)memoryto store8arincwordsfortransmission.thedatarateofthe transmitterissoftwareselectablebydividingthemaster clock,clk,byeither10or80.themasterclockisusedto setthetimingofthearinctransmissionwithintherequired resolution. applications ! ! ! avionicsdatacommunication serialtoparallelconversion paralleltoserialconversion features ! ! ! ! ! ! ! ! ! ! ! arincspecification429compatible 16-bitparalleldatabus directreceiverinterfacetoarincbus timingcontrol10timesthedatarate selectabledataclocks receivererrorrejectionperarinc specification429 automatictransmitterdatatiming selftestmode parityfunctions lowpower,single5voltsupply industrial&fullmilitarytemperatureranges ! descsmdpartnumber holtintegratedcircuits 4-29 (ds8282rev.a) 01/01 january2001 44-pinplasticquadflatpack(pqfp) (seepage4-38foradditionalpackagepinconfigurations) 33-n/c 32-n/c 31- 30-entx 29- 28-429do 27-tx/r 26- 25- 24-bd00 23-bd01 cwstrx 429do pl2 pl1 n/c-1 -2 -3 sel-4 -5 -6 bd15-7 bd14-8 bd13-9 bd12-10 bd11-11 d/r1 d/r2 en1 en2 hi-8282pqi & hi-8282pqt
symbolfunctiondescription vccpower+5v5% 429di1(a)inputarincreceiver1positiveinput 429di1(b)inputarincreceiver1negativeinput 429di2(a)inputarincreceiver2positiveinput 429di2(b)inputarincreceiver2negativeinput outputreceiver1datareadyflag outputreceiver2datareadyflag selinputreceiverdatabyteselection(0=byte1)(1=byte2) inputdatabuscontrol,enablesreceiver1datatooutputs inputdatabuscontrol,enablesreceiver2datatooutputsifishigh bd15i/odatabus bd14i/odatabus bd13i/odatabus bd12i/odatabus bd11i/odatabus bd10i/odatabus bd09i/odatabus bd08i/odata bus bd07i/odatabus bd06i/odatabus gndpower0v bd05i/odatabus bd04i/odatabus bd03i/odatabus bd02i/odatabus bd01i/odatabus bd00i/odatabus inputlatchenableforbyte1enteredfromdatabustotransmitterfifo. inputlatchenableforbyte2enteredfromdatabustotransmitterfifo.mustfollow tx/routputtransmitterreadyflag.goeslowwhenarincwordloadedintofifo.goeshigh aftertransmissionandfifoempty. 429dooutput"ones"dataoutputfromtransmitter. output"zeroes"dataoutputfromtransmitter. entxinputenabletransmission inputclockforcontrolwordregiste r clkinputmasterclockinput txclkoutputtransmitterclockequaltomasterclock(clk),dividedbyeither10or80. inputmasterreset,activelow d/r1 d/r2 en1 en2en1 pl1 pl2pl1. 429do cwstr mr pindescription hi-8282 holtintegratedcircuits 4-30
functionaldescription data busfunctioncontroldescription pin ifenabled,aninternalconnection bdo5selftest0=enableismadepassing429doand tothereceiverlogicinputs receiver1ifenabled,arincbits9and, bdo6decoder1=enable10mustmatchthenexttwo controlwordbits ifreceiver1decoderis bdo7--enabled,thearincbit9 mustmatchthisbit ifreceiver1decoderis bdo8--enabled,thearincbit10 mustmatchthisbit receiver2ifenabled,arincbits9and bdo9decoder1=enable10mustmatchthenexttwo controlwordbits ifreceiver2decoderis bd10--enabled,thenarincbit9 mustmatchthisbit ifreceiver2decoderis bd11--enabled,thenarin cbit10 mustmatchthisbit invertlogic0enablesnormaloddparity bd12xmtr1=enableandlogic1enablesevenparity parityoutputintransmitter32ndbit bd13xmtrdata0=10clkisdividedeitherby10or clkselect1=8080toobtainxmtrdataclock bd14rcvrdta0=10clkisdividedeitherby10or clkselect1=8080toobtainrcvrdataclock 429do controlwordregister thehi-8282contains10dataflipflopswhosedinputsarecon- nectedtothedatabusandclocksconnectedto.each flipflopprovidesoptionstotheuserasfollows: cwstr thereceivers arincbusinterface figure1showstheinputcircuitforeachreceiver.thearinc429 specificationrequiresthefollowingdetectionlevels: thehi-8282guaranteesrecognitionoftheselevelswithacommon modevoltagewithrespecttogndlessthan4vfortheworstcase condition(4.75vsupplyand13vsignallevel). thetolerancesinthedesignguaranteedetectionoftheabove levels,sotheactualacceptancerangesareslightlylarger.ifthe arincsignalisoutoftheactualacceptanceranges,includingthe nulls,thechiprejectsthedata. statedifferentialvoltage one+6.5voltsto+13volts null+2.5voltsto-2.5volts zero-6.5voltsto-13volts byte2 databdbdbdbdbdbdbdbdbdbdbdbdbdbdbdbd bus15141312111009080706050403020100 arinc29282726252423222120191817161514 bit arinc429dataformat thefollowingtableshowsthebitpositionsinexchangingdatawith thereceiverorthetransmitter.arincbit1isthefirstbit transmittedorreceived. databdbdbdbdbdbdbdbdbdbdbdbdbdbdbdbd bus15141312111009080706050403020100 arinc13121110931303212345678 bit byte1 holtintegratedcircuits 4-31
hi-8282 receiverlogicoperation bittiming bitrate pulserisetime pulsefalltime pulsewidth figure2showsablockdiagramofthelogicsectionofeachreceiver. thearinc429specificationcontainsthefollowingtiming specificationforthereceiveddata: 100kbps1%12k-14.5kbps 1.50.5sec105sec 1.50.5sec105sec 5sec5%34.5to41.7sec againthehi-8282acceptssignalsthatmeetthesespecifications andrejectsoutsidethetolerances.thewaythelogicoperation achievesthisisdescribedbelow: 1.keytotheperformanceofthetimingcheckinglogicisanac- curate1mhzclocksource.lessthan0.1%erroris recommmended. 2.thesamplingshiftregistersare10bi tslongandmustshow threeconsecutiveones,zerosornullstobeconsideredvalid data.additionally,fordatabits,theoneorzerointheupperbits ofthesamplingshiftregistersmustbefollowedbyanullinthe lowerbitswithinthedatabittime.foranullinthewordgap, threeconsecutivenullsmustbefoundinboththeupperand lowerbitsofthesamplingshiftregister.inthismannerthemini- mumpulsewidthisguaranteed. highspeedlowspeed functionaldescription(con't) 3.eachdatabitmustfollowitspredecessorbynotlessthan 8samplesandnomorethan12samples.inthismannerthe bitrateischecked.withexactly1mhzinputclockfrequency, theacceptabledatabitratesareasfollows: 83kbps10.4kbps 125kbps15.6kbps 4.thewordgaptimersamplesthenullshiftregisterevery 10inputclocks(80forlowspeed)afterthelastdatabitofa validreception.ifthenullispresent,thewordgapcounteris incremented.acountof3willenablethenextreception. thereceiverparitycircuitcountsonesreceived,includingthe paritybit,arincbit32.iftheresu ltisodd,then"0"willappearin the32ndbit. highspeedlowspeed databitratemin databitratemax receiverparity retrievingdata once32validbitsarerecognized,thereceiverlogicgenerates anendofsequence(eos).ifthereceiverdecoderisenabled andthe9thand10tharincbitsmatchthecontrolword programbitsorifthereceiverdecoderisdisabled,theneos clocksthedatareadyflagflipfloptoa"1",or(orboth) willgolow.thedataflagforareceiverwillremainlowuntilafter arincbytesfromthatreceiverareretrieved.thisis accomplishedbyactivatingwithsel,thebyteselector,low toretrievethefirstbyteandactivatingwithselhighto retrievethesecondbyte.retrievesdatafromreceiver1and ret rievesdatafromreceiver2. ifanotherarincwordisreceived,andaneweosoccurs beforethetwobytesareretrieved,thedataisoverwrittenbythe newword. d/r1d/r2 en en eni en2 both sel en d/r decoder control bits / mux control latch enable control 32to16driver 32bitlatch 32bitshiftregister topins control bitbd14 clock option clock clk bit counter and endof sequence parity check 32nd bit data bitclock eos wordgap wordgap timer bitclock end start sequence control error clock error detection shiftregister shiftregister null zeros shiftregister ones eos bits9&10 figure2. receiverblockdiagram holtintegratedcircuits 4-32
transmitter ablockdiagramofthetransmittersectionisshowninfigure3. thefifoisloadedsequentiallybyfirstpulsingtoloadbyte1 andthentoloadbyte2.thecontrollogicautomaticallyloads the31bitwordinthenextavailablepositionofthefifo.iftx/r, thetransmitterreadyflagishigh(fifoempty),then8words, each31bitslong,maybeloaded.iftx/rislow,thenonlythe availablepositionsmaybeloaded.ifall8positionsarefull,the fifoignoresfurtherattemptstoloaddata. whenentxgoeshigh,enablingtransmission,thefifo positionsareincrementedwiththetopregisterloading intothe datatransmissionshiftregister.within2.5dataclocksthefirst databitappearsateither429door.the31bitsinthe datatransmissionshiftregisterarepresentedsequentiallytothe outputsinthearinc429formatwiththefollowingtiming: arincdatabittime10clocks80clocks databittime5clocks40clocks nullbittime5clocks40clocks wordgaptime40clocks320clocks thewordcounterdetectswhenallloadedpositionsare transmittedandsetsthetransmitterreadyflag,tx/r,high. fifooperation datatransmission pl1 pl2 429do highspeedlowspeed transmitterparity theparitygeneratorcountstheonesinthe31-bitword.ifthe bd12controlwordbitissetlow,the32ndbittransmittedwillmake parityodd.ifthecontrolbitishightheparityiseven. ifthebd05controlwordbitissetlow,429doorbecome inputstothereceiverbypassingtheinterfacecircuitry. thetworeceiversareindependentofthetransmitter.therefore, controlofdataexchangesarestrictlyattheoptionoftheuser.the onlyrestrictionsare: 1.thereceiveddatamaybeoverwrittenifnotretrieved withinonearincwordcycle. 2.thefifocanstore8wordsmaximumandignores attemp tstoloadadditiondataiffull. 3.byte1ofthetransmitterdatamustbeloadedfirst. 4.eitherbyteofthereceiveddatamayberetrievedfirst. bothbytesmustberetrievedtoclearthedatareadyflag. 5.afterentx,transmissionenable,goeshighitcannotgo lowuntiltx/r,transmitterreadyflag,goeshigh.otherwise, onearincwordislostduringtransmission. selftest systemoperation 429do holtintegratedcircuits 4-33
repeateroperation therepeatermodeofoperationallowsadatawordthathasbeen receivedbythehi-8282tobeplaceddirectlyintoitsfifofor transmission.aftera32-bitwordhasbeenshiftedintothereceiver shiftregister,theflagwillgolow.alogic"0"isplacedonthesel lineandisstrobed.thisisthesameprocedureasfornormal receiveroperationanditplacesthelowerbyte(16)ofthedataword onthedatabus.bystrobingatthesame d/r en pl1 hi-8282 timeas,thebytewillalsobeplacedintothetransmitterfifo. selisthentakenhighandisstrobedagaintoplacetheupper byteofthedatawordonthedatabus.bystrobingatthesame timeas,thesecondbytewillalsobeplacedintothefifo.the datawordisnowreadytobetransmittedaccordingtotheparity programmedintothecontrolwordregister. innormaloperation,eitherbyteofareceiveddatawordmayberead fromthereceiverlatchesfirstbyuseofselinput.duringrepeater operationhowever,thelowerbyteofthedatawordmustberead first.thisisnecessarybecause,asthedataisbe ingread,itisalso beingloadedintothefifoandthetransmitterfifoisalways loadedwiththelowerbyteofthedatawordfirst. en en pl2 en 429do 429do arincbit null data data data null null wordgap bit1 nextword bit32 bit31 bit30 cwhld t cwset t cwstr t databus cwstr valid databus selen t d/r t ensel t dataen t d/ren t end/r t en t ensel t selen t dataen t endata t endata t enen t byte1valid byte2valid holtintegratedcircuits 4-34
hi-8282 pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t databus pl1 tx/r byte2valid pl t pl12 t dwset t byte1valid arincbit 429do or 429do pl2 entx tx/r pl2en t endat t dtx/r t entx/r t data bit1 data bit2 data bit32 don'tcare 429di d/r en pl1 pl2 sel tx/r entx 429do bit32 don'tcare d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit1 bit32 holtintegratedcircuits 4-35
limits parameterconditionsunit symbol differentialinputvoltage:onevpins2to3,4to5:common6.510.013.0v zerovmodevoltagelessthan4v-13.0-10.0-6.5v nullvwithrespecttognd-2.502.5v inputresistance:differentialr12k togndr1227k tovccr1227k inputcurrent:inputsinki200a inputsourcei-450a inputcapacitance:differentialcpins2to3,4to520pf (guaranteedbutnottested)togndc20pf tovccc20pf inputvoltage:inputvoltagehiv2.1v inputvoltagelov0.7v inputcurrent:inputsinki1.5a inputsourcei-1.5a inputvoltage:inputvoltagehiv3.5v inputvoltagelov0.7v inputcurrent:inputsinki10a i nputsourcei-20a outputvoltage:logic"1"outputvoltagevi=-1.5ma2.7v logic"0"outputvoltagevi=1.8ma0.4v outputcurrent:outputsinkiv=0.4v3.0ma (bi-directionalpins)outputsourceiv=v-0.4v1.5ma outputcurrent:outputsinkiv=0.4v3.6ma (allotheroutputs)outputsourceiv=v-0.4v1.5ma outputcapacitance:c15pf standbysupplycurrent:i20ma operatingsupplycurrent:i20ma mintypmax arincinputs-pins2,3,4&5 bi-directionalinputs-pins11-20,22-27 allotherinputs-pins8-10,28,29,33,34,37,39 outputs-pins6,7,11-20,22-27,30-32,38 supplyinput-pin1 ih il nul i g h ih il i g h ih il ih il ih il ih il ohoh olol olout ohoutcc olout ohoutcc o cc1 cc2 w w w vcc=5v5%,gnd=0v,ta=operatingtemperaturerange(unlessotherwisespecified). powerdissipation500mw operatingtemperaturerange:(industrial)-40cto+85c (military)-55cto+125c storagetemperaturerange:-65cto+150c supplyvoltagevcc-0.3vto+7v voltageatpins2,3,4&5-29vto+29v voltageatanyotherpin-0.3vtovcc+0.3v dccurrentdrainperinputpin10ma note:stressesabovethoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.thesea restressratingsonly. functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsection softhespecificationsisnotimplied. exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability. holtintegratedcircuits 4-36
limits parametersymbolunits mintypmax controlwordtiming receivertiming fifotiming transmissiontiming repeateroperationtiming masterresetpulsewidth arincdatarateandbittiming pulsewidth-t130ns setup-databusvalidtohight140ns hold-hightodatabushi-zt0ns delay-startarinc32ndbittolow:highspeedt16s lowspeedt128s delay-lowtol0wt0ns delay-lowtohight200ns setup-seltol0wt20ns hold-seltohight50ns delay-l0wtodatabusvalidt200ns delay-hightodatabushi-zt30ns pulsewidth-ort240ns spacing-hightonextl0wt50ns pulsewidth-ort200ns setup-databusvalidtohight110ns hold-hightodatabushi-zt20ns spacing-ort0ns delay-hightotx/rlowt840ns spacing-hightoentxhight0s delay-entxhighto429door:highspeedt25s delay-entxhi ghto429door:lowspeedt200s delay-32ndarincbittotx/rhight400ns spacing-tx/rhightoentxl0wt0ns delay-lowtolowt0ns hold-hightohight0ns delay-tx/rlowtoentxhight0ns t400ns 1% cwstr cwstr cwstr d/r d/ren end/r en en en en en1en2 enen pl1pl2 pl pl pl1pl2 pl2 pl2 429d0 429d0 enpl plen cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen pl dwset dwhld pl12 tx/r pl2en endat endat dtx/r entx/r enpl plen tx/ren mr holtintegratedcircuits 4-37 vcc=5v,gnd=0v,ta=operatingtemperaturerangeandfclk=1mhz0.1%with60/40dutycycle +
additionalhi-8282pinconfigurations (seepage4-29forthe44-pinplasticquadflatpack) holtintegratedcircuits 4-38 hi-8282c hi-8282j-44 hi-8282u 44-pinj-leadcerquad 44-pinceramiclcc hi-8282s 40-pinceramicsidebrazeddip 44-pinplasticplcc
part number description temperature range flow burn in lead finish hi-8282c 40 pin ceramic side brazed dip -40c to +85c i no gold hi-8282ct 40 pin ceramic side brazed dip -55c to +125c t no gold hi-8282cm-01 40 pin ceramic side brazed dip -55c to +125c m yes solder hi-8282cm-03* 40 pin ceramic side brazed dip -55c to +125c dscc yes solder hi-8282j-44 44 pin plastic j lead -40c to +85c i no solder hi-8282jt-44 44 pin plastic j lead -55c to +125c t no solder hi-8282pqi 44 pin plastic quad flat pack -40c to +85c i no solder hi-8282pqt 44 pin plastic quad flat pack -55c to +125c t no solder hi-8282s 44 pin ceramic leadless chip carrier -40c to +85c i no gold hi-8282st 44 pin ceramic leadless chip carrier -55c to +125c t no gold hi-8282sm-01 44 pin ceramic leadless chip carrier -55c to +125c m yes solder hi-8282u 44 pin cerquad -40c to +85c i no solder hi-8282ut 44 pin cerquad -55c to +125c t no solder hi-8282 *smd#5962-8688002qa holtintegratedcircuits 4-39 package
packagetype: 214443 .620 .012 (15.748 .305) .688 .005 (17.475 .127) max. .650 (16.510 .254) sq. .200 (5.080) max. .050 (1.270) .019 .051) .100 .007 (2.540 44-pinj-leadcerquad 44u .039 .005 (.990 .127) packagetype: 2.020max (51.308max) .225max (5.715max) .100bsc (2.540bsc) .018typ (.457typ) .050typ (1.270typ) .085 .009 (2.159 .229) .125min (3.175min) .610 .010 (15.494 .254) .600 .010 (15.240 .254) .595 .010 (15.113 .254) .010 + .002 /- .001 (.254 + .051 /- .025) 40-pinceramicside-brazeddip 40c hi-8282packagedimensions inches(millimeters) holtintegratedcircuits 1
packagetype: pinno.1ident .045x45 .050 .005 (1.27 .127) .045x45 pinno.1 44-pinplasticplcc seedetail a .172 .008 (4.369 .203) detaila .020min (.508 min ) .025 .045 r .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .015.002 (.381 .051) .009 .011 44j hi-8282packagedimensions inches(millimeters) holtintegratedcircuits 2 packagetype: 0 q 7 detaila seedetaila sq. 44pqs 44-pinplasticquadflatpack(pqfp) .007 (.17) .547.010 (13.90.25) .394.004 (10.0.10) sq. max. .014..002 (.35.05) .035+.006/-.004 (.88+.15/-.10) .008 (.20r) typ. .012 (.30r) typ. .079+.004/-.006 (2.00+.10/-.15) .097 (2.45) max. .0315bsc (.80bsc)
packagetype: 44-pinceramicleadlesschipcarrier 44s .651 .011 (16.535 .279) sq. .075 .004 (1.905 .101) .326 .006 (8.280 .152) pin1 .050bsc (1.270bsc) .009r.006 (.229r .152) .092 . 028 (2.336 .711) .025 .003 (.635 .076) .050 . 005 (1.270 .127) .020index (.508index) .040x453plcs (1.016x453plcs) pin1 hi-8282packagedimensions inches(millimeters) holtintegratedcircuits 3

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