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| process CP336V small signal transistor npn - high voltage transistor chip geometry principal device types gross die per 5 inch wafer 57,735 process details process epitaxial planar die size 17.3 x 17.3 mils die thickness 7.1 mils base bonding pad area 3.9 x 3.9 mils emitter bonding pad area 3.9 x 3.9 mils top side metalization al-si - 30,000? back side metalization au - 12,000? cmpt5551 ctlt5551-m832d cxt5551 czt5551 czt5551e www.centralsemi.com r1 (26-october 2010)
process CP336V typical electrical characteristics www.centralsemi.com r1 (26-october 2010) |
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