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equator hardware reference MAP-CA dsp datasheet equator technologies, inc. june 20, 2001 document number: hwr.ca.ds.2001.06.20 .com .com .com 4 .com u datasheet
equator hardware reference MAP-CA dsp datasheet june 20, 2001 copyright ? 2000 - 2001 equator technologies, inc., and hitachi, ltd. equator makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. equator reserves the right to change or discontinue this product at any time, without notice. there are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document. the following are trademarks of equator technologies, inc., and may be used to identify equator products only: equator, map, map1000, map1000a, MAP-CA, map series, broadband signal processor, bsp, firtree, datastreamer, ds, immediac, immediatools, immediatoolslite, media intrinsics, versaport, softv, stingray, equator around, and the equator around logo. other product and company names contained herein may be trademarks of their respective owners. the MAP-CA digital signal processor was jointly developed by equator technologies, inc., and hitachi, ltd. .com .com .com .com 4 .com u datasheet
i equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 type style conventions with the exception of section and subsection headings, the formatting of text in the following document adheres to the following conventions: normal descriptive text is presented in times new roman font. italicized times new roman text is used for document titles. underlined times new roman text is used for emphasis in normal descriptive text. any input or output text for any computer program is presented in courier new font. this includes source code, command-line text, and program output. italicized courier new text is used for any portion of a path name, including individual file names. bold courier new text is used for any placeholder for a set of text input or output items for a program. .com .com .com .com 4 .com u datasheet
ii MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
iii equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 table of contents introduction to the MAP-CA digital signal processor chip ..........................................xi chapter 1 architecture overview .......................................................................................... 1 1.1 the vliw core............................................................................................................. ....... 2 1.1.1 execution units......................................................................................................... .... 2 1.1.1.1 i-alu................................................................................................................. ... 3 1.1.1.2 ig-alu ................................................................................................................ .3 1.1.1.3 simple interlocks .................................................................................................. 3 1.1.1.4 extensive predication............................................................................................ 3 1.1.2 register resources...................................................................................................... .. 3 1.1.2.1 global registers .................................................................................................... 3 1.1.2.2 breakpoint registers ............................................................................................. 3 1.1.2.3 general registers .................................................................................................. 3 1.1.2.4 predicate registers ................................................................................................ 3 1.1.2.5 plc/plv 128-bit registers.................................................................................... 4 1.2 interrupts and exceptions ................................................................................................. .... 4 1.2.1 core interrupts and exceptions..................................................................................... 4 1.2.2 interrupt controller .................................................................................................... ... 4 1.3 timers.................................................................................................................... ............... 5 1.4 memory hierarchy .......................................................................................................... ..... 5 1.4.1 caches.................................................................................................................. ......... 5 1.4.2 address translation ..................................................................................................... .5 1.5 databuses and controllers ................................................................................................. ... 6 1.5.1 memory interface controller ........................................................................................ 6 1.5.2 data transfer switch (dts) ......................................................................................... 6 1.5.3 datastreamer dma controller..................................................................................... 6 1.5.4 pci bus ................................................................................................................. ........ 6 1.5.5 i/o bus................................................................................................................. ......... 7 1.6 coprocessors.............................................................................................................. ........... 7 1.6.1 vlx ..................................................................................................................... .......... 7 1.6.2 video filter ............................................................................................................ ....... 7 1.6.3 des module .............................................................................................................. ... 7 1.7 i/o interfaces ............................................................................................................ ............ 8 1.7.1 audio interfaces........................................................................................................ .... 8 1.7.1.1 iec958 audio interface ........................................................................................ 8 1.7.1.2 i 2 s interface .......................................................................................................... 8 1.7.2 video interfaces........................................................................................................ .... 8 1.7.2.1 transport channel interfaces ................................................................................ 8 .com .com .com .com 4 .com u datasheet
iv MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 1.7.2.2 itu-656 input interface ........................................................................................ 8 1.7.2.3 itu-656 output interface ..................................................................................... 8 1.7.2.4 general purpose data port (gpdp) ...................................................................... 8 1.7.3 display refresh controller ........................................................................................... 9 1.7.4 dacs .................................................................................................................... ........ 9 1.7.5 i 2 c interface unit ....................................................................................................... 10 1.7.6 rom controller.......................................................................................................... 10 1.7.7 reset strap ............................................................................................................. ..... 10 2.1 the c compiler ............................................................................................................ ...... 11 2.1.1 the firtree media intrinsics extensions ................................................................... 11 2.2 libraries................................................................................................................. ............. 11 chapter 2 software development ........................................................................................ 11 2.3 assembler ................................................................................................................. .......... 12 2.4 linker .................................................................................................................... ............. 12 2.5 debugger .................................................................................................................. .......... 12 2.6 simulators................................................................................................................ ........... 12 2.7 boot ...................................................................................................................... .............. 12 chapter 3 bga pin_out assignments ............................................................................ 13 chapter 4 signal descriptions ............................................................................................... 17 4.1 interface summary ......................................................................................................... .... 17 4.2 legend .................................................................................................................... ............ 18 4.3 processor clock ........................................................................................................... ....... 18 4.4 sdram ..................................................................................................................... ......... 19 4.5 pci bus................................................................................................................... ............ 20 4.6 iec958.................................................................................................................... ............ 22 4.7 i 2 s .............................................................................................................................. ........ 22 4.8 multi-function signal pins................................................................................................ .23 4.8.1 transport channel interfaces (tci)............................................................................ 24 4.8.2 itu-656 inputs .......................................................................................................... .25 4.8.3 itu-656 output .......................................................................................................... 25 4.8.4 general purpose data port (gpdp)............................................................................ 26 4.8.5 flash rom............................................................................................................... ... 26 4.8.6 reset straps............................................................................................................ ..... 27 4.9 analog crt................................................................................................................ ........ 28 4.10 i 2 c.............................................................................................................................. ...... 28 4.11 boundary scan (jtag) .................................................................................................... 2 9 4.11.1 pull up resistors ...................................................................................................... 29 4.11.2 tap state machine................................................................................................... 29 4.11.3 instruction registers ................................................................................................. 3 0 4.11.4 test data registers ................................................................................................... 3 1 4.11.5 boundary scan register............................................................................................ 31 4.11.6 device identification register .................................................................................. 31 .com .com .com .com 4 .com u datasheet
v equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.12 power/ground pins........................................................................................................ ... 32 4.13 signal list summary ...................................................................................................... .. 33 chapter 5 external connection examples ......................................................................... 35 5.1 sdram .................................................................................................................... ......... 35 5.2 iec958.................................................................................................................... ............ 38 5.3 i 2 s .............................................................................................................................. ........ 39 5.4 transport channel interface (tci) ..................................................................................... 40 5.5 ntsc decoder .............................................................................................................. ..... 41 5.6 ntsc encoder.............................................................................................................. ...... 41 5.7 crt ....................................................................................................................... ............. 42 5.8 i 2 c.............................................................................................................................. ........ 42 5.9 rom ....................................................................................................................... ............ 43 chapter 6 electrical specifications ...................................................................................... 45 6.1 absolute maximum ratings............................................................................................... 45 6.2 power supply specifications .............................................................................................. 4 5 6.3 dc characteristics ....................................................................................................... ...... 46 6.4 ac characteristics........................................................................................................ ...... 48 6.4.1 pll reference clock input ....................................................................................... 48 6.4.2 sdram interface timing .......................................................................................... 49 6.4.3 pci bus timing .......................................................................................................... 50 6.4.4 iec958 interface timing ............................................................................................ 52 6.4.5 i 2 s interface timing ................................................................................................... 52 6.4.6 transport channel interface timing........................................................................... 55 6.4.7 itu-r bt.601/656 interface timing.......................................................................... 56 6.4.8 general purpose data port.......................................................................................... 57 6.4.9 i 2 c interface timing................................................................................................... 58 appendix a glossary .............................................................................................................. 61 appendix b package specifications .................................................................................... 63 b.1 mechanical specifications ................................................................................................. 63 b.1.1 outline and footprint ................................................................................................. 63 b.1.1.1 top and bottom views....................................................................................... 63 b.1.1.2 side view ........................................................................................................... 64 b.2 package materials ......................................................................................................... ..... 64 b.2.1 materials specification............................................................................................... 64 b.2.2 index location .......................................................................................................... .65 .com .com .com .com 4 .com u datasheet
vi MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
vii equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 list of tables table 1-1: system events....................................................................................................... ......... 4 table 1-2: operation events .................................................................................................... ....... 4 table 1-3: supported interrupts ................................................................................................ ...... 5 table 3-1: pin assignments ..................................................................................................... ..... 13 table 4-1: processor clock signal description ............................................................................ 18 table 4-2: memory interface signals............................................................................................ 19 table 4-3: pci interface signals ............................................................................................... .... 20 table 4-4: iec958 interface signals ............................................................................................ .22 table 4-5: i 2 s interface signals .................................................................................................... 22 table 4-6: multiple signal pins ................................................................................................ .... 23 table 4-7: primary tci interface signals ..................................................................................... 24 table 4-8: secondary tci interface signals ................................................................................. 24 table 4-9: primary itu-r bt.601/656 input interface signals ................................................... 25 table 4-10: secondary itu-r bt.601/656 input interface signals ............................................. 25 table 4-11: itu-r bt.601/656 output interface signals ............................................................ 25 table 4-12: gpdp interface signals ............................................................................................. 26 table 4-14: reset straps ....................................................................................................... ........ 27 table 4-13: rom interface signals .............................................................................................. 27 table 4-15: crt interface signals.............................................................................................. .. 28 table 4-16: i 2 c interface signals.................................................................................................. 28 table 4-17: jtag interface signals............................................................................................. .29 table 4-18: jtag instructions.................................................................................................. .... 30 table 4-19: power/ground pins.................................................................................................. .. 32 table 4-20: MAP-CA dsp pin list.............................................................................................. 33 table 6-1: absolute maximum ratings ........................................................................................ 45 table 6-2: voltage variation................................................................................................... ...... 45 table 6-3: steady state current ................................................................................................ .... 46 table 6-4: pci signals ........................................................................................................ ......... 46 table 6-6: temperature rating .................................................................................................. ... 47 table 6-7: video dac outputs ................................................................................................... .47 table 6-5: non-pci signals ..................................................................................................... ..... 47 table 6-8: pll reference clock input conditions ...................................................................... 48 table 6-9: sdram interface timing parameters ........................................................................ 49 table 6-10: pci interface timing parameters .............................................................................. 51 .com .com .com .com 4 .com u datasheet
viii MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 table 6-11: pci measurement conditions.................................................................................... 51 table 6-12: iec958 interface timing parameters ........................................................................ 52 table 6-13: i 2 s clock ratios ........................................................................................................ 52 table 6-14: i 2 s output timing parameters .................................................................................. 53 table 6-15: i 2 s input timing parameters - slave mode............................................................... 54 table 6-16: i 2 s input timing parameters - master mode ............................................................ 54 table 6-18: itu-r bt.601/656 input interface timing parameters ............................................ 56 table 6-17: tci timing parameters ............................................................................................. 5 6 table 6-19: itu-r bt.601/656 output interface timing parameters.......................................... 57 table 6-21: gpdp output timing parameters ............................................................................. 58 table 6-20: gpdp input timing parameters ................................................................................ 58 table 6-22: i 2 c interface timing parameters ............................................................................... 59 table b-1: material used....................................................................................................... ....... 64 .com .com .com .com 4 .com u datasheet
ix equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 list of figures figure 1-1: MAP-CA dsp block diagram ..................................................................................... 1 figure 1-2: the vlx coprocessor ............................................................................................... ... 7 figure 1-3: display refresh controller ........................................................................................ ... 9 figure 3-1: view of balls from the bottom ................................................................................... 13 figure 3-2: MAP-CA dsp pins viewed from top ......................................................................... 16 figure 4-1: MAP-CA dsp interface ............................................................................................. 1 7 figure 4-2: tap state transition diagram ................................................................................... 30 figure 4-3: boundary scan block diagram .................................................................................. 31 figure 4-4: device identification register .................................................................................... 31 figure 5-1: 64-bit, 4mb configuration using 32, 8mb parts ...................................................... 35 figure 5-2: 64-bit, 16 mb configuration using 8, 16 mb parts .................................................. 35 figure 5-4: 64-bit, 64 mb configuration using 16, 64 mb parts ................................................ 36 figure 5-3: 64-bit, 16 mb configuration using 16 16mb parts .................................................. 37 figure 5-6: 64-bit, 128mb configuration using 16, 128mb parts .............................................. 37 figure 5-5: 64-bit, 64mb configuration using 16, 128mb parts ................................................ 38 figure 5-7: iec958 interface .................................................................................................. ...... 38 figure 5-8: i 2 s interface ................................................................................................................ 39 figure 5-9: transport channel interface ....................................................................................... 40 figure 5-10: itu-r bt.656 ntsc/pal decoder interface ......................................................... 41 figure 5-11: ntsc/pal encoder interface .................................................................................. 41 figure 5-12: crt .............................................................................................................. ............ 42 figure 5-13: i 2 c interface ............................................................................................................. 42 figure 5-14: rom connections .................................................................................................. .. 43 figure 6-1: sdram timing measurement conditions ................................................................ 49 figure 6-2: pci output timing measurement conditions ............................................................ 50 figure 6-3: pci input timing measurement conditions .............................................................. 50 figure 6-4: i 2 s data format .......................................................................................................... 52 figure 6-5: i 2 s output timing measurement conditions ............................................................. 53 figure 6-6: i 2 s input timing measurement - slave mode ........................................................... 53 figure 6-7: i 2 s input timing measurement - master mode ......................................................... 54 figure 6-8: internal serial clock generation for i 2 s master mode .............................................. 55 figure 6-9: tci timing measurement conditions ....................................................................... 55 figure 6-10: itu-r bt.601/656 input timing measurement conditions .................................... 56 figure 6-11: itu-r bt.601/656 output timing measurement conditions ................................. 57 .com .com .com .com 4 .com u datasheet
x MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 figure 6-12: gpdp input timing measurement conditions ........................................................ 57 figure 6-13: gpdp output timing measurement conditions ...................................................... 58 figure 6-14: i 2 c timing measurement conditions ...................................................................... 58 figure b-1: 352 pin bga outline and footprint - top and bottom views ................................. 63 figure b-2: 352 pin bga outline and footprint - side views .................................................... 64 figure b-3: index location .................................................................................................... ....... 65 .com .com .com .com 4 .com u datasheet
xi equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 vliw core highly pipelined very long instruction word processor that issues four operations per clock cycle - four 32-bit integer alus, two 64-bit shuf- fle/partitioned add units, and two 128-bit multimedia units - 128 32-bit general purpose registers, which can be treated as sixty-four 64-bit general purpose registers - thirty-two 1-bit predicate registers - eight special 128-bit registers 11+ gops sustained 16-bit simd operations @300 mhz 24+ gops sustained 8-bit simd operations @300 mhz 30+ gops @ 300 mhz for sum of absolute differences block matching 1800 mips @ 300 mhz in 32-bit integer arithmetic bi-endian support memory hierarchy 32 kb two way set associative, lru replacement policy, compressed format instruction cache 32 kb four way set associative, four bank interleaved, true lru, write-back data cache separate mmus for instruction, data and dma with fully associative sixteen entry tlb for each mmu glueless high speed 133 mhz sdram/sgram interface, supporting up to 128 mb vliw processor on-chip memories coprocessors MAP-CA dsp map for consumer appliances pci jtag flash rom i/f display refresh controller iec958 i 2 s i 2 c itu-656 in sdram controller tci in gpdp in itu-656 in tci in itu-656 out gpdp out plls core i/o ntsc/pal decoder demod fec video camera tuner ntsc/pal encoder tv monitor 27 mhz vcxo voltage regulators 64-bit sdram @ 133 mhz 3.3v 1.8v i 2 c audio codec rgb monitor flash rom jtag 32-bit pci bus @ 33/66 mhz system diagram introduction to the MAP-CA digital signal processor chip the MAP-CA digital signal processor offers a highly integrated single chip solution for broadband prod- ucts such as set-top boxes, digital tvs, video conferencing systems, medical imaging products, digital video editing equipment, and office automation products. the MAP-CA dsp is a member of the map series vliw processors. a parallelizing c compiler, linker, source level debugger, simulators, and libraries are available. reference software modules, including mpeg-2 encode and decode, jpeg encode and decode, video post-filtering, audio, telephony, and video teleconferencing codecs are also available to accelerate customer product development. because core media applications can be delivered in software on the MAP-CA dsp platform, it is easy to add, remove or enhance the functions of final products. the MAP-CA dsp provides the proven and effective solution for rapidly evolving broadband applications. .com .com .com .com 4 .com u datasheet
xii MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 coprocessors programmable vlx (16-bit risc processor) with acceleration for variable length decoding and encoding with 4 kb data memory and 4 kb instruction memory 4 (vertical) 5 (horizontal) / 3 5 / 2 5 tap video filter with 6kb line buffer memory programmable datastreamer (64 channel dma engine) with 8 kb buffer memory des support io interfaces 33 mhz/66 mhz 32-bit pci bus iec958 audio interfaces i 2 s audio interfaces video input: - two dvb compliant transport channel inter- faces or - one dvb compliant transport channel inter- face and one itu-r bt.601/656 input or - two itu-r bt.601/656 inputs or - one of any of the above and one general data port one itu-r bt.601/656 video output or one general data port display refresh controller (drc) with on-chip color space conversion, palette table lookup, alpha-blending, and hardware cursor 110 mhz ramdac with sync on green for analog rgb monitor i 2 c master/slave interface flash rom (eeprom) interface data sheet overview this data sheet provides the following information: an overview of the MAP-CA dsp architecture a description of the software development platform a description of the hardware development platform packaging information electrical specifications for additional information, contact equator technologies, inc. at: info@equator.com http://www.equator.com equator technologies, inc. 1300 white oaks road campbell, ca 95008 phone: (408) 369-5200 fax: (408) 371-9106 or mb-info@comp.hitachi.co.jp http:/www.hitachi.co.jp/MAP-CA/ hitachi, ltd. hitachi omori 2nd bldg., 27-18 minami oi 6-chome shinagawa-ku tokyo, japan 140-8572 phone: +81-3-5471-2719 fax: +81-3-5471-2565 .com .com .com .com 4 .com u datasheet
equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 1 the MAP-CA digital signal processor is a high per- formance processor providing broadband applica- tions with solutions addressing the convergence of communications, consumer appliances and com- puting. the MAP-CA dsp combines general pur- pose risc-like processing with high performance signal and image processing. the MAP-CA dsp supports programmable video, image, and signal processing software implementations of compres- sion and decompression algorithms. the MAP-CA dsp matches the cost and performance features of dedicated fixed function chips, with the added flex- ibility to rapidly respond to evolving standards. figure 1-1 shows a block diagram of the MAP-CA dsp. the MAP-CA dsp consists of a vliw core, programmable coprocessors, on-chip memories, and i/o interfaces. the vliw core executes four operations in parallel and supports partitioned simd operations for 8, 16, 32, and 64-bit data types. coprocessors on the MAP-CA digital signal processor help accelerate serial operations like variable length encod- ing/decoding and video filtering. several audio/video interfaces are supported, including itu-r bt.601/656 input and output; mpeg-2 transport channel interface (tci); iec958 and i 2 s digital audio interfaces. two video inputs can be used at the same time. the display refresh controller (drc) supports rgb computer screen refresh and also has hardware support for overlay- 32 kb data cache glueless sdram controller itu- 656 in gpdp in 2 itu- 656 in video in b video in a gpdp out 2 itu- 656 out video out iec958 i 2 s audio i/o i 2 c i 2 c display refresh controller 32-bit iob analog rgb sdram tci in tci in plls 27 mhz video filter 6 kb vf memory vlx 8 kb vlx memory romcon jtag boundary scan jtag flash rom (shared pins) 1 32-bit 66 mhz pci register file register file i-alu ig-alu i-alu ig-alu vliw core 32kb instruction cache 64-bit dts datastreamer dma controller des figure 1-1: MAP-CA dsp block diagram 1. some pins have multiple uses. see chapter 3, chapter 4, and chapter 6 for more information 2. itu-656 out is unavailable for use when gpdp in is enabled due to sharing of interface signals. chapter 1 architecture overview .com .com .com .com 4 .com u datasheet
2 the vliw core MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 ing a hardware cursor and graphics/text or a second- ary video channel on the primary video channel. an i 2 c bus interface is also provided. these i/o functions execute in parallel with the cpu and eliminate the need for several external asics with their associated cost and bandwidth issues. a glueless sdram controller supports access up to a 133 mhz sdram. the MAP-CA digital signal processor supports a 128 mb memory size. a 32-bit 33/66 mhz pci bus interface is also sup- ported. the MAP-CA dsp boots from either the pci bus or the flash rom interface. there are three on-chip plls (core/sdram, pixel, audio) that generate all the internal clocks from a single 27 mhz external clock input ( pclk ). the tci_vdac pin can be used to output a controlling signal that can be used to drive a one bit sigma-delta modulator for an external vcxo which in turns modulates the frequency on pclk . 1.1 the vliw core real-time handling of multimedia data stresses pro- cessor performance. there are three basic ways to increase a processor ? s performance: decrease the cycle time, decrease the number of cycles required to execute an instruction, and execute more instruc- tions per cycle. the first two are becoming increas- ingly difficult to improve beyond process scheduling, while the last is now receiving more attention. executing more instructions per cycle exploits the natural parallelism available in most software. very long instruction word (vliw) pro- cessors use this parallelism by packing multiple operations into a single instruction word, which is then executed as a unit. vliw architectures differ from superscalar archi- tectures in that the grouping and scheduling of instructions for execution is done at compile time, rather than execution time. the immediac com- piler searches for eligible operations, checks for dependencies and resource conflicts, and packages these eligible operations into vliws. the compiler can explore beyond the limited search window seen in superscalar architectures and cross natural boundaries, such as branches, to search for opportu- nities for parallelism. the immediac compiler uses a technique known as ? trace scheduling ? to search a whole routine for eligible operations. by moving the difficult task of finding parallelism into software, vliw techniques dramatically sim- plify the cpu design by reducing gate count and freeing valuable die area for other performance enhancements or lower costs. while vliw is pri- marily designed to exploit parallelism, its simplifi- cation of the processor architecture allows for reduced cycle times as well. 1.1.1 execution units the MAP-CA dsp operations are primarily 3-oper- and risc operations. as in a typical risc architec- ture, load and store operations are the only means of referencing memory. the MAP-CA dsp has four functional units: two i-alus, and two ig-alus. each i-alu contains a load-store unit, an integer alu, and a branch unit. each ig-alu contains an integer/graphics unit and a multimedia operation unit. the i-alu and ig-alu support different operations, but many integer and logical operations are implemented in both units. this overlap allows the compiler to schedule more operations in parallel and make more efficient use of all the functional units. there are 128 32-bit registers usable separately or in pairs as 64-bit registers, 32 1-bit predicate regis- ters, and eight special 128-bit registers. the 128-bit (plc/plv) registers are used for fir filter, sad, fft, add, dct, and other specialized partitioned integer operations. the large register files help min- imize unnecessary instruction dependencies caused by logically distinct register reuses. each MAP-CA digital signal processor instruction contains four operations. the media intrinsics oper- ations include partitioned operations over these data types. load and store operations can perform one, two, four, and eight byte accesses, with support for both little-endian and big-endian byte orderings. dynamic address translation and virtual memory protection are fully supported. the 1-bit logical val- ues are also used to support predicated execution, which substantially enhances available parallelism by allowing partial speculation and eliminating branching. .com .com .com .com 4 .com u datasheet
the vliw core 3 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 1.1.1.1 i-alu the i-alu performs the following operations: 32-bit integer arithmetic operations including compare logical and bitwise logical operations whose results can be sent to general or predicate regis- ters address calculations for indexed addressing memory reference branching system control operations 1.1.1.2 ig-alu the ig-alu performs the following operations: 32-bit integer arithmetic operations (same as the i-alu) logical and bitwise logical operations (same as the i-alu) 64-bit integer arithmetic operations shift/extract/merge operations 64-bit simd operations (with 8-bit, 16-bit, and 32-bit partitions) including selection, compari- son, selection of maximums and minimums, addition, multiply-add, complex multiplication, inner product, and sum of absolute differences 128-bit partitioned (with 8-bit, 16-bit, and 32-bit partitions) simd operations including inner- product with new partition shift-in for efficient fir operation and sum of absolute differences with new partition shift-in for efficient block matching operation 1.1.1.3 simple interlocks certain operations require more than one cycle to complete. no hardware interlocks are needed to prevent issue of an operation that attempts to read a result not yet completed. the immediac compiler is responsible for correct scheduling, not hardware. register scoreboarding is supported for outstanding loads. 1.1.1.4 extensive predication nearly all operations can have their effect con- trolled by the value of a selected (1-bit) predicate register. a predicate register is tested to determine whether or not the operation should be performed. this allows the compiler to aggressively convert control flow into data flow, enabling a substantially higher degree of instruction-level parallelism. this also greatly helps to reduce any penalties for branching, without the cost and complexity of hard- ware branch prediction. 1.1.2 register resources there are several types of registers on the MAP-CA digital signal processor. these include system regis- ters, breakpoint registers, general purpose registers, predicate registers, and special purpose 128-bit reg- isters. 1.1.2.1 global registers global registers on the MAP-CA dsp consist of system registers and implementation-dependent i/o registers (pio registers). dedicated operations manipulate the system registers; conventional load and store operations manipulate the i/o registers. 1.1.2.2 breakpoint registers MAP-CA dsp has two sets of breakpoint registers: instruction-breakpoint and data-breakpoint regis- ters. these registers provide hardware breakpoint capability for various debugging tools. instruc- tion-breakpoint registers cause an exception when an operation in the specified address is about to be executed. similarly, the data-breakpoint registers cause an exception when the data at the specified address is about to be accessed. in both cases, a mask can be used to specify a range of addresses. by registering an exception handling routine associ- ated with either of these exceptions, a software developer can control what happens when a hard- ware breakpoint occurs. for example, the exception handling routine may be used to signal an external application such as a source-level debugger that a breakpoint has occurred. 1.1.2.3 general registers there are 128 32-bit registers that can be treated as 64-bit general registers using even-odd pairs of the 32-bit registers. 1.1.2.4 predicate registers there are 32 1-bit predicate registers. predicate reg- isters are used in predicated operations, logical operations, and branches. they provide a destina- tion for operations with a judged condition. .com .com .com .com 4 .com u datasheet
4 interrupts and exceptions MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 1.1.2.5 plc/plv 128-bit registers the ig-alu has eight special 128-bit registers ? two pairs of partitioned local constant (plc) reg- isters and two pairs of partitioned local variable (plv) registers. t hese registers are used for power- ful simd digital signal processor partitioned opera- tions. the registers can be configured as sixteen 8-bit operation partitions, eight 16-bit operation partitions, or four 32-bit operation partitions. for numerous digital signal processing and compres- sion algorithms, this allows MAP-CA dsp to match the cost/performance of fixed-function chips without the loss of re-programmability. 1.2 interrupts and exceptions the MAP-CA dsp has a flexible interrupt struc- ture. interrupts and exceptions internal to the core are reflected directly in system registers. all other interrupts from on-chip devices and pci interrupts from external devices are gathered by an on-chip interrupt controller. the interrupt controller also provides a number of software interrupts. routing, masking, and prioritization of interrupts is completely software programmable. each of the interrupts handled by the interrupt controller can be individually masked, or routed to one of four core interrupts or to one of two pci interrupt signals. 1.2.1 core interrupts and exceptions table 1-1 and table 1-2 list the events that can trig- ger interrupts or exceptions within the core. when an event occurs, a bit is set in an ? event seen ? sys- tem register. if the event is not masked (or not maskable), the address for a handler will be fetched from one of nine event vector system registers, depending on the event. 1.2.2 interrupt controller the MAP-CA digital signal processor interrupt controller supports multiple maskable interrupts from outside of the core. non-core interrupt sources include on-chip devices such as tci, the drc, the table 1-1: system events name event maskable io0..io3 i/o interrupts (from interrupt controller) yes sint0..sint1 software interrupts yes fcnt free running counter overflow yes intv0..intv1 interval timers yes ilpc illegal program counter no ibpt instruction address break yes bpop breakpoint operation no sys system call (trap instruction) no itlbaa itlb application access no itlbr itlb reference no itlbm itlb miss no table 1-2: operation events name event maskable illo illegal operation no plv privilege violation no dbpt data address break yes daln data alignment error no dtlbkw dtlb kernel write no dtlbaw dtlb application write no dtlbaa dtlb application access no dtlbr dtlb reference no dtlbm dtlb miss no .com .com .com .com 4 .com u datasheet
timers 5 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 datastreamer dma controller, and pci interrupts from external devices or hosts. software-generated shoulder-tap interrupts are provided for multipro- cessing or inter-process communication support. MAP-CA dsp interrupts can be examined and con- trolled via pio registers in the romcon control block. routing and masking of interrupts is pro- grammable. each interrupt can be individually masked or routed to one of four core interrupts or to one of two pci interrupt signals. software inter- rupts can be similarly masked and routed. they may be asserted or de-asserted under software con- trol. table 1-3 shows the supported interrupts. 1.3 timers the MAP-CA digital signal processor has two inde- pendent programmable interval timers plus a free-running counter. each interval timer has a 32-bit counter register and period register. the counter is incremented once per cycle. when the counter reaches the period value, the counter is reloaded, a bit is set in the system event seen reg- ister (esr), and a maskable interrupt is asserted. the free-running counter counts up once per cycle as well. when it overflows to zero, a bit is set in esr and a maskable interrupt is asserted. the transport channel interface also has a program- mable timer that counts at a rate of 27 mhz and can be used to generate an interrupt upon rollover. 1.4 memory hierarchy the MAP-CA dsp supports several on-chip memo- ries and access to sdram and other memories via the pci bus. the vliw is equipped with a 32 kb instruction cache and 32 kb data cache used for caching instructions and data from sdram. in addition to supporting i-alu ports, the data cache supports a port to the dts (data transfer switch), which makes data in the data cache available to the datastreamer controller. a 4 kb instruction memory and a 4 kb data mem- ory are used by the vlx coprocessor. the video filter uses a 6 kb line buffer memory. these mem- ories, totaling 14 kb, are also accessible by the vliw core through un-cached load/store opera- tions. in addition, these memories are also available to the datastreamer dma controller and for exter- nal use via pci. the line buffer memory is used to store the content of flash rom at system boot up. 1.4.1 caches the MAP-CA dsp has a 32 kb instruction cache and a separate, multi-bank 32 kb data cache. both caches are physically addressed, so that problems of aliasing and context switching do not arise. for fast address translation, the cache index is virtual but the tags are physical. the instruction cache holds instructions in a com- pressed form. it is organized as a two-way set asso- ciative cache with a lru replacement algorithm. the data cache is a 32 kb, four-way set-associative (with true lru replacement), write-back cache. the data cache supports four simultaneous 64-bit data accesses per cycle. the cache is non-blocking; up to 8 outstanding misses to different cache lines and up to 48 outstanding misses overall are allowed. 1.4.2 address translation the MAP-CA dsp provides memory management support in the form of separate tlbs for the instruction stream, each i-alu data access, and the datastreamer dma controller. the four tlbs table 1-3: supported interrupts name interrupt irqalwaysone debug interrupt, always asserted irqiic i 2 c irqtci0 primary tci irqdrc display refresh controller irqntscin0 primary itu-r bt.601/656 in irqntscin1 secondary itu-r bt.601/656 in irqtci1 secondary tci irqpciaa pci interrupt pin a irqpciab pci interrupt pin b irqntscout itu-r bt.601/656 output irqiec958 iec958 audio irqiis i 2 s audio irqpciapme pcia power management event irqds0 datastreamer interrupt 0 irqds1 datastreamer interrupt 1 irqdstlb datastreamer tlb miss irqdsbufovrflow datastreamer i/o input overflow irqsoftware software-controlled interrupts .com .com .com .com 4 .com u datasheet
6 databuses and controllers MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 (itlb, two dtlbs, and dstlb) can be pro- grammed independently. the dts-id is part of the virtual address and can be used to direct accesses when the tlbs are disabled. each tlb has sixteen fully-associative entries. each entry contains a virtual page number (vpn), an 8-bit address space identifier (asid), access protection bits, and page size information. each entry can map a page of any valid size, where the valid sizes are 16 kb, 64 kb, 256 kb, 1 mb, 4 mb, 16 mb, 64 mb, 256 mb, and 1 gb. when a tlb miss occurs, an exception is gener- ated. the exception handler can modify a tlb entry and retry the failed operation. separate excep- tion handlers can be installed for data, instruction, and datastreamer controller tlb misses. 1.5 databuses and controllers the various buses and controllers on the MAP-CA digital signal processor are described in the follow- ing sections. 1.5.1 memory interface controller the memory controller unit allows customers to easily build high-performance, external memory up to 128 mb using sdram/sgram without any external glue logic. local memory supports exter- nally initiated pci accesses through the address translation unit within the pci module. the memory controller unit also includes hard- ware that queues, prioritizes, and transfers data from memory to memory or from memory to cache asynchronously to the initiating software. the on-chip core pll generates the clock for the memory controller and provides clock synchroniza- tion between the MAP-CA dsp and external sdram. this provides support for various combi- nations of cpu core and memory speeds. 1.5.2 data transfer switch (dts) the dts is a split-transaction bus. the dts con- tains the data and address buses, a high speed bridg- ing system, and a bus arbiter. the bridge, arbiter, and bus arrangement is a very high-speed commu- nication solution that allows multiple media appli- cations to be executed concurrently. the arbiter can handle multiple requestors using priority based scheduling. 1.5.3 datastreamer dma controller the datastreamer dma controller is a high perfor- mance, programmable dma engine that performs buffered data transfer between different MAP-CA dsp memory subsystems or between memories and i/o devices. the datastreamer controller is pro- grammed and controlled by software. the datastreamer controller then performs the requested transfer without further intervention from the core. the datastreamer controller can perform the fol- lowing classes of transfers: memory-to-memory: perform block transfers, preload data into the cache, fill a memory region with 0 or 1 bits memory-to-i/o and i/o-to-memory: perform i/o transfers the datastreamer dma controller features include: an 8 kb internal memory that can be partitioned into as many as 64 variable-sized buffers. each buffer is simultaneously the sink for an input i/o or memory channel and the source for an output i/o or memory channel. sixty-four independent programmable channels for transfers between various memories and the datastreamer controller's internal buffer, channel programs, called descriptor lists, allow transfers of arbitrary or infinite length to be spec- ified. regular and irregular patterns of contigu- ous or non-contiguous transfers are easy to specify. memories that can be read or written include sdram, on-chip memories, and pci bus acces- sible memories. cache preloading can also be performed. interrupts can be triggered by descriptors, allowing end-of-transfer or mid-stream interrupts to be generated. 1.5.4 pci bus the pci unit implements a 32-bit pci 2.1 interface with speed up to 66 mhz. the pci interface is a single function device with two bars. certain fields in the configuration registers may be initial- ized on power-up through rom control. as a pci target, the pci interface allows access to the MAP-CA digital signal processor sdram (coher- ently or non-coherently with respect to the data .com .com .com .com 4 .com u datasheet
coprocessors 7 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 cache). the pci interface also allows access to sev- eral programmer-visible control registers, pio space and sdram. as a pci master, the pci inter- face allows the vliw core, the datastreamer dma controller, and coprocessors to initiate pci bus requests. the pci unit can initiate memory, i/o and configuration commands on the pci bus. the MAP-CA digital signal processor can act as a host on the pci bus. there are three pairs of request/grant lines for other devices on a pci bus. this enables a multi-processor configuration to connect up to four MAP-CAs together on a pci bus without a bridge. the pci interface implements two separate inter- rupt lines. if the MAP-CA dsp is not the host, any internal interrupt can be routed to any of these pc interrupts. if the MAP-CA dsp is the host, the pci interrupts are sampled by the MAP-CA dsp and can be routed to the MAP-CA dsp vliw core. the MAP-CA dsp is a 3.3v-only i/o device. if the MAP-CA dsp is used in a system with a 5v pci bus architecture, then a 5v-to-3.3v level translator is required. 1.5.5 i/o bus all on-chip peripheral devices are connected via the internal i/o bus (iob). this is a 32-bit internal bus running at one half of the vliw core frequency. the iob connects to the dts through the datastreamer controller. the iob can handle real-time requests. 1.6 coprocessors coprocessors on the MAP-CA dsp help off-load ? serial ? tasks from the vliw core or accelerate special purpose processing for video operations. the coprocessors operate in parallel with the vliw core resulting in improved video processing. 1.6.1 vlx the variable length encoder/decoder (figure 1-2) or vlx is a 16-bit risc coprocessor with thirty-two 16-bit registers. the vlx off-loads the bit sequen- tial tasks of variable length encoding and variable length decoding (vle/vld) from the vliw cpu core and accelerates applications such as jpeg, mpeg, h.263, jbig, and dv. the vlx includes special purpose hardware for bitstream processing, hardware-accelerated mpeg-2 table lookup, and general purpose variable length decoding. 1.6.2 video filter a polyphase (8 phase) 2d video filter takes 4:2:0 or 4:2:2 yuv stream as input and scales either up or down as required. 4 (vertical) 5 (horizontal) fil- ters support up to 768 horizontal pixels, 3 5 up to 1024 horizontal pixels, and 2 5 up to 1536 hori- zontal pixels. the video filter pumps out scaled 4:4:4 yuv data to the drc through the video bus. the video filter can also pump out 4:4:4 yuv data to the sdram for debug purposes. its features are described below. supports 8-bit coefficients. supports both interspersed and co-sited pixel positioning. supports vertical 4-tap polyphase (8-phase) fil- ters for luminance and chrominance. supports horizontal 5-tap polyphase (8-phase) filters for luminance and chrominance. can scale up to a maximum resolution of 2047 2047 (depends upon memory bandwidth available for the video scaling operation). can scale up from a minimum resolution of 17 4. the maximum scale down ratio is 1:7. 1.6.3 des module the MAP-CA digital signal processor includes hardware support for encryption and decryption of data according to the national bureau of standards data encryption standard and certain implementa- tions thereof as defined in fips publications 46-2, 46-3, 74, and 81 and ansi publication x9.52-1998 . for more information on this support, contact your equator technologies or hitachi sales representa- tive. figure 1-2: the vlx coprocessor 16-bit cpu bitstream processor registers 32-bit i/o bus 16-bit 64-bit vlx instruction memory (4 kb) data memory (4 kb) .com .com .com .com 4 .com u datasheet
8 i/o interfaces MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 1.7 i/o interfaces 1.7.1 audio interfaces 1.7.1.1 iec958 audio interface this interface supports several audio standards: sony/philips digital interface (s/pdif) audio engineering society/european broadcast union (aes/ebu) interface toslink interface (requires external ir devices) the MAP-CA dsp iec958 interface can insert even or odd parity on each sub-frame of the output bit stream. 1.7.1.2 i 2 s interface the inter-ic sound (i 2 s) interface drives high qual- ity audio d/a converters for home theater. the MAP-CA digital signal processor interface meets the requirements of the standard serial data protocol and provides connection for up to three stereo dacs and one adc. the interface supports 48 khz, 44.1 khz, and 32 khz audio sample rates. simultaneous input and output must be at the same sample rate. the MAP-CA dsp iis supports both master and slave mode interface. in slave mode there is the choice of using either external inputs or internally generated signals for the sample rate clock and serial bit clock. 1.7.2 video interfaces the MAP-CA dsp provides two video input ports and one video output port. each input port supports either transport channel interface input or itu-r bt.601/656 input. the output port supports an itu-r bt.601/656 compliant output. in addition, the primary video input port and/or the output port can be used in a general purpose mode for transferring data (general purpose data port) for input or output respectively. 1.7.2.1 transport channel interfaces the video input unit implements two dvb compli- ant transport channel interfaces which receive demodulated channel data in transport layer format. the transport channel interface (tci) accepts mpeg-2 system transport packets in either byte parallel or, by default, bit serial form. data rates up to 80mbps (serial) or 30 mb/s (byte-wide parallel) are supported. by default, serial data is input on tci_data[0] and parallel data is input on tci_data[7:0] with bit 7 the most significant. these orientations can be reversed by pio program- ming. the tci synchronizes packet data received in broadcast applications such as satellite or cable. the tci can detect inline sync bytes, which are the first byte of every transport header. alternatively, the tci can utilize the external tci_sync signal. once byte-sync has been detected, the tci moves byte-aligned data into the MAP-CA dsp ? s memory using the datastreamer dma controller. the number of bytes in each packet is programma- ble. at the end of every packet, the tci appends an eight-byte postscript that includes time stamps from the local clock counters. this information can be used in conjunction with the program clock refer- ences embedded in the transport stream to track the timing reference. this is accomplished by using a software loop filter to implement a 1-bit sigma-delta modulator to provide a controlling volt- age for the external vcxo that drives pclk . the sigma-delta data stream is output at 1.5 mhz on the tci_vdac pin via the primary tci. in addition to the local clock counters, there is a programmable 27 mhz timer in each tci module that generates an interrupt on overflow (rollover). 1.7.2.2 itu-656 input interface this interface provides direct connection to an itu-r bt.601/656 format ntsc/pal video input decoder. the external decoder can be controlled using the i 2 c serial bus. 1.7.2.3 itu-656 output interface a glueless interface to a ntsc/pal video encoder is provided, enabling the MAP-CA digital signal processor to directly generate high-quality ntsc or pal video-output signals. this interface supports 8-bit 525 and 625 line resolutions with either sepa- rate h/vsync (itu-r bt. 601) or inline sync (itu-r bt.656). advanced video post-filtering on the MAP-CA dsp processor via software can pro- duce flicker-free output when converting inter- lace-to-progressive output. the external ntsc/pal encoder can be controlled using the i 2 c serial bus. 1.7.2.4 general purpose data port (gpdp) the general purpose data port provides an 8-bit par- allel input/output port. together with a clock and a .com .com .com .com 4 .com u datasheet
i/o interfaces 9 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 couple of handshake signals, this provides an alter- native to pci for multiple map chips to communi- cate. the data bandwidth supported is up to 60 mb/s depending upon other system activity. 1.7.3 display refresh controller sophisticated video blending, 2d graphics with alpha blending, pip, and hardware cursor overlays for epgs (electronic program guides) and naviga- tion services have been designed into the display refresh controller. color space conversion, gamma correction, and choice of ycbcr or rgb output format is supported. see figure 1-3 on page 9. the drc supports a maximum screen resolution of 1280 1024. this monitor resolution requires a minimum pixel clock frequency of 108 mhz to support a rate of 16 bits per pixel. 1.7.4 dacs the MAP-CA dsp rgb dacs (digital-to-analog converters) are part of the display refresh control- memory controller datastreamer video filter ds d ds p ds c ds a ds g ds d s u s v ds v crtc display list state control pixel output cursor gen. alpha channel graphics format conversion video #2 format scale alpha channel video bus key mux alpha pipe/ insert dp switch dp #1 dp #2 mux mux palette ram 256 24 color space conversion rgb yuv dp switch dmab alpha blender cursor insert r g b dac ? s signature analyzer fast bus horizontal blender & chroma subsampler ccir 656 formatter slow bus < 85 mhz ccir656 output nibble mode ntsc/pal encoder ntsc output figure 1-3: display refresh controller .com .com .com .com 4 .com u datasheet
10 i/o interfaces MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 ler block. the 8-bit dacs allow pixel clock rates up to 110 mhz. the MAP-CA dsp generates rs-343a compatible monitor signals into dou- bly-terminated 75 ? load and is capable of driving standard svga monitors. the full scale output level is determined by an external reference voltage v ref at 1.235v and an external resistor r nominal = 1117 ? . the full scale level can be adjusted by adjusting the resistor value. the dacs output the three primary analog color signals ? red video, green video and blue video ? with the video sync information superimposed on the green video output. also, separate hsync and vsync reference signals are provided. 1.7.5 i 2 c interface unit the inter-ic (i 2 c) bus was originally developed by philips to facilitate communications and control among integrated circuits in consumer electronics. using this two-wire serial interface, the MAP-CA dsp can function as a master or slave device to relay status and control information to external devices. the i 2 c interface unit has an additional output sig- nal, iic_select that allows MAP-CA dsp soft- ware to control an external analog multiplexer/level converter that can switch between a regular i 2 c bus and any other external bus (such as ddc for a mon- itor interface). this signal can also be used as a gen- eral purpose output. 1.7.6 rom controller the rom controller (romcon) unit performs four distinct functions. the chip configuration and rom boot sequencer is a state machine for reading chip configuration and boot code at system startup. the flash rom interface controls the actual reading and writing of an off-chip flash rom device. the interrupt controller/collector provides a means for enabling, setting, and clearing hard- ware and software interrupts to the vliw core and pci bus controller. the pll i/o provides pio access to the pro- grammable registers related to the various on-chip plls. the three plls for the core/sdram, pixel, and audio clocks are pro- grammed indirectly via pio registers within the romcon unit. the purpose of the configuration/boot sequencer is to control the boot up process of the chip. during reset, the resistor straps connected to the ntsc_out_data[7:0] pins are examined to determine how MAP-CA digital signal processor will configure itself and boot. if the resistor straps indicate to boot from rom, the boot sequencer directs the flash rom interface controller to trans- fer bytes from the external rom device to the MAP-CA dsp configuration registers and to the pci configuration registers. the 6 kb line buffer memory of the video filter is then used to store the bootstrap program for system boot up. romcon copies the next 6 kb from rom into the video fil- ter memory (vfmem) through an 8-bit configura- tion bus. after the boot code has been loaded, romcon unstalls (restarts) the vliw cpu, which in turn begins to execute the boot code out of vfmem. the romcon unit operates at 27 mhz during the configuration loading, since the core pll cannot be programmed to be taken out of bypass mode until after the vliw core has been unstalled. alternatively, for booting via the pci interface, romcon plays a mostly passive role. in this case, an external host loads the vfmem with boot code and initiates boot of the vliw core via a pio write to unstall the vliw cpu. romcon also runs power-on diagnostics during the boot and may be paused at various points for status testing. romcon requires minimal chip resources so that standard power-on diagnostics can run without having to bring up all portions of the chip, allowing the chip to be tested in more man- ageable stages. 1.7.7 reset strap during reset, the eight ntsc_out_data pins are used as inputs to read pre-boot configuration set- tings. these are settings that must be known before the actual boot process begins ? namely, whether the system should boot from rom and whether pci should serve as host for its bus. there are also four straps available whose meaning can be defined in software. each pin strap is pulled high (to vdd33) or low (to gnd) through a 4.7 k ? resistor. the pins are sam- pled into flip-flops until reset is de-asserted and then saved in the software-visible strapbits field of pio register configbuscontrol. for more informa- tion see section 4.8.6, ? reset straps, ? on page 27. .com .com .com .com 4 .com u datasheet
equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 11 the immediatools software toolkit includes immediac optimizing, parallelizing c-language compiler firtree media intrinsic c-language extensions assembler linker source-level debugger assembly-level debugger profiling , translating simulator two virtual-machine simulators, one nearly cycle-accurate assorted libraries the immediac compiler supports development in a host environment that differs from the target envi- ronment. the virtual-machine simulators allow testing and debugging on your host system. the supported host development environments are microsoft windows nt and red hat linux. 2.1 the c compiler the MAP-CA digital signal processor development system includes the immediac compiler with firtree media intrinsic extensions. the firtree extensions are proprietary simd-style high-speed media processing extensions. the immediac compiler uses aggressive optimiza- tion and global scheduling technology (including trace scheduling) to deliver full hardware perfor- mance without using laborious assembly language programming. the compiler allows programmers to focus efforts on algorithm optimization versus assembly scheduling, resource allocation, and debugging. unlike existing dsps or dedicated-function devices which have heretofore been used to meet media processing requirements, the MAP-CA dsp is pro- grammed in a high-level language (c). benefits of programming in c include reduced development costs reduced time to market lower system costs reduced maintenance time software-based upgrades the compiler uses complex inline expansion, asser- tions, and loop unrolling with trace frequency esti- mation algorithms to maximize c code efficiency. the optimizations include uncover instruction-level parallelism manage registers, pipelines and functional units generate instruction operation schedules that exploit parallelism support extensive global optimization, analysis and scheduling provide local scheduling and optimization support media-oriented machine facilities manages all timing dependencies to maximize scheduling efficiency the immediac compiler shell program lets you compile, examine, test, profile, assemble, and link source programs with a single command, by using various options. 2.1.1 the firtree media intrinsics extensions the firtree media intrinsics c-language exten- sions read 128-bit words of data memory, which contain multiple data items, and perform operations simultaneously on each of the items within the word. the firtree media intrinsics extensions per- form operations on partitioned native data types within 32-bit or 64-bit operands, making use of the plv and plc registers on the ig-alu to store intermediate values. 2.2 libraries the immediatools software development toolkit includes standard c runtime libraries and libraries specifically designed to support MAP-CA digital chapter 2 software development .com .com .com .com 4 .com u datasheet
12 assembler MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 signal processor resources, such as the datastreamer dma controller and vlx coproces- sor for media applications. 2.3 assembler the MAP-CA dsp assembler lets the programmer take the assembly language source files generated by the compiler, and convert them into object code files, ready for the linker. developers will not typi- cally write assembly language modules themselves. 2.4 linker the linker combines object code files into an exe- cutable module, accepting both object files and libraries as input. during linking, the linker resolves all external references. 2.5 debugger the development environment includes a source-level debugger based on gdb (gnu debug- ger). the extended gdb (egdb) runs on both the windows nt and red hat linux platforms. the egdb debugger allows the user to: load a MAP-CA dsp application from the host pc file system onto the MAP-CA dsp and run it set, list, and clear software and hardware break- points single step through both c source code and assembly instructions source level debug of optimized c code examine and deposit values into local variables, global variables and pio space examine and deposit values into all registers examine the stack, including stack backtracing numerous freeware or low-cost gdb gui front ends exist on both the windows nt and linux platforms that will transparently layer on egdb's command line interface and provide a window-based debug- ging environment. 2.6 simulators the software developer's toolkit includes three soft- ware simulators: trsim, sim, and casim. trsim is a high speed, instruction level simulator of the MAP-CA digital signal processor core unit. this simulator works on an intermediate representa- tion of a software program and can be used to ini- tially develop applications and experiment with the performance of different algorithms and use of compiler options. sim is also a high-speed, instruction-level simula- tor. this simulator works off actual MAP-CA dsp binaries. sim is a functional simulator of the MAP-CA dsp core unit with data cache, datastreamer controller, and a subset of i/o devices. it provides runtime checks against resource constraints and all MAP-CA dsp features neces- sary to simulate a MAP-CA dsp running a real-time operating system and applications. casim is a nearly cycle-accurate software simulator for the MAP-CA dsp and models more accurately the core, datastreamer dma controller, vlx, instruction and data caches, memories, and buses. like sim, this simulator operates off actual MAP-CA digital signal processor binaries. casim provides more detailed runtime checks against resource constraints. casim provides visibility into internal machine state and bandwith and augments debugging and tuning of interactions between vliw core, datastreamer controller, and vlx pro- grams. sim and casim work in conjunction with the source-level debugger. 2.7 boot software must contain boot code for execution on MAP-CA dsp. this boot code configures tlbs and caches. equator software tools can automati- cally add boot code when building an application. .com .com .com .com 4 .com u datasheet
13 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 table 3-1: pin assignments signal name ball audioclk_byp_in a2 a avdd18 b3 avss c4 avdd18 d5 avss a3 pixelclk_byp_in b4 b ntsc_out_data[3] c5 b ntsc_out_data[4] b5 b ntsc_out_data[5] a4 b ntsc_out_data[6] c6 b ntsc_out_data[7] d7 b video_ina[0] b6 b video_ina[1] c7 b video_ina[2] d8 b video_ina[3] a6 b video_ina[4] b7 b video_ina[5] a7 b video_ina[6] c8 b video_ina[7] d9 b signal name ball video_ina[8] b8 b video_ina[9] c9 b tcia_inuse a8 tcia_sync a9 tcia_clk c10 tcia_vdac b10 ntsc_ina_clk27 a10 b video_inb[0] c11 b video_inb[1] b11 b video_inb[2] a11 b video_inb[3] d12 b signal name ball video_inb[4] c12 b video_inb[5] b12 b video_inb[6] a13 b video_inb[7] c13 b video_inb[8] d13 b video_inb[9] b13 b tcib_inuse a14 tcib_sync b14 tcib_clk c14 ntsc_inb_clk27 d14 vsync a16 signal name ball hsync b15 tms b16 trst c15 avss a17 gdac_fscale b17 gdac_comp c16 avdd33 d16 gdac_green c17 gdac_blue a18 gdac_red a19 gdac_cvgg(avss) c18 signal name ball chapter 3 bga pin_out assignments signal assignment on the bga352 package is shown here. figure 3-1 shows the bottom view, with the balls facing the viewer. figure 3-2 shows the top view of the chip with pin assignments.. in table 3-1, pins marked with an (b) have multiple functions assigned (see chapter 4) 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 25 24 23 18 17 22 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 26 25 24 23 18 17 22 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 figure 3-1: view of balls from the bottom .com .com .com .com 4 .com u datasheet
14 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 avddx (avdd18) d17 avssx (avss) b19 tdi a20 tck b20 tdo c19 no connection a21 sddata[0] b21 sddata[1] c20 sddata[2] d19 sddata[3] a23 sddqm[0] b22 sddata[4] c21 sddata[5] a24 sddata[6] b23 sddata[7] c22 sddata[8] d21 sddata[9] a25 sddata[10] b24 sddata[11] c23 sddqm[1] d22 sddata[12] d24 sddata[13] b26 sddata[14] c25 sddata[15] e24 sddata[16] d25 sddata[17] d26 sddata[18] e25 sddata[19] f24 sddqm[2] f26 sddata[20] g24 sddata[21] g25 sddata[22] h25 sddata[23] h24 sddata[24] h26 sddata[25] j24 signal name ball sddata[26] j25 sddata[27] k24 sddqm[3] k26 sddata[28] l24 sddata[29] l25 sddata[30] m25 sddata[31] m24 sdcs_[0] m26 sdcs_[1] n24 sdcs_[2] n25 sdcs_[3] p26 sdrtnclk p24 sdclk r25 sdclk1 r24 sdclk2 t26 sdras_ t25 sdcas_ t24 sdwe_ u25 sdadr[0] u24 sdadr[1] v26 sdadr[2] v24 sdadr[3] w25 sdadr[4] y26 sdadr[5] w24 sdadr[6] y25 sdadr[7] y24 sdadr[8] aa25 sdadr[9] aa24 sdadr[10] ab26 sdadr[11] ad26 sdadr[12] ab24 sdadr[13] ad25 sddata[32] ac24 sddata[33] ab23 avss ac22 signal name ball avssq (avss) ad23 avddq (avdd18) ae24 avdd18 af25 sdclk_byp_in ac21 c pclk ad22 d coreclk_byp_in ae23 c pci_clk af24 sddata[34] ad21 sddata[35] af23 sddqm[4] af22 sddata[36] ae21 sddata[37] ac19 sddata[38] ad20 sddata[39] af21 sddata[40] af20 sddata[41] ac18 sddata[42] ad19 sddata[43] ae19 sddqm[5] ad18 sddata[44] af19 sddata[45] ae18 sddata[46] ad17 sddata[47] ae17 sddata[48] af17 sddata[49] ad16 sddata[50] af16 sddata[51] ac15 sddqm[6] ad15 sddata[52] ae15 sddata[53] af15 sddata[54] ad14 sddata[55] ae14 sddata[56] af13 sddata[57] ad13 signal name ball sddata[58] af12 sddata[59] ae12 sddqm[7] ad12 sddata[60] ac12 sddata[61] af11 sddata[62] ad11 sddata[63] af10 pci_ad[0] ae10 pci_ad[1] ad10 pci_ad[2] ae9 pci_ad[3] af8 pci_ad[4] ad9 pci_ad[5] ae8 pci_ad[6] ac9 pci_ad[7] ad8 pci_cbe_[0] af7 pci_ad[8] af6 pci_ad[9] ad7 pci_ad[10] ac8 pci_ad[11] ae6 pci_ad[12] af5 pci_ad[13] af4 pci_ad[14] ad6 pci_ad[15] af3 pci_cbe_[1] ae4 pci_par ad5 pci_serr_intb_ ac6 pci_stop_ af2 pci_devsel_ ae3 pci_trdy_ ad4 pci_irdy_ ac5 vss ad2 vdd18 ae1 vdd18 ac3 vss ab3 signal name ball pci_frame_ ac2 pci_cbe_[2] ac1 pci_ad[16] ab1 pci_ad[17] aa2 pci_ad[18] aa3 pci_ad[19] aa1 pci_ad[20] y3 pci_ad[21] y2 pci_ad[22] w1 pci_ad[23] w2 pci_idsel w3 pci_cbe_[3] v1 pci_ad[24] v3 pci_ad[25] u1 pci_ad[26] u4 pci_ad[27] u3 pci_ad[28] u2 pci_ad[29] t3 pci_ad[30] t2 pci_ad[31] r3 pci_req_[0] r2 pci_req_[1] r1 pci_req_[2] p3 pci_gnt_[0] p1 pci_gnt_[1] n1 pci_gnt_[2] n2 pclk_out n3 e pci_rst_ m2 pci_inta_ m3 pci_pme_ l1 iic_sda l2 iic_sck l3 iic_select k1 iis_in_data k3 iis_in_lr j1 signal name ball .com .com .com .com 4 .com u datasheet
15 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 iis_in_bclk k4 iis_out_data[0] j2 b iis_out_data[1] j3 b iis_out_data[2] h2 b iis_out_lr g1 iis_out_bclk h3 iec958_in g2 iec958_out g3 rom_cs_ f1 ntsc_out_hsync f3 b ntsc_out_vsync e1 b ntsc_out_data[0] e2 b ntsc_out_data[1] e3 b ntsc_out_data[2] c1 b audioclk_out c2 pixelclk_out d3 f vdd18 d6 vdd18 d11 vdd18 d15 vdd18 d20 vdd18 e23 vdd18 g23 vdd18 h23 vdd18 k23 vdd18 m23 vdd18 p23 vdd18 t23 signal name ball vdd18 v23 vdd18 w23 vdd18 aa23 vdd18 ac20 vdd18 ac16 vdd18 ac11 vdd18 ac7 vdd18 ab4 vdd18 aa4 vdd18 w4 vdd18 t4 vdd18 p4 vdd18 n4 vdd18 m4 vdd18 j4 vdd18 g4 vdd18 f4 vdd33 c3 vdd33 d4 vdd33 e4 vdd33 d10 vdd33 d18 vdd33 c24 vdd33 d23 vdd33 f23 vdd33 j23 vdd33 l23 vdd33 n23 signal name ball vdd33 r23 vdd33 u23 vdd33 y23 vdd33 ad24 vdd33 ac23 vdd33 ac17 vdd33 ac14 vdd33 ac13 vdd33 ac10 vdd33 ad3 vdd33 ac4 vdd33 y4 vdd33 v4 vdd33 r4 vdd33 l4 vdd33 h4 vss a1 vss b1 vss b2 vss a5 vss b9 vss a12 vss a15 vss b18 vss a22 vss a26 vss b25 vss c26 signal name ball vss e26 vss f25 vss g26 vss j26 vss k25 vss l26 vss n26 vss p25 vss r26 vss u26 vss v25 vss w26 vss aa26 vss ab25 vss ac26 vss ac25 vss ae26 vss ae25 vss af26 vss ae22 vss ae20 vss af18 vss ae16 vss af14 vss ae13 vss ae11 vss af9 vss ae7 signal name ball vss ae5 vss af1 vss ae2 vss ad1 vss ab2 vss y1 vss v2 vss t1 vss p2 vss m1 vss k2 vss h1 vss f2 vss d1 vss d2 a. if unused, nci (vss) and tie to ground b. multi-function pins c. connect to 27 mhz or lower clock d. connect to 27 mhz clock e. if unused, nco and floating f. leave floating signal name ball .com .com .com .com 4 .com u datasheet
16 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 vss vss ntsc_out _data[2] vss ntsc_out _vsync rom_cs_ iis_out_ lr vss iis_in_lr iic_ select pci_ pme_ vss pci_gnt _[1] pci_gnt _[0] pci_req _[1] vss pci_ad [25] pci_ cbe_[3] pci_ad [22] vss pci_ad [19] pci_ad [16] pci_ cbe_[2] vss vsbc (vdd18) vss pci_ irdy_ pci_par vss pci_ad [12] vss audioclk _out vss ntsc_out _data[0] vss iec958 _in iis_out data[2] iis_out data[0] vss iic_sda pci_rst_ pci_gnt _[2] vss pci_req _[0] pci_ad [30] pci_ad [28] vss pci_ad [23] pci_ad [21] pci_ad [17] vss pci_ frame_ vsbb (vss) vss pci_ stop_ avss avdd18 vdd33 pixelclk _out ntsc_out _data[1] ntsc_out _hsync iec958 _out iis_out _bclk iis_out data[1] iis_in _data iic_sck pci_ inta_ pclk_out pci_req _[2] pci_ad [31] pci_ad [29] pci_ad [27] pci_ad [24] pci _idsel pci_ad [20] pci_ad [18] vdbc (vss) vdbb (vdd18) vdd33 pci_ devsel_ pci_ad [15] ntsc_out _data[5] pixelclk _byp_in avss vdd33 vdd33 vdd18 vdd18 vdd33 vdd18 iis_in _blk vdd33 vdd18 vdd18 vdd18 vdd33 vdd18 pci_ad [26] vdd33 vdd18 vdd33 vdd18 vdd18 vdd33 pci_ trdy_ pci_cbe [1] pci_ad [13] vss ntsc_out _data[4] ntsc_out _data[3] avdd18 pci_serr intb_ pci_ad [14] pci_ad [11] pci_ad [8] video_ ina[3] video_ ina[0] ntsc_out _data[6] vdd18 vdd18 pci_ad [9] vss pci_cbe [0] video_ ina[5] video_ ina[4] video_ ina[1] ntsc_out _data[7] pci_ad [10] pci_ad [7] pci_ad [5] pci_ad [3] tcia_ inuse video_ ina[8] video_ ina[6] video_ ina[2] pci_ad [6] pci_ad [4] pci_ad [2] vss tcia_ sync vss video_ ina[9] video_ ina[7] vdd33 pci_ad [1] pci_ad [0] sddata [63] ntsc_ina clk27 tcia_ vdac tcia_clk vdd33 vdd18 sddata [62] vss sddata [61] video_ inb[2] video_ inb[1] video_ inb[0] vdd18 sddata [60] sddqm [7] sddata [59] sddata [58] vss video_ inb[5] video_ inb[4] video_ inb[3] vdd33 sddata [57] vss sddata [56] video_ inb[6] video_ inb[9] video_ inb[7] video_ inb[8] sddata [54] sddata [55] vss tcib_ inuse tcib_ sync tcib_clk ntsc_inb _clk27 sddata [51] sddqm [6] sddata [52] sddata [53] vss hsync trst vdd18 vdd18 sddata [49] vss sddata [50] vsync tms gdac_ comp avdd33 vdd33 sddata [46] sddata [47] sddata [48] avss gdac_ fscale gdac_ green avddx avdd18 sddata [41] sddqm [5] sddata [45] vss gdac_ blue vss gdac_cv gg(avss ) vdd33 sddata [37] sddata [42] sddata [43] sddata [44] gdac_ red avssx (avss) tdo sddata [2] vdd18 sddata [38] vss sddata [40] tdi tck sddata [1] vdd18 sdclk_ byp_in sddata [34] sddata [36] sddata [39] no con- nection sddata [0] sddata [4] sddata [8] avss pclk vss sddqm [4] vss sddata [0] sddata [7] sddata [1] sddata [3] sddata [6] sddata [11] vdd33 vdd18 vdd33 vdd18 vdd18 vdd33 vdd18 vdd33 vdd18 vdd33 vdd18 vdd33 vdd18 vdd33 vdd18 vdd18 vdd33 vdd18 sddata [33] vdd33 avssq (avss) coreclk_ byp_in sddata [35] sddata [5] sddata [10] vdd33 sddata [12] sddata [15] sddata [19] sddata [20] sddata [23] sddata [25] sddata [27] sddata [28] sddata [31] sdcs_ [1] sdrtnclk sdclk1 sdcas_ sdadr[0] sdadr[2] sdadr[5] sdadr[7] sdadr[9] sdadr [12] sddata [32] vdd33 avddq (avdd 18) pci_clk sddata [9] vss sddata [14] sddata [16] sddata [18] vss sddata [21] sddata [22] sddata [26] vss sddata [29] sddata [30] sdcs_ [2] vss sdclk sdras_ sdwe_ vss sdadr[3] sdadr[6] sdadr[8] vss vss sdadr [13] vss avdd18 vss sddata [13] vss sddata [17] vss sddqm [2] vss sddata [24] vss sddqm [3] vss sdcs_ [0] vss sdcs_ [3] vss sdclk2 vss sdadr[1] vss sdadr[4] vss sdadr [10] vss sdadr [11] vss vss audioclk _byp_in vdd33 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 1234567891011121314151617181920212223242526 figure 3-2: MAP-CA dsp pins viewed from top vdd33 multi-function pins vss vdd18 crt (drc) avss jtag sdram avdd18 plls pci i 2 c i 2 s .com .com .com .com 4 .com u datasheet
equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 17 chapter 4 signal descriptions 4.1 interface summary processor clock (pll) MAP-CA dsp pci pclk coreclk_byp_in pixelclk_byp_in / xmt_clk audioclk_out tcia_vdac sdclk_byp_in audioclk_byp_in pclk_out pci_ad[31:0] pci_cbe[3:0] pci_frame# pci_trdy# pci_irdy# pci_stop# pci_par pci_devsel# pci_clk pci_rst# pci_inta# pci_idsel pci_req#[2:0] pci_gnt#[2:0] pci_serr_intb# pci_pme# iis_in_data iis_in_lr iis_in_bclk iis_out_lr iis_out_bclk i 2 s (rom_oe#)/iis_out_data[2] (rom_wrt#)/iis_out_data[1] (rom_ale)/iis_out_data[0] rom_cs# flash rom video output sdram controller sdadr[13:0] sddata[63:0] sdcs[3:0]# sdras# sdcas# sdwe# sddqm[7:0] sdclk sdclk1 sdclk2 sdrtnclk i 2 c iic_sda iic_sck iic_select gdac_fscale gdac_comp gdac_blue gdac_green gdac_red vsync hsync crt (drc) tcib_inuse tcib_sync tcib_clk tcib_err# / ntsc_inb_vsync tcib_enable / ntsc_inb_hsync tcib_data[7:0] / ntsc_inb_data[7:0] ntsc_inb_clk27 tcia_inuse tcia_sync tcia_clk tcia_err# / ntsc_ina_vsync / xmt_ack tcia_enable / ntsc_ina_hsync / rcv_req tcia_data[7:0] / ntsc_ina_data[7:0] / rcv_data_in[7:0] ntsc_ina_clk27 / rcv_clk video input input a input b iec958 iec958_in iec958_out jtag tck tms tdi tdo trst (rom_addr[19]/rom_addr[21]/rom_addr[1])/ ntsc_out_hsync / xmt_req (rom_addr[18]/rom_addr[20]/rom_addr[0])/ ntsc_out_vsync / rcv_ack / (rom_addr[9:2]/rom_addr[17:10]/rom_data[7:0])/ ntsc_out_data[7:0] / xmt_data_out[7:0] ( ) --- valid during boot-up < > --- valid during reset # --- active low signal figure 4-1: MAP-CA dsp interface .com .com .com .com 4 .com u datasheet
18 legend MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.2 legend all tables in this section use the following abbreviations: a ..................................... analog signal b......................................bi-directional i ....................................... input o ..................................... output od .................................... open drain or active pull down trailing ? _ ? ...................... active low ()......................................parentheses indicate number of shared signal pins 4.3 processor clock there is a single 27 mhz reference clock signal for generating internal clocks. signal # of pins i/o description pclk 1i 27 mhz vcxo input that serves as the reference signal to the three on-chip plls. it is also a reference clock for the video output and the i 2 c interface coreclk_byp_in 1i bypass input for the core clock sdclk_byp_in 1i bypass input for the sdram clock. pixelclk_byp_in 1i transmit clock for gpdp (xmt_clk) or pll-bypass input for pixel clock audioclk_byp_in 1i bypass input for the audio clock. pclk_out (coreclk_out) 1o output for the core clock. pixelclk_out 1o output for the pixel clock. audioclk_out 1o audio clock output used for i 2 s interface master mclk tcia_vdac 1o sigma-delta output from software loop filter for controlling external vcxo for pclk total 9 table 4-1: processor clock signal description .com .com .com .com 4 .com u datasheet
sdram 19 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.4 sdram the MAP-CA dsp supports either sdram or sgram memory system using the signals shown in table 4-2. the MAP-CA digital signal processor supports a memory system of 64-bit or 32-bit data width. the MAP-CA dsp supports dram widths of 8-bit, 16-bit or 32-bits. signal # of pins i/o description sdadr[13:0] 14 o address lines indicate row addresses when sdras_ is active and indicate column addresses when sdcas_ is active sddata[63:0] 64 b data input/output lines transfer data between the memory and the MAP-CA dsp. these are also input mask bits for write-per-bit. when block write is activated, these lines provide column address mask sdcs_[3:0] 4o chip select signal lines indicate that the command on the output lines is for each memory chip. if this signal is high, the output command(s) will be ignored by each corresponding memory chip sdras_ 1o sdras_ is part of the output command to the sdram/sgram sdcas_ 1o sdcas_ is part of the output command to the sdram/sgram sdwe_ 1o write enable (sdwe_) is part of the output command sddqm[7:0] 8o during read, sddqm=1 turns off the output buffers of sdram/sgram. during write, sddqm=1 prevents a write to the current memory location sdclk,sdclk1,sdclk2 3o sdclk, sdclk1 and sdclk2 are driven by the MAP-CA dsp sdram clock. all sdram/sgram input signals are sampled on the positive edge of sdclk sdrtnclk 1i sdrtnclk is driven by sdclk. this signal is used for latching the data from sdram/sgram total 97 table 4-2: memory interface signals .com .com .com .com 4 .com u datasheet
20 pci bus MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.5 pci bus the MAP-CA dsp provides the pci bus as the primary system interface. table 4-3 lists the pci signals. signal # of pins i/o description pci_ad[31:0] 32 b pci multiplexed address and data lines. the address is driven when pci_frame_ is first asserted. data is transferred on this bus in subsequent clocks. pci_cbe_[3:0] 4b for pci cycles, the bus command and byte enables are used to transfer the pci command during the address phase and are used to transfer byte lane enables during subsequent data phases. pci_frame_ 1b transaction framing for pci transfers. the initial assertion indicates the address phase and the start of a pci transaction. continued assertion determines the burst size of the transaction. pci_trdy_ 1b the target ready signal is asserted when the pci target is ready for a data transfer. pci_irdy_ 1b the initiator ready signal is asserted when the pci master is ready for a data transfer. pci_stop_ 1b pci_stop_ is asserted by the target to request the master to stop the current transaction. pci_par 1b a single parity bit is calculated over pci_ad[31:0], and pci_c_be[3:0] and transferred over this signal. pci_devsel_ 1b a target asserts the pci_devsel_ signal line to indicate it has decoded the address on the pci_ad[31:0] bus and will participate in (claim) the current transaction. the pci bus master must monitor the pci_devsel_ signal line to determine if a target bus has claimed the transaction or if it will execute a master abort termination. pci_devsel_ will be tri-stated from the leading edge of pci_rst_. pci_devsel_ remains tri-stated until driven by the target. pci_clk 1i pci_clk provides timing for all pci transactions on the pci bus. all other pci signals are sampled on the rising edge of pci_clk, and all timing parameters are defined with respect to this edge. note: the MAP-CA dsp core clock pll does not use this clock as a core pll reference clock. pci_rst_ 1i this signal indicates a reset of all pci resources. in addition, the internal MAP-CA dsp cpu core, etc. are reset by the assertion of this signal. pci pad cell drivers are disabled by the assertion of this signal, as specified in the pci 2.1 document. table 4-3: pci interface signals .com .com .com .com 4 .com u datasheet
pci bus 21 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 pci_inta_ 1 b (od) when the MAP-CA digital signal processor is not designated as the pci bus ? host ? , then this signal is the open drain output generating an asynchronous level sensitive interrupt on the pci bus. the MAP-CA dsp pad cell does not contain a pull up for this signal. when the MAP-CA dsp is designated as the pci bus ? host ? then this signal is an interrupt request input from pci devices. the MAP-CA dsp sees and utilizes this interrupt. pci_idsel 1i the initialization device select is used as a slot addressed chip select input during configuration read and write transactions. this signal is inactive in a self-hosted configuration. pci_req_[2:0] 3b the assertion of pci_req_ in a non-self-hosted configuration indicates that the MAP-CA dsp desires the use of the pci bus. pci_gnt_[2:0] 3b the assertion of pci_gnt_ in a non-self-hosted environment indicates that the MAP-CA dsp has been granted the use of the pci bus. pci_serr_intb_ 1 b (od) this open drain output may generate either an asynchronous level sensitive interrupt or the pci bus or optionally signal system error. see the MAP-CA digital signal processor configuration control register for the signal ? s current use. when the MAP-CA dsp is not designated as the pci bus ? host ? , then this signal is the open drain output generating an asynchronous level sensitive interrupt on the pci bus. the MAP-CA dsp pad cell does not contain a pull up for this signal. when the MAP-CA dsp is designated as the pci bus ? host ? , then this signal is an interrupt request input from pci devices. the MAP-CA dsp sees and utilizes this interrupt. pci_pme_ 1 b (od) when MAP-CA dsp is not in pci host mode, this signal is an open drain output used to request a change in power management state. when MAP-CA dsp is in pci host mode, this is an input signal to which pci devices indicate changes in power management state. total 54 signal # of pins i/o description table 4-3: pci interface signals .com .com .com .com 4 .com u datasheet
22 iec958 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.6 iec958 the MAP-CA dsp provides an iec958 interface as shown in table 4-4. 4.7 i 2 s the MAP-CA dsp provides interfaces for i 2 s digital audio input and output as shown in table 4-5. signal # of pins i/o description iec958_in 1i serial input line for iec958 digital audio. iec958_out 1o serial output line for iec958 digital audio. total 2 table 4-4: iec958 interface signals signal # of pins i/o description iis_in_data 1i serial data input iis_in_lr 1i select left/right channel in the serial input iis_in_bclk 1i i 2 s input bit clock iis_out_data[2:0] 3o serial output data (3 stereo lines) iis_out_lr 1o select left/right channel in serial output lines iis_out_bclk 1o i 2 s output bit-rate clock total a a. audioclk_out, defined in section 4.3 on page 18, serves as the output mclk in master mode. 8 table 4-5: i 2 s interface signals .com .com .com .com 4 .com u datasheet
multi-function signal pins 23 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.8 multi-function signal pins table 4-6 lists the pin name and pin number of the shared pins on the MAP-CA digital signal processor, along with the signal name associated with each mode-specific function. ball # pin name itu-656 mode tci mode gpdp mode rom boot mode reset mode b4 pixelclk_byp_in - - xmt_clk - - c5 ntsc_out_data[3] - - xmt_data_out[3] rom_addr[5,13]/rom_data[3] reset_strap[3] b5 ntsc_out_data[4] - - xmt_data_out[4] rom_addr[6,14]/rom_data[4] reset_strap[4] a4 ntsc_out_data[5] - - xmt_data_out[5] rom_addr[7,15]/rom_data[5] reset_strap[5] c6 ntsc_out_data[6] - - xmt_data_out[6] rom_addr[8,16]/rom_data[6] reset_strap[6] d7 ntsc_out_data[7] - - xmt_data_out[7] rom_addr[9,17]/rom_data[7] reset_strap[7] b6 video_ina[0] ntsc_ina_data[0] tcia_data[0] rcv_data_in[0] - - c7 video_ina[1] ntsc_ina_data[1] tcia_data[1] rcv_data_in[1] - - d8 video_ina[2] ntsc_ina_data[2] tcia_data[2] rcv_data_in[2] - - a6 video_ina[3] ntsc_ina_data[3] tcia_data[3] rcv_data_in[3] - - b7 video_ina[4] ntsc_ina_data[4] tcia_data[4] rcv_data_in[4] - - a7 video_ina[5] ntsc_ina_data[5] tcia_data[5] rcv_data_in[5] - - c8 video_ina[6] ntsc_ina_data[6] tcia_data[6] rcv_data_in[6] - - d9 video_ina[7] ntsc_ina_data[7] tcia_data[7] rcv_data_in[7] - - b8 video_ina[8] ntsc_ina_hsync tcia_enable rcv_req - - c9 video_ina[9] ntsc_ina_vsync tcia_err# xmt_ack - - a10 ntsc_ina_clk27 - - rcv_clk - - c11 video_inb[0] ntsc_inb_data[0] tcib_data[0] - - - b11 video_inb[1] ntsc_inb_data[1] tcib_data[1] - - - a11 video_inb[2] ntsc_inb_data[2] tcib_data[2] - - - d12 video_inb[3] ntsc_inb_data[3] tcib_data[3] - - - c12 video_inb[4] ntsc_inb_data[4] tcib_data[4] - - - b12 video_inb[5] ntsc_inb_data[5] tcib_data[5] - - - a13 video_inb[6] ntsc_inb_data[6] tcib_data[6] - - - c13 video_inb[7] ntsc_inb_data[7] tcib_data[7] - - - d13 video_inb[8] ntsc_inb_hsync tcib_enable - - - b13 video_inb[9] ntsc_inb_vsync tcib_err# - - - j2 iis_out_data[0] - - - rom_ale - j3 iis_out_data[1] - - - rom_wrt# - h2 iis_out_data[2] - - - rom_ole# - f3 ntsc_out_hsync - - xmt_req rom_addr[21,19,1] - e1 ntsc_out_vsync - - rcv_ack rom_addr[20,18,0] - 22 ntsc_out_data[0] - - xmt_data_out[0] rom_addr[2,10]/rom_data[0] reset_strap[0] e3 ntsc_out_data[1] - - xmt_data_out[1] rom_addr[3,11]/rom_data[1] reset_strap[1] c1 ntsc_out_data[2] - - xmt_data_out[2] rom_addr[4,12]/rom_data[2] reset_strap[2] table 4-6: multiple signal pins .com .com .com .com 4 .com u datasheet
24 multi-function signal pins MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.8.1 transport channel interfaces (tci) the MAP-CA digital signal processor provides two parallel/serial tci interfaces. see table 4-7 and table 4-8 . signal # of pins i/o description tcia_data[7:0] (8) i tci data input: all 8 bits of input are used in parallel mode. only tci_data[0] is used in serial mode tcia_enable (1) i transport channel enable: 1 = accept a tci input sample 0 = ignore tci input sample tcia_inuse 1o video input port external mux select. this pin can also be used as a general purpose output if dynamic muxing of the video input is not required. tcia_sync 1i demodulator/fec has marked the synchronization point in the mpeg2 transport stream packet. the packet size is programmable. tcia_err_ (1) i this active low signal indicates that the demodulator/fec has detected an uncorrectable error in the current packet. tcia_clk 1i transport channel clock total 3(10) table 4-7: primary tci interface signals signal # of pins i/o description tcib_data[7:0] (8) i tci data input: all 8-bits of input are used in parallel mode. only tci_data[0] is used in serial mode. tcib_enable (1) i transport channel enable: 1 = accept a tci input sample 0 = ignore tci input sample tcib_inuse 1o video input port external mux select. this pin can also be used as a general purpose output if dynamic muxing of the video input is not required. tcib_sync 1i demodulator/fec has marked the synchronization point in the mpeg2 transport stream packet. the packet size is programmable. tcib_err_ (1) i this active low signal indicates that the demodulator/fec has detected an uncorrectable error in the current packet. tcib_clk 1i transport channel clock total 3(10) table 4-8: secondary tci interface signals .com .com .com .com 4 .com u datasheet
multi-function signal pins 25 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.8.2 itu-656 inputs analog video can be digitized according to itu-r bt.601/656 via a ntsc, pal or svideo decoder and then input to the MAP-CA dsp. the interface signals for the primary and secondary video inputs are shown in table 4-9 and table 4-10. 4.8.3 itu-656 output the MAP-CA digital signal processor has a digital itu-r bt.601/656 output interface as shown in table 4-11. signal # of pins i/o description ntsc_ina_clk27 1 i 27mhz clock from video decoder ntsc_ina_hsync (1) i horizontal sync ntsc_ina_vsync (1) i vertical sync ntsc_ina_data[7:0] (8) i itu-r bt.601/656 formatted video input stream total 1(10) table 4-9: primary itu-r bt.601/656 input interface signals signal # of pins i/o description ntsc_inb_clk27 1i 27mhz clock from video decoder ntsc_inb_hsync (1) i horizontal sync ntsc_inb_vsync (1) i vertical sync ntsc_inb_data[7:0] (8) i itu-r bt.601/656 formatted video input stream total 1(10) table 4-10: secondary itu-r bt.601/656 input interface signals signal # of pins i/o description pclk (1) i 27mhz pixel clock from vcxo clock input. see section 4.3. ntsc_out_hsync 1o horizontal sync ntsc_out_vsync 1o vertical sync ntsc_out_data[7:0] 8b itu-r bt.601/656 formatted ntsc/pal output data configured as input only when used for rom interface or reset strap total 10(1) table 4-11: itu-r bt.601/656 output interface signals .com .com .com .com 4 .com u datasheet
26 multi-function signal pins MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.8.4 general purpose data port (gpdp) the primary video input port and the video output port can be coupled together to function as a general purpose 8-bit duplex data port. 4.8.5 flash rom a flash rom (eeprom) interface is provided on the MAP-CA digital signal processor to assist in boot-up. the flash rom is active during the boot up process and must be disabled through its chip-select signal. see section 3.3.2, equator hardware reference manual, volume 4, MAP-CA i/o interfaces for information about programming the timing parameters of the rom interface. signal # of pins i/o description xmt_clk (1) i transmitter output clock, shared with pixelclk_byp_in xmt_req (1) o gpdp on MAP-CA digital signal processor is ready to transmit data. shared with ntsc_out_hsync xmt_ack (1) i output source is ready to accept data, shared with video_ina[9] xmt_data_out[7:0] (8) o parallel data output on ntsc_out_data[7:0] rcv_clk (1) i receiver input clock shared with ntsc_ina_clk27 rcv_req (1) i input source is ready to send data. shared with video_ina[8] rcv_ack (1) o gpdp on MAP-CA dsp is ready to accept data, shared with ntsc_out_vsync rcv_data_in[7:0] (8) i parallel data input on video_ina[7:0] total (22) table 4-12: gpdp interface signals .com .com .com .com 4 .com u datasheet
multi-function signal pins 27 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.8.6 reset straps the board resistor straps are sampled on the de-assertion (rising edge) of pci_rst_. signal # of pins i/o description rom_cs_ 1o this pin is the chip enable signal. rom_oe_ (1) o this active low signal is asserted on rom read cycles. this signal is multiplexed with iis_out_data[2]. rom_wrt_ (1) o this active low signal is asserted on rom write cycles. this signal is multiplexed with iis_out_data[1]. rom_ale (1) o address latch enable: rom_addr[9:2] and rom_addr[19:18] are latched on the falling edge, rom_addr[17:10] and rom_addr[21:20] are latched on the rising edge; this signal is multiplexed with iis_out_data[0]. rom_addr[19:18]/ rom_addr[21:20]/ rom_addr[1:0] (2) o rom_addr[19]/rom_addr[21]/rom_addr[1] is muxed with ntsc_out_hsync. rom_addr[18]/rom_addr[20]/rom_addr[0] is muxed with ntsc_out_vsync. rom_addr[9:2]/ rom_addr[17:10]/ rom_data[7:0] (8) b rom data and address bus. these signals are multiplexed with ntsc_out_data[7:0]. total 1(13) table 4-13: rom interface signals signal # of pins i/o description reset_strap[7:4] (sw_strap[3:0]) (4) i resistor straps for use by software. these signals are multiplexed with rom_data[7:4] and ntsc_out_data[7:4]. reset_strap[1] (pci_host) (1) i vdd = 1 = MAP-CA dsp is hosting the primary pci bus gnd = 0 = MAP-CA dsp is not hosting the signal is multiplexed with rom_data[1] and ntsc_out_data[1]. reset_strap[0] (rom_boot) (1) i vdd = 1 = flash rom is used for boot gnd = 0 = romless boot the signal is multiplexed with rom_data[0] and ntsc_out_data[0]. total (6) table 4-14: reset straps .com .com .com .com 4 .com u datasheet
28 analog crt MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.9 analog crt an rgb monitor can be directly driven by the MAP-CA digital signal processor. 4.10 i 2 c the MAP-CA dsp provides an i 2 c interface to communicate with external peripherals such as ntsc decoders, ntsc encoders, and demodulators. the pin description is shown in table 4-16. signal # of pins i/o description vsync 1o vertical synchronization signal for crt hsync 1o horizontal synchronization signal for crt gdac_fscale 1a full scale current adjusting resistor gdac_comp 1a vref bypass and compensation capacitor gdac_blue 1a analog blue output gdac_green 1a analog green output gdac_red 1a analog red output total 7 table 4-15: crt interface signals signal # of pins i/o description iic_sda 1b (od) i 2 c data line iic_sck 1b (od) i 2 c clock line iic_select 1o i 2 c-bus external mux select. this pin can also be used as general purpose output total 3 table 4-16: i 2 c interface signals .com .com .com .com 4 .com u datasheet
boundary scan (jtag) 29 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.11 boundary scan (jtag) MAP-CA dsp supports boundary scan interface based on ieee 1149.1 standard test access port and boundary-scan architecture for testing the MAP-CA dsp and other devices on the board. a bsdl (boundary scan description language) file is available from equator. 4.11.1 pull up resistors the ieee 1149.1 requires that tdi, tms, and trst have internal pull-up resistors. in the MAP-CA digital signal processor, trst has an internal pull-down resistor and trst, as well as other tap pins, can be left unconnected if the system does not use boundary scan. 4.11.2 tap state machine figure 4-2 shows the internal states of the tap (test access port) state machine. these conform to the state transitions specified by ieee 1149.1 . the state changes according to the value on tms at the rising edge of tck. the tdi value is sampled at the rising edge of tck, and shifted at the falling edge. the tdo value changes at the falling edge of tck. when not in the shift-dr or shift-ir state, tdo has a high-impedance. if trst is zero, tdo goes to the test logic reset state asynchronously. signal # of pins i/o description t ck 1i reference clock. this specifies the timing for all the transactions of jtag interface. t ms 1i test interface mode select signal. t di 1i test interface data input t do 1o test interface data output t rst 1i active-low reset for the circuitry. it must be low at power up. total 5 table 4-17: jtag interface signals .com .com .com .com 4 .com u datasheet
30 boundary scan (jtag) MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.11.3 instruction registers the MAP-CA digital signal processor supports public instructions defined in ieee 1149.1 . encoding of the boundary scan instructions are listed in table 4-18. the instruction register is five bits long and instruction bit combinations not listed here are reserved. instruction code description bypass 0b11111 connects tdi and tdo with one bit shift register extest 0b00000 the instruction connects the boundary scan registers and the MAP-CA digital signal processor system pins. sample/ preload 0b11100 sample the MAP-CA dsp output or load the MAP-CA dsp input, without affecting the MAP-CA dsp system pins idcode 0b11001 connects the MAP-CA dsp device with the device identification register between tdi and tdo intest 0b11011 the instruction connects boundary scan registers and MAP-CA dsp internals. clamp 0b11101 sets all system output pins to the value previously loaded by boundary scan instruction. highz 0b11110 places all system output pins in a high-impedance state. table 4-18: jtag instructions test logic reset run test/idle select dr scan capture dr select ir scan capture ir shift ir shift dr exit1 dr pause dr exit2 dr update dr exit1 ir pause ir exit2 ir update ir 1 0 0 1 0 1 1 1 1 0 1 0 0 1 0 1 0 0 1 0 10 0 1 0 0 1 1 0 1 1 1 figure 4-2: tap state transition diagram .com .com .com .com 4 .com u datasheet
boundary scan (jtag) 31 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.11.4 test data registers figure 4-3 illustrates the structure of the boundary scan logic.. 4.11.5 boundary scan register the boundary scan register is a shift register on the pad for controlling the MAP-CA digital signal processor ? s system pins. using extest and sample/preload commands, it can perform a jtag (ieee 1149.1) compliant boundary scan test. the relation between the MAP-CA dsp pins and the boundary scan register can be found in the bsdl. 4.11.6 device identification register figure 4-4 shows the format of the device identification register. for the MAP-CA dsp, the manufacturer ? s id is a twelve bit value equal to b000000001111. the upper twelve bits of the part number are b010001010011. the lower four bits of the part number and the version number varies according to the major or minor revision of the MAP-CA dsp. figure 4-3: boundary scan block diagram boundary scan register device id register bypass register decode logic instruction register tdo tap controller tck trst tms tdi ve rs i o n 4 bit part number manufacturer ? s id 16 bit 12 bit figure 4-4: device identification register .com .com .com .com 4 .com u datasheet
32 power/ground pins MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 4.12 power/ground pins the following power and ground pins are provided on MAP-CA digital signal processor. name # of pins description vdd18 30 digital core vdd vdd33 27 i/o power supply 3.3v vss 57 digital vss avdd18 3 clean analog vdd avss 4 clean analog vss avdd33 1 clean analog vdd avddq 1 clean analog vdd for core pll avssq 1 clean analog vss for core pll avddx 1 clean analog vdd for video dac avssx 1 clean analog vss for video dac gdac_cvgg 1 clean analog vss for video dac total 127 table 4-19: power/ground pins .com .com .com .com 4 .com u datasheet
signal list summary 33 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 4.13 signal list summary interface frequency pin count remarks MAP-CA dsp clocks various 9 reference clocks including bypass clocks pci 66/33 mhz 54 host/system interface sdram 133 mhz 97 memory interfaces (sdram, eeprom) flash rom 5 mhz 1(13) reset straps - (6) configuration inputs iec958 32/44.1/48 khz sample rate 2 digital audio i/o i 2 s 32/44.1/48 khz sample rate 1.536/2.116 mhz bit rate 8 digital audio i/o itu-r bt.601/656 in 27 mhz 28 (22) a a. see section 4.8.4 for more information about the gpdp shared pins. two video input streams: 2 tci or 2 itu-656, or 1 tci and 1 itu-656, or gpdp and 1 video input (tci or itu-656) parallel/serial tci 30/80 mhz gpdp 60 mhz itu-r bt.601/656 out 27 mhz 10(1) digital video out or gpdp crt out 25-110 mhz 7 analog video out i 2 c 100/400 khz 3 peripheral control test 25 mhz 5 boundary scan (jtag) signal pins total - 220 power/ground - 127 miscellaneous - 2 reserved (tie to ground) - 3 no connection (leave floating) total 352 table 4-20: MAP-CA dsp pin list .com .com .com .com 4 .com u datasheet
34 signal list summary MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
35 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 chapter 5 external connection examples 5.1 sdram sdadr[13,9:0] sddata[63:32] sdras# sdcas# sdqm[7:4] sdwe# sdclk sdrtnclk 128 k 2 banks 32-bit sdram 128 k 2 banks 32-bit sdram 128 k 2 banks 32-bit sdram 128 k 2 banks 32-bit sdram sddata[63:32] sddqm[7:4] sdcs#[0] sdcs#[1] sdcs#[3] n.c. sdcs#[2] n.c. figure 5-1: 64-bit, 4mb configuration using 32, 8mb parts sdadr[13,10:0] sddata[63:56] sdras# sdcas# sdqm[7] sdwe# sdclk sdrtnclk 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram 1 m 2 banks 8 bit sdram sddata[55:48] sddqm[6] sddata[47:40] sddqm[5] sddata[39:32] sddqm[4] sdcs#[0] sddata[31:24] sddata[23:16] sddata[16:8] sddata[7:0] sddqm[3] sddqm[2] sddqm[1] sddqm[0] sdcs#[1] n.c. sdcs#[2] n.c. sdcs#[3] n.c. figure 5-2: 64-bit, 16 mb configuration using 8, 16 mb parts .com .com .com .com 4 .com u datasheet
36 sdram MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 sdadr[13:0] sddata[63:48] sdras# sdcas# sdqm[7:6] sdwe# sdclk sdrtnclk 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram 1 m 4 banks 16-bit sdram sddata[47:32] sddqm[5:4] sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] sdcs#[0] sdcs#[1] sdcs#[3] n.c. sdcs#[2] n.c. figure 5-4: 64-bit, 64 mb configuration using 16, 64 mb parts .com .com .com .com 4 .com u datasheet
sdram 37 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 sdadr[13,10:0] sddata[63:48] sdras# sdcas# sdqm[7:6] sdwe# sdclk sdrtnclk 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram 512 k 2 banks 16-bit sdram sddata[47:32] sddqm[5:4] sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] sdcs#[0] sdcs#[1] sdcs#[3] n.c. sdcs#[2] n.c. figure 5-3: 64-bit, 16 mb configuration using 16 16mb parts sdadr[13:0] sddata[63:48] sdras# sdcas# sdqm[7:6] sdwe# sdclk sdrtnclk 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram sddata[47:32] sddqm[5:4] sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] sdcs#[0] sdcs#[1] sdcs#[2] n.c. sdcs#[2] n.c. figure 5-6: 64-bit, 128mb configuration using 16, 128mb parts .com .com .com .com 4 .com u datasheet
38 iec958 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 5.2 iec958 sdadr[13:0] sddata[63:48] sdras# sdcas# sdqm[7:6] sdwe# sdclk sdrtnclk 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram 2m 4 banks 16 bit sdram sddata[47:32] sddqm[5:4] sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] sdcs#[0] sdcs#[2] n.c. sdcs#[2] n.c. sdcs#[1] n.c. figure 5-5: 64-bit, 64mb configuration using 16, 128mb parts iec958_out iec958_in iec958 interface MAP-CA dsp iec958 coupler figure 5-7: iec958 interface .com .com .com .com 4 .com u datasheet
i 2 s 39 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 5.3 i 2 s note: reference designs may use iis_out_bclk and iis_out_lr as input clocks. see the reference board documentation. i 2 s interface i 2 s audio codec i 2 s audio dac i 2 s audio dac iis_in_bclk iis_in_lr iis_in_data iis_out_bclk iis_out_lr iis_out_data[0] MAP-CA dsp iis_out_data[1] iis_out_data[2] audioclk_out adc dac figure 5-8: i 2 s interface .com .com .com .com 4 .com u datasheet
40 transport channel interface (tci) MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 5.4 transport channel interface (tci) satellite/cable source decoder (qam-qpsk) & forward error correction MAP-CA dsp video in port 0 tcia_clk tci_data tcia_enable tcia_sync tcia_err# tcia_inuse 6k 1k 5v cer. tant. o.c. tcia_vdac vcxo 27mhz pclk figure 5-9: transport channel interface .com .com .com .com 4 .com u datasheet
ntsc decoder 41 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 5.5 ntsc decoder 5.6 ntsc encoder ntsc/pal decoder pixel_clk ntsc_ina_hsync ntsc_ina_vsync ntsc_ina_data[7:0] ntsc_ina_clk27 MAP-CA dsp video in port 0 figure 5-10: itu-r bt.656 ntsc/pal decoder interface ntsc_out_hsync ntsc_out_vsync ntsc_out_data[7:0] pclk ntsc/pal encoder vcxo 27mhz itu-r bt.601/656 output MAP-CA dsp figure 5-11: ntsc/pal encoder interface .com .com .com .com 4 .com u datasheet
42 crt MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 5.7 crt 5.8 i 2 c 75 ? c c z 0 = 37.5 ? gdac_green gdac_blue gdac_red vsync hsync gdac_comp v ref = 1.235v l note: gdac_blue and gdac_red have the same connections as those of gdac_green. gdac_fscale r = 1117 ? z l = 75 ? MAP-CA dsp analog crt interface figure 5-12: crt i 2 c MAP-CA dsp iic_sda iic_select i 2 c data line other data line i 2 c clock line other clock line mux mux iic_sck figure 5-13: i 2 c interface .com .com .com .com 4 .com u datasheet
rom 43 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 5.9 rom figure 5-14: rom connections flash rom interface MAP-CA dsp flash rom latch latch latch latch rom_data[7:0] addr[9:2] addr[17:10] rom_addr[1:0] addr[21:20] addr[19:18] rom_cs_l rom_wr_l rom_oe_l rom_ale .com .com .com .com 4 .com u datasheet
44 rom MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 45 chapter 6 electrical specifications 6.1 absolute maximum ratings stresses which occur above or below those listed in table 6-1 may cause permanent damage to the MAP-CA digital signal processor. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2 power supply specifications parameter min max unit vdd18 (measured to vss) -0.5 2.5 v vdd33 (measured to vss) -0.5 4.6 v avdd18 (measured to avss) -0.5 2.5 v avdd33 (measured to avss) -0.5 4.6 v avddq (measured to avssq) -0.5 2.5 v avddx (measured to avss) -0.5 2.5 v voltage on any signal pin a a. this device employs cmos devices on all signal pins. it should be handled as an esd sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v can induce destructive latchup. - 0.5 vdd33 + 0.5 v storage temperature -55 125 o c junction temperature 0 85 o c table 6-1: absolute maximum ratings power supply nominal vo l t a g e vo l t a g e variation vdd18 1.8 v 5% vdd33 3.3 v 5% avdd18 1.8 v 5% avdd33 3.3 v 5% avddx 1.8 v 5% table 6-2: voltage variation .com .com .com .com 4 .com u datasheet
46 dc characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 the typical estimated total power consumption is 6 w. 6.3 dc characteristics note: during power-up, vdd18 must come up before or simultaneously with vdd33. vdd33 should not exceed vdd18 by more than 0.4 v while vdd18 is less than 1v. there is no restriction on the power-down sequence. power supply nominal vo l t a g e estimated max steady state current vdd18 1.8 v 2.8 a vdd33 3.3 v 0.25 a avdd18 1.8 v 10 ma avdd33 3.3 v 80 ma avddx 1.8 v 5 ma table 6-3: steady state current parameter description condition min max unit v il input low voltage - -0.5 0.7 v v ih input high voltage - 0.5 vdd33 vdd33 + 0.5 v v ol output low voltage i out = 1500 a - 0.1 vdd33 v v oh output high voltage i out = 500 a 0.9 vdd33 - v i li input leakage current 0 < v in < vdd33 -10 10 a i oz tri-state output leakage 0 < v in < vdd33 -10 10 a c in input pin capacitance - - 10 pf c idsel idsel pin capacitance - - 8 pf c clk pci_clk pin capacitance - 5 12 pf table 6-4: pci signals .com .com .com .com 4 .com u datasheet
dc characteristics 47 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 parameter description condition min max unit v il input low voltage - -0.5 0.6 v v ih input high voltage - 2.0 vdd33 + 0.5 v v ol output low voltage i out = 2 ma - 0.4 v v oh output high voltage i out = 2 ma 2.4 - v i li input leakage current 0 < v in < vdd33 -10 10 a i lipu leakage current of pull up pin 0 < v in < vdd33 -300 10 a i lipd leakage current of pull down pin 0 < v in < vdd33 -10 300 a i oz tri-state output leakage 0 < v in < vdd33 -10 10 a c in input pin capacitance - - 10 pf c io input/output pin capacitance - - 12 pf table 6-5: non-pci signals parameter min max unit operating temperature 0 75 o c table 6-6: temperature rating note: the relationship between gdac_fscale_f and the full scale output current on iog is: iog (ma) = 24.12 * gdac_comp(v) / gdac_fscale_f(ohm) where gdac_comp is 1.235 v (typical). parameter symbol min typical max unit resolutions (fs) - 8 8 8 bits integral nonlinearity inl - - 2 lsb differential nonlinearity dnl - - 1 lsb table 6-7: video dac outputs .com .com .com .com 4 .com u datasheet
48 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 6.4 ac characteristics the ac timing specifications listed in this section assume a 20 pf load on all output signals of the MAP-CA dsp. 6.4.1 pll reference clock input monotonicity - - guaranteed - - white level relative to blank - 17.69 19.05 20.40 ma white level relative to black - 16.74 17.62 18.50 ma black level relative to blank - 0.95 1.44 1.90 ma blank level on iog - 6.29 7.62 8.96 ma blank level on ior, iob - 0 5 50 a sync level on iog - 0 5 50 a lsb size - - 69.1 - a dac-to-dac matching - - 2 5 % output resistance raout - 37.5 - ? description va l u e rise/fall time 2 ns maximum (0.4v to 2.4v) duty cycle 50% 10% maximum cycle to cycle jitter 200 ps table 6-8: pll reference clock input conditions parameter symbol min typical max unit table 6-7: video dac outputs .com .com .com .com 4 .com u datasheet
ac characteristics 49 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 6.4.2 sdram interface timing correct setup and hold times can be guaranteed through internal delay adjustment, controlled by bits [30:24] of the synchronizer/clock control register in MAP-CA dsp memory block. the sdmrckdly and sdmckdly fields control internal delay circuits that affect the timing of signals going to and from the sdram components. they should be adjusted so that setup and hold requirements of both the sdram and the MAP-CA dsp are met. symbol description min max unit f sdram a a. f sdram = 1 / t sdram sdclk frequency - 133 mhz t os output setup time for address, data, control (sdcs_, sdras_, sdcas_, sdwe_, sddqm) 1.9 - ns t oh b b. the center of the rising edges of sdclk1 and sdclk2 is used as the reference point. output hold time of address, data, control (sdcs_, sdras_, sdcas_, sdwe_, sddqm) 1.5 - ns t ds c, d c. sdrtnclk is used as the reference clock. d. a matching mechanism is provided to compensate for the propagation delay through circuit board traces to and from the external sdram devices. to optimize read timing margin, sdrtnclk should be connected to sdclk with a dedicated trace, with an optional lumped rc load attached to the middle, to account for the number of sdram devices attached to the clock line. input data setup time 1 - ns t dh c, d input data hold time 2 - ns table 6-9: sdram interface timing parameters e e. measured with sdmrckdly = 0 and sdmckdly = 3. sdclk, sdclk1, sdclk2 address, data-out, control sdrtnclk data-in t oh t os t ds t dh t sdram figure 6-1: sdram timing measurement conditions .com .com .com .com 4 .com u datasheet
50 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 6.4.3 pci bus timing v tl v th v test t rval t fval v trise t off t on tri-state output output delay output delay pci_clk v tfall figure 6-2: pci output timing measurement conditions pci_clk input v th v tl v test input valid t su v test t h v test v max v tl v th figure 6-3: pci input timing measurement conditions .com .com .com .com 4 .com u datasheet
ac characteristics 51 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 symbol description min max unit t pci_clk clock cycle time 15 30 ns t high clock high time 6 - ns t low clock low time 6 - ns clk slew clock slew rate 1.5 4 v/ns t su(bus) input set up time to clk, bussed signals 3 - ns t su(ptp) input set up time to clk, point-to-point signals 5 - ns t val(bus) clk to signal valid delay, bussed signals 2 6 ns t val(ptp) clk to signal valid delay, point to point signal 2 6 ns t on float to active delay 2 - ns t off active to float delay - 14 ns t h input hold time from clock 500 - ps t rst a a. pci_rst_ is asserted and de-asserted asynchronously with respect to pci_clk. all output drivers are floated when pci_rst_ is active. reset active time after power stable 1 - ms t rst-clk reset active time after clk stable 100 - s t rst-off reset active to output float delay - 40 ns table 6-10: pci interface timing parameters symbol va l u e unit v max 0.4 vdd33 v v test 0.4 vdd33 v v tfall 0.615 vdd33 v v th 0.6 vdd33 v v tl 0.2 vdd33 v v trise 0.285 vdd33 v input signal slew rate 1.5 v/ns table 6-11: pci measurement conditions .com .com .com .com 4 .com u datasheet
52 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 6.4.4 iec958 interface timing 6.4.5 i 2 s interface timing the audio pll generates audioclk_out for use by external codecs as master mclk. mclk can be programmed for either 12.288 mhz or 16.933 mhz to achieve the desired audio sample rate (lrclk), according to table 6-13. the msb:lsb ordering can be reversed by software programming. symbol description min typical max unit f s audio sample rate 32, 44.1, 48 khz table 6-12: iec958 interface timing parameters lrclk a (khz) a. lrclk = iis_in_lr or iis_out_lr. mclk b (mhz) b. mclk = audioclk_out; mclk defaults to 27 mhz on power-up (audio pll bypassed). sclk c (mhz) c. sclk = iis_in_bclk or iis_out_bclk. mclk/ lrclk mclk/ sclk bits/ frame d d. bits/frame = 2*bits/channel = sclk/lrclk. when mclk/lrclk = 384, 24 bits per channel are always transmitted, but the number of valid bits is selectable from 16, 18, 20 or 24. bits/ channel 48 12.288 1.536 256 8 32 16 44.1 16.933 e e. mclk defaults to 16.933 mhz when audio pll is enabled. 2.116 384 8 48 24 32 12.288 1.536 384 8 48 24 table 6-13: i 2 s clock ratios n n-1 n-2 n-3 32 0 1 l s b m s b nn-1n-2 n-3 32 0 1 l s b m s b left channel right channel one serial bit clock delay from lrclk transmit 4 4 figure 6-4: i 2 s data format .com .com .com .com 4 .com u datasheet
ac characteristics 53 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 symbol description min max unit f s output sample rate 32, 44.1, 48 khz t slr sclk falling to lrclk delay -10 10 ns t sdo sclk falling to sdata valid -10 10 ns table 6-14: i 2 s output timing parameters t slr t sdo iis_out_bclk iis_out_lr iis_out_data figure 6-5: i 2 s output timing measurement conditions t slrh t slrs t low t high t bclk t sds t sdh iis_in_bclk iis_in_lr iis_in_data figure 6-6: i 2 s input timing measurement - slave mode .com .com .com .com 4 .com u datasheet
54 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 symbol description min max unit f s input sample rate 32, 44.1, 48 khz f mclk mclk frequency see table 6-13 from table t bclk sclk period 8/f mclk -from table t low sclk pulse width low 2/f mclk -from table t high sclk pulse width high 2/f mclk -from table t slrh sclk rising to lrclk hold 20 - ns t slrs sclk rising to lrclk setup 20 - ns t sds sdata valid to sclk rising setup 20 - ns t sdh sclk rising to sdata hold time 20 - ns table 6-15: i 2 s input timing parameters - slave mode symbol description min typical max unit f s input sample rate - 32, 44.1, 48 - khz f mclk mclk frequency see table 6-13 from table t bclk sclk period 8/f mclk - - from table t sclkr sclk rising to lrclk edge - t bclk /2 - s t sds sdata valid to sclk rising setup (1/f mclk )+10 - - ns t sdh sclk rising to sdata hold (1/f mclk )+15 - - ns table 6-16: i 2 s input timing parameters - master mode t sclkr t sds t sdh iis_out_bclk iis_out_lr iis_in_data figure 6-7: i 2 s input timing measurement - master mode .com .com .com .com 4 .com u datasheet
ac characteristics 55 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 6.4.6 transport channel interface timing note: the timing diagram and table 6-17 are relevant to the primary tci input port. timing relationships, input setup, and hold times are identical for the secondary tci input port. however, the tci_vdac output is not present on the secondary output port. inputs video_ina[9:0] includes tci_data[7:0] (bits 7:0), tci_enable (bit 8), and tci_err_ (bit 9) internal lrck mclk internal sclk sdata n 2 n n = mclk / sclk figure 6-8: internal serial clock generation for i 2 s master mode tci_clk tci_sync t h t s tci_data tci_enable tci_err_ t tci figure 6-9: tci timing measurement conditions .com .com .com .com 4 .com u datasheet
56 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 6.4.7 itu-r bt.601/656 interface timing symbol description min max unit f tci tci clock frequency a, b, c, d - 27 (parallel) 80 (serial) mhz t h hold time 1 - ns t s setup time 4 - ns table 6-17: tci timing parameters a. in parallel mode, it is required that t core > f tci_clk . b. in serial mode, it is required that t core > ? f tci_clk . c. for correct audio clock counter operation, f core /f audio > 4, where f audio is the frequency of audioclk_out produced by the on-chip pll. d. for correct video clock counter operation, f core /f video > 4, where f video is the frequency of pclk. symbol description min max unit f ntsc_in ntsc input clock frequency - 27 mhz t h input hold time for video_ina[9:0], from cross over of rising clock 1 - ns t s input setup time video_ina[9:0], to the cross over of rising clock 5 - ns table 6-18: itu-r bt.601/656 input interface timing parameters t ntsc_in ntsc_ina_clk27 ntsc_ina_hsync ntsc_ina_vsync ntsc_ina_data[7:0] t s t h figure 6-10: itu-r bt.601/656 input timing measurement conditions .com .com .com .com 4 .com u datasheet
ac characteristics 57 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 . 6.4.8 general purpose data port note: this timing diagram and table include information for the primary video input port. the primary video input bus video_ina[9:0] includes the byte-wide data bus (bits 7:0), horizontal sync (bit 8), and vertical sync (bit 9). the secondary video input signals have identical timing relationships symbol description min max unit t pclk pclk cycle time 18.5 37 ns t delay maximum delay time - 11 ns t hold output hold time 4 - ns table 6-19: itu-r bt.601/656 output interface timing parameters t pclk pclk t delay ntsc_out_data[7:0] ntsc_out_hsync ntsc_out_vsync t hold figure 6-11: itu-r bt.601/656 output timing measurement conditions t rcv rcv_clk rcv_data_in[7:0] rcv_req xmt_ack t s t h figure 6-12: gpdp input timing measurement conditions .com .com .com .com 4 .com u datasheet
58 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 6.4.9 i 2 c interface timing symbol description min max unit t rcv receive clock cycle time - 60 mhz t h hold time 0 - ns t s setup time 4 - ns table 6-20: gpdp input timing parameters symbol description min max unit t xmt transmit clock cycle time - 60 mhz t hold output hold time 3.0 - ns t delay maximum delay time - 8 ns table 6-21: gpdp output timing parameters t xmt xmt_clk t delay xmt_data_out[7:0] xmt_req rcv_ack t hold figure 6-13: gpdp output timing measurement conditions t f t hd_sta t low t r start t su_dat t f t hd_dat t high t hd_sta t su_sta stop t buf t r t su_sto repeated start iic_sda iic_sck start figure 6-14: i 2 c timing measurement conditions .com .com .com .com 4 .com u datasheet
ac characteristics 59 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 symbol a a. all values referred to v ihmin and v ilmax levels. see table 6-5. description standard mode fast mode unit min max min max f sck iic_sck clock frequency. 0 100 0 400 khz t hd_sta hold time (repeated) start condition. after this period, the first clock pulse is generated. 2.3 - 0.57 - s t low low period of the iic_sck clock. 4.7 - 1.27 - s t high high period of the iic_sck clock. 4.0 - 0.6 - s t su_sta setup time for a repeated start condition. 4.7 - 0.6 - s t hd_dat data hold time. 0 b b. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3.45 0 b 0.9 s t su_dat data setup time. 250 - 250 - ns t r rise time of both iic_sda and iic_sck signals. - 1000 20 + 0.1c b c c. c b = total capacitance of one bus line in pf. 300 ns t f fall time of both iic_sda and iic_sck signals. - 300 20 + 0.1c b 300 ns t su_sto setup time for stop condition. 4.0 - 0.6 - s t buf bus free time between a stop and start condition. 4.7 - 1.3 - s c b capacitive load for each bus line. - 400 - 400 pf table 6-22: i 2 c interface timing parameters .com .com .com .com 4 .com u datasheet
60 ac characteristics MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
61 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 appendix a glossary these acronyms and names used in this data sheet . these are their expansion or explanation. bsdl ...............................boundary scan description language datastreamer controller ....high speed dma engine that operates independent from vliw core, also referred to as the ds controller drc .................................display refresh controller dts..................................data transfer switch - high speed MAP-CA dsp series internal data bus fec ..................................forward error correction i-alu ..............................integer alu (arithmetic logic unit) - performs loads, stores, branches, integer arithmetic, and logical operations ig-alu ............................integer, graphics unit - performs integer arithmetic and (partitioned) multimedia operations MAP-CA dsp ..................media accelerated processor for consumer appliances mmu ...............................memory management unit plc ..................................128-bit partitioned local constant register plv ..................................128-bit partitioned local variable register simd ...............................single instruction multiple data tlb..................................translation lookaside buffer vlx ..................................a coprocessor on MAP-CA dsp that can accelerate variable length encoding and variable length decoding. .com .com .com .com 4 .com u datasheet
62 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com .com 4 .com u datasheet
63 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 appendix b package specifications this appendix to the MAP-CA dsp datasheet describes the specifications of the 352 pin bga package b.1 mechanical specifications b.1.1 outline and footprint the following sections use millimeter (mm) as the unit of measure. b.1.1.1 top and bottom views (33.0 sq.) package index 35.00.1 sq. 4-c(1.0) af1 a26 26row 26column (1.27) 25=(31.75) 1.6250.20 af26 a2 (21.64 sq.) bump no.a 1 pkg top view pkg bottom view figure b-1: 352 pin bga outline and footprint - top and bottom views .com .com .com .com 4 .com u datasheet
64 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 b.1.1.2 side view b.2 package materials b.2.1 materials specification segment material package substrate bt resin encapsulation epoxy with filler heat spreader cu + ni plating solder ball 37 pb - 63 sn table b-1: material used. (0.63) (0.5) 1.130.20 0.60.1 (ball height) -c- ma x.0 .4 0 0.20 c // 0.35 c 0.750.15 (1.27) pkg side view note 1. resin height is measured from substrate bottom surface note 2. bump pitch is measured center to center. note 3. package index shows bump #a1 corner. note 4. numbers in () are for reference only. figure b-2: 352 pin bga outline and footprint - side views .com .com .com .com 4 .com u datasheet
65 equator technologies, inc. MAP-CA dsp datasheet june 20, 2001 b.2.2 index location (15.52) package index (16.1) (9.0) (9.0) bga substrate heat spreader
figure b-3: index location .com .com .com .com 4 .com u datasheet
66 MAP-CA dsp datasheet hitachi, ltd. june 20, 2001 .com .com .com 4 .com u datasheet

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