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seiko instruments inc. hardware specification S-7600a tcp/ip network protocol lsi s e ik o in s t r um en t s u sa in c. phone +1-909-934-9334 fax +1-909-975-5699 2 99 0 w es t lo mi ta b ou l e var d t o rr a nc e, ca l i for n ia 90 50 5 S-7600a tcp/ip network protocol stack lsi re v i si on 1. 2
S-7600a hardware specification seiko instruments inc. i table of contents 1. introduction ............................................................................................................................... ............... 1 1.1. p roduct o verview ............................................................................................................................... ... 1 1.2. f eatures ............................................................................................................................... ..................... 1 1.3. b enefits ............................................................................................................................... ...................... 1 1.4. t rademarks ............................................................................................................................... ................ 2 1.5. d efinitions ............................................................................................................................... ................. 2 1.6. a pplicable d ocuments ........................................................................................................................... 2 1.7. c autions ............................................................................................................................... ..................... 2 2. functional block diagram ................................................................................................................ 3 3. terminals ............................................................................................................................... ...................... 4 3.1. p in a ssignment ............................................................................................................................... .......... 4 3.2. p ackage d imensions ............................................................................................................................... .5 3.3. p in d escription ............................................................................................................................... ......... 6 3.4. p in c onfiguration ............................................................................................................................... .... 7 4. electrical characteristics ............................................................................................................. 8 4.1. a bsolute m aximum r atings ................................................................................................................... 8 4.2. r ecommended o perating c onditions ................................................................................................. 8 4.3. dc c haracteristics ............................................................................................................................... .9 4.4. p ower c urrent c onsumption .............................................................................................................. 9 5. mpu interface ............................................................................................................................... ........... 10 5.1. o verview ............................................................................................................................... .................. 10 5.2. p arallel i nterface ............................................................................................................................... 10 5.2.1. 68k family mpu mode .................................................................................................................... 11 5.2.1.1. write cycle timing ............................................................................................................................... ...... 11 5.2.1.2. read cycle timing ............................................................................................................................... ...... 12 5.2.2. x80 family mpu mode .................................................................................................................... 13 5.2.2.1. write cycle timing ............................................................................................................................... ...... 13 5.2.2.2. read cycle timing ............................................................................................................................... ...... 14 5.3. s erial i nterface ............................................................................................................................... ..... 15 5.3.1. write cycle timing ........................................................................................................................... 15 5.3.2. read cycle timing ........................................................................................................................... 16 5.4. i nterrupt ............................................................................................................................... .................. 17 6. memory requirements ....................................................................................................................... 18 6.1. o verview ............................................................................................................................... .................. 18 6.2. m emory i nterface a rchitecture ....................................................................................................... 18 6.3. m emory m ap ............................................................................................................................... ............. 19 7. S-7600a register definitions ........................................................................................................... 20 7.1. o verview ............................................................................................................................... .................. 20 7.2. i api r egister m ap ............................................................................................................................... .. 20 7.3. r egister d efinitions ............................................................................................................................. 23 7.3.1. revision register (0x00) ................................................................................................................ 23 7.3.2. general control register (0x01) ................................................................................................... 23 7.3.3. generic socket location register (0x02) .................................................................................... 24 7.3.4. master interrupt (0x04) ................................................................................................................... 24 7.3.5. serial port configuration / status register (0x08) ..................................................................... 25 7.3.6. serial port interrupt register (0x09) ............................................................................................ 27
S-7600a hardware specification seiko instruments inc. ii 7.3.7. serial port interrupt mask register (0x0a) ................................................................................. 27 7.3.8. serial port data register (0x0b) .................................................................................................. 28 7.3.9. baud rate divider registers (0x0c-0x0d) ................................................................................ 28 7.3.10. our ip address registers (0x10-0x13) ...................................................................................... 28 7.3.11. clock divider registers (0x1c-0x1d) ........................................................................................ 29 7.3.12. index register (0x20) ................................................................................................................... 29 7.3.13. type of service register (tos) (0x21) ..................................................................................... 29 7.3.14. socket config status low register (0x22) ............................................................................... 30 7.3.15. socket status mid register (0x23) ............................................................................................. 32 7.3.16. socket activate register (0x24) ................................................................................................. 33 7.3.17. socket interrupt register (0x26) ................................................................................................. 33 7.3.18. socket data available register (0x28) ...................................................................................... 34 7.3.19. socket interrupt mask low register (0x2a) ............................................................................. 35 7.3.20. socket interrupt mask high register (0x2b) ............................................................................ 35 7.3.21. socket interrupt low register (0x2c) ........................................................................................ 36 7.3.22. socket interrupt high register (0x2d) ....................................................................................... 36 7.3.23. socket data register (0x2e) ...................................................................................................... 37 7.3.24. tcp data send and buffer out length registers (0x30 - 0x31) ........................................... 37 7.3.25. buffer in length registers (0x32-0x33) .................................................................................... 37 7.3.26. urgent pointer / udp datagram size registers (0x34-0x35) ................................................ 37 7.3.27. their port registers (0x36-0x37) ............................................................................................... 38 7.3.28. our port registers (0x38-0x39) .................................................................................................. 38 7.3.29. socket status high register (0x3a) .......................................................................................... 38 7.3.30. their ip address registers (0x3c-0x3f) .................................................................................. 39 7.3.31. ppp control and status register (0x60) ................................................................................... 40 7.3.32. ppp interrupt code (0x61) .......................................................................................................... 41 7.3.33. ppp max retry, (0x62) ................................................................................................................. 41 7.3.34. pap string (0x64) ......................................................................................................................... 42 8. serial port interface ........................................................................................................................ 43 8.1. o verview ............................................................................................................................... .................. 43 8.2. s erial p ort r egister m ap ................................................................................................................... 43 8.2.1. hardware flow control (rts/cts handshaking) ....................................................................... 44 8.2.2. serial port control ............................................................................................................................ 44 9. reset functions ............................................................................................................................... ...... 45 9.1. o verview ............................................................................................................................... .................. 45 9.1.1. hardware reset function .................................................................................................................. 45 9.1.2. software reset function ................................................................................................................... 45 10. application examples ....................................................................................................................... 46 10.1.1. in case of x80 family mpu with lcd controller ....................................................................... 46 10.1.2. in case of 68k family mpu with lcd controller ....................................................................... 47 10.1.3. in case of serial interface with lcd controller .......................................................................... 48
S-7600a hardware specification seiko instruments inc. iii list of figures f igure 2.-1 b lock diagram ..................................................................................................................... 3 f igure 3.-1 p in a ssignment .................................................................................................................... 4 f igure 3.-2 p ackage d imensions ........................................................................................................... 5 f igure 3.-3 c onfiguration of e ach pin ................................................................................................. 7 f igure 5.-4 68 f amily mpu w rite t iming ............................................................................................ 11 f igure 5.-5 68 f amily mpu r ead t iming .............................................................................................. 12 f igure 5.-6 x 80 f amily mpu w rite c ycle t iming .............................................................................. 13 f igure 5.-7 x 80 f amily mpu r ead c ycle t iming ................................................................................ 14 f igure 5.-8 s erial i nterface w rite t iming ......................................................................................... 15 f igure 5.-9 s erial i nterface r ead t iming ......................................................................................... 16 f igure 5.-1 int1 interrupt timing ....................................................................................................... 17 f igure 6.-1 m emory i nterface a rchitecture .................................................................................... 18 f igure 8.-1 s erial d ata f ormat ......................................................................................................... 43 f igure 9.-1 h ardware reset timing ..................................................................................................... 45 f igure 9.-2 s oftware reset timing .................................................................................................... 45 f igure 10.-1 e xample for x 80 f amily mpu ......................................................................................... 46 f igure 10.-2 e xample for 68 k f amily mpu ......................................................................................... 47 f igure 10.-3 e xample for s erial interface ........................................................................................ 48
S-7600a hardware specification seiko instruments inc. iv list of tables t able 3.-1 p in a ssignment ............................................................................................................................... .. 4 t able 3.-2 p in d escription ............................................................................................................................... . 6 t able 4.-1 a bsolute m aximum r atings .................................................................................................. 8 t able 4.-2 r ecommended o perating c onditions ................................................................................. 8 t able 4.-3 dc c haracteristics ............................................................................................................. 9 t able 4.-4 p ower c urrent c onsumption ............................................................................................. 9 t able 5.-1 i nterface s election ........................................................................................................... 10 t able 5.-2 c onnection r elationship between mpu and p ins ........................................................... 10 t able 5.-3 68 k f amily mpu w rite c ycle t iming ................................................................................. 11 t able 5.-4 68 k f amily mpu r ead c ycle t iming .................................................................................. 12 t able 5.-5 x 80 f amily mpu w rite c ycle t iming ................................................................................ 13 t able 5.-6 x 80 f amily mpu r ead c ycle t iming .................................................................................. 14 t able 5.-7 s erial i nterface w rite c ycle t iming .............................................................................. 15 t able 5.-8 s erial i nterface r ead c ycle t iming ................................................................................ 16 t able 5.-9 i nterrupt s election t able ................................................................................................ 17 t able 6.-1 S-7600a m emory m ap (b ank 0).......................................................................................... 19 t able 6.-2 S-7600a m emory m ap (b ank 1).......................................................................................... 19 t able 7.-1 i api r egister m ap .............................................................................................................. 21 t able 7.-2 i api r egister m ap (c ontinued )......................................................................................... 22 t able 7.-3 r evision r egister b it d efinitions .................................................................................... 23 t able 7.-4 r evision r egister d escription ........................................................................................ 23 t able 7.-5 g eneral c ontrol r egister b it d efinitions ..................................................................... 23 t able 7.-6 g eneral c ontrol r egister d escription ......................................................................... 23 t able 7.-7 g eneric s ocket l ocation r egister b it d efinitions ....................................................... 24 t able 7.-8 g eneric s ocket l ocation r egister d escription ............................................................ 24 t able 7.-9 m aster i nterrupt r egister b it d efinitions .................................................................... 24 t able 7.-10 m aster i nterrupt r egister d escriptions (c ontinued )................................................ 25 t able 7.-11 c onf s tatus r egister b it d efinitions ........................................................................... 25 t able 7.-12 c onf s tatus r egister d escription ............................................................................... 26 t able 7.-13 s erial p ort i nterrupt r egister b it d efinitions ............................................................ 27 t able 7.-14 s erial p ort i nterrupt r egister d escription ................................................................ 27 t able 7.-15 s erial p ort i nterrupt m ask r egister b it d efinitions .................................................. 27 t able 7.-16 s erial p ort i nterrupt m ask r egister d escription ...................................................... 27 t able 7.-17 o ur ip a ddress r egister b it d efinitions (0 x 10)............................................................ 28 t able 7.-18 o ur ip a ddress r egister b it d efinitions (0 x 11)............................................................ 28 t able 7.-19 o ur ip a ddress r egister b it d efinitions (0 x 12)............................................................ 29 t able 7.-20 o ur ip a ddress r egister b it d efinitions (0 x 13)............................................................ 29 t able 7.-21 i ndex r egister b it d efinition .......................................................................................... 29 t able 7.-22 i ndex r egister d escription ............................................................................................. 29 t able 7.-23 s ocket c onfig s tatus l ow r egister b it d efinitions .................................................... 30 t able 7.-24 s ocket c onfig s tatus l ow r egister d escription ........................................................ 31 t able 7.-25 s ocket s tatus m id r egister b it d efinitions .................................................................. 32 t able 7.-26 s ocket s tatus m id r egister d escription ...................................................................... 32 t able 7.-27 s ocket a ctivate r egister b it d efinitions ...................................................................... 33 t able 7.-28 s ocket a ctivate r egister d escription .......................................................................... 33 t able 7.-29 s ocket i nterrupt r egister b it d efinitions ................................................................... 33 t able 7.-30 s ocket i nterrupt r egister d escription ........................................................................ 34 t able 7.-31 s ocket d ata a vail r egister b it d efinitions .................................................................. 34 t able 7.-32 s ocket d ata a vail r egister d escription ....................................................................... 34 t able 7.-33 s ocket i nterrupt m ask l ow r egister b it d efinitions .................................................. 35 t able 7.-34 s ocket i nterrupt m ask l ow r egister d escription ...................................................... 35 t able 7.-35 s ocket i nterrupt m ask h igh r egister b it d efinitions ................................................. 35 t able 7.-36 s ocket i nterrupt m ask h igh r egister d escription ...................................................... 35 t able 7.-37 s ocket i nterrupt l ow r egister b it d efinitions ........................................................... 36 t able 7.-38 s ocket i nterrupt l ow r egister d escription ................................................................ 36 t able 7.-39 s ocket i nterrupt h igh r egister b it d efinitions ........................................................... 36
S-7600a hardware specification seiko instruments inc. v t able 7.-40 s ocket i nterrupt h igh r egister d escription ............................................................... 37 t able 7.-41 t heir p ort r egister b it d efinitions (0 x 36).................................................................... 38 t able 7.-42 t heir p ort r egister b it d efinitions (0 x 37).................................................................... 38 t able 7.-43 o ur p ort r egister b it d efinitions (0 x 38) ...................................................................... 38 t able 7.-44 o ur p ort r egister b it d efinitions (0 x 39) ...................................................................... 38 t able 7.-45 s ocket s tatus h igh r egister b it d efinitions ................................................................ 38 t able 7.-46 s ocket s tatus h igh r egister d escription .................................................................... 39 t able 7.-47 t heir ip a ddress r egister b it d efinitions (0 x 3c)......................................................... 39 t able 7.-48 t heir ip a ddress r egister b it d efinitions (0 x 3d)......................................................... 39 t able 7.-49 t heir ip a ddress r egister b it d efinitions (0 x 3e) ......................................................... 39 t able 7.-50 t heir ip a ddress r egister b it d efinitions (0 x 3f) ......................................................... 39 t able 7.-51 ppp c ontrol and s tatus r egister b it d efinitions (0 x 60)............................................ 40 t able 7.-52 ppp c ontrol s tatus r egister d escription .................................................................. 40 t able 7.-53 ppp i nterrupt c ode r egister b it d efinitions ............................................................... 41 t able 7.-54 ppp i nterrupt e rror c odes ........................................................................................... 41 t able 7.-55 ppp m ax r etry r egister ................................................................................................. 41 t able 7.-56 pap s tring f ormat .......................................................................................................... 42 t able 7.-57 pap s tring e xample ......................................................................................................... 42 t able 8.-1 s erial p ort r egister m ap ................................................................................................ 43
s- 7600a hardw a re specif i cat ion seiko instruments inc. 1 1. introduction 1.1. product overview the S-7600a is a lsi that integrates tcp/ip network stack. it offers your devices a quicker and easier connectivity to a network with its on-chip serial interface and a static ram that operates as a buffer. implementing this lsi into your system can significantly reduce your software development cost. also its low operating frequency gives benefits to the power consumption. the S-7600a also supports a microprocessor interface via the iready iapi tm register set, and connection to physical transport layer interface. iapi consists of a set of register and operating definitions that allow any micro controller system to interface with the internal modules. 1.2. feat ures industry standard protocols support : tcp/ip (ver. 4.0) ppp (std-51-compliant) udp general purpose sockets : configured for two sockets mpu interface : 68k/x80(moto/intel) bus interface or synchronous serial interface physical transport layer interface : universal asynchronous receiver/transmitter (uart) low clock rate : multiplied four by the bit-rate operating frequency : 256khz typical low power consumption : full-transmitting operating current consumption : 0.9ma typ. non-transmitting operating current consumption : 150a typ. standby current consumption : 1.0a typ. stand-by mode : held by reset signal wide operating voltage range : 2. 4v to 3.6v easier application development : portable iapi tm support 1.3. be ne fits off-loads mips allowing system to operate with low end and low cost processors. consumes minimal power-up to 1/100 of competing solution.
s- 7600a hardw a re specif i cat ion seiko instruments inc. 2 1.4. t r ademarks iready iapi tm and iapi tm is a trademark of iready corporation. all other products and brand names are trademarks and registered trademarks of their respective companies. 1.5. definitions i p internet protocol ppp point-to-point protocol tcp transmission control protocol udp user datagram protocol api application programming interface 1.6. applicable documents S-7600a functional specification S-7600a api application manual 1.7. cautions 1. do not apply a voltage or current that exceeds the absolute maximum ratings to terminals. if applied, the ic may malfunction or be destroyed. the standard values are set with sufficient margins, but use the ic within the recommended operating conditions to optimize device quality. 2. measures against static electricity when transporting or storing ics, use conductive containers or metal coated boxes. check that there is no current leakage in electrical facilities, and be sure to ground them. also ensure that workbenches and people who handle ics are grounded. excessive external noise to the power supply or i/o terminals of cmos ics causes latch-up, leading to faults and damage. if latch-up has occurred, immediately turn off the device, eliminate the cause, and turn on the device again. keep the ic away from mechanical vibration, shock, and sudden changes in temperature. these may cause wires to break. environment use and store ics below the absolute maximum rated temperature. do not use or store ics where condensation can occur. do not use ics where they are directly exposed to dust, salt, or acid gas such as so 2 . these may cause leaks between element leads and cause corrosion. to store ics for a long time, do not process them. during storage, do not apply any load to ics.
s- 7600a hardw a re specif i cat ion seiko instruments inc. 3 2. functi onal bl ock di agr a m figure 2-1 shows a functional block diagram of the S-7600a. there are blocks of the network stack and other functions related to it. the S-7600a has the interface for a host mpu and a physical layer for various data terminal equipment. figure 2-1 block diagram the transport and network layers contain: two general sockets that provide connectivity between the application layer and the transport layer. tcp/udp module that allows for reliable (retransmission) and unreliable (no retransmission) datagram deliveries. ip module that provides connectionless packet delivery. ppp module that provides point-to-point connection link between two hosts. mpu interface ctsx network stack physical layer interface sram 10kbytes sd(7:0) cs psx c86 rs readx writex busyx intctl int1 int2x dsrx ri rxd dcd dtrx rtsx txd resetx clk ppp ip udp tcp sram interface s2p 16-byte fifo p2s 1-byte buffer
S-7600a hardware specification seiko instruments inc. 4 3. terminals 3.1. pin assignment figure 3-1 shows pin assignment in package. table 3-1 shows signal names, listed by pin number. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 resetx 13 to7 25 ti3 37 sd7 2 test 14 to6 26 rs 38 nc 3 clk 15 to5 27 cs 39 ti2 4 vss 16 to4 28 c86 40 sd6 5 ctsx 17 to3 29 readx 41 ti1 6 dsrx 18 to2 30 vss 42 vdd 7 ri 19 to1 31 psx 43 sd5 8 rxd 20 vdd 32 writex 44 sd4 9 dcd 21 ti7 33 intctrl 45 sd3 10 dtrx 22 ti6 34 int1 46 sd2 11 rtsx 23 ti5 35 int2x 47 sd1 12 txd 24 ti4 36 busyx 48 sd0 table 3-1 pin assignment txd rtsx dtrx dcd rxd ri dsrx ctsx vss clk test resetx 12 ti4 ti5 ti6 ti7 vdd to1 to2 to3 to4 to5 to6 to7 1 48 37 36 25 24 13 ti3 rs cs c86 readx vss psx writex intctrl int1 int2x busyx sd7 nc ti2 sd6 ti1 vdd sd5 sd4 sd3 sd2 sd1 sd0 figure 3-1pin assignment
S-7600a hardware specification seiko instruments inc. 5 3.2. package dimensions S-7600a is housed in a 48-pin qfp package with 0.5mm pin pitch spacing. the package layout is depicted in figure 3-2. figure 3-2 package dimensions 0~ 0. 2 0 1.7 max . 0.20 +0.10 -0.05 0.50 1. 4 0 0 .2 0 9.00.3 7.0 9. 0 0 .3 0. 5 0 .3 112 13 24 25 36 37 48 7. 0 0.15 +0.10 -0.06 unit:mm
s- 7600a hardw a re specif i cat ion seiko instruments inc. 6 3.3. pin d escript i on the pins and signal descriptions are listed by function in table 3-2. name i/o description type vdd1,vdd2 - positive power supply vss1,vss2 - gnd potential resetx i reset input a test, ti1 to ti7 i test input (pull-down resistor is built in) when normal use, connect to v ss or open b to1 to to7 o test output when normal use, c o nn ec t t o v ss or open d clk i clock input c ctsx i clear to send input c dsrx i data set ready input c ri i ring indicator input c rxd i serial received data input c dcd i data carrier detect input c dtrx o data terminal ready output d rtsx o request to send output d txd o serial transmit data output d rs i register selection input c cs i chip selection input c c86 i mpu interface mode selection input 68k mode : 1 x80 mode : 0 c readx i x80 mode : read requirement input 68k mode : enable input c psx i parallel/serial interface selection input c writex i x80 mode : write requirement input 68k mode : read/write selection input c intctrl i int1/int2x drive type(cmos/od) selection input c int1 *ot interrupt output(active high) from S-7600a chip to mpu e int2x *ot interrupt output(active low) from S-7600a chip to mpu e busyx o busy indicator output d sd7 *b x80/68k mode : data bus serial mode : serial data input f sd6 *b x80/68k mode : data bus serial mode : serial clock input f sd5 *b x80/68k mode : data bus serial mode : serial data output f sd0 to sd4 *b data bus f *ot : tri-state output *b : bi-directional table 3-2 pin description
S-7600a hardware specification seiko instruments inc. 7 3.4. pin configuration figure 3-3 shows configuration of each pin. ab cd ef figure 3-3 configuration of each pin pad in in in cin oen oen cin cin vss pad pad pad pad pad
S-7600a hardware specification seiko instruments inc. 8 4. electrical characteristics 4.1. absolute maximum ratings parameter symbol conditions rating unit storage temperature t sta -40 to +125 c operating temperature t opr -10 to +70 c power supply voltage v dd ta=25 c -0.3 to +4.0 v input voltage v in ta=25 c v ss -0.3 to v dd +0.3 v output voltage v out ta=25 c v ss to v dd v table 4-1 absolute maximum ratings 4.2. recommended operating conditions parameter symbol conditions min. typ. max. unit note operating frequency range f opr ta=-10 to +70 c - 0.256 5 mhz 1 clock pulse width pw ta=-10 to +70 c 80 - - ns operating voltage range v dd ta=-10 to +70 c 2.4 - 3.6 v input voltage v in ta=-10 to +70 c 0-v dd v note1: the clock is given by the clk pin and needs to be as four times or more fast as the baud rate. (the multiplier is an integer whose tolerance is <2%) table 4-2 recommended operating conditions
S-7600a hardware specification seiko instruments inc. 9 4.3. dc characteristics unless otherwise specified: v dd =3.0v, v ss =0v, ta=25 c parameter symbol conditions min. typ. max. unit low level input voltage v il 0.2 v dd --v high level input voltage v ih -- 0.8 v dd v low level input leakage current i ll v in =v ss -1.0 - 1.0 a high level input leakage current i lh all input terminals without pull-down resister v in =v dd -1.0 - 1.0 a high level input current i ih all input terminals with pull-down resister v in =v dd 18 70 220 a low level output current i ol v ol =0.4v 5.0 - - ma high level output current i oh v oh =2.6v - - -3.5 ma schmitt hysteresis voltage v wd - 0.46 - v table 4-3 dc characteristics 4.4. power current consumption unless otherwise specified: v dd =3.0v, v ss =0v, ta=25 c parameter symbol conditions min. typ. max. unit full-transmitting operating current consumption i dd1 ta=-10 to +70 c f opr =256khz - 0.9 2.2 ma non-transmitting operating current consumption i dd2 ta=-10 to +70 c f opr =256khz resetx=v ss - 150 300 a standby current consumption is ta=-10 to +70 c - 1.0 15.0 a table 4-4 power current consumption
S-7600a hardware specification seiko instruments inc. 10 5. mpu interface 5.1. overview the S-7600a supports two mpu interfaces: parallel and serial. in parallel interface mode, S-7600a can interface with x80 family mpu or 68k family mpu. psx cs rs read x writex busyx c86 sd7 sd6 sd5 sd4 to sd0 h: parallel x80 cs rs read x writex busyx l d7 d6 d5 d4 to d0 h: parallel 68k cs rs e r/wx busyx h d7 d6 d5 d4 to d0 l: serial cs rs h or l r/wx busyx h or l si scl so hi-z table 5-1 interface selection 5.2. parallel interface setting psx to h select the parallel interface. in parallel interface mode the S-7600a can interface with either x80 family mpu or 68k family mpu. the desired mpu mode can be selected by setting the c86 pin to h or l. rs 68k family mpu r/wx x80 family mpu function readx writex 1 1 0 1 read register 1 0 1 0 write register 0 1 0 1 read index register 0 0 1 0 write index register table 5-2 connection relationship between mpu and pins
s- 7600a hardw a re specif i cat ion seiko instruments inc. 11 5.2.1. 68k family mpu mode this mode can be selected by pulling the c86 input pin h and the psx input pin h. in this mode, the address and data are muxed into a single 8-bit bus. all cycles start by placing an address on the bus and setting the rs pin to l. in this mode writex signal works as read/write(r/wx) signal and readx is the enable(e) signal for 68k family mpu interface. after the address cycle, the mpu generates a read or writes strobe by setting the readx and writex pins. the S-7600a mpu interface logic assert a busyx signal low during data write and read phases. the mpu samples the busyx signal before starting a new cycle. the c p u can initiate a new cycle if the bit is ?h?. 5.2.1.1. w r i t e cycl e t i mi ng figure 5-4 68 family mpu write timing symbol description min max notes t cyc6 system cycle time 100 ns - t ah6 address hold time 20ns - t aw6 address setup time 20ns - t ds6 data setup time 20ns - t dh6 data hold time 20 ns - t ew enable pulse width 40 ns 1.9clk t bd6 busyx delay time - 30ns cl=80pf t bc6 busyx pulse width 2clk - t bod6 busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-3 68k family mpu write cycle timing cs writex (r/wx) clk busyx readx (e) rs sd7 to 0 t ah6 t aw6 t dh6 t ds6 t bd6 t bc6 t dh6 t ah6 t aw6 t cyc6 adress t ew data t ds6 t ew t bod6
s- 7600a hardw a re specif i cat ion seiko instruments inc. 12 5.2.1.2. read cycl e t i mi ng figure 5-5 68 family mpu read timing symbol description min max notes t cyc6 system cycle time 100 ns - t ah6 address hold time 20ns - t aw6 address setup time 20ns - t ds6 data setup time 20ns - t dh6 data hold time 20 ns - t acc6 access time - 30ns cl=80pf t oh6 output disable time 20 ns - cl=80pf t ew enable pulse width 40 ns 1.9clk t bd6 busyx delay time - 30ns cl=80pf t bc 6 busyx pulse widt h 2cl k 3 c lk t bod6 busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-4 68k family mpu read cycle timing cs writex (r/wx) clk busyx readx (e) rs sd7 to 0 t ah6 t dh6 t ds6 t bd6 t bc6 t oh6 t oh6 t aw6 t aw6 t ah6 t acc6 t acc6 t cyc6 t aw6 t ah6 adress data adress t ew t ew t ew t bod6
S-7600a hardware specification seiko instruments inc. 13 5.2.2. x80 family mpu mode this mode is selected by pulling the c86 input pin l and the psx input pin h. in this mode, the address and data are muxed onto a single 8-bit bus. all cycles start with the address placed on the bus. this address is then latched internally on the rising edge of writex . the rs pin l indicates that the writex strobe is for the address phase. in the next phase, data is either written or read by generating writex or readx strobe. the mpu interface logic will assert the busyx signal after readx or writex strobes are de-asserted. the busyx signal is de-asserted after the S-7600a complete a read or writes operation. the mpu samples the busyx signal before starting a new cycle. the mpu can initiate a new cycle after the busyx signal gets de-asserted. 5.2.2.1. write cycle timing figure 5-6 x80 family mpu write cycle timing symbol description min max notes t cyc8 system cycle time 100 ns - t ah8 address hold time 20ns - t aw8 address setup time 20ns - t ds8 data setup time 20ns - t dh8 data hold time 20 ns - t cc8 control pulse width 40 ns 1.9clk t bd8 busyx delay time - 30ns cl=80pf t bc8 busyx pulse width 2clk - t bod8 busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-5 x80 family mpu write cycle timing cs readx clk busyx writex rs sd7 to 0 t ah8 t aw8 t cc8 t dh8 t ds8 t bd8 t bc8 t dh8 t ah8 t aw8 t cyc8 adress data t cc8 t ds8 t bod8
S-7600a hardware specification seiko instruments inc. 14 5.2.2.2. read cycle timing figure 5-7 x80 family mpu read cycle timing symbol description min max notes t cyc8 system cycle time 100 ns - t ah8 address hold time 20ns - t aw8 address setup time 20ns - t ds8 data setup time 20ns - t dh8 data hold time 20 ns - t acc8 access time - 30ns cl=80pf t oh8 output disable time 20 ns - cl=80pf t cc8 control pulse width 40 ns 1.9clk t bd8 busyx delay time - 30ns cl=80pf t bc8 busyx pulse width 2clk - t bod8 busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-6 x80 family mpu read cycle timing cs readx clk busyx writex rs sd7 to 0 t ah8 t dh8 t bd8 t bc8 t oh8 t oh8 t aw8 t aw8 t ah8 t acc8 t acc8 t cyc8 t aw8 t ah8 adress data adress t cc8 t cc8 t cc8 t ds8 t bod8
S-7600a hardware specification seiko instruments inc. 15 5.3. serial interface this mode is selected by pulling the psx input pin l. in this mode bit 6 of the data bus is used as the serial clock and bit 5 and 7 are used as data input and data output. bit 0 to 4 are high impedance. by pulling writex signal to h or l, the mpu performs a read or write operation. 5.3.1. write cycle timing figure 5-8 serial interface write timing symbol description min max notes t cycs system cycle time 100 ns 1.9clk t clls clock l time 40ns - t clhs clocl h time 40 ns - t ass address setup time 20ns - t ahs address hold time 20ns - t dss data setup time 20ns - t dhs data hold time 20 ns - t bds busyx delay time - 30ns cl=80pf t bcs busyx pulse width 2clk - t bods busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-7 serial interface write cycle timing cs writex (r/wx) clk busyx sd6 (scl) rs sd7 (si) t ahs t ass t bds t bcs a7 t ass a6 a5 a4 a3 a2 a1 a0 t ahs t cycs t dss t dhs t bods t clls t clhs d7 d6 d5 d4 d3 d2 d1 d0
S-7600a hardware specification seiko instruments inc. 16 5.3.2. read cycle timing figure 5-9 serial interface read timing symbol description min max notes t cycs system cycle time 100 ns 1.9clk t clls clock l time 40ns - t clhs clocl h time 40 ns - t ass address setup time 20ns - t ahs address hold time 20ns - t dss data setup time 20ns - t dhs data hold time 20 ns - t dds data delay time - 30ns cl=80pf t ohs output disable time - 20ns cl=80pf t bds busyx delay time - 30ns cl=80pf t bcs busyx pulse width 2clk - t bods busyx output disable time - 30ns cl=80pf notes: clk is the clock of S-7600a timing is specified of 50% of the signal waveform. rise/fall time(20%,80%) of the input signal is 15nsec or less. table 5-8 serial interface read cycle timing c s writex c lk b usyx sd6 rs sd7 t ahs t ass t bd t bcs t cycs t dhs t dds t dss t ohs t ahs t ass t ass t ahs t ohs s d5 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t dds t bods a7 a6 a5 a4 a3 a2 a1 a0 t clls t clh
S-7600a hardware specification seiko instruments inc. 17 5.4. interrupt the interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the S-7600as interrupt register. the interrupt signal returns to an inactive level if the flag clears. show the interrupt timing in the figure 5-1. the int1 and int2x can be open drain or cmos output depending on the setting of intctl . the int1 and int2x outputs are cmos if intctl is h otherwise outputs are open drain. table 5-9 defines the interrupt selection. interrupt flag intctl int1 int2x set h h l set l h l reset h l h reset l hi-z hi-z table 5-9 interrupt selection table figure 5-1 int1 interrupt timing cs clk busyx writex rs sd7 to 0 adress data int1 clear interrupt (x80 family mpu mode, intctl=high)
S-7600a hardware specification seiko instruments inc. 18 6. memory requirements 6.1. overview S-7600a contains too general sockets along with the tcp/udp/ip and ppp protocols. their total memory requirement is 10k bytes. this memory is included on the S-7600a chip. 6.2. memory interface architecture the network stack feeds all of its memory requests into a single memory arbiter inside of the network stack core. the arbiter then feeds out one memory request to the sram interface. this interface serves to translate the network stack's timing into signal timing required by the sram. this architecture is shown in figure 6-1. tcp / udp ip ppp network stack serial port memory arbiter sram interface sram figure 6-1 memory interface architecture
S-7600a hardware specification seiko instruments inc. 19 6.3. memory map a custom memory map is generated to compact the size of the sram required to support S-7600a. s- 7600a has two 5k byte memory banks (0 and 1). this mapping is as shown in table 6-1 and table 6- 2. table 6-1 S-7600a memory map (bank 0) address size contents 0x0000 - 0x07ff 2 k socket 0 receive buffer 0x0800 - 0x0bff 1 k socket 0 send buffer 0x0c00 - 0x0fff 1 k tcp data base 0x1000 - 0x13ff 1 k ip buffer table 6-2 S-7600a memory map (bank 1) address size contents 0x0000 - 0x07ff 2 k socket 1 receive buffer 0x0800 - 0x0bff 1 k socket 1 send buffer 0x0c00 - 0x0fff 1 k ppp buffer 0x1000 - 0x13ff 1 k pap buffer
S-7600a hardware specification seiko instruments inc. 20 7. S-7600a register definitions 7.1. overview this section covers the S-7600a's api registers. the register are divided into three types: global, direct and indexed. global registers occupy the address space from 0x00 to 0x1d and 0x60 to 0x6f. direct and indexed registers occupy the configuration space from 0x20 to 0x3f. indexed register require the socket index to be set prior to accessing the registers. 7.2. iapi register map table 7-1 and table 7-2 shows the complete iapi register map for the S-7600a chip. all registers not listed are reserved, and should not be accessed.
S-7600a hardware specification seiko instruments inc. 21 table 7-1 iapi register map add register bit definitions 0x00 revision major revision number minor revision number 0x01 general_control - - - - - - - sw_ rst 0x02 general_socket_ location 0 0 0 0 0 0 s1 s0 0x04 master_interrupt - - - - - pt_ int link _int sock _int 0x08 serial_port_config s_ da v dcd dsr/ hwfc cts ri dtr rts sctl 0x09 serial_port_int pt_ int ------- 0x0a serial_port_int_ mask pint _en dsint_ en ------ 0x0b serial_port_data serial data register 0x0c - 0x0d baud_rate_div baud rate divider registers 0x10 - 0x13 our_ip_address our ip address 0x1c clock_div_low low byte for 1 khz clock divider 0x1d clock_div_high high byte for 1 khz clock divider 0x20 index socket index 0x21 tos* type of service field 0x22 socket_ config_status_low* to buff_ empty buff_ full data_ avail/ rst -protocol_type 0x23 socket_status_mid* urg rst term conu tcp state 0x24 socekt_activate - - - --- s1 s0 0x26 socket_interrupt - - - --- i1 i0 0x28 socket_data_avail - - - --- dav1 dav0 note: 1)reserved bits are signified by a dash (-). all reserved bits should be written as 0. 2)indexed registers are signified by an asterisk (*).
S-7600a hardware specification seiko instruments inc. 22 table 7-2 iapi register map (continued) add register bit definitions 0x2a socket_interrupt_ mask_low* to _ en buff_ emp_ en buff_f ull data_ avail_ en ---- 0x2b socket_interrupt_ mask_high* urg_en rst_ en term_ en conu en ---- 0x2c socket_interrupt_low* to buff_ empty buff_ full data_ avail ---- 0x2d socket_interrupt_high* urg rst te r m conu ---- 0x2e socket_data* socket 8-bit data 0x30 tcp_data_send (wo)* any write causes data to be sent 0x30 - 0x31 buffer_out (ro)* buffer out length 0x32 - 0x33 buffer_in (ro)* buffer in length 0x34 - 0x35 urgent_data_pointer* urgent data offset pointer, udp datagram size 0x36 - 0x37 their_port* target port address 0x38 - 0x39 our_port* our port address 0x3a socket_status_high* - - - - - - - snd _bsy 0x3c - 0x3f their_ip_address* target ip address 0x60 ppp_control_status ppp_int con_ val use_ pap to_ dis ppp_ int_en kick ppp_ en ppp_ up / srset 0x61 ppp_interrupt_code interrupt code 0x62 ppp_max_retry - ppp maximum retry 0x64 ppp_string pap user name and password note: 1)reserved bits are signified by a dash (-). all reserved bits should be written as 0. 2)indexed registers are signified by an asterisk (*).
S-7600a hardware specification seiko instruments inc. 23 7.3. register definitions 7.3.1. revision register (0x00) (read-only, default 0x 21 10 ) this direct read-only register reports back the design revision. see the design revision form in table 7- 3 and table 7-4. table 7-3 revision register bit definitions bit 7 6 5 4 3 2 1 0 def. major revision number minor revision number default 0x 2 1 0x 1 0 table 7-4 revision register description bit bit name access description 7:4 major revision number r this nibble indicates the major revision number for the S-7600a core. 3:0 minor revision number r this nibble indicates the minor revision number for the S-7600a core. 7.3.2. general control register (0x01) (read/write, default 0x00) this direct register contains the master software reset. see the register format in table 7-5 and table 7-6.see the wave format in figure 9.-2. table 7-5 general control register bit definitions bit 7 6 5 4 3 2 1 0 def. -------sw_rst default 0000000 0 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-6 general control register description bit bit name access description 0 sw_rst r/w software reset. this active high reset returns the S-7600a core to power-on reset settings. it is self-clearing and does not need to be written to 0 for proper operations. 0 = normal operation 1 = soft reset
S-7600a hardware specification seiko instruments inc. 24 7.3.3. generic socket location register (0x02) (read-only) this register is used to report back the location of general sockets to the software layer. only bits [1:0] will be set because the S-7600a chip is equipped with two general sockets. table 7-7 generic socket location register bit definitions bit 7 6 5 4 3 2 1 0 def. s7 s6 s5 s4 s3 s2 s1 s0 value 00000011 table 7-8 generic socket location register description bit bit name access description 7 s7 r not available 6 s6 r not available 5 s5 r not available 4 s4 r not available 3 s3 r not available 2 s2 r not available 1 s1 r general socket 1 available 0 s0 r general socket 0 available 7.3.4. master interrupt (0x04) (read-only, default 0x00) this direct register indicates the source of the S-7600a interrupt. table 7-9 master interrupt register bit definitions bit 7 6 5 4 3 2 1 0 def. ----- pt_int link_int sock_int default 0000000 0 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0.
S-7600a hardware specification seiko instruments inc. 25 table 7-10 master interrupt register descriptions (continued) bit bit name access description 2 pt_int r physical transport interrupt the physical transport triggers this interrupt. an application should check the serial port int register to determine the actual cause of the interrupt. 1 link_int r link layer interrupt the link layer triggers this interrupt. an application should check the ppp interrupt code register to determine the actual cause of the interrupt. 0 sock_int r socket interrupt one of the sockets that need servicing causes this interrupt. an application should check the socket interrupt register to determine the actual socket number. 7.3.5. serial port configuration / status register (0x08) (read/write, default 0x0xx110b) this register configures the serial port as shown in table 7-11 and table 7-12. table 7-11 conf status register bit definitions bit 7 6 5 4 3 2 1 0 def. s_dav dcd dsr/ hwfc cts ri dtr rts sctl default 0- 0 - - 1 10
S-7600a hardware specification seiko instruments inc. 26 table 7-12 conf status register description bit bit name access description 7 s_dav r/w serial port data available when read, bit indicates that serial port data is available. this bit should be written 0. 6 dcd r/w carrier detect this bit reflects the current state of the dcd bit on the serial port. it is independent of the sctl bit setting. this bit should be written 0. 5 dsr / hwfc r/w data send ready / hardware flow control when read, this bit reflects the current state of the dsr bit on the serial port. when this bit written: 0 = hardware flow control is deactivated 1 = hardware flow control activated refer to chapter 8 for more information about hardware flow control. 4 cts r clear to send this read-only bit reflects the current state of the cts bit on the serial port. it is independent of the sctl bit setting. 3 ri r ring indicator this read-only bit reflects the current state of the ri bit on the serial port. it is independent of the sctl bit setting. 2 dtr r/w data terminal ready reading this bit follows the current state of the dtr bit on the serial port. the mpu can control the dtr by writing to this bit. 1 rts r/w request to send reading this bit follows the current state of the rts bit on the serial port. the mpu can control the rts by writing to this bit. 0 sctl r/w serial port control this bit determines who controls the serial port. when this bit is low (default), the mpu controls the port. when the sctl bit is high, the network stack controls the serial port. 0 = mpu controls port 1 = hardware controls port
S-7600a hardware specification seiko instruments inc. 27 7.3.6. serial port interrupt register (0x09) (read-only, default 0x000000b) this register indicates the state of the serial port interrupt. table 7-13 serial port interrupt register bit definitions bit 7 6 5 4 3 2 1 0 def. pt_int - - --- - - default 0 - 0 000 0 0 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-14 serial port interrupt register description bit bit name access description 7 pt_int r port transport interrupt this bit indicates when the serial port interrupt is active. this condition depends on the states of the pint_en and dsint_en bits in the serial port interrupt mask register. when pint_en is 1, an interrupt will occur whenever data is available in the serial port input fifo ("s_dav" in the serial port configuration/status register is 1). when dsint_en is 1, an interrupt will be active whenever the cpu can write to the serial port data register to transmit a byte of data. if both pint_en and dsint_en are enabled, the interrupt will be active if either condition is met. 7.3.7. serial port interrupt mask register (0x0a) (read/write, default 0x00) this register enables the serial port interrupts. the default for this register is 0x00 (interrupts disabled). table 7-15 serial port interrupt mask register bit definitions bit 7 6 5 4 3 2 1 0 def. pint_en dsint_en - - - - - - default 0 0 0 000 0 0 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-16 serial port interrupt mask register description bit bit name access description 7 pint_en r/w port interrupt enable this is the enable for the port interrupt. 6 dsint_en r/w data sent interrupt enable. this is enable for the data sent interrupt.
S-7600a hardware specification seiko instruments inc. 28 7.3.8. serial port data register (0x0b) (read/write) this register sends data to and reads data from the serial port uart. the data is valid when the s_dav bit in the serial port config register is set. data can be written to this register when the pt_int bit in the serial port interrupt register is set. see the register description in table 7.-14. note: this register should only be used when the sctl bit in the serial port config register is low. 7.3.9. baud rate divider registers (0x0c-0x0d) (read/write, default 0x0000) these registers set the baud rate for the serial port. calculate the value by using the following formula: program value = [(clk frequency) / (baud rate)] - 1 where clk is the clock for the S-7600a core example: the clock rate of the S-7600a is 256 khz and a baud rate of 64 kbps is desired, the programmed value should be: (256 khz / 64 k) - 1 = 4 - 1 = 3 note: the lowest value that should be programmed into these registers is 0x0003. 7.3.10. our ip address registers (0x10-0x13) (read/write, default 0x00000000) these registers store our ip address or the ip address of the local device. the 0x10 register stores the least significant byte and the 0x13 register stores the most significant byte. if the system controller dose not write an ip address, it will be negotiated for during ppp negotiations (floating ip address). when a ppp connection is established (indicated by bit 0, register 60) these registers can be read to query the ip address obtained. table 7-17 our ip address register bit definitions (0x10) bit 7 6 5 4 3 2 1 0 def. least significant byte of the local ip address default 0x00 table 7-18 our ip address register bit definitions (0x11) bit 7 6 5 4 3 2 1 0 def. 3rd byte of the local ip address default 0x00
S-7600a hardware specification seiko instruments inc. 29 table 7-19 our ip address register bit definitions (0x12) bit 7 6 5 4 3 2 1 0 def. 2nd byte of the local ip address default 0x00 table 7-20 our ip address register bit definitions (0x13) bit 7 6 5 4 3 2 1 0 def. most significant byte of the local ip address default 0x00 7.3.11. clock divider registers (0x1c-0x1d) (read/write, default 0x03e7) these registers program the 1khz clock generator. this clock is used internally for various S-7600a timing functions. the following equation determines the value programmed into these registers: (clk freq/1 khz) - 1 = divide count where clk freq is S-7600a clock frequency. therefore, for a 1 mhz clock, the divide count equals 1m / 1khz - 1= 999 = 0x03e7. 7.3.12. index register (0x20) (read/write, default 0x00) this register must be programmed prior to accessing indexed socket registers. valid programmed values are 0x00 and 0x01. if the socket number has not changed since the last access, this register not need to be reprogrammed. table 7-21 index register bit definition bit 7 6 5 4 3 2 1 0 def. socket index [7:0] default 0x00 table 7-22 index register description bit bit name access description 7:0 socket_index r/w 0x00 : general socket 0 selected 0x01: general socket 1 selected all other values are reserved 7.3.13. type of service register (tos) (0x21) (read/write, default 0x00) this register configures the tos field in the ip header for outgoing datagrams. it is an optional setting that defaults to 0x00.
S-7600a hardware specification seiko instruments inc. 30 7.3.14. socket config status low register (0x22) (read/write, default 0x00) this register configures the socket. table 7-23 socket config status low register bit definitions bit 7 6 5 4 3 2 1 0 def. to buff_ empty buff_full data_ avail / rst -protocol_type default 00 0 00 0 note: reserved bits are signified by a dash ( - ). all reserved bits should be written as 0.
S-7600a hardware specification seiko instruments inc. 31 table 7-24 socket config status low register description bit bit name access description 7 to r tcp timeout this bit indicates that a tcp timeout condition occurred while attempting to establish a tcp connection or while waiting for a tcp packet after the connection was established. 0 = normal operating condition 1 = timeout occurred 6 buff_empty r this bit indicates whether or not a sockets outgoing data buffer is empty. the bit sets on an empty condition. it then clears and remains clear as long as there is any data in the sockets outgoing data buffer. 0 = buffer not empty 1 = buffer empty 5 buff_full r this bit indicates whether space is available to write data. it also triggers an interrupt when the outgoing data buffer is full, and the buff_full_en bit in the socket interrupt mask low register (0x2a) is set. the data register should not be written to when this bit is a 1. 0 = buffer space available 1 = no buffer space available 4 data_avail / rst r/w writing this bit resets all socket parameters to default settings. it is self-clearing and dose not need to be written to low for proper operations. before resetting, ensure that snd_bsy bit of socket status high register (0x3a) is 0. when read, this bit indicates that the socket has data available. 2:0 protocol_type r/w these bits are used to set the protocol of the socket. all decodes not shown are reserved. 010 = tcp client mode 101 = udp mode 110 = tcp server mode
S-7600a hardware specification seiko instruments inc. 32 7.3.15. socket status mid register (0x23) (read-only, default 0x00) this read-only register reports other socket status conditions. table 7-25 socket status mid register bit definitions bit 7 6 5 4 3 2 1 0 def. urg rst term conu tcp state default 0000 0x0 table 7-26 socket status mid register description bit bit name access description 7 urg r this bit indicates the arrival of urgent data. writing a 1 to the urg bit in the socket interrupt register (bit 7) clears this bit. 0 = no urgent data present 1 = urgent data present 6rst r this bit indicates when the socket receives the rst signal from the tcp peer. 0 = no rst received 1 = rst received 5term r this bit indicates when the socket terminates from the source and triggers an interrupt if the term_en bit is set in the socket interrupt mask high register (0x2b). the interrupt mask setting does not effect the reporting of this status bit. 0 = normal operating condition 1 = socket terminated from source this bit becomes 1 when the S-7600a receives a tcp segment with the fin flag on. this means that the remote peer has requested to close the tcp connection. 4 conu r this bit indicates when the socket establishes a connection to a host machine. the bit clears when the connection terminates (by either end). 0 = no connection established 1 = connection established 3:0 tcp state r these bits indicate the current tcp state. 0 = closed 1 = syn_sent 2 = established 3 = close_wait 4 = last_ack 5 = fin_wait1 6 = fin_wait2 7 = closing 8 = time_wait 9 = listen a = syn_recvd
S-7600a hardware specification seiko instruments inc. 33 7.3.16. socket activate register (0x24) (read/write, default 0x00) this register is used to activate the sockets and also show the current status of each socket. setting a bit to 1 activates the corresponding socket. this register defaults to 0x00 upon resets. table 7-27 socket activate register bit definitions bit 7 6 5 4 3 2 1 0 def. ------s1s0 default 00000000 table 7-28 socket activate register description bit bit name access description 1 s1 r/w this bit is used to activate general socket 1. 0 = general socket 1 inactive 1 = general socket 1 active 0 s0 r/w this bit is used to activate general socket 0. 0 = general socket 0 inactive 1 = general socket 0 active 7.3.17. socket interrupt register (0x26) (read-only, default 0x00) this register indicates which socket has interrupts pending. when identification of an interrupting socket occurs, the actual source of the interrupt is determined by examining the specific sockets interrupt register. table 7-29 socket interrupt register bit definitions bit 7 6 5 4 3 2 1 0 def. ------i1i0 default 00000000
S-7600a hardware specification seiko instruments inc. 34 table 7-30 socket interrupt register description bit bit name access description 1 i1 r this bit is used to indicate that socket 1 has an interrupt pending. 0 = general socket 1 interrupt inactive 1 = general socket 1 interrupt active 0 i0 r this bit is used to indicate that socket 0 has an interrupt pending. 0 = general socket 0 interrupt inactive 1 = general socket 0 interrupt active 7.3.18. socket data available register (0x28) (read-only, default 0x00) this read-only register indicates which socket has data pending in the input buffer. a 1 in a bit position indicates that the socket has data available. the bit remains set as long as there is data available. table 7-31 socket data avail register bit definitions bit 7 6 5 4 3 2 1 0 def. - - - - - - dav1 dav0 default 000 0 0 0 0 0 table 7-32 socket data avail register description bit bit name access description 1 dav1 r this bit is used to indicate that socket 1 has data available. 0 = general socket 1 has no data available 1 = general socket 1 has data available 0 dav0 r this bit is used to indicate that socket 0 has data available. 0 = general socket 0 has data available 1 = general socket 0 has data available
S-7600a hardware specification seiko instruments inc. 35 7.3.19. socket interrupt mask low register (0x2a) (read/write, default 0x00) this register reports certain interrupt conditions. setting a bit enables the corresponding interrupt. table 7-33 socket interrupt mask low register bit definitions bit 7 6 5 4 3 2 1 0 def. to_en buff_ emp_en buff_full_en data_avail_en - - - - default 0 0 0 0 0000 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-34 socket interrupt mask low register description bit bit name access description 7 to_en r/w writing a 1 enables the timeout interrupt. 6 buff_empty_en r/w writing a 1 enables the buffer empty interrupt. 5 buff_full_en r/w writing a 1 enables the buffer full interrupt. 4 data_avail_en r/w writing a 1 enables the data available interrupt. 7.3.20. socket interrupt mask high register (0x2b) (read/write, default 0x00) this register enables certain types of interrupt conditions. setting bits enables their corresponding interrupts. table 7-35 socket interrupt mask high register bit definitions bit 7 6 5 4 3 2 1 0 def. urg_en rst_en term_en conu_en - - - - default 00 000000 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-36 socket interrupt mask high register description bit bit name access description 7 urg_en r/w writing a 1 to enable the urgent data interrupt. 6 rst_en r/w writing a 1 to enable the connection reset interrupt. 5 term_en r/w writing a 1 to enable the socket termination interrupt. 4 conu_en r/w writing a 1 to enable the connection up interrupt.
S-7600a hardware specification seiko instruments inc. 36 7.3.21. socket interrupt low register (0x2c) (read/write, default 0x00) this register reports certain interrupt conditions. when an interrupt condition occurs and its enable bit is set, the hardware sets the corresponding bit. writing a "1" to the bit clears it. disabling the corresponding enable bit prevents the interrupt from showing. table 7-37 socket interrupt low register bit definitions bit 7 6 5 4 3 2 1 0 def. to buff_emplty buff_full data_avail - - - - default 0 0 0 0 0000 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0. table 7-38 socket interrupt low register description bit bit name access description 7 to r/w this interrupt is generated when a timeout condition occurred while trying to establish a connection. writing a 1 to this bit clears the interrupt. 6 buff_empty r/w this interrupt is generated when outgoing buffer is empty. writing a 1 to this bit clears the interrupt. 5 buff_full r/w this interrupt is generated when there is more buffer space available. writing a 1 to this bit clears the interrupt. 4 data_avail r/w this interrupt is generated when data is available from the incoming buffer. writing a 1 to this bit clears the interrupt. 7.3.22. socket interrupt high register (0x2d) (read/write, default 0x00) this register reports certain interrupt conditions. when an interrupt condition occurs and its enable bit is set, the hardware sets the corresponding bit. writing a "1" to the bit clears it. disabling the corresponding enable bit prevents the interrupt from showing. table 7-39 socket interrupt high register bit definitions bit 7 6 5 4 3 2 1 0 def. urg rst term conu - - - - default 00000000 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0.
S-7600a hardware specification seiko instruments inc. 37 table 7-40 socket interrupt high register description bit bit name access description 7 urg r/w this interrupt is generated when urgent data arrives. the system interface should read the urgent data pointer register to see the location of the data. writing a 1 to this bit clears the interrupt. 6 rst r/w this interrupt is generated when a tcp peer sends the socket rst flag indicating that the current tcp session is not valid. writing a 1 to this bit clears this interrupt. when this condition occurs, the hardware no longer operates and re-initializing the socket is recommended. 5 term r/w this interrupt is generated when the socket connection is terminated and a tcp fin flag is received. writing a 1 to this bit clears the interrupt. 4 conu r/w this interrupt is generated when a connection is established. writing a 1 to this bit clears the interrupt. 7.3.23. socket data register (0x2e) (memory mapped read/write, default 0x00) this register is used by a system controller to read incoming data packets and write outgoing data. data transmissions start for tcp connections only after a write occurs at 0x30. 7.3.24. tcp data send and buffer out length registers (0x30 - 0x31) (read/write, default 0x03ff) when read, these registers report the amount of space available in the outgoing buffer. register 0x30 stores the least significant byte; 0x31 stores the most significant byte. writing any data to 0x30 causes data transmissions to start on tcp connections. 7.3.25. buffer in length registers (0x32-0x33) (read-only, default 0x0000) these read-only registers report the amount of data available in the received data buffer. 0x32 stores the least significant byte; 0x33 stores the most significant byte. 7.3.26. urgent pointer / udp datagram size registers (0x34-0x35) (read-only, default 0x0000) these read-only registers report the offset to the start of urgent data (as marked through the tcp header) relative to the incoming data buffer. register 0x34 stores the least significant byte; 0x35 stores the most significant byte. when a socket is configured as a udp socket, these registers indicate the size of the current udp datagram. the least significant byte is stored in 0x34 and the most significant byte is stored in 0x35.
S-7600a hardware specification seiko instruments inc. 38 7.3.27. their port registers (0x36-0x37) (read/write, default 0x0000) these registers specify the destination port for an outgoing data packets. for client mode, this value must be set prior to activating the socket. for tcp server mode, these register are automatically setup on a connection with the peers port number. register 0x36 stores the least significant byte and 0x37 stores the most significant byte. table 7-41 their port register bit definitions (0x36) bit 7 6 5 4 3 2 1 0 def. least significant byte of the target port number default 0x00 table 7-42 their port register bit definitions (0x37) bit 7 6 5 4 3 2 1 0 def. most significant byte of the target port number default 0x00 7.3.28. our port registers (0x38-0x39) (read/write) these registers are used it indicate the source port for an outgoing data packet. when setting a tcp client or sending data using udp, these registers should be set to the proper value. normally in client applications, the software increments the value of this register. the tcp and udp server application should set these registers to be the value used by the server applications. register 0x38 stores the least significant byte; 0x39 stores the most significant byte. table 7-43 our port register bit definitions (0x38) bit 7 6 5 4 3 2 1 0 def. least significant byte of the local port number default 0x00 table 7-44 our port register bit definitions (0x39) bit 7 6 5 4 3 2 1 0 def. most significant byte of the local port number default 0x00 7.3.29. socket status high register (0x3a) (read-only, default 0x00) this register reports the busy status of the socket. table 7-45 socket status high register bit definitions bit 7 6 5 4 3 2 1 0 def. - - - - - - - snd_bsy default 00000000 note: reserved bits are signified by a dash (-). all reserved bits should be written as 0.
S-7600a hardware specification seiko instruments inc. 39 table 7-46 socket status high register description bit bit name access description 0 snd_bsy r this bit indicates that the current socket is busy sending tcp segments. before the socket is reset, this bit should be 0. 0 = socket not busy 1 = socket busy 7.3.30. their ip address registers (0x3c-0x3f) (read/write, default 0x00000000) these registers indicate the destination ip address for the socket. the value must be set prior to activating the socket. the registers can be written in any order. table 7-47 their ip address register bit definitions (0x3c) bit 7 6 5 4 3 2 1 0 def. least significant byte of destination ip address default 0x00 table 7-48 their ip address register bit definitions (0x3d) bit 7 6 5 4 3 2 1 0 def. 3rd byte of destination ip address default 0x00 table 7-49 their ip address register bit definitions (0x3e) bit 7 6 5 4 3 2 1 0 def. 2nd byte of destination ip address default 0x00 table 7-50 their ip address register bit definitions (0x3f) bit 7 6 5 4 3 2 1 0 def. most significant byte of destination ip address default 0x00
S-7600a hardware specification seiko instruments inc. 40 7.3.31. ppp control and status register (0x60) (read/write, default 0x00) this register control the ppp layer and reports its status. table 7-51 ppp control and status register bit definitions (0x60) bit 7 6 5 4 3 2 1 0 def. ppp_int con_val use_ pap to_dis ppp_int_en kick ppp_en ppp_up /srst default 0000 0000 table 7-52 ppp control status register description bit bit name access description 7 ppp_int r/w ppp interrupt this bit indicates that the ppp triggered an interrupt condition. read the ppp interrupt code register to determine the cause. writing a 1 to this bit position clears the interrupt. 6 con_val r/w connection valid this bit indicates to the network stack that the underlying connection is up and valid. 0 = connection down 1 = connection up 5 use_pap r/w this bit enables pap authentication within the ppp protocol. if enabled, a pap request is issued after pap authentication is negotiated. the pap string enters through register 0x64. 0 = pap disabled (default) 1 = pap enabled 4to_dis r/w timeouts disabled this bit disables the ppp block from timeouts for diagnostic purposes. it should remain enable for normal operations. 0 = timeouts enabled (default) 1 = timeouts disabled 3 ppp_int_en r/w ppp interrupt enable this bit enables the ppp interrupt. 0 = ppp interrupt disabled (default) 1 = ppp interrupt enabled 2kick w ppp kick start when written to a 1, this bit will start the ppp if it falls into a timeout condition. it clears once the kick operation performs. this bit is self-clearing. 1 ppp_en r/w ppp enable this bit enables the ppp layer. the bit must be set before any transmissions occur. 0 = ppp disabled (default) 1 = ppp enabled
S-7600a hardware specification seiko instruments inc. 41 bit bit name access description 0 ppp_up/srst r/w when read, this bit indicates when the ppp layer establishes a connection. 0 = ppp connection down 1 = ppp connection established when written, this bit will reset the ppp engine. it is self- clearing and goes not need to be written low for normal operations. 0 = ppp normal operation 1 = ppp reset 7.3.32. ppp interrupt code (0x61) (read-only, default 0x00) this register indicates the interrupt condition that causes the ppp interrupt to trigger. table 7-53 ppp interrupt code register bit definitions bit 7 6 5 4 3 2 1 0 def. ppp interrupt code default 0 table 7-54 ppp interrupt error codes error code definition 0x00 reserved 0x01 ppp failed initial lcp negotiations 0x02 ppp failed ncp negotiations 0x03 unexpected lcp closure 0x04 termination request received 0x05 pap failed negotiations 7.3.33. ppp max retry, (0x62) (read/write, default 0x0a) this register configures the maximum retry number. this number is used to determine the maximum number of configuration requests that are sent during the ppp negotiation stage. table 7-55 ppp max retry register bit 7 6 5 4 3 2 1 0 def. - ppp maximum retry default 0x0 0xa note: reserved bits are signified by a dash (-).
S-7600a hardware specification seiko instruments inc. 42 7.3.34. pap string (0x64) (write-only) this write-only register enters the string for the pap configuration request packet. enter the string according to the format shown table 7-56. table 7-56 pap string format byte string [0] length of username [1] first byte of username [2] second byte of username [n] last byte of username (where n is the length of the username string) [n+1] length of password [n+2] first byte of password [n+m+1] last byte of password (where m is the length of the password string) as an example, if the username string is joe and the password is public, enter the bytes as shown in table 7-57. table 7-57 pap string example byte:0 0x03 length of username string byte:1 0x6a character j byte:2 0x6f character o byte:3 0x65 character e byte:4 0x06 length of password string byte:5 0x70 character p byte:6 0x75 character u byte:7 0x62 character b byte:8 0x6c character l byte:9 0x69 character i byte:a 0x63 character c if pap is used, the use_pap bit must be set in the ppp control and status register (0x60) prior to entering the pap string.
s- 7600a hardw a re specif i cat ion seiko instruments inc. 43 8. serial port interface 8.1. overview the S-7600a chip contains a on-board serial port for physical transports. the data format of the serial port is fixed at 1 start bit (logic "0"), 8 data bits, 1 stop bit (logic "1") and no parity bits. the data bits are sent out, least significant bit first. this data format is shown in figure 8-1. also included with the serial port is a 16- bi t receive fifo and a n 8 - bi t send buffer. figur e 8-1 s e r ial d a ta format 8.2. serial port r e gist er m a p the following registers are used to communicate with the serial port. table 8-1 serial port register map add register bit definitions 0x08 serial_port_config s_dav dcd dsr/ hwfc cts r i d tr rts sctl 0 x 0 9 se r i al_po r t_in t p t _ in t ds i nt - - - - - - 0x0a serial_port_int_ mask pin t _ e n dsint_ en ------ 0x0b serial_port_data serial port data register 0x0c - 0x0d baud_rate_div baud rate divider registers rxd / txd start stop d0 d1 d2 d3 d4 d5 d6 d7
S-7600a hardware specification seiko instruments inc. 44 8.2.1. hardware flow control (rts/cts handshaking) the hardware flow control is turned off by default. in this mode, data is transmitted independent of the state of the ctsx signal. while the mpu is in control of the serial port, it can monitor the state of all the serial port control signals and control when data gets sent or received, either through polling the status bits or interrupts. it can also control the rtsx signal by asserting the rts bit in the serial port config register. when the S-7600a controls the serial port, data will be sent out as soon as it is available from the ppp layer. when receiving data, the software in the mpu control mode should read the data out of the 16-byte fifo fast enough to prevent buffer overflow. hardware flow control can be turned on by writing a "1" to bit 5 ( dsr/hwfc ) of the serial port config register (0x08). with the hardware flow control turned on, full rts/cts handshaking is supported. when the serial port detects that cts is de-asserted, it will stop sending data until cts is reasserted. any byte output at the time cts is de-asserted will complete, but no further bytes will be sent until cts is asserted. in the other direction, the S-7600a will de-assert rts if the serial ports 16-byte fifo is half full. this indicates to the machine on the other end of the serial line to stop transmitting data. the rts bit will reassert when the mpu or the S-7600a has read data out of the receive fifo and room becomes empty. if the machine communicating with the S-7600a over the serial port does not support rts/cts handshaking, the receive fifo may overflow and data loss will occur. 8.2.2. serial port control the control of the serial port is turned over to the mpu by default and after any reset condition. in this mode, any data written to the serial port data register will be sent out and all data received will be made available to the mpu via this same register. prior to using the data register, the mpu should set the baud rate div register to the proper setting. an interrupt can be triggered when data is available from the serial port by asserting the pint_en bit. when this bit is asserted, an interrupt will trigger any time that there is data available to be read from the port. if there is more then one byte in the receive fifo, the interrupt will remain active until all bytes are read. an interrupt can also trigger indicating that the outgoing data byte has been sent, by asserting the dsint_en bit. this interrupt will trigger whenever there is no more data to be sent. the mpu turns over control to the S-7600a by asserting the sctl bit in the serial port config register. when the S-7600a controls the port, the mpu should not access the serial port data register. the s- 7600a chip will automatically send ppp packets to the serial port and read incoming bytes from the serial port. the serial port interrupts are not valid when the S-7600a controls the port.
S-7600a hardware specification seiko instruments inc. 45 9. reset functions 9.1. overview the S-7600a has two reset functions which are hardware reset and software reset. 9.1.1. hardware reset function the S-7600a operates to be synchronous to the clk signal(clock input). when the resetx pin set to low level in one clock period minimum, the S-7600a accept hardware reset input and starts initializing internal circuit at positive edge timing of forth clock. after the resetx pin return to high level, the s- 7600a maintains initialized state and turns normal state at positive edge timing of forth clock. see the figure 9-1. figure 9-1 hardware reset timing 9.1.2. software reset function the S-7600a is able to initialize the internal circuit by the general control register(0x01). show the reset timing in case of x80 family mpu mode. see the figure 9-2. figure 9-2 software reset timing initialized 2n 1s 3r d 4t h 4t h 3r d 2n d 1s clk resetx min. 1 clock normal normal state normal state cs clk busyx writex rs sd7 to 0 address data h01 initialized state 80 family mpu mode
s- 7600a hardw a re specif i cat ion seiko instruments inc. 46 10. application examples 10.1.1. in case of x80 family mpu with lcd controller figure 10-1 example for x80 family mpu lcd controller (s-4592,etc.) S-7600a x80 f a mi l y mpu -personal computer -modem -pdc -piafs driver/ receiver decoder ps writex readx cs sd0 to sd7 rs res wr wr rd rd d0 to d7 iorq a1 to a7 a0 reset c86 c86 psx cs rs d0 to d7 res
S-7600a hardware specification seiko instruments inc. 47 10.1.2. in case of 68k family mpu with lcd controller figure 10-2 example for 68k family mpu lcd controller (s-4592,etc.) S-7600a 68k family mpu -personal computer -modem -pdc -piafs driver/ receiver decoder ps r/wx (writex) e (readx) cs sd0 to sd7 rs res r/w wr e rd d0 to d7 vma a1 to a7 a0 reset c86 c86 psx cs rs d0 to d7 res
S-7600a hardware specification seiko instruments inc. 48 10.1.3. in case of serial interface with lcd controller figure 10-3 example for serial interface lcd controller (s-4592,etc.) S-7600a mpu -personal computer -modem -pdc -piafs driver/ receiver ps scl (sd6) so (sd5) cs si (sd7) rs res sclk scl sin so sout port2 port1 reset c86 c86 readx cs rs si res psx port3 busy
s- 7600a hardw a re specif i cat ion seiko instruments inc. 49 seiko instruments inc. 1-8, nakase, mihama-ku, chiba-shi, chiba 261, japan components sales div. telephone : +81-43-211-1196 facsimile : +81-43-211-8032 e-mail : component@sii.co.jp seiko instruments usa inc. electronic components div. 2990 w. lomita blvd, torrance, ca 90505, usa telephone : +1-909-934-9334 facsimile : +1-909-975-5699 e-mail : seiko-ecd@salessupport.com h tt p://www.seiko-usa-ecd.com notice if the products, systems, or assemblies, incorporating seiko instruments inc. tcp/ip network protocol stack lsi infringe upon any patent, copyright, or other intellectual property right, seiko instruments inc. shall not be responsible for any matters or damages arising out of or in connection with such patent copyright or other intellectual property right infringement.

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