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| july 2005 1/167 rev. 4.0 ST7LITE3 8-bit mcu with single voltage flash, data eeprom, adc, timers, spi, linsci ? memories ? 8 kbytes program memory: single voltage ex - tended flash (xflash) program memory with read-out protection, in-circuit programming and in-application programming (icp and iap), data retention: 20 years at 55c. ? 384 bytes ram ? 256 bytes data eeprom with read-out pro - tection. 300k write/erase cycles guaranteed, data retention: 20 years at 55c. clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and an auxiliary voltage detector (avd) with interrupt capability for implement - ing safe power-down procedures ? clock sources: internal rc1% oscillator, crys - tal/ceramic resonator or external clock ? optional x4 or x8 pll for 4 or 8 mhz internal clock ? five power saving modes: halt, active-halt, wait and slow, auto wake up from halt i/o ports ? up to 15 multifunctional bidirectional i/o lines ?7 high sink outputs 5 timers ? configurable watchdog timer ? two 8-bit lite timers with prescaler, 1 realtime base and 1 input capture ? two 12-bit auto-reload timers with 4 pwm outputs, input capture and output compare functions 2 communication interfaces ? master/slave linsci ? asynchronous serial interface ? spi synchronous serial interface interrupt management ? 10 interrupt vectors plus trap and reset ? 12 external interrupt lines (on 4 vectors) a/d converter ? 7 input channels ? 10-bit resolution instruction set 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions development tools ? full hardware/software development package ? dm (debug module) device summary dip20 so20 features ST7LITE30 ST7LITE35 ST7LITE39 program memory - bytes 8k ram (stack) - bytes 384 (128) data eeprom - bytes - - 256 peripherals lite timer, autoreload timer, spi, linsci, 10-bit adc operating supply 2.7v to 5.5 v cpu frequency up to 8mhz (w/ ext osc up to 16mhz) up to 8mhz (w/ ext osc up to 16mhz and int 1mhz rc 1% pllx8/4mhz) operating temperature -40c to +85c packages so20 300?, dip20 1
table of contents 2/167 ST7LITE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 data eeprom read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 table of contents 3/167 9.6 auto wake up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 dual 12-bit autoreload timer 3 (at3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.5 linsci serial communication interface (l in master/slave) . . . . . . . . . . 88 11.6 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 151 13.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 15.1 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.2 device ordering info rmation and transfer of customer code . . . . 160 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.1 clearing active interrupts outside interrupt routine . . . . . . . . . . . . 163 16.2 linsci limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3 ST7LITE3 4/167 1 introduction the ST7LITE3 is a member of the st7 microcon - troller family. all st7 devices are based on a com - mon industry-standard 8-bit core, featuring an en - hanced instruction set. the ST7LITE3 features flash memory with byte-by-byte in-circuit programming (icp) and in- application programm ing (iap) capability. under software control, the ST7LITE3 device can be placed in wait, slow, or halt mode, reduc - ing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro - controllers feature true bit manipulation, 8x8 un - signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 13 on page 129 . the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. figure 1. general block diagram 8-bit core alu address and data bus reset port a control ram (384 bytes) pa7:0 (8 bits) v ss v dd power supply program (8k bytes) lvd memory 8-bit lite timer 2 port b spi pb6:0 (7 bits) wdg adc 12-bit auto-reload timer 2 linsci debug module osc1 osc2 internal clock pll x 8 ext. 1mhz int. 1mhz 1% rc osc to 16mhz clkin / 2 or pll x4 data eeprom ( 256 bytes) 1 ST7LITE3 5/167 2 pin description figure 2. 20-pin so and dip package pinout 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v ss v dd ain5/pb5 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 ss /ain0/pb0 osc1/clkin osc2 pa5 (hs)/atpwm3/iccdata pa4 (hs)/atpwm2 pa3 (hs)/atpwm1 pa2 (hs)/atpwm0 pa1 (hs)/atic pa0 (hs)/ltic (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 rdi/ain6/pb6 pa7 (hs)/tdo pa6/mco/iccclk/break reset ei3 ei2 ei0 ei1 ei2 1 ST7LITE3 6/167 pin description (cont?d) legend / abbreviations for table 1 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ? output: od = open drain, pp = push-pull the reset configuration of each pin is shown in bold which is valid as lo ng as the device is in reset state. table 1. device pin description pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1 v ss s ground 2 v dd s main power supply 3 reset i/o c t x x top priority non maskable interrupt (active low) 4 pb0/ain0/ ss i/o c t x ei3 x x x port b0 adc analog input 0 or spi slave select (active low) caution: no negative current injection allowed on this pin. for details, refer to section 13.2.2 on page 130 5 pb1/ain1/sck i/o c t x x x x port b1 adc analog input 1 or spi serial clock caution: no negative current injection allowed on this pin. for details, refer to section 13.2.2 on page 130 6 pb2/ain2/miso i/o c t x x x x port b2 adc analog input 2 or spi master in/ slave out data 7 pb3/ain3/mosi i/o c t x ei2 x x x port b3 adc analog input 3 or spi master out / slave in data 8 pb4/ain4/ clkin** i/o c t x x x x x port b4 adc analog input 4 or external clock input 9 pb5/ain5 i/o c t x ei2 x x x port b5 adc analog input 5 10 pb6/ain6/rdi i/o c t x x x x port b6 adc analog input 6 or lin sci input 11 pa7/tdo i/o c t hs x x x x port a7 linsci output 1 ST7LITE3 7/167 note: for input with interrupt possibility ?ei x ? defines the associated external interrupt vector which can be as - signed to one of the i/o pins using the eisr register. each interrupt can be either weak pull-up or floating defined through option register or. 12 pa6 /mco/ iccclk/ break i/o c t x ei1 x x port a6 main clock output or in circuit commu - nication clock or external break caution: during normal operation this pin must be pulled- up, internally or ex - ternally (external pull-up of 10k manda - tory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in t he application, even if the pin is configured as output, any re - set will put it bac k in input pull-up. 13 pa5 /atpwm3/ iccdata i/o c t hs x x x port a5 auto-reload timer pwm3 or in circuit communication data 14 pa4/atpwm2 i/o c t hs x x x port a4 auto-reload timer pwm2 15 pa3/atpwm1 i/o c t hs x ei0 x x port a3 auto-reload timer pwm1 16 pa2/atpwm0 i/o c t hs x x x port a2 auto-reload timer pwm0 17 pa1/atic i/o c t hs x x x port a1 auto-reload timer input capture 18 pa0/ltic i/o c t hs x x x x port a0 lite timer input capture 19 osc2 o resonator oscillator inverter output 20 osc1/clkin i resonator oscillator inverter input or external clock input pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1 ST7LITE3 8/167 3 register & memory map as shown in figure 3 , the mcu is capable of ad - dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 384 bytes of ram, 256 bytes of data eeprom and 8 kbytes of user pro - gram memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see fig - ure 3 ) mapped in the upper part of the st7 ad - dressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device op - tions are configurable by option byte. important: memory locations marked as ?re - served? must never be accessed. accessing a re - seved area can have unpredictable effects on the device. figure 3. memory map 1. dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flash space (including the rc calibration values locations) has been erased (after the read out protection removal), then the rc calibration values can still be obtained through these addresses. 0000h ram flash memory (8k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 2 ) 1000h 10ffh ffe0h ffffh (see table 5 ) 0200h reserved 01ffh short addressing ram (zero page) 128 bytes stack 0180h 01ffh 0080h 00ffh (384 bytes) e000h 1100h dfffh reserved ffdfh 16-bit addressing ram 0100h 017fh 1 kbyte 7 kbytes sector 1 sector 0 8k flash ffffh fc00h fbffh e000h program memory data eeprom (256 bytes) dee0h rccrh1 rccrl1 see section 7.1 on page 22 and note 1) dee1h dee2h rccrh0 rccrl0 dee3h dee4h 1 ST7LITE3 9/167 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register ffh 1) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register ffh 1) 00h 00h r/w r/w r/w 2) 0006h 0007h reserved area (2 bytes) 0008h 0009h 000ah 000bh 000ch lite timer 2 ltcsr2 ltarr ltcntr ltcsr1 lticr lite timer control/status register 2 lite timer auto-reload register lite timer counter register lite timer control/status register 1 lite timer input capture register 0fh 00h 00h 0x00 0000h xxh r/w r/w read only r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h auto- reload timer 3 atcsr cntr1h cntr1l atr1h atr1l pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l aticrh aticrl atcsr2 breakcr atr2h atr2l dtgr timer control/status register counter register 1 high counter register 1 low auto-reload register 1 high auto-reload register 1 low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low timer control/status register 2 break control register auto-reload register 2 high auto-reload register 2 low dead time generator register 0x00 0000h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only r/w r/w r/w r/w r/w 0026h to 002dh reserved area (8 bytes) 002eh wdg wdgcr watchdog control register 7fh r/w 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w 1 ST7LITE3 10/167 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura - tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 3. for a description of the dm registers, see the st7 icc reference manual. 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d control and data register low 00h xxh x0h r/w read only r/w 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity cont rol/status register ffh 0000 0xx0h r/w r/w 003bh reserved area (1 byte) 003ch itc eisr external interrupt selection register 00h r/w 003dh to 003fh reserved area (3 bytes) 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h linsci (lin mas - ter/slave) scisr scidr scibrr scicr1 scicr2 scicr3 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci control register 3 sci extended receive prescaler register sci extended transmit prescaler register c0h xxh 00xx xxxxb xxh 00h 00h 00h 00h read only r/w r/w r/w r/w r/w r/w r/w 0048h reserved area (1 byte) 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm 3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) address block register label register name reset status remarks 1 ST7LITE3 11/167 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program - ming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be pro - grammed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be programmed or erased without removing the device from the application board. ? in-application programming. in this mode, sector 1 and data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu - nication) which allows an st7 plugged on a print - ed circuit board (pcb) to communicate with an ex - ternal programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in-circuit communi - cations). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory contain - ing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. ? download icp driver code in ram from the iccdata pin ? execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controll ed by user software. this allows it to be adapted to the user application, (us - er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory ar - eas except sector 0, which is write/erase protect - ed to allow recovery in case errors occur during the programming operation. 1 ST7LITE3 12/167 flash program memory (cont?d) 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input serial data pin ? pb4/osc1: main clock input for external source (not required on devices without osc1/osc2 pins) ?v dd : application board power supply (option - al, see note 3) notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another de - vice forces the signal. refer to the programming tool documentation for recommended resistor val - ues. 2. during the icp session, the programming tool must control the reset pin. this can lead to con - flicts between the programming tool and the appli - cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli - cation reset circuit in this case. when using a classical rc network with r>1k or a reset man - agement ic with open drain output and pull-up re - sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program - ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the pb4 pin of the st7 when the clock is not available in the applica - tion or if the selected clock option is not pro - grammed in the option byte. st7 devices with mul - ti-oscillator capability ne ed to have osc2 ground - ed in this case. caution: during normal operation iccclk pin must be pulled- up, internally or externally (exter - nal pull-up of 10k mandatory in noisy environ - ment). this is to avoid entering icc mode unex - pectedly during a reset. in the application, even if the pin is configured as ou tput, any reset will put it back in input pull-up. figure 4. typical icc interface icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 c l2 c l1 clkin osc2 optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4) note with the icp option disabled with st7 mdt10-epb that the external clock has to be provided on pb4 (osc1/pb4) 1 ST7LITE3 13/167 flash program memory (cont?d) 4.5 memory protection there are two different types of memory protec - tion: read out protection and write/erase protec - tion which can be applied individually. 4.5.1 read out protection readout protection, when selected provides a pro - tection against program memory content extrac - tion and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. both program and data e 2 memory are protected. in flash devices, this protection is removed by re - programming the option. in this case, both pro - gram and data e 2 memory are automatically erased and the device can be reprogrammed. ? read-out protection selection is enabled and re - moved through the fmp_r bit in the option byte. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impos - sible to both overwrite and erase program memo - ry. it does not apply to e 2 data. its purpose is to provide advanced security to applications and pre - vent any change being made to the memory con - tent. warning : once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc proto - col, refer to the st7 flash programming refer - ence manual and to the st7 icc protocol refer - ence manual . 4.7 register description flash control/status register (fcsr) read / write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing op - erations. when an epb or another programming tool is used (in socket or icp mode), the rass keys are sent automatically. 7 0 0 0 0 0 0 opt lat pgm 1 ST7LITE3 14/167 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. usin g the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltage (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 5. eeprom block diagram eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus 1 ST7LITE3 15/167 data eeprom (cont?d) 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eep - rom control/status register (eecsr). the flow - chart in figure 6 describes these different memory access modes. read operation (e2lat=0) the eeprom can be read as a normal rom loca - tion when the e2lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that read ing data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe - cute machine code. write operation (e2lat=1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 32 data latches ac - cording to its address. when pgm bit is set by the software, all the previ - ous bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is dete rmined by the last eep - rom write sequence. to avoid wrong program - ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note : care should be taken during the program - ming cycle. writing to the same memory location will over-program the memory (logical and be - tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 8 . figure 6. data eeprom programming flowchart read mode e2lat=0 e2pgm=0 write mode e2lat=1 e2pgm=0 read bytes in eeprom area write up to 32 bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2lat 01 cleared by hardware 1 ST7LITE3 16/167 data eeprom (cont?d) figure 7. data e 2 prom write operation note: if a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem - ory is not guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition 1 ST7LITE3 17/167 data eeprom (cont?d) 5.4 power saving modes wait mode the data eeprom can enter wait mode on ex - ecution of the wfi instruction of the microcontrol - ler or when the microcontroller enters active-halt mode.the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. active-halt mode refer to wait mode. halt mode the data eeprom immediately enters halt mode if the microcontroller executes the halt in - struction. ther efore the eeprom will stop the function in progress, and data may be corrupted. 5.5 access error handling if a read access occurs while e2lat=1, then the data bus will not be driven. if a write access occurs while e2lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memo ry data will not be guar - anteed. 5.6 data eeprom read-out protection the read-out protection is enabled through an op - tion bit (see section 15.1 on page 158 ). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out (including a re-write protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire pro - gram memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 8. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 1 ST7LITE3 18/167 data eeprom (cont?d) 5.7 register description eeprom control/status register (eec - sr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hard - ware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note : if the e2pgm bit is cleared during the pro - gramming cycle, the memory data is not guaran - teed table 3. data eeprom register map and reset values 7 0 0 0 0 0 0 0 e2lat e2pgm address (hex.) register label 7 6 5 4 3 2 1 0 0030h eecsr reset value 0 0 0 0 0 0 e2lat 0 e2pgm 0 1 ST7LITE3 19/167 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the 6 cpu registers shown in figure 9 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg - ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in - struction (pre) to indicate that the following in - struction refers to the y register.) the y register is not affected by the interrupt auto - matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 9. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1 ST7LITE3 20/167 cpu registers (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in - terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in - structions. these bits can be individually tested and/or con - trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be - tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc - tion. the h bit is useful in bcd arithmetic subrou - tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter - rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in - structions and is tested by the jrm and jrnm in - structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur - rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre - sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc - tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in - dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft - ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 7 0 1 1 1 h i n z c 1 ST7LITE3 21/167 cpu registers (cont?d) stack pointer (sp) read/write reset value: 01ffh the stack pointer is a 16-bit register which is al - ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10 ). since the stack is 128 bytes deep, the 9 most sig - nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc - tion (rsp), the stack pointer contains its reset val - ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in - struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with - out indicating the stack overflow. the previously stored information is then overwritten and there - fore lost. the stack also wraps in case of an under - flow. the stack is used to save the return address dur - ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc - tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10 . ? when an interrupt is received, the sp is decre - mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in - terrupt five location s in the stack area. figure 10. stack manipulation example 15 8 0 0 0 0 0 0 0 1 7 0 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h stack higher address = 01ffh stack lower address = 0180h 1 ST7LITE3 22/167 7 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re - ducing the number of external components. main features clock management ? 1 mhz internal rc oscillator (enabled by op - tion byte) ? 1 to 16 mhz or 32khz external crystal/ceramic resonator (selected by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8 or 4 (enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detect or (avd) with interrupt capability for monitoring the main supply (en - abled by option byte) 7.1 internal rc oscillator adjustment the device contains an internal rc oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5v-5.5v). it must be calibrat - ed to obtain the frequency required in the applica - tion. this is done by software writing a 8-bit cali - bration value in the rc cr (rc control register) and in the bits [6:5] in the sicsr (si control sta - tus register). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be load - ed in the rccr. predefined calibration values are stored in eeprom for 3v and 5v v dd supply volt - ages at 25c, as shown in the following table. 1. dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flas h space (including the rc calibration values locations) has been erased (after the read out protection removal), then the rc calibration values can still be obtained through these four addresses. for compatibility reasons with the sicsr register, cr[1:0] bits are stored in the 5th and 6th position of dee1 and dee3 addresses. note: ? see ?electrical characteristics? on page 129. for more information on the frequency and accuracy of the rc oscillator. ? to improve clock stability, it is recommended to place a decoupling capacitor between the v dd and v ss pins. ? these bytes are systematically programmed by st, including on fastrom devices. conse - quently, customers intending to use fastrom service must not use these bytes. ? rccr0 and rccr1 calibration values will not be erased if the read-out protection bit is reset af - ter it has been set . see ?read out protection? on page 13. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an ex - ternal reference signal. 7.2 phase locked loop the pll can be used to multiply a 1mhz frequen - cy from the rc oscillator or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is ena - bled and the multiplication factor of 4 or 8 is select - ed by 2 option bits. ? the x4 pll is intended for operation with v dd in the 2.7v to 3.3v range ? the x8 pll is intended for operation with v dd in the 3.3v to 5.5v range refer to section 15.1 for the option byte descrip - tion. if the pll is disabled and the rc oscillator is ena - bled, then f osc = 1mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. rccr conditions ST7LITE3 addresses rccrh0 v dd =5v t a =25c f rc =1mhz dee0h 1) (cr[9:2] bits) rccrl0 dee1h 1) (cr[1:0] bits) rccrh1 v dd =3.3v t a =25c f rc =1mhz dee2h 1) (cr[9:2] bits) rccrl1 dee3h 1) (cr[1:0] bits) 1 ST7LITE3 23/167 phase locked loop (cont?d) figure 11. pll output frequency timing diagram when the pll is started, after reset or wakeup from halt mode or awufh mode, it outputs the clock after a delay of t startup . when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilization time of t stab (see figure 11 and 13.3.4internal rc os cillator and pll ) refer to section 7.6.4 on page 32 for a description of the locked bit in the sicsr register. 7.3 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, mu st be kept cleared. bit 1 = mco main clock out enable this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc 1: slow mode (f cpu = f osc /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency ad - justment bits these bits must be written immediately after reset to adjust the rc oscillato r frequency an d to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency these bits are used with the cr[1:0] bits in the sicsr register. refer to section 7.6.4 on page 32 note: to tune the oscillator, write a series of differ - ent values in the register until the correct frequen - cy is reached. the fastest method is to use a di - chotomy starting with 80h. 4/8 x freq. locked bit set t stab t lock input output freq. t startup t 7 0 0 0 0 0 0 0 mco sms 7 0 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 1 ST7LITE3 24/167 figure 12. clock management block diagram mccsr sms mco mco f cpu peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc f ltimer lite timer 2 counter 8-bit f cpu to cpu and 1 0 cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 rccr f osc osc1 osc2 osc 1-16 mhz clkin or 32khz /2 divider tunable 1mhz oscillator 1% rc osc option bit pll 1mhz -> 8mhz pll 1mhz -> 4mhz 8mhz 4mhz option bits osc,plloff, oscrange[2:0] /2 divider pllx4x8 /32 divider clkin/2 (ext clock) crystal osc /2 pll rc osc clock cr1 cr0 sicsr option bits oscrange[2:0] clkin clkin clkin/ 1 ST7LITE3 25/167 7.4 multi-osc illator (mo) the main clock of the st7 can be generated by four different source types coming from the multi- oscillator block (1 to 16mhz or 32khz): an external source 5 crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 4 . refer to the electrical characteristics section for more details. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. note: when the multi- oscillator is not used, pb4 is selected by default as external clock. crystal/ceramic oscillators this family of oscillators has the advan tage of pro - ducing a very accurate rate on the main clock of the st7. the selection with in a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 158 for more details on the frequency ranges). in this mode of the multi-oscil - lator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization ti me. the loading capaci - tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator in this mode, the tunable 1%rc oscillator is used as main clock source. the two oscillator pins have to be tied to ground. the calibration is done through the rccr[7:0] and sicsr[6:5] registers. table 4. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 1 ST7LITE3 26/167 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three re - set sources as shown in figure 14 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is al - ways kept low during the delay phase. the reset service routine vector is fixed at ad - dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 13 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (see table below) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically select - ed depending on the clock source chosen by op - tion byte: the reset vector fetch phase duration is 2 clock cycles. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 11 ). figure 13. reset sequence phases 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac - cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 15 ). this de - tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 14. reset block diagram clock source cpu clock cycle delay internal rc oscillator 256 external clock (connected to clkin pin) 256 external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter 1 ST7LITE3 27/167 reset sequence manager (cont?d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris - tics section. 7.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net - work connected to the reset pin. 7.5.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in - ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd ST7LITE3 29/167 figure 17. reset and supply management block diagram low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avdie avdf status flag 0 0 lvdrf locked wdgrf 0 1 ST7LITE3 30/167 system integrity management (cont?d) 7.6.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup - ply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) refer - ence value for rising voltage in order to avoid par - asitic detection (hysteresis). the output of the avd comparator is directly read - able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd functions only if the lvd is en - abled through the option byte. 7.6.2.1 monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 15.1 on page 158 ). if the avd interrupt is enabled, an interrupt is gen - erated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon - troller. see figure 18 . figure 18. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset 1 ST7LITE3 31/167 system integrity management (cont?d) 7.6.3 low power modes 7.6.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re - set (rim instruction). mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. the avd becomes inactive and the avd in - terrupt cannot be used to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no 1 ST7LITE3 32/167 system integrity management (cont?d) 7.6.4 register description system integrity (si) control/status register (sicsr) read / write reset value: 0000 0xx0 (0xh) bit 7 = reserved, must be kept cleared. bits 6:5 = cr[1:0] rc oscillator frequency ad - justment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator fre quency and to obtain an accuracy of 1%. refer to section 7.3 on page 23 bit 4 = wdgrf watchdog reset flag this bit indicates that the last reset was generat - ed by the watchdog peripheral. it is set by hard - ware (watchdog reset) and cleared by software (by reading sicsr register) or an lvd reset (to en - sure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. bit 3 = locked pll locked flag this bit is set and cleared by hardware. it is set au - tomatically when the pll reaches its operating fre - quency. 0: pll not locked 1: pll locked bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generat - ed by the lvd block. it is set by hardware (lvd re - set) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen - erated when the avdf bit is set. refer to figure 18 and to section 7.6.2.1 for additional details. 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automati - cally cleared when software enters the avd inter - rupt routine. 0: avd interrupt disabled 1: avd interrupt enabled application notes the lvdrf flag is not cleared when another re - set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi - nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 7 0 0 cr1 cr0 wdg rf locked lvdrf avdf avdie reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x 1 ST7LITE3 33/167 8 interrupts the st7 core may be interrupted by one of two dif - ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? the i bit of the cc register is set to prevent addi - tional interrupts. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address - es). the interrupt service routine should finish with the iret instruction which caus es the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared an d the main program will resume. priority management by default, a servicing interrupt cannot be inter - rupted because the i bit is set by hardware enter - ing in interrupt routine. in the case when several interrupts are simultane - ously pending, an hardware priority defines which one will be serviced first (see the interrupt map - ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi - cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in the interrupt mapping ta - ble). 8.1 non maskable software interrupt this interrupt is entered when the trap instruc - tion is executed regardless of the state of the i bit. it will be serviced accord ing to the flowchart on figure 19 . 8.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to le ave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the mis - cellaneous or interrupt register (if available) ap - plies to the ei source. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ? the i bit of the cc register is cleared. ? the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: ? writing ?0? to the corresponding bit in the status register or ? access to the status register while the flag is set followed by a read or write of an associated reg - ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en - abled) will therefore be lost if the clear sequence is executed. 1 ST7LITE3 34/167 interrupts (cont?d) figure 19. interrupt processing flowchart table 5. interrupt mapping note 1 : this interrupt exits the mcu from ?auto wake-up from halt? mode only. note 2 : these interrupts exit the mcu from ?active-halt? mode only. n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu 7 interrupt awucsr yes 1) fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 lite timer lite timer rtc2 interrupt ltcsr2 no fff0h-fff1h 6 linsci linsci interrupt scicr1/ scicr2 no ffeeh-ffefh 7 si avd interrupt sicsr no ffech-ffedh 8 at timer at timer output compare interrupt or input capture interrupt pwmxcsr or atcsr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes 2) ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes 2) ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes ffe2h-ffe3h 13 at timer at timer overflow interrupt 2 atcsr2 no ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? 1 ST7LITE3 35/167 interrupts (cont?d) external interrupt control register (eicr) read / write reset value: 0000 0000 (00h) bit 7:6 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to table 6 . bit 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to table 6 . bit 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to table 6 . bit 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to table 6 . note: these 8 bits can be written only when the i bit in the cc register is set. table 6. interrupt sensitivity bits . external interrupt selection regis - ter (eisr) read / write reset value: 0000 0000 (00h) bit 7:6 = ei3[1:0] ei3 pin selection these bits are written by software. they select the port b i/o pin used for the ei3 external interrupt ac - cording to the table below. external interrupt i/o pin selection * reset state bit 5:4 = ei2[1:0] ei2 pin selection these bits are written by software. they select the port b i/o pin used for the ei2 external interrupt ac - cording to the table below. external interrupt i/o pin selection * reset state 7 0 is31 is30 is21 is20 is11 is10 is01 is00 isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 7 0 ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00 ei31 ei30 i/o pin 0 0 no interrupt * 0 1 pb0 1 0 pb1 1 1 pb2 ei21 ei20 i/o pin 0 0 no interrupt * 0 1 pb3 1 0 pb5 1 1 pb6 1 ST7LITE3 36/167 interrupts (cont?d) bit 3:2 = ei1[1:0] ei1 pin selection these bits are written by software. they select the port a i/o pin used for the ei1 external interrupt ac - cording to the table below. external interrupt i/o pin selection * reset state bit 1:0 = ei0[1:0] ei0 pin selection these bits are written by software. they select the port a i/o pin used for the ei0 external interrupt ac - cording to the table below. external interrupt i/o pin selection * reset state bits 1:0 = reserved. ei11 ei10 i/o pin 0 0 no interrupt* 0 1 pa4 1 0 pa5 1 1 pa6 ei01 ei00 i/o pin 0 0 no interrupt* 0 1 pa1 1 0 pa2 1 1 pa3 1 ST7LITE3 37/167 9 power saving modes 9.1 introduction to give a large measure of flexibility to the applica - tion in terms of power consumption, five main pow - er saving modes are implemented in the st7 (see figure 20 ): slow wait (and slow-wait) active halt auto wake up from halt (awufh) halt after a reset the normal operating mode is se - lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency di vided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. figure 20. power saving mode transitions 9.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillato r frequency is divided by 32. the cpu and peripherals are clocked at this - lower frequency. note : slow-wait mode is activated when enter - ing wait mode while the device is already in slow mode. figure 21. slow mode clock transition power consumption wait slow run active halt high low slow wait auto wake up from halt halt sms f cpu normal run mode request f osc f osc /32 f osc 1 ST7LITE3 38/167 power saving modes (cont?d) 9.3 wait mode wait mode places the mcu in a low power con - sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the pro - gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22 . figure 22. wait mode flow-chart note: 1. before servicing an interr upt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on 256 or 4096 cpu clock cycle delay 1 ST7LITE3 39/167 power saving modes (cont?d) 9.4 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the ?halt? instruction when active-halt is disabled (see section 9.5 on page 40 for more details) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on reception of ei - ther a specific interrupt (see table 5, ?interrupt mapping,? on page 34 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediat ely turned on and the 256 cpu cycle delay is used to stabilize the oscillator. after the start up delay, the cpu resumes opera - tion by servicing the interrupt or by fetching the re - set vector which woke it up (see figure 24 ). when entering halt mode, the i bit in the cc reg - ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up im - mediately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in - cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla - tor). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op - tion bit of the option byte. the halt instruction when executed while the watchdog system is en - abled, can generate a watchdog reset (see sec - tion 15.1 on page 158 for more details). figure 23. halt timing overview figure 24. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec - tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific inte rrupts can exit the mcu from halt mode (such as external interrupt). re - fer to table 5, ?interrupt mapping,? on page 34 for more details. 4. before servicing an interr upt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [active halt disabled] reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle halt instruction (active halt disabled) (awucsr.awuen=0) 1 ST7LITE3 40/167 power saving modes (cont?d) 9.4.0.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? or ?floating inter - rupt? before executing the halt instruction. the main reason for this is that the i/o may be wrong - ly configured due to external interference or by an unforeseen logical condition. ? for the same reason, reinitialize the level sensi - tiveness of each external interrupt as a precau - tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo - ry. for example, avoid defining a constant in pro - gram memory with the value 0x8e. ? as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be - fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre - sponding to the wake-up event (reset or external interrupt). 9.5 active-halt mode active-halt mode is the lowest power con - sumption mode of the mcu with a real time clock (rtc) available. it is entered by executing the ?halt? instruction. the decision to enter either in active-halt or halt mode is given by the ltc - sr/atcsr register status as shown in the follow - ing table:. the mcu can exit active-halt mode on recep - tion of a specific interrupt (see table 5, ?interrupt mapping,? on page 34 ) or a reset. ? when exiting active-halt mode by means of a reset, a 256 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 26 ). ? when exiting active-halt mode by means of an interrupt, the cpu immediately resumes oper - ation by servicing the inte rrupt vector which woke it up (see figure 26 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately (see note 3). in active-halt mode, on ly the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex - ternal or auxiliary oscillator). note: as soon as active-halt is enabled, exe - cuting a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. ltcsr1 tb1ie bit atcsr ovfie1 bit atcsr ck1 bit atcsr ck0 bit meaning 0 x x 0 active-halt mode disabled 0 0 x x 1 x x x active-halt mode enabled x 1 0 1 1 ST7LITE3 41/167 power saving modes (cont?d) figure 25. active-halt timing overview figure 26. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the rtc1 interrupt and some specific inter - rupts can exit the mcu from active-halt mode. refer to table 5, ?interrupt mapping,? on page 34 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 9.6 auto wake up from halt mode auto wake up from halt (awufh) mode is simi - lar to halt mode with the additional of an internal rc oscillator for wake-up. compared to active- halt mode, awufh has lower power consump - tion (the main clock is not kept running), but there is no accurate realtime clock available. it is entered by executing the halt instruction when the awuen bit in the awucsr register has been set. figure 27. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divid - er and a programmable prescaler controlled by the awupr register. the output of this prescaler pro - vides the delay time. when the delay has elapsed the awuf flag is set by hardware and an interrupt wakes-up the mcu from halt mode. at the same time the main oscillator is immediately turned on and a 256 cycle delay is used to stabilize it. after this start-up delay, the cpu resumes operation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 12-bit auto-re - lad timer, allowing the f awu_rc to be measured using the main oscillator clock as a reference time - base. halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu delay (active halt enabled) (awucsr.awuen=0) clock cycle awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to 1 0 awuck opt bit input capture 32-khz oscillator timer auto-reload 1 ST7LITE3 42/167 power saving modes (cont?d) similarities with halt mode the following awufh mode behaviour is the same as normal halt mode: ? the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a re - set (see section 9.4 halt mode ). ? when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. there - fore, if an interrupt is pending, the mcu wakes up immediately. ? in awufh mode, the main oscillator is turned off causing all internal processing to be stopped, in - cluding the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an exte rnal or auxiliary oscil - lator like the awu oscillator). ? the compatibility of watchdog operation with awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can gen - erate a watchdog reset. figure 28. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu 1 ST7LITE3 43/167 power saving modes (cont?d) figure 29. awufh mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec - tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrup t and some specific in - terrupts can exit the mcu from halt mode (such as external interrupt). refer to table 5, ?interrupt mapping,? on page 34 for more details. 4. before servicing an interr upt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg - ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1) 1 ST7LITE3 44/167 power saving modes (cont?d) 9.6.0.1 register description awufh control/status register (awucsr) read / write reset value: 0000 0000 (00h) bits 7:3 = reserved. bit 1= awuf auto wake up flag this bit is set by hardw are when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 2= awum auto wake up measurement this bit enables the aw u rc oscillator and con - nects its output to the input capture of the 12-bit auto-reload timer. this allo ws the timer to be used to measure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupr register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake up fr om halt enabled this bit enables the auto wake up from halt fea - ture: once halt mode is entered, the awufh wakes up the microcontroller after a time delay de - pendent on the awu prescaler value. it is set and cleared by software. 0: awufh (auto wake up from halt) mode disa - bled 1: awufh (auto wake up from halt) mode ena - bled awufh prescaler register (awupr) read / write reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto wake up prescaler these 8 bits define the awupr dividing factor (as explained below in awu mode, the period that the mcu stays in halt mode (t awu in figure 28 on page 42 ) is de - fined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on the product, an interrupt is generated immediately after a halt instruction, or the awupr remains unchanged. table 7. awu register map and reset values 7 0 0 0 0 0 0 awuf awum awuen 7 0 awu pr7 awu pr6 awu pr5 awu pr4 awu pr3 awu pr2 awu pr1 awu pr0 awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + = address (hex.) register label 7 6 5 4 3 2 1 0 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 0 0 0 0 0 awuf awum awuen 1 ST7LITE3 45/167 10 i/o ports 10.1 introduction the i/o ports allow data transfer. an i/o port can contain up to 8 pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include exter - nal interrupt, alternate signal input/output for on- chip peripherals or analog input. 10.2 functional description a data register (dr) and a data direction regis - ter (ddr) are always associated with each port. the option register (or) , which allows input/out - put options, may or may not be implemented. the following description take s into account the or register. refer to the port configuration table for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corre - sponding to pin x of the port. figure 30 shows the generic i/o block diagram. 10.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull-up. re - fer to i/o port implementation section for configu - ration. notes : 1. writing to the dr modifies the latch value but does not change the state of the input pin. 2. do not use read/mod ify/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or lev - el input on the i/o generates an interrupt request via the corresponding interrupt vector (eix). falling or rising edge se nsitivity is programmed in - dependently for each interrupt vector. the exter - nal interrupt control register (eicr) or the miscel - laneous register controls this sensitivity, depend - ing on the device. external interrupts are hardware interrupts. fetch - ing the corresponding interrupt vector automatical - ly clears the request latch. modifying the sensitivity bits will clear any pending interrupts. 10.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open- drain. refer to i/o port implementation section for configuration. dr value and output pin status 10.2.3 alternate functions many st7s i/os have one or more alternate func - tions. these may include output signals from, or input signals to, on-chip peripherals. the device pin description table describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripher - al?s control register). the peripheral configures the i/o as an output and takes priority over standard i/ o programming. the i/o?s state is readable by ad - dressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this will increase current con - sumption. before using an i/o as an alternate in - put, configure it without interrupt. otherwise spuri - ous interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution : i/os which can be configured as both an analog and digital alternate function need special atten - tion. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. dr push-pull open-drain 0 v ol v ol 1 v oh floating 1 ST7LITE3 46/167 i/o ports (cont?d) figure 30. i/o port general block diagram table 8. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note 1: the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ol is implemented to protect the de - vice against positive stress. note 2: for further details on port configuration, please refer to table 10 and table 11 on page 49 . configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note 1) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral note : refer to the port configuration table for device specific information. combinational logic 1 ST7LITE3 47/167 i/o ports (cont?d) table 9. i/o configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate functi on output status. 2. when the i/o port is in output configuration and th e associated alternate function is enabled as an input, the alternate function reads the pin stat us given by the dr register content. 3. for true open drain, these elements are not implemented. hardware configuration input 1) open-drain output 2) push-pull output 2) note 3 condition pad v dd r pu external interrupt polarity data b u s pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input to on-chip peripheral combinational logic note 3 pad r pu data bus dr dr register access r/w v dd register pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register bit from on-chip periphera l note 3 1 ST7LITE3 48/167 i/o ports (cont?d) analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi - mum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port de - pends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to anoth - er should be done in a sequence that prevents un - wanted side effects. recommended safe transi - tions are illustrated in figure 31 . other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed volt - age levels. refer to section 13.8 . 10.5 low power modes 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). related documentation an 970: spi communication between st7 and eeprom an1045: s/w implementation of i2c bus master an1048: software lcd driver 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 1 ST7LITE3 49/167 i/o ports (cont?d) the i/o port register configurations are summa - rised as follows. standard ports pa7:0, pb6:0 interrupt ports ports where the external interrupt capability is selected using the eisr register table 10. port configuration (standard ports) note: on ports where the external inte rrupt capability is sele cted using the eisr r egister, the configura - tion will be as follows: table 11. port configuration (external interrupts) table 12. i/o port register map and reset values mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 port pin name input (ddr=0) output (ddr=1) or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up open drain push-pull port b pb6:0 floating pull-up open drain push-pull port pin name input with interrupt (ddr=0 ; eisr 00) or = 0 or = 1 port a pa6:1 floating pull-up port b pb5:0 floating pull-up address (hex.) register label 7 6 5 4 3 2 1 0 0000h padr reset value msb 1 1 1 1 1 1 1 lsb 1 0001h paddr reset value msb 0 0 0 0 0 0 0 lsb 0 0002h paor reset value msb 0 1 0 0 0 0 0 lsb 0 0003h pbdr reset value msb 1 1 1 1 1 1 1 lsb 1 0004h pbddr reset value msb 0 0 0 0 0 0 0 lsb 0 0005h pbor reset value msb 0 0 0 0 0 0 0 lsb 0 1 ST7LITE3 50/167 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur - rence of a software fault, usually generated by ex - ternal interference or by unforeseen logical condi - tions, which causes the application program to abandon its normal sequence. the watchdog cir - cuit generates an mcu reset on expiry of a pro - grammed time period, unless the program refresh - es the counter?s contents before the t6 bit be - comes cleared. 11.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 16000 machine cy - cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 30s. figure 32. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 16000 t1 t2 t3 t4 t5 1 ST7LITE3 51/167 watchdog timer (cont?d) the application program must write in the cr reg - ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 13 .watchdog timing ): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme - diate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re - set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. table 13.watchdog timing notes: the timing variation shown in table 13 is due to the unknown status of the prescaler when writing to the cr register. 11.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 15.1 on page 158 . 11.1.4.1 using halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruc - tion to refresh the wdg counter, to avoid an unex - pected wdg reset immediately after waking up the microcontroller. f cpu = 8mhz wdg counter code min [ms] max [ms] c0h 1 2 ffh 127 128 1 ST7LITE3 52/167 watchdog timer (cont?d) 11.1.5 interrupts none. 11.1.6 register description control register (cr) read / write reset value: 0111 1111 (7f h) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch - dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 7 0 wdga t6 t5 t4 t3 t2 t1 t0 1 ST7LITE3 53/167 watchdog timer (cont?d) table 14. watchdog timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 002eh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 1 ST7LITE3 54/167 11.2 dual 12-bit autoreload timer 3 (at3) 11.2.1 introduction the 12-bit autoreload timer can be used for gen - eral-purpose timing function s. it is based on one or two free-running 12-bit upcounters with an input capture register and four pwm output channels. there are 6 external pins: ? four pwm outputs ? atic/ltic pin for the input capture function ? break pin for forcing a break condition on the pwm outputs 11.2.2 main features single timer or dual timer mode with two 12-bit upcounters (cntr1/cntr2) and two 12-bit autoreload registers (atr1/atr2) maskable overflow interrupts pwm mode ? generation of four independent pwmx signals ? dead time generation for half bridge driving mode with programmable dead time ? frequency 2khz-4mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes output compare mode input capture mode ? 12-bit input capture register (aticr) ? triggered by rising and falling edges ? maskable ic interrupt ? long range input capture break control flexible clock control figure 33. single timer mode (encntr2=0) atic pwm0 pwm1 pwm2 pwm3 pwm3 duty cycle generator 12-bit input capture pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 clock control 1ms f cpu edge detection circuit output compare cmp interrupt from lite timer ovf1 interrupt oe0 oe1 oe2 oe3 dead time generator dte bit bpen bit break function 1 ST7LITE3 55/167 dual 12-bit autoreload timer 3 (cont?d) figure 34. dual timer mode (encntr2=1) pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture 12-bit autoreload register 2 12-bit upcounter 2 pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 clock control 1ms f cpu output compare cmp interrupt ovf1 interrupt ovf2 interrupt edge detection circuit oe0 oe1 oe2 oe3 atic dte bit bpen bit break function 1 ST7LITE3 56/167 dual 12-bit autoreload timer 3 (cont?d) 11.2.3 functional description 11.2.3.1 pwm mode this mode allows up to four pulse width modulat - ed signals to be generated on the pwmx output pins. pwm frequency the four pwm signals can have the same fre - quency (f pwm ) or can have two different frequen - cies. this is selected by the encntr2 bit which enables single timer or dual timer mode (see fig - ure 33 and figure 34 ). the frequency is controlled by the counter period and the atr register value. in dual timer mode, pwm2 and pwm3 can be generated with a differ - ent frequency controlled by cntr2 and atr2. f pwm = f counter / (4096 - atr) following the above formula, ? if f counter is 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094),the mini - mum value is 1 khz (atr register value = 0). duty cycle the duty cycle is selected by programming the dcrx registers. these are preload registers. the dcrx values are transferre d in active duty cycle registers after an overflow event if the correspond - ing transfer bit (tranx bit) is set. the tran1 bit controls the pwmx outputs driven by counter 1 and the tran2 bit controls the pwmx outputs driven by counter 2. pwm generation and output compare are done by comparing these active dcrx values with the counter. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (4096 - atr) where atr is equal to 0. with this maximum reso - lution, 0% and 100% duty cycle can be obtained by changing the polarity. at reset, the counter starts counting from 0. when a upcounter overflow occurs (ovf event), the preloaded duty cycle values are transferred to the active duty cycle registers and the pwmx sig - nals are set to a high level. when the upcounter matches the active dcrx value the pwmx signals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding ac - tive dcrx register must be greater than the con - tents of the atr register. the maximum value of atr is 4094 because it must be lower than the dcr value which must be 4095 in this case. polarity inversion the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the corresponding transfer bit in the atcsr2 register is set (reset value). see figure 35 . figure 35. pwm polarity inversion the data flip flop (dff) applies the polarity inver - sion when triggered by the counter overflow input. output control the pwmx output signals can be enabled or disa - bled using the oex bits in the pwmcr register. pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tranx atcsr2 register 1 ST7LITE3 57/167 dual 12-bit autoreload timer 3 (cont?d) figure 36. pwm function figure 37. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter counter pwmx output t with mod00=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with mod00=1 and opx=1 1 ST7LITE3 58/167 dual 12-bit autoreload timer 3 (cont?d) dead time generation a dead time can be inserted between pwm0 and pwm1 using the dtgr regi ster. this is required for half-bridge driving where pwm signals must not be overlapped. the non-overlapping pwm0/ pwm1 signals are generated through a program - mable dead time by setting the dte bit. dead time value = dt[6:0] x tcounter1 dtgr[7:0] is buffered in side so as to avoid de - forming the current pwm c ycle. the dtgr effect will take place only after an overflow. notes: 1. dead time is generated only when dte=1 and dt[6:0] 0 . if dte is set and dt[6:0]=0, pwm out - put signals will be at their reset state. 2. half bridge driving is poss ible only if polarities of pwm0 and pwm1 are not inverted, i.e. if op0 and op1 are not set. if polarity is inverted, overlapping pwm0/pwm1 signals will be generated. figure 38. dead time generation in the above example, when the dte bit is set: ? pwm goes low at dcr0 ma tch and goes high at atr1+tdt ? pwm1 goes high at dcr0+tdt and goes low at atr match. with this programmable delay (tdt), the pwm0 and pwm1 signals which are generated are not overlapped. dcr0+1 atr1 dcr0 t dt t dt t dt = dt[6:0] x t counter1 pwm 0 pwm 1 cntr1 ck_cntr1 t counter1 ovf pwm 0 pwm 1 if dte = 0 if dte = 1 counter = dcr0 counter = dcr1 1 ST7LITE3 59/167 dual 12-bit autoreload timer 3 (cont?d) break function the break function can be used to perform an emergency shutdown of the application being driv - en by the pwm signals. the break function is activated by the external break pin (active low). in order to use the break pin it must be prev iously enabled by soft - ware setting the bpen bit in the breakcr regis - ter. when a low level is detected on the break pin, the ba bit is set and the break function is activat - ed. in this case, the 4 pwm signals are stopped. software can set the ba bit to activate the break function without using the break pin. when the break function is activated (ba bit =1): ? the break pattern (pwm[3:0] bits in the break - cr) is forced directly on the pwmx output pins (after the inverter). ? the 12-bit pwm counter cntr1 is put to its re - set value, i.e. 00h. ? the 12-bit pwm counter cntr2 is put to its re - set value,i.e. 00h. ? atr1, atr2, preload and active dcrx are put to their reset values. ? the pwmcr register is reset. ? counters stop counting. when the break function is deactivated after ap - plying the break (ba bit goes from 1 to 0 by soft - ware): ? the control of the 4 pwm outputs is transferred to the port registers. figure 39. block diagram of break function pwm0 pwm1 pwm2 pwm3 1 0 pwm0 pwm1 pwm2 pwm3 breakcr register break pin pwm counter -> reset value atrx & dcrx -> reset value pwm mode -> reset value when ba is set: (active low) (inverters) note : the break pin value is latched by the ba bit. pwm0 pwm1 pwm2 pwm3 bpen ba 1 ST7LITE3 60/167 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.2 output compare mode to use this function, load a 12-bit value in the preload dcrxh and dcrxl registers. when the 12-bit upcounter (cntr1) reaches the value stored in the active dcrxh and dcrxl reg - isters, the cmpfx bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. the output compare function is always performed on cntr1 in both single timer mode and dual timer mode, and never on cntr2. the difference is that in single timer mode the counter 1 can be compared with any of the four dcr registers, and in dual timer mode, counter 1 is compared with dcr0 or dcr1. notes: 1. the output compare function is only available for dcrx values other than 0 (reset value). 2. duty cycle registers are buffered internally. the cpu writes in preload duty cycle registers and these values are transferred in active duty cycle registers after an overflow event if the corre - sponding transfer bit (tran1 bit) is set. output compare is done by comparing these active dcrx values with the counter. figure 40. block diagram of output compare mode (single timer) dcrx output compare circuit counter 1 (atcsr) cmpie preload duty cycle regx active duty cycle regx cntr1 tran1 (atcsr2) ovf (atcsr) cmpfx (pwmxcsr) cmp request interrupt 1 ST7LITE3 61/167 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.3 input capture mode the 12-bit aticr register is used to latch the val - ue of the 12-bit free running upcounter cntr1 af - ter a rising or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is gen - erated if the icie bit is set. the icf bit is reset by reading the aticrh/aticrl register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. any further input capture is inhibited while the icf bit is set. figure 41. block diagram of input capture mode figure 42. input capture timing diagram atcsr ck0 ck1 icie icf 12-bit autoreload register 12-bit upcounter1 f cpu atic 12-bit input capture register ic interrupt request atr1 aticr cntr1 (1 ms f ltimer @ 8mhz) timebase off counter1 t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag interrupt 08h 09h 0ah interrupt aticr read 09h 1 ST7LITE3 62/167 dual 12-bit autoreload timer 3 (cont?d) long input capture pulses that last between 8s and 2s can be meas - ured with an accuracy of 4s if f osc = 8mhz in the following conditions: ? the 12-bit at3 timer is clocked by the lite timer (rtc pulse: ck[1:0] = 01 in the atcsr register) ? the ics bit in the atcsr2 register is set so that the ltic pin is used to trigger the at3 timer cap - ture. ? the signal to be captured is connected to ltic pin ? input capture registers lticr, aticrh and aticrl are read this configuration allows to cascade the lite timer and the 12-bit at3 timer to get a 20-bit input cap - ture value. refer to figure 43 . figure 43. long range input capture block diagram notes: 1. since the input capture flags (icf) for both tim - ers (at3 timer and lt timer) are set when signal transition occurs, software must mask one inter - rupt by clearing the corresponding icie bit before setting the ics bit. 2. if the ics bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the input capture signal because of different values on ltic and atic. to avoid this situation, it is recommend - ed to do as follows: ? first, reset both icie bits. ? then set the ics bit. ? reset both icf bits. ? and then set the icie bit of desired interrupt. 3 . how to compute a pulse length with long input capture feature. as both timers are used, computing a pulse length is not straight-forward. the procedure is as fol - lows: ? at the first input capture on the rising edge of the pulse, we assume that values in the registers are as follows: lticr = lt1 aticrh = ath1 aticrl = atl1 hence aticr1 [11:0] = ath1 & atl1 refer to figure 44 on page 63 . lt i c at i c ics 1 0 12-bit input capture register off f cpu f lt i m e r 12-bit upcounter1 12-bit autoreload register 8-bit input capture register 8-bit timebase counter1 f osc/32 lticr cntr1 aticr atr1 8 lsb bits 12 msb bits lite timer 12-bit artimer 20 cascaded bits 1 ST7LITE3 63/167 dual 12-bit autoreload timer 3 (cont?d) ? at the second input capt ure on the falling edge of the pulse, we assume that the values in the reg - isters are as follows: lticr = lt2 aticrh = ath2 aticrl = atl2 hence aticr2 [11:0] = ath2 & atl2 now pulse width p between first capture and sec - ond capture will be: p = decimal (f9 ? lt1 + lt2 + 1) * 0.004ms + dec - imal (aticr2 - aticr1 ? 1) * 1ms figure 44. long range input capture timing diagram 11.2.4 low power modes f9h 00h lt1 f9h 00h lt2 ath1 & atl1 00h 0h lt1 ath1 lt2 ath2 f osc/32 tb counter1 cntr1 ltic lticr aticrh 00h atl1 atl2 aticrl aticr = aticrh[3:0] & aticrl[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ath2 & atl2 _ _ _ mode description slow the input frequency is divided by 32 wait no effect on at timer active- halt at timer halted except if ck0=1, ck1=0 and ovfie=1 halt at timer halted. 1 ST7LITE3 64/167 11.2.5 interrupts note 1: the cmp and at3 ic events are connect - ed to the same interrupt vector. the ovf event is mapped on a separate vector (see interrupts chapter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). note 2: only if ck0=1 and ck1=0 (f counter = f ltimer ) interrupt event 1) event flag enable control bit exit from wait exit from halt exit from active -halt overflow event ovf1 ovie1 yes no yes 2) at3 ic event icf icie yes no no cmp event cmpfx cmpie yes no no 1 ST7LITE3 65/167 dual 12-bit autoreload timer 3 (cont?d) 11.2.6 register description timer control status register (atcsr) read / write reset value: 0x00 0000 (x0h) bit 7 = reserved. bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the aticr register (a read access to aticrh or aticrl will clear this flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred bit 5 = icie ic interrupt enable. this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled bits 4:3 = ck[1:0] counter clock selection. these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf1 overflow flag. this bit is set by hardware and cleared by software by reading the tcsr register. it indicates the tran - sition of the counter1 cntr1 from ffh to atr1 value. 0: no counter overflow occurred 1: counter overflow occurred bit 1 = ovfie1 overflow interrupt enable. this bit is read/write by software and cleared by hardware after a reset. 0: overflow interrupt disabled. 1: overflow interrupt enabled. bit 0 = cmpie compare interrupt enable . this bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: output compare interrupt disabled. 1: output compare interrupt enabled. counter register 1 high (cntr1h) read only reset value: 0000 0000 (000h) counter register 1 low (cntr1l) read only reset value: 0000 0000 (000h) bits 15:12 = reserved. bits 11:0 = cntr1[11:0] counter value . this 12-bit register is read by software and cleared by hardware after a reset. the counter cntr1 is incremented continuously as soon as a counter clock is selected. to obtain the 12-bit cntr1 val - ue, software should read the counter value in two consecutive read operations, lsb first. when a counter overflow occurs, th e counter restarts from the value specified in the atr1 register. 7 6 0 0 icf icie ck1 ck0 ovf1 ovfie1 cmpie counter clock selection ck1 ck0 off 0 0 off 1 1 f ltimer (1 ms timebase @ 8 mhz) 0 1 f cpu 1 0 15 8 0 0 0 0 cntr1_ 11 cntr1_ 10 cntr1_ 9 cntr1_ 8 7 0 cntr1_ 7 cntr1_ 6 cntr1_ 5 cntr1_ 4 cntr1_ 3 cntr1_ 2 cntr1_ 1 cntr1_ 0 1 ST7LITE3 66/167 dual 12-bit autoreload timer 3 (cont?d) autoreload register (atr1h) read / write reset value: 0000 0000 (00h) autoreload register (atr1l) read / write reset value: 0000 0000 (00h) bits 11:0 = atr1[11:0] autoreload register 1. this is a 12-bit register which is written by soft - ware. the atr1 register value is automatically loaded into the upcounter cntr1 when an over - flow occurs. the register value is used to set the pwm frequency. pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:0 = oe[3:0] pwmx output enable . these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled (i/o pin free for general pur - pose i/o) 1: pwm mode enabled pwmx control status register (pwmxcsr) read / write reset value: 0000 0000 (00h) bits 7:2= reserved, must be kept cleared. bit 1 = opx pwmx output polarity. this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted. 1: the pwm signal is inverted. bit 0 = cmpfx pwmx compare flag. this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates that the upcounter value matches the active dcrx register value. 0: upcounter value does not match dcrx value. 1: upcounter value matches dcrx value. break control register (breakcr) read/write reset value: 0000 0000 (00h) bits 7:6 = reserved. forced by hardware to 0. bit 5 = ba break active. this bit is read/write by software, cleared by hard - ware after reset and set by hardware when the break pin is low. it acti vates/deacti vates the break function. 0: break not active 1: break active 15 8 0 0 0 0 atr11 atr10 atr9 atr8 7 0 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 7 0 0 oe3 0 oe2 0 oe1 0 oe0 7 6 0 0 0 0 0 0 0 opx cmpfx 7 0 0 0 ba bpen pwm3 pwm2 pwm1 pwm0 1 ST7LITE3 67/167 dual 12-bit autoreload timer 3 (cont?d) bit 4 = bpen break pin enable. this bit is read/write by software and cleared by hardware after reset. 0: break pin disabled 1: break pin enabled bit 3:0 = pwm[3:0] break pattern. these bits are read/write by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active. pwmx duty cycle register high (dcrxh) read / write reset value: 0000 0000 (00h) pwmx duty cycle register low (dcrxl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved. bits 11:0 = dcrx[11:0] pwmx duty cycle value this 12-bit value is writ ten by software. it defines the duty cycle of the corresponding pwm output signal (see figure 36 ). in pwm mode (oex=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwmx output signal (see figure 36 ). in output compare mode, they define the value to be com - pared with the 12-bit upcounter value. input capture register high (aticrh) read only reset value: 0000 0000 (00h) input capture register low (aticrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved. bits 11:0 = icr[11:0] input capture data . this is a 12-bit register which is readable by soft - ware and cleared by hardware after a reset. the aticr register contains captured the value of the 12-bit cntr1 register when a rising or falling edge occurs on the atic or ltic pin (depending on ics). capture will only be performed when the icf flag is cleared. timer control register2 (atcsr2) read/write reset value: 0000 0011 (03h) bits 7:6 = reserved. forced by hardware to 0. bit 5 = ics input capture shorted this bit is read/write by software. it allows the at - timer cntr1 to use the ltic pin for long input capture. 0 : atic for cntr1 input capture 1 : ltic for cntr1 input capture 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 7 0 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 15 8 0 0 0 0 icr11 icr10 icr9 icr8 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 7 0 0 0 ics ovfie2 ovf2 encnt r2 tran2 tran1 1 ST7LITE3 68/167 dual 12-bit autoreload timer 3 (cont?d) bit 4 = ovfie2 overflow interrupt 2 enable this bit is read/write by software and controls the overflow interrupt of counter2. 0: overflow interrupt disabled. 1: overflow interrupt enabled. bit 3 = ovf2 overflow flag. this bit is set by hardware and cleared by software by reading the atcsr2 register. it indicates the transition of the counter2 from fffh to atr2 val - ue. 0: no counter overflow occurred 1: counter overflow occurred bit 2 = encntr2 enable counter2 this bit is read/write be software and switches the second counter cntr2. if this bit is set, pwm2 and pwm3 will be generated using cntr2. 0: cntr2 stopped. 1: cntr2 starts running. bit 1= tran2 transfer enable2 this bit is read/write by software, cleared by hard - ware after each completed transfer and set by hardware after reset. it controls the transfers on cntr2. it allows the value of the preload dcrx registers to be transferred to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. ( only dcr2/dcr3 can be cont rolled with this bit ) bit 0 = tran1 transfer enable 1 this bit is read/write by software, cleared by hard - ware after each completed transfer and set by hardware after reset. it controls the transfers on cntr1. it allows the value of the preload dcrx registers to be transferred to the active dcrx reg - isters after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. autoreload register2 (atr2h) read / write reset value: 0000 0000 (00h) autoreload register (atr2l) read / write reset value: 0000 0000 (00h) bits 11:0 = atr2[11:0] autoreload register 2. this is a 12-bit register which is written by soft - ware. the atr2 register value is automatically loaded into the upcounter cntr2 when an over - flow of cntr2 occurs. the register value is used to set the pwm2/pwm3 frequency when encntr2 is set. dead time generator register (dtgr) read/write reset value: 0000 0000 (00h) bits 7 = dte dead time enable this bit is read/write by software. it enables a dead time generation on pwm0/pwm1. 0: no dead time insertion. 1: dead time insertion enabled. bit 6:0 = dt[6:0] dead time value these bits are read/write by software. they define the dead time inserted between pwm0/pwm1. dead time is calculated as follows: dead time = dt[6:0] x tcounter1 15 8 0 0 0 0 atr11 atr10 atr9 atr8 7 0 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 7 0 dte dt6 dt5 dt4 dt3 dt2 dt1 dt0 1 ST7LITE3 69/167 dual 12-bit autoreload timer 3 (cont?d) table 15. register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0d atcsr reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf1 0 ovfie1 0 cmpie 0 0e cntr1h reset value 0 0 0 0 cntr1_11 0 cntr1_10 0 cntr1_9 0 cntr1_8 0 0f cntr1l reset value cntr1_7 0 cntr1_6 0 cntr1_5 0 cntr1_4 0 cntr1_3 0 cntr1_2 0 cntr1_1 0 cntr1_0 0 10 atr1h reset value 0 0 0 0 atr11 0 atr10 0 atr9 0 atr8 0 11 atr1l reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 12 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 13 pwm0csr reset value 0 0 0 0 0 0 op0 0 cmpf0 0 14 pwm1csr reset value 0 0 0 0 0 0 op1 0 cmpf1 0 15 pwm2csr reset value 0 0 0 0 0 0 op2 0 cmpf2 0 16 pwm3csr reset value 0 0 0 0 0 0 op3 0 cmpf3 0 17 dcr0h reset value 0 0 0 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 19 dcr1h reset value 0 0 0 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1a dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1b dcr2h reset value 0 0 0 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1c dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1d dcr3h reset value 0 0 0 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1e dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1f aticrh reset value 0 0 0 0 icr11 0 icr10 0 icr9 0 icr8 0 20 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 ST7LITE3 70/167 21 atcsr2 reset value 0 0 ics 0 ovfie2 0 ovf2 0 encntr2 0 tran2 1 tran1 1 22 breakcr reset value 0 0 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 23 atr2h reset value 0 0 0 0 atr11 0 atr10 0 atr9 0 atr8 0 24 atr2l reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 25 dtgr reset value dte 0 dt6 0 dt5 0 dt4 0 dt3 0 dt2 0 dt1 0 dt0 0 address (hex.) register label 76 5 4 3 2 1 0 1 ST7LITE3 71/167 11.3 lite timer 2 (lt2) 11.3.1 introduction the lite timer can be used for general-purpose timing functions. it is based on two free-running 8- bit upcounters and an 8-bit input capture register. 11.3.2 main features realtime clock (rtc) ? one 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? one 8-bit upcounter with autoreload and pro - grammable timebase period from 4s to 1.024ms in 4s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability figure 45. lite timer 2 block diagram ltcsr1 8-bit timebase /2 8-bit f ltimer 8 ltic f osc /32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8mhz f osc ) to 12-bit at timer f ltimer ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase 0 0 8-bit autoreload register 8 ltcntr ltarr counter 2 counter 1 0 0 interrupt request 1 ST7LITE3 72/167 lite timer (cont?d) 11.3.3 functional description 11.3.3.1 timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs when the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time pe - riod between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. 11.3.3.2 timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. so ftware can write a new value at anytime in the ltarr register, this value will be automatically loade d in the counter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an inter - rupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. 11.3.3.3 input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr register contains the value of counter 1. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read-only register and always con - tains the data from the last input capture. input capture is inhibited if the icf bit is set. figure 46. input capture timing diagram. 04h 8-bit counter 1 t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4s (@ 8mhz f osc ) f cpu by s/w 07h reading ltic register 1 ST7LITE3 73/167 lite timer (cont?d) 11.3.4 low power modes 11.3.5 interrupts note: the tbxf and icf interrupt events are con - nected to separate interrupt vectors (see inter - rupts chapter). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is reset (rim instruction). 11.3.6 register description lite timer control/status register 2 (ltcsr2) read / write reset value: 0x00 0000 (x0h) bits 7:2 = reserved, mu st be kept cleared. bit 1 = tb2ie timebase 2 interrupt enable . this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled bit 0 = tb2f timebase 2 interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr2 register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred lite timer autore load register (ltarr) read / write reset value: 0000 0000 (00h) bits 7:0 = ar[7:0] counter 2 reload value. these bits register is read/write by software. the ltarr value is automatica lly loaded into counter 2 (ltcntr) when an overflow occurs. mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active-halt no effect on lite timer halt lite timer stops counting interrupt event event flag enable control bit exit from wait exit from active halt exit from halt timebase 1 event tb1f tb1ie yes yes no timebase 2 event tb2f tb2ie yes no no ic event icf icie yes no no 7 0 0 0 0 0 0 0 tb2ie tb2f 7 0 ar7 ar7 ar7 ar7 ar3 ar2 ar1 ar0 1 ST7LITE3 74/167 lite timer (cont?d) lite timer counter 2 (ltcntr) read only reset value: 0000 0000 (00h) bits 7:0 = cnt[7:0] counter 2 reload value. this register is read by software. the ltarr val - ue is automatically loaded into counter 2 (ltcn - tr) when an overflow occurs. lite timer control/status register (ltcsr1) read / write reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable. this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, so ftware must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection. this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) bit 4 = tb1ie timebase interrupt enable . this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled bit 3 = tb1f timebase interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bits 2:0 = reserved lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of t he 8-bit up-counter will be captured when a rising or falling edge occurs on the ltic pin. 7 0 cnt7 cnt7 cnt7 cnt7 cnt3 cnt2 cnt1 cnt0 7 0 icie icf tb tb1ie tb1f - - - 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 1 ST7LITE3 75/167 lite timer (cont?d) table 16. lite timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 08 ltcsr2 reset value 0 0 0 0 0 0 tb2ie 0 tb2f 0 09 ltarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0a ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0b ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 0 0 0 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 ST7LITE3 76/167 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 47 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 4 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in - put by spi slaves ? ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi - vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand - ard i/o ports on the master device . 1 ST7LITE3 77/167 serial peripheral interface (cont?d) figure 47. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 1 ST7LITE3 78/167 serial peripheral interface (cont?d) 11.4.3.1 functional description a basic example of inte rconnections between a single master and a single slave is illustrated in figure 48 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is alwa ys initiated by the mas - ter. when the master device transmits data to a slave device via mosi pin, the slave device re - sponds by sending data to the master device via the miso pin. this im plies full duplex communica - tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 51 ) but master and slave must be programmed with the same timing mode. figure 48. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1 ST7LITE3 79/167 serial peripheral interface (cont?d) 11.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis - ter (see figure 50 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ? ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 49 ): if cpha=1 (data latched on 2nd clock edge): ? ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag - ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ? ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg - ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.4.5.3 ). figure 49. generic ss timing diagram figure 50. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1 ST7LITE3 80/167 serial peripheral interface (cont?d) 11.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit ) may be not taken into account): 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 51 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 11.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig - nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg - ister is read. 11.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol - lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 51 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 11.4.3.2 and figure 49 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 11.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig - nificant bit first. the transmit sequence begins when the slave de - vice receives the clock signal and the most signifi - cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg - ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.4.5.2 ). 1 ST7LITE3 81/167 serial peripheral interface (cont?d) 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 51 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 51 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di - agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re - setting the spe bit. figure 51. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) 1 ST7LITE3 82/167 serial peripheral interface (cont?d) 11.4.5 error flags 11.4.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re - quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph - eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig - inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de - fault state. 11.4.5.2 overrun condition (ovr) an overrun condition occurs, when the master de - vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.4.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu oper - ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 52 ). figure 52. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result 1 ST7LITE3 83/167 serial peripheral interface (cont?d) 11.4.5.4 single master and multimaster configurations there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured, using a device as the master and four device s as slaves (see figure 53 ). the master device selects the individual slave de - vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con - nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com - mand fields. multi-master system a multi-master system ma y also be configured by the user. transfer of master control could be im - plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 53. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device 1 ST7LITE3 84/167 serial peripheral interface (cont?d) 11.4.6 low power modes 11.4.6.1 using the spi to wake-up the device from halt mode in slave configuration, the spi is able to wake-up the device from halt mode through a spif inter - rupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per - form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake-up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so if slave se - lection is configured as external (see section 11.4.3.2 ), make sure the mast er drives a low level on the ss pin when the slave enters halt mode. 11.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events caus e the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper - ation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the soft - ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of trans - fer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no 1 ST7LITE3 85/167 serial peripheral interface (cont?d) 11.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or over - run error occurs (spif=1, modf=1 or ovr=1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not init ially connected to the ex - ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 17 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func - tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de - termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re - setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 17. spi master mode sck frequency 7 0 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 1 ST7LITE3 86/167 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr regist er. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter - nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg - ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se - quence. it is cleared by a software sequence (see figure 52 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.4.5.2 ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.4.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.4.3.2 slave select management . 0: hardware management ( ss managed by exter - nal pin) 1: software management (internal ss signal con - trolled by ssi bit. external ss pin free for gener - al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo - cated in the buffer and not the content of the shift register (see figure 47 ). 7 0 spif wcol ovr modf - sod ssm ssi 7 0 d7 d6 d5 d4 d3 d2 d1 d0 1 ST7LITE3 87/167 table 18. spi register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0031h spidr reset value msb x x x x x x x lsb x 0032h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0033h spicsr reset value spif 0 wcol 0 ovr 0 modf 0 0 sod 0 ssm 0 ssi 0 1 ST7LITE3 88/167 11.5 linsci serial communication interface (lin master/slave) 11.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of - fers a very wide range of baud rates using two baud rate generator systems. the lin-dedicated features support the lin (local interconnect network) protocol for both master and slave nodes. this chapter is divided into sci mode and lin mode sections. for information on general sci communications, refer to the sci mode section. for lin applications, refer to both the sci mode and lin mode sections. 11.5.2 sci features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver overrun, noise and frame error detection six interrupt sources ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error ? parity interrupt parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.5.3 lin features ? lin master ? 13-bit lin synch break generation ? lin slave ? automatic header handling ? automatic baud rate re-synchronization based on recognition and measurement of the lin synch field (for lin slave nodes) ? automatic baud rate adjustment (at cpu fre - quency precision) ? 11-bit lin synch brea k detection capability ? lin parity check on the lin identifier field (only in reception) ? lin error management ? lin header timeout ? hot plugging support 1 ST7LITE3 89/167 linsci ? serial communication interface (cont?d) 11.5.4 general description the interface is externally connected to another device by two pins: ? tdo: transmit data output. when the transmit - ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena - bled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re - covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as characters comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the character is com - plete. this interface uses three types of baud rate gener - ator: ? a conventional type for commonly-used baud rates. ? an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. ? a lin baud rate generator with automatic resyn - chronization. 1 ST7LITE3 90/167 linsci ? serial communication interface (sci mode) (cont?d) figure 54. sci block diagram (in conventional baud rate generator mode) wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 lhe 1 ST7LITE3 91/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.5 sci mode - functional description conventional baud rate generator mode the block diagram of the serial control interface in conventional baud rate generator mode is shown in figure 54 . it uses 4 registers: ? two control registers (scicr1 and scicr2) ? a status register (scisr) ? a baud rate register (scibrr) extended prescaler mode two additional prescalers are available in extend - ed prescaler mode. they are shown in figure 56 . ? an extended prescaler receiver register (scier - pr) ? an extended prescaler transmitter register (sci - etpr) 11.5.5.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg - ister (see figure 55 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as a continuous logic high level for 10 (or 11) full bit times. a break character is a character with a sufficient number of low level bits to break the normal data format followed by an extra ?1? bit to acknowledge the start bit. figure 55. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle line bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle line start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break character start bit extra ?1? data character break character start bit extra ?1? data character next data character next data character 1 ST7LITE3 92/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.5.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be - tween the internal bus and the transmit shift regis - ter (see figure 54 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to send a preamble of 10 (m=0) or 11 (m=1) consecutive ones (idle line) as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis - ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i[|1:0] bits are cleared in the ccr register. when a transmission is taking place, a write in - struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in - struction to the scidr register places the data di - rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a character transmission is complete (after the stop bit or after the break character) the tc bit is set and an interrupt is generated if the tcie is set and the i[1:0] bits are cleared in the ccr reg - ister. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break character length de - pends on the m bit (see figure 55 ) as long as the sbk bit is set, the sci sends break characters to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break character to guarantee the recogni - tion of the start bit of the next character. idle line setting the te bit drives the sci to send a pream - ble of 10 (m=0) or 11 (m=1) consecutive ?1?s (idle line) before the first character. in this case, clearing and then setting the te bit during a transmission sends a preamble (idle line) after the current word. note that the preamble du - ration (10 or 11 consecutive ?1?s depending on the m bit) does not take into account the stop bit of the previous character. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. 1 ST7LITE3 93/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.5.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi - cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be - tween the internal bus and the received shift regis - ter (see figure 54 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re - ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. idle line when an idle line is detected, there is the same procedure as a data received character plus an in - terrupt if the ilie bit is set and the i[|1:0] bits are cleared in the ccr register. overrun error an overrun error occurs when a character is re - ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when an overrun error occurs: ? the or bit is set. ? the rdr content will not be lost. ? the shift register will be overwritten. ? an interrupt is generated if the rie bit is set and the i[|1:0] bits are cleared in the ccr register. the or bit is reset by an access to the scisr reg - ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov - ery by discriminating between valid incoming data and noise. when noise is detected in a character: ? the nf bit is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read oper - ation followed by a scidr register read operation. framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni - zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper - ation followed by a scidr register read operation. break character ? when a break character is received, the sci handles it as a framing error. to differentiate a break character from a framing error, it is neces - sary to read the scidr. if the received value is 00h, it is a break character. otherwise it is a framing error. 1 ST7LITE3 94/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.5.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en - abled. 11.5.5.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal - er, whereas the conventional baud rate genera - tor retains industry standard software compatibili - ty. the extended baud rate generator block diagram is described in figure 56 . the output clock rate sent to the transmitter or to the receiver will be the out put from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set - ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu 1 ST7LITE3 95/167 linsci ? serial communication interface (sci mode) (cont?d) figure 56. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register 1 ST7LITE3 96/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.5.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira - ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interr upts are inhibited. a muted receiver may be woken up in one of the following ways: ? by idle line detection if the wake bit is reset, ? by address mark detection if the wake bit is set. idle line detection receiver wakes-up by idle line detection when the receive line has recognis ed an idle line. then the rwu bit is reset by hardware but the idle bit is not set. this feature is useful in a multiprocessor system when the first characters of the message deter - mine the address and when each message ends by an idle line: as soon as the line becomes idle, every receivers is waken up and analyse the first characters of the message which indicates the ad - dressed receiver. the receivers which are not ad - dressed set rwu bit to enter in mute mode. con - sequently, they will not treat the next characters constituting the next part of the message. at the end of the message, an idle line is sent by the transmitter: this wakes up every receivers which are ready to analyse the addressing characters of the new message. in such a system, the inter-characters space must be smaller than the idle time. address mark detection receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an ad - dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. this feature is useful in a multiprocessor system when the most significant bit of each character (except for the break character) is reserved for ad - dress detection. as soon as the receivers re - ceived an address character (most significant bit =?1?), the receivers are waken up. the receivers which are not addressed set rwu bit to enter in mute mode. consequently, they will not treat the next characters constituting the next part of the message. 11.5.5.7 parity control hardware byte parity control (generation of parity bit in transmission and parity checking in recep - tion) can be enabled by setting the pce bit in the scicr1 register. depending on the character for - mat defined by the m bit, the possible sci charac - ter formats are as listed in table 19 . note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit table 19. character formats legend: sb = start bit, stb = stop bit, pb = parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in - terface checks if the received data byte has an even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is se - lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen - erated if pcie is set in the scicr1 register. m bit pce bit character format 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data | pb | stb | 1 ST7LITE3 97/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.6 low power modes 11.5.7 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre - sponding enable control bit is set and the inter - rupt mask in the cc regist er is reset (rim instruc - tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit - ting/receiving until halt mode is exit - ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com - plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error or lin synch error detected or/ lhe yes no idle line detected idle ilie yes no parity error pe pie yes no lin header detection lhdf lhie yes no 1 ST7LITE3 98/167 linsci ? serial communication interface (sci mode) (cont?d) 11.5.8 sci mode register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the scicr2 register. it is cleared by a software se - quence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register bit 6 = tc transmission complete. this bit is set by hardwar e when transmission of a character containing data is complete. an inter - rupt is generated if tcie=1 in the scicr2 regis - ter. it is cleared by a software sequence (an ac - cess to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre - amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se - quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detected. this bit is set by hardware when an idle line is de - tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se - quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc - curs). bit 3 = or overrun error the or bit is set by hardware when the word cur - rently being received in the shift register is ready to be transferred into the rdr register whereas rdrf is still set. an interr upt is genera ted if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol - lowed by a read to the scidr register). 0: no overrun error 1: overrun error detected note: when this bit is set, rdr register contents will not be lost but the shift register will be overwrit - ten. bit 2 = nf character noise flag this bit is set by hardware when noise is detected on a received character. it is cleared by a software sequence (an access to the scisr register fol - lowed by a read to the scidr register). 0: no noise 1: noise is detected note: this bit does not generate interrupt as it ap - pears at the same time as the rdrf bit which it - self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza - tion, excessive noise or a break character is de - tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error or break character detected notes: ? this bit does not generate an interrupt as it ap - pears at the same time as the rdrf bit which it - self generates an interrupt. if the word currently being transferred causes both a frame error and an overrun error, it will be transferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a byte parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the sta - tus register followed by an access to the scidr data register). an interrupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error detected 7 0 tdre tc rdrf idle or 1) nf 1) fe 1) pe 1) 1 ST7LITE3 99/167 linsci ? serial communication interface (sci mode) (cont?d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) 1) this bit has a different function in lin mode, please refer to the lin mode register description. bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit - ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans - fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark note: if the line bit is set, the wake bit is de-ac - tivated and replaced by the lhdm bit bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control (generation and detec - tion for byte parity, detection only for lin parity). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected afte r the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard - ware parity control when a parity error is detected (pe bit set). the parity error involved can be a byte parity error (if bit pce is set and bit lpe is reset) or a lin parity error (if bit pce is set and bit lpe is set). 0: parity error interrupt disabled 1: parity error interrupt enabled 7 0 r8 t8 scid m wake pce 1) ps pie 1 ST7LITE3 100/167 linsci ? serial communication interface (sci mode) (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00 h) 1) this bit has a different function in lin mode, please refer to the lin mode register description. bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: in sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission comple te interrupt ena - ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled in the scisr register 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode notes: ? before selecting mute mode (by setting the rwu bit) the sci must first receive a data byte, other - wise it cannot function in mute mode with wake - up by idle line detection. ? in address mark detection wake-up configura - tion (wake bit=1) the rwu bit cannot be modi - fied by software while the rdrf bit is set. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1 ? and then to ?0?, the transmitter will send a break word at the end of the current word. data register (scidr) read/write reset value: undefined contains the received or transmitted data char - acter, depending on whether it is read from or writ - ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg - ister (see figure 54 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 54 ). 7 0 tie tcie rie ilie te re rwu 1) sbk 1) 7 0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 1 ST7LITE3 101/167 linsci ? serial communication interface (sci mode) (cont?d) baud rate register (scibrr) read/write reset value: 0000 0000 (00h) note: when lin slave mode is disabled, the sci - brr register controls the conventional baud rate generator. bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention - al baud rate generator mode. bit 2:0 = scr[2:0] sci receiver rate divider. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate cloc k in conventional baud rate generator mode. 7 0 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 1 0 0 3 0 1 4 1 0 13 1 1 tr dividing factor sct2 sct1 sct0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 ST7LITE3 102/167 linsci ? serial communication interface (sci mode) (cont?d) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00 h) bit 7:0 = erpr[7:0] 8-bit extended receive pres - caler register. the extended baud rate generator is activated when a value other than 00h is stored in this regis - ter. the clock frequency from the 16 divider (see figure 56 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not active af - ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00 h) bit 7:0 = etpr[7:0] 8-bit extended transmit pres - caler register. the extended baud rate generator is activated when a value other than 00h is stored in this regis - ter. the clock frequency from the 16 divider (see figure 56 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not active af - ter a reset. note: in lin slave mode, the conventional and extended baud rate generators are disabled. 7 0 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 7 0 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 ST7LITE3 103/167 linsci ? serial communication interface (lin mode) 11.5.9 lin mode - functional description. the block diagram of the serial control interface, in lin slave mode is shown in figure 58 . it uses 6 registers: ? three control registers: scicr1, scicr2 and scicr3 ? two status registers: the scisr register and the lhlr register mapped at the scierpr address ? a baud rate register: lpr mapped at the sci - brr address and an associated fraction register lpfr mapped at the scietpr address the bits dedicated to lin are located in the scicr3. refer to the register descriptions in sec - tion 11.5.10 for the definitions of each bit. 11.5.9.1 entering lin mode to use the linsci in lin mode the following con - figuration must be set in scicr3 register: ? clear the m bit to configure 8-bit word length. ? set the line bit. master to enter master mode the lslv bit must be reset in this case, setting t he sbk bit will send 13 low bits. then the baud rate can programmed using the scibrr, scierpr and scietpr registers. in lin master mode, the conventional and / or ex - tended prescaler define the baud rate (as in stand - ard sci mode) slave set the lslv bit in the scicr3 register to enter lin slave mode. in this case, setting the sbk bit will have no effect. in lin slave mode the lin baud rate generator is selected instead of the conventional or extended prescaler. the lin baud rate generator is com - mon to the transmitter and the receiver. then the baud rate can be programmed using lpr and lprf registers. note: it is mandatory to set the lin configuration first before programming lpr and lprf, because the lin configuration uses a different baud rate generator from the standard one. 11.5.9.2 lin transmission in lin mode the same procedure as in sci mode has to be applied for a lin transmission. to transmit the lin header the proceed as fol - lows: ? first set the sbk bit in the scicr2 register to start transmitting a 13-bit lin synch break ? reset the sbk bit ? load the lin synch field (0x55) in the scidr register to request synch field transmission ? wait until the scidr is empty (tdre bit set in the scisr register) ? load the lin message identifier in the scidr register to request identifier transmission. ST7LITE3 104/167 linsci ? serial communication interface (lin mode) (cont?d) figure 57. lin characters bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle line start bit 8-bit word length (m bit is reset) lin synch break = 13 low bits start bit extra ?1? data character next data character bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field lin synch field measurement for baud rate autosynchronization ST7LITE3 105/167 linsci ? serial communication interface (lin mode) (cont?d) figure 58. sci block diag ram in lin slave mode wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock f cpu / ldiv sbk rwu re te ilie rie tcie tie scicr2 lin slave baud rate auto synchronization f cpu scicr3 line lase lhie lsf lhdf extended prescaler conventional baud rate generator + /16 scibrr lpr7 lpr0 lin slave baud rate generator 0 1 unit ldum lhdm lhe lslv ST7LITE3 106/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.9.3 lin reception in lin mode the reception of a byte is the same as in sci mode but the linsci has features for han - dling the lin header automatically (identifier de - tection) or semiautomatically (synch break detec - tion) depending on the lin header detection mode. the detection mode is selected by the lhdm bit in the scicr3. additionally, an automatic resynchronization fea - ture can be activated to compensate for any clock deviation, for more details please refer to section 11.5.9.5 lin baudrate . lin header handling by a slave depending on the lin header detection method the linsci will signal the detection of a lin head - er after the lin synch break or after the identifier has been successfully received. note: it is recommended to combine the header detec - tion function with mute mode. putting the linsci in mute mode allows the detection of headers only and prevents the reception of any other charac - ters. this mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not rele - vant for the application. synch break detection (lhdm = 0): when a lin synch break is received: ? the rdrf bit in the scisr register is set. it in - dicates that the content of the shift register is transferred to the scidr register, a value of 0x00 is expected for a break. ? the lhdf flag in the scicr3 register indicates that a lin synch break field has been detected. ? an interrupt is generated if the lhie bit in the scicr3 register is set and the i[1:0] bits are cleared in the ccr register. ? then the lin synch field is received and meas - ured. ? if automatic resynchronization is enabled (la - se bit = 1), the lin synch field is not trans - ferred to the shift register: there is no need to clear the rdrf bit. ? if automatic resynchronization is disabled (la - se bit =0), the lin synch field is received as a normal character and transferred to the scidr register and rdrf is set. note: in lin slave mode, the fe bit detects all frame er - ror which does not correspond to a break. identifier detection (lhdm = 1): this case is the same as the previous one except that the lhdf and the rdrf flags are set only af - ter the entire header has been received (this is true whether automatic resynchronization is ena - bled or not). this indicates that the lin identifier is available in the scidr register. notes: during lin synch field measurement, the sci state machine is switched off: no characters are transferred to the data register. lin slave parity in lin slave mode (line and lslv bits are set) lin parity checking can be enabled by setting the pce bit. in this case, the parity bits of the lin identifier field are checked. the identifier character is rec - ognised as the 3 rd received character after a break character (included): the bits involved are the two msb positions (7 th and 8 th bits if m=0; 8 th and 9 th bits if m=0) of the identifier character. the check is performed as specified by the lin specification: lin synch lin synch identifier parity bits field field break identifier field parity bits id0 start bit stop bit id1 id2 id3 id4 id5 p0 p1 identifier bits p1 id1 id3 id4 id5 = p0 id0 = id1 id2 id4 m=0 ST7LITE3 107/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.9.4 lin error detection lin header error flag the lin header error flag indicates that an invalid lin header has been detected. when a lin header error occurs: ? the lhe flag is set ? an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. if autosynchronization is enabled (lase bit =1), this can mean that the lin synch field is corrupt - ed, and that the sci is in a blocked state (lsf bit is set). the only way to recover is to reset the lsf bit and then to clear the lhe bit. ? the lhe bit is reset by an access to the scisr register followed by a read of the scidr register. lhe/ovr error conditions when auto resynchronization is disabled (lase bit =0), the lhe flag detects: ? that the received lin synch field is not equal to 55h. ? that an overrun occurred (as in standard sci mode) ? furthermore, if lhdm is se t it also detects that a lin header reception timeout occurred (only if lhdm is set). when the lin auto-resynchronization is enabled (lase bit=1), the lhe flag detects: ? that the deviation error on the synch field is outside the lin specification which allows up to +/-15.5% of period deviation between the slave and master oscillators. ? a lin header reception timeout occurred. if t header > t header_max then the lhe flag is set. refer to figure 59 . (only if lhdm is set to 1) ? an overflow during the synch field measure - ment, which leads to an overflow of the divider registers. if lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). ? that an overrun occurred on fields other than the synch field (as in standard sci mode) deviation error on the synch field the deviation error is checking by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the master oscillator). two checks are performed in parallel: ? the first check is based on a measurement be - tween the first falling edg e and the last falling edge of the synch field. let?s refer to this period deviation as d: if the lhe flag is set, it means that: d > 15.625% if lhe flag is not set, it means that: d < 16.40625% if 15.625% d < 16.40625%, then the flag can be either set or reset depending on the dephas - ing between the signal on the rdi line and the cpu clock. ? the second check is based on the measurement of each bit time between both edges of the synch field: this checks that each of these bit times is large enough compared to the bit time of the cur - rent baud rate. when lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). lin header time-out error when the lin identifier field detection method is used (by configuring lhdm to 1) or when lin auto-resynchronization is enabled (lase bit=1), the linsci automatically monitors the t header_max condition given by the lin protocol. if the entire header (up to and including the stop bit of the lin identifier field) is not received within the maximum time limit of 57 bit times then a lin header error is signalled and the lhe bit is set in the scisr register. figure 59. lin header reception timeout the time-out counter is enabled at each break de - tection. it is stopped in the following conditions: - a lin identifier field has been received - an lhe error occurred (other than a timeout er - ror). - a software reset of lsf bit (transition from high to low) occurred during the analysis of the lin synch field or if lhe bit is set due to this error during the lin synchr field (if lase bit = 1) then the sci goes into a blocked state (lsf bit is set). lin synch lin synch identifier field field break t header ST7LITE3 108/167 linsci ? serial communication interface (lin mode) (cont?d) if lhe bit is set due to this error during fields other than lin synch field or if lase bit is reset then the current received header is discarded and the sci searches for a new break field. note on lin header time-out limit according to the lin spec ification, the maximum length of a lin header which does not cause a timeout is equal to 1.4*(34 + 1) = 49 t bit_master . t bit_master refers to the master baud rate. when checking this timeout, the slave node is de - synchronized for the reception of the lin break and synch fields. consequently, a margin must be allowed, taking into acc ount the worst case: this occurs when the lin identifier lasts exactly 10 t bit_master periods. in this case, the lin break and synch fields last 49-10 = 39t bit_master peri - ods. assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. this leads to a maximum allowed header length of: 39 x (1/0.845) t bit_master + 10t bit_master = 56.15 t bit_slave a margin is provided so that the time-out occurs when the header length is greater than 57 t bit_slave periods. if it is less than or equal to 57 t bit_slave periods, then no timeout occurs. lin header length even if no timeout occurs on the lin header, it is possible to have access to the effective lin head - er length (t header ) through the lhl register. this allows monitoring at software level the t frame_max condition given by the lin protocol. this feature is only available when lhdm bit =1 or when lase bit =1. mute mode and errors in mute mode when lhdm bit =1, if an lhe error occurs during the analysis of the lin synch field or if a lin header time-out occurs then the lhe bit is set but it doesn?t wake up from mute mode. in this case, the current header analysis is discarded. if needed, the software has to reset lsf bit. then the sci searches for a new lin header. in mute mode, if a framing error occurs on a data (which is not a break), it is discarded and the fe bit is not set. when lhdm bit =1, any lin header which re - spects the following conditions causes a wake up from mute mode: - a valid lin break field (at least 11 dominant bits followed by a recessive bit) - a valid lin synch field (without deviation error) - a lin identifier field without framing error. note that a lin parity error on the lin identifier field does not prevent wake up from mute mode. - no lin header time-out should occur during header reception. figure 60. lin synch field measurement lin synch break extra ?1? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br = sm.t cpu lpr(n) lpr(n+1) lpr = t br / (16.t cpu ) = rounding (sm / 128) t cpu = cpu period t br = baud rate period t br t br = 16.lp.t cpu sm=synch measurement register (15 bits) ST7LITE3 109/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.9.5 lin baudrate baud rate programming is done by writing a value in the lpr prescaler or performing an automatic resynchronization as described below. automatic resynchronization to automatically adjust the baud rate based on measurement of the lin synch field: ? write the nominal lin pr escaler value (usually depending on the nominal baud rate) in the lpfr / lpr registers. ? set the lase bit to ena ble the auto synchroni - zation unit. when auto synchronization is enabled, after each lin synch break, the time duration between 5 fall - ing edges on rdi is sampled on f cpu and the re - sult of this measurement is stored in an internal 15-bit register called sm (not user accessible) (see figure 60 ). then the ldiv value (and its as - sociated lpfr and lpr registers) are automati - cally updated at the end of the fifth falling edge. during lin synch field measurement, the sci state machine is stopped and no data is trans - ferred to the data register. 11.5.9.6 lin slave baud rate generation in lin mode, transmission and reception are driv - en by the lin baud rate generator note: lin master mode uses the extended or conventional prescaler register to generate the baud rate. if line bit = 1 and lslv bit = 1 then the conven - tional and extended baud rate generators are disabled: the baud rate for the receiver and trans - mitter are both set to the same value, depending on the lin slave baud rate generator: with: ldiv is an unsigned fixed point number. the man - tissa is coded on 8 bits in the lpr register and the fraction is coded on 4 bits in the lpfr register. if lase bit = 1 then ldiv is automatically updated at the end of each lin synch field. three registers are used internally to manage the auto-update of the lin divider (ldiv): - ldiv_nom (nominal value written by software at lpr/lpfr addresses) - ldiv_meas (results of the field synch meas - urement) - ldiv (used to generate the local baud rate) the control and interactions of these registers is explained in figure 61 and figure 62 . it depends on the ldum bit setting (lin divider update meth - od) note: as explained in figure 61 and figure 62 , ldiv can be updated by two concurrent actions: a transfer from ldiv_meas at the end of the lin sync field and a transfer from ldiv_nom due to a software write of lpr. if both operations occur at the same time, the transfer from ldiv_nom has priority. tx = rx = (16 * ldiv) f cpu ST7LITE3 110/167 linsci ? serial communication interface (lin mode) (cont?d) figure 61. ldiv read / write operations when ldum=0 figure 62. ldiv read / write operations when ldum=1 mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generarion lin sync field measurement write lpr mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update rdrf=1 at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generarion lin sync field measurement ST7LITE3 111/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.9.7 linsci clock tolerance linsci clock tolerance when unsynchronized when lin slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the linsci clock is +/-15%. if the deviation is within this range then the lin synch break is detected properly when a new re - ception occurs. this is made possible by the fact that masters send 13 low bits for the lin synch break, which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a ?fast? slave and then considered as a lin synch break. according to the lin specifica - tion, a lin synch break is valid when its duration is greater than t sbrkts = 10. this means that the lin synch break must last at least 11 low bits. note: if the period desynchronization of the slave is +15% (slave too slow), the character ?00h? which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35). consequently, a valid lin synch break must last at least 11 low bits. linsci clock tolerance when synchronized when synchronization has been performed, fol - lowing reception of a lin synch break, the lins - ci, in lin mode, has the same clock deviation tol - erance as in sci mode, which is explained below: during reception, each bit is oversampled 16 times. the mean of the 8 th , 9 th and 10 th samples is considered as the bit value. consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%. 11.5.9.8 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error. note: the transmitter can be either a master or a slave (in case of a slave listening to the re - sponse of another slave). ?d meas : error due to the lin synch measure - ment performed by the receiver. ?d quant : error due to the baud rate quantisa - tion of the receiver. ?d rec : deviation of the local oscillator of the receiver: this deviation can occur during the reception of one complete lin message as - suming that the deviation has been compen - sated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the linsci clock tolerance: d tra + d meas +d quant + d rec + d tcl < 3.75% figure 63 . bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 ST7LITE3 112/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.9.9 error due to lin synch measurement the lin synch field is measured over eight bit times. this measurement is performed using a counter clocked by the cpu clock. the edge detections are performed using the cpu clock cycle. this leads to a precision of 2 cpu clock cycles for the measurement which lasts 16*8*ldiv clock cy - cles. consequently, this error (d meas ) is equal to: 2 / (128*ldiv min ). ldiv min corresponds to the minimum lin prescal - er content, leading to the maximum baud rate, tak - ing into account the maximum deviation of +/-15%. 11.5.9.10 error due to baud rate quantisation the baud rate can be adjusted in steps of 1 / (16 * ldiv). the worst case occurs when the ?real? baud rate is in the middle of the step. this leads to a quantization error (d quant ) equal to 1 / (2*16*ldiv min ). 11.5.9.11 impact of clock deviation on maximum baud rate the choice of the nominal baud rate (ldiv nom ) will influence both the quantisation error (d quant ) and the measurement error (d meas ). the worst case occurs for ldiv min . consequently, at a given cpu frequency, the maximum possible nominal baud rate (lpr min ) should be chosen with respect to the maximum tol - erated deviation given by the equation: d tra + 2 / (128*ldiv min ) + 1 / (2*16*ldiv min ) + d rec + d tcl < 3.75% example: a nominal baud rate of 20kbits/s at t cpu = 125ns (8mhz) leads to ldiv nom = 25d. ldiv min = 25 - 0.15*25 = 21.25 d meas = 2 / (128*ldiv min ) * 100 = 0.00073% d quant = 1 / (2*16*ldiv min ) * 100 = 0.0015% lin slave systems for lin slave systems (the line and lslv bits are set), receivers wake up by lin synch break or lin identifier detection (depending on the lhdm bit). hot plugging feature for lin slave nodes in lin slave mute mode (the line, lslv and rwu bits are set) it is possible to hot plug to a net - work during an ongoing communication flow. in this case the sci monitors the bus on the rdi line until 11 consecutive dominant bits have been de - tected and discards all the other bits received. ST7LITE3 113/167 linsci ? serial communication interface (lin mode) (cont?d) 11.5.10 lin mode register description status register (scisr) read only reset value: 1100 0000 (c0h) bits 7:4 = same function as in sci mode, please refer to section 11.5.8 sci mode register de - scription . bit 3 = lhe lin header error . during lin header this bit signals three error types: ? the lin synch field is corrupted and the sci is blocked in lin synch state (lsf bit=1). ? a timeout occurred during lin header reception ? an overrun error was detected on one of the header field (see or bit description in section 11.5.8 sci mode register description )). an interrupt is generated if rie=1 in the scicr2 register. if blocked in the lin synch state, the lsf bit must first be reset (to exit lin synch field state and then to be able to clear lhe flag). then it is cleared by the following software sequence : an access to the scisr register followed by a read to the scidr register. 0: no lin header error 1: lin header error detected note: apart from the lin header this bit signals an over - run error as in sci mode, (see description in sec - tion 11.5.8 sci mode register description ) bit 2 = nf noise flag in lin master mode (line bit = 1 and lslv bit = 0) this bit has the same function as in sci mode, please refer to section 11.5.8 sci mode register description in lin slave mode (line bit = 1 and lslv bit = 1) this bit has no meaning. bit 1 = bit 1 = fe framing error. in lin slave mode, this bit is set only when a real framing error is detected (if the stop bit is dominant (0) and at least one of the other bits is recessive (1). it is not set when a break occurs, the lhdf bit is used instead as a break flag (if the lhdm bit=0). it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error detected bit 0 = pe parity error. this bit is set by hardware when a lin parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the sta - tus register followed by an access to the scidr data register). an interrupt is generated if pie=1 in the scicr1 register. 0: no lin parity error 1: lin parity error detected control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bits 7:3 = same function as in sci mode, please refer to section 11.5.8 sci mode register de - scription . bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control for lin identifier parity check. 0: parity control disabled 1: parity control enabled when a parity error occurs, the pe bit in the scisr register is set. bit 1 = reserved bit 0 = same function as in sci mode, please refer to section 11.5.8 sci mode register description . 7 0 tdre tc rdrf idle lhe nf fe pe 7 0 r8 t8 scid m wake pce ps pie ST7LITE3 114/167 linsci ? serial communication interface (lin mode) (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00 h) bits 7:2 same function as in sci mode, please re - fer to section 11.5.8 sci mode register descrip - tion . bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode notes: ? mute mode is recommended for detecting only the header and avoiding the reception of any other characters. for more details please refer to section 11.5.9.3 lin reception . ? in lin slave mode, when rdrf is set, the soft - ware can not set or clear the rwu bit. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1 ? and then to ?0?, the transmitter will send a break word at the end of the current word. control register 3 (scicr3) read/write reset value: 0000 0000 (00h) bit 7= ldum lin divider update method. this bit is set and cleared by software and is also cleared by hardware (when rdrf=1). it is only used in lin slave mode. it determines how the lin divider can be updated by software. 0: ldiv is updated as soon as lpr is written (if no auto synchronization update occurs at the same time). 1: ldiv is updated at the next received character (when rdrf=1) after a write to the lpr register notes: - if no write to lpr is performed between the set - ting of ldum bit and the reception of the next character, ldiv will be upd ated with the old value. - after ldum has been set, it is possible to reset the ldum bit by software. in this case, ldiv can be modified by writing into lpr / lpfr registers. bit 6:5 = line, lslv lin mode enable bits. these bits configure the lin mode: the lin master configuration enables: the capability to send li n synch breaks (13 low bits) using the sbk bit in the scicr2 register. the lin slave configuration enables: ? the lin slave baud rate generator. the lin divider (ldiv) is then represented by the lpr and lpfr registers. the lpr and lpfr reg - isters are read/write accessible at the address of the scibrr register and the address of the scietpr register ? management of lin headers. ? lin synch break detection (11-bit dominant). ? lin wake-up method (see lhdm bit) instead of the normal sci wake-up method. ? inhibition of break transmission capability (sbk has no effect) ? lin parity checking (in conjunction with the pce bit) bit 4 = lase lin auto synch enable. this bit enables the auto synch unit (asu). it is set and cleared by software. it is only usable in lin slave mode. 0: auto synch unit disabled 1: auto synch unit enabled. bit 3 = lhdm lin header detection method this bit is set and cleared by software. it is only us - able in lin slave mode. it enables the header de - tection method. in addition if the rwu bit in the 7 0 tie tcie rie ilie te re rwu sbk 7 0 ldum line lslv lase lhdm lhie lhdf lsf line lslv meaning 0 x lin mode disabled 1 0 lin master mode 1 1 lin slave mode ST7LITE3 115/167 linsci ? serial communication interface (lin mode) (cont?d) scicr2 register is set, the lhdm bit selects the wake-up method (repla cing the wake bit). 0: lin synch break detection method 1: lin identifier field detection method bit 2 = lhie lin header interrupt enable this bit is set and cleared by software. it is only us - able in lin slave mode. 0: lin header interrupt is inhibited. 1: an sci interrupt is generated whenever lhdf=1. bit 1= lhdf lin header detection flag this bit is set by hardwa re when a lin header is detected and cleared by a software sequence (an access to the scisr register followed by a read of the scicr3 register). it is only usable in lin slave mode. 0: no lin header detected. 1: lin header detected. notes: the header detection method depends on the lhdm bit: ? if lhdm=0, a header is detected as a lin synch break. ? if lhdm=1, a header is detected as a lin identifier, meaning that a lin synch break field + a lin synch field + a lin identifier field have been consecutively received. bit 0= lsf lin synch field state this bit indicates that the lin synch field is being analyzed. it is only used in lin slave mode. in auto synchronization mo de (lase bit=1), when the sci is in the lin synch field state it waits or counts the falling edges on the rdi line. it is set by hardware as soon as a lin synch break is detected and cleared by hardware when the lin synch field analysis is finished (see figure 64 ). this bit can also be cleared by software to exit lin synch state and return to idle mode. 0: the current character is not the lin synch field 1: lin synch field state (lin synch field under - going analysis) figure 64. lsf bit set and clear lin divider registers ldiv is coded using the two registers lpr and lp - fr. in lin slave mode, the lpr register is acces - sible at the address of the scibrr register and the lpfr register is accessible at the address of the scietpr register. lin prescaler register (lpr) read/write reset value: 0000 0000 (00h) lpr[7:0] lin prescaler (mantissa of ldiv) these 8 bits define the value of the mantissa of the lin divider (ldiv): caution: lpr and lpfr registers have different meanings when reading or writing to them. conse - quently bit manipulation instructions (bres or bset) should never be used to modify the lpr[7:0] bits, or the lpfr[3:0] bits. 7 0 lpr7 lpr6 lpr5 lpr4 lpr3 lpr2 lpr1 lpr0 lpr[7:0] rounded mantissa (ldiv) 00h sci clock disabled 01h 1 ... ... feh 254 ffh 255 lin synch lin synch identifier parity bits field field break 11 dominant bits lsf bit ST7LITE3 116/167 linsci ? serial communication interface (lin mode) (cont?d) lin prescaler fraction register (lpfr) read/write reset value: 00 00 0000 (00h) bits 7:4= reserved. bits 3:0 = lpfr[3:0] fraction of ldiv these 4 bits define the fraction of the lin divider (ldiv): 1. when initializing ldiv, the lpfr register must be written first. then, the write to the lpr register will effectively update ldiv and so the clock gen - eration. 2. in lin slave mode, if the lpr[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off. examples of ldiv coding: example 1: lpr = 27d and lpfr = 12d this leads to: mantissa (ldiv) = 27d fraction (ldiv) = 12/16 = 0.75d therefore ldiv = 27.75d example 2: ldiv = 25.62d this leads to: lpfr = rounded(16*0.62d) = rounded(9.92d) = 10d = ah lpr = mantissa (25.620d) = 25d = 1bh example 3: ldiv = 25.99d this leads to: lpfr = rounded(16*0.99d) = rounded(15.84d) = 16d 7 0 0 0 0 0 lpfr 3 lpfr 2 lpfr 1 lpfr 0 lpfr[3:0] fraction (ldiv) 0h 0 1h 1/16 ... ... eh 14/16 fh 15/16 ST7LITE3 117/167 linsci ? serial communication interface (lin mode) (cont?d) lin header length register (lhlr) read only reset value: 0000 0000 (00 h). note: in lin slave mode when lase = 1 or lhdm = 1, the lhlr register is accessible at the address of the scierpr register. otherwise this register is always read as 00h. bit 7:0 = lhl[7:0] lin header length. this is a read-only register, which is updated by hardware if one of the following conditions occurs: - after each break detection, it is loaded with ?ffh?. - if a timeout occurs on t header , it is loaded with 00h. - after every successful lin header reception (at the same time than the setting of lhdf bit), it is loaded with a value (lhl) which gives access to the number of bit times of the lin header length (t header ). the coding of this value is explained below: lhl coding: t header_max = 57 lhl(7:2) represents the mantissa of (57 - t head - er ) lhl(1:0) represents the fraction (57 - t header ) example of lhl coding: example 1: lhl = 33h = 001100 11b lhl(7:3) = 1100b = 12d lhl(1:0) = 11b = 3d this leads to: mantissa (57 - t header ) = 12d fraction (57 - t header ) = 3/4 = 0.75 therefore: (57 - t header ) = 12.75d and t header = 44.25d example 2: 57 - t header = 36.21d lhl(1:0) = rounded(4*0.21d) = 1d lhl(7:2) = mantissa (36.21d) = 36d = 24h therefore lhl(7:0) = 10010001 = 91h example 3: 57 - t header = 36.90d lhl(1:0) = rounded(4*0.90d) = 4d the carry must be propagated to the matissa : lhl(7:2) = mantissa (36.90d) + 1= 37d = therefore lhl(7:0) = 10110000= a0h 7 0 lhl7 lhl6 lhl5 lhl4 lhl3 lhl2 lhl1 lhl0 lhl[7:2] mantissa (57 - t header ) mantissa ( t header ) 0h 0 57 1h 1 56 ... ... ... 39h 56 1 3ah 57 0 3bh 58 never occurs ... ... ... 3eh 62 never occurs 3fh 63 initial value lhl[1:0] fraction (57 - t header ) 0h 0 1h 1/4 2h 1/2 3h 3/4 ST7LITE3 118/167 linsci ? serial communication interf ace (lin master/slave) (cont?d) table 20. linsci1 register map and reset values addr. (hex.) register name 7 6 5 4 3 2 1 0 40 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 41 scidr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 42 scibrr lpr (lin slave mode) reset value scp1 lpr7 0 scp0 lpr6 0 sct2 lpr5 0 sct1 lpr4 0 sct0 lpr3 0 scr2 lpr2 0 scr1 lpr1 0 scr0 lpr0 0 43 scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 44 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 45 scicr3 reset value np 0 line 0 lslv 0 lase 0 lhdm 0 lhie 0 lhdf 0 lsf 0 46 scierpr lhlr (lin slave mode) reset value erpr7 lhl7 0 erpr6 lhl6 0 erpr5 lhl5 0 erpr4 lhl4 0 erpr3 lhl3 0 erpr2 lhl2 0 erpr1 lhl1 0 erpr0 lhl0 0 47 scitpr lpfr (lin slave mode) reset value etpr7 ldum 0 etpr6 0 0 etpr5 0 0 etpr4 0 0 etpr3 lpfr3 0 etpr2 lpfr2 0 etpr1 lpfr1 0 etpr0 lpfr0 0 ST7LITE3 119/167 11.6 10-bit a/d converter (adc) 11.6.1 introduction the on-chip analog to digital converter (adc) pe - ripheral is a 10-bit, successive approximation con - verter with internal sample and hold circuitry. this peripheral has up to 7 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 7 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.6.2 main features 10-bit conversion up to 7 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 65 . 11.6.3 functional description 11.6.3.1 analog power supply v dda and v ssa are the high and low level refer - ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 65. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 0 slow 0 0 r adc c adc hold control f adc f cpu 0 1 1 0 div 2 div 4 slow bit ST7LITE3 120/167 10-bit a/d converter (adc) (cont?d) 11.6.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re - sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the a dcdrh register and 03h in the adcdrl register (with out overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad - cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.6.3.3 a/d conversion the analog input ports must be configured as in - put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl 3. read adcdrh. this clears eoc automati - cally. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automati - cally. 11.6.4 low power modes note: the a/d converter may be disabled by re - setting the adon bit. this feature allows reduced power consumption when no conversion is need - ed and between single shot conversions. 11.6.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. ST7LITE3 121/167 10-bit a/d converter (adc) (cont?d) 11.6.6 register description control/status register (adccsr) read / write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft - ware reading the adcdrh register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit de - scription. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4:3 = reserved. must be kept cleared. bit 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register high (adcdrh) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of analog converted value control and data register low (ad - cdrl) read / write reset value: 0000 0000 (00h) bit 7:5 = reserved. forced by hardware to 0. bit 4 = reserved. forced by hardware to 0. bit 3 = slow slow mode this bit is set and cleared by software. it is used together with the speed bi t to configure the adc clock speed as shown on the table below. bit 2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of analog converted value 7 0 eoc speed adon 0 0 ch2 ch1 ch0 channel pin* ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 ain5 1 0 1 ain6 1 1 0 7 0 d9 d8 d7 d6 d5 d4 d3 d2 7 0 0 0 0 0 slow 0 d1 d0 f adc slow speed f cpu /2 0 0 f cpu 0 1 f cpu /4 1 x ST7LITE3 122/167 table 21. adc register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0036h adcdrl reset value 0 0 0 0 0 0 0 0 slow 0 0 0 d1 0 d0 0 ST7LITE3 123/167 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi - vided in two sub-modes called long and short: ? long addressing mode is more powerful be - cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy - cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in - structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 22. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow - ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 ST7LITE3 124/167 st7 addressing modes (cont?d) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa - tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con - tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address - ing space. direct (long) the address is a word, thus allowing 64 kbyte ad - dressing space, but requires 2 bytes after the op - code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af - ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad - dressing space and requires 2 bytes after the op - code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point - er). the pointer address follows the opcode. the indi - rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations ST7LITE3 125/167 st7 addressing modes (cont?d) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un - signed addition of an index register value (x or y) with a pointer value located in memory. the point - er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 23. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad - dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac - tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera - tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative ST7LITE3 126/167 12.2 instruction groups the st 7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op - codes for an 8-bit cpu (256 opcodes), three differ - ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre - cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di - rect bit, or direct relative addressing mode to an instruction using the corre - sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc - tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the de - vice against unexpected behaviour, a system of il - legal opcode detection is implemented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, com - bined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid op - code forming an unauthorized combination does not generate a reset. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf ST7LITE3 127/167 instruction groups (cont?d) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > ST7LITE3 128/167 instruction groups (cont?d) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z ST7LITE3 129/167 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re - ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max - imum values are guaranteed in the worst condi - tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min - imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 66 . figure 66. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de - vice is described in figure 67 . figure 67. pin input voltage c l st7 pin v in st7 pin ST7LITE3 130/167 13.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi - mum ratings? may cause permanent damage to the device. this is a stress rating only and func - tional operation of the device under these condi - tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for exampl e, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7LITE3 132/167 operating conditions (cont?d) the rc oscillator and pll ch aracteristics are temper ature-dependent and are grou ped in two tables. 13.3.1.1 devices with ??6? order code suffix (tested for t a = -40 to +85c) @ v dd = 4.5 to 5.5v notes: 1. rccr0 is a factory- calibrated setting for 1000khz with 0.2 accuracy @ t a =25c, v dd =5v. see ?internal rc os - cillator adjustment? on page 22 2. min value is obtained for hot temperature and max value is obtained for cold temperature. 3. data based on characterization results, not tested in production 4. measurement made with rc calibrated at 1mhz. 5. guaranteed by design. 6. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy. 7. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11 on page 23 . symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a =25c,v dd =5v 1600 khz rccr = rccr0 1 ) ,t a =25c,v dd =5v 995 1000 1005 acc rc accuracy of internal rc oscillator with rccr=rccr0 1) t a =25c, v dd =4.5 to 5.5v -1 +1 % t a =-40 to +85c, v dd =4.5 to 5.5v -2 2) +5 2) % t a =0 to +85c, v dd =4.5 to 5.5v -2 +2 % i dd(rc) rc oscillator current con - sumption t a =25c,v dd =5v 600 3)4) a t su(rc) rc oscillator setup time t a =25c,v dd =5v 10 1) s f pll x8 pll input clock 1 3) mhz t lock pll lock time 7) 2 ms t stab pll stabilization time 7) 4 ms acc pll x8 pll accuracy f rc = 1mhz@t a =25c,v dd =4.5 to 5.5v 0.1 6) % f rc = 1mhz@t a =-40 to +85c,v dd =5v 0.1 6) % t w(jit) pll jitter period f rc = 1mhz 8 5) khz jit pll pll jitter ( ? f cpu /f cpu ) 1 5) % i dd(pll) pll current consumption t a =25c 550 3) a ST7LITE3 133/167 operating conditions (cont?d) figure 69. typical accura cy with rccr=rccr0 vs v dd = 4.5 to 5.5v and temperature figure 70. typical rccr0 vs v dd and temperature -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 4.5 5 5.5 vdd (v) accuracy (%) -45c 0c 25c 90c 110c 130c 0.9 0.95 1 1.05 1.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 vdd supply (v) frequency (mhz) -45c' 0c' 25c' 90c' 110c' 130c' ST7LITE3 134/167 operating conditions (cont?d) 13.3.1.2 devices with ??6? order code suffix (tested for t a = -40 to +85c) @ v dd = 3.0 to 3.6v notes: 1.rccr1 is a factory-calibrated setting for 1000khz with 0.2 accuracy @ t a =25c, v dd =3.3v. see ?internal rc oscillator adjustment? on page 22 . 2.data based on characterization re sults, not tested in production 3. measurement made with rc calibrated at 1mhz. 4. guaranteed by design. 5. averaged over a 4ms period. after t he locked bit is s et, a period of t stab is required to reach acc pll accuracy 6.after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11 on page 23 . symbol parameter conditions min typ max unit f rc internal rc oscillator fre - quency rccr = ff (reset value), t a =25c, v dd = 3.3v 1600 khz rccr=rccr1 1) ,t a =25c,v dd = 3.3v 995 1000 1005 acc rc accuracy of internal rc oscillator when calibrated with rccr=rccr1 1)2) t a =25c, v dd =3.0 to 3.6v -1 +1 % t a =-40 to +85c, v dd =3.0 to 3.6v -3 +3 t a =0 to +85c, v dd =3.0 to 3.6v -3 +3 i dd(rc) rc oscillator current con - sumption t a =25c,v dd =3.3v 500 2)3) a t su(rc) rc oscillator setup time t a =25c,v dd =3.3v 10 1) s f pll x4 pll input clock 1 2) mhz t lock pll lock time 6) 2 ms t stab pll stabilization time 6) 4 ms acc pll x4 pll accuracy f rc = 1mhz@t a =25c, v dd =2.7 to 3.3v 0.1 5) % f rc = 1mhz@t a =-40 to +85c, v dd = 3.3v 0.1 5) % t w(jit) pll jitter period f rc = 1mhz 8 4) khz jit pll pll jitter ( ? f cpu /f cpu ) 1 4) % i dd(pll) pll current consumption t a =25c 450 2) a ST7LITE3 135/167 operating conditions (cont?d) figure 71. typical accura cy with rccr=rccr1 vs v dd = 3-3.6v and temperature figure 72. typical rccr1 vs v dd and temperature -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 33.33.6 vdd (v) accuracy (%) -45c 0c 25c 90c 110c 130c 0.9 0.95 1 1.05 1.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 vdd supply (v) frequency (mhz) -45c' 0c' 25c' 90c' 110c' 130c' ST7LITE3 136/167 operating conditions (cont?d) figure 73. pll ? f cpu /f cpu versus time figure 74. pllx4 output vs clkin frequency note: f osc = f clkin /2*pll4 figure 75. pllx8 output vs clkin frequency note: f osc = f clkin /2*pll8 t w(jit) ? f cpu /f cpu t min max 0 t w(jit) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 11.522.53 external input clock frequency (mhz) output frequency (mhz) 3.3 3 2.7 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4 ST7LITE3 137/167 13.3.2 operating condi tions with low voltage detector (lvd) t a = -40 to 85c, unless otherwise specified notes: 1. not tested in production. 2. not tested in production. the v dd rise time rate condition is needed to in sure a correct device power-on and lvd reset. when the v dd slope is outside these values, the lvd may not ensure a proper reset of the mcu. 13.3.3 auxiliary voltage detector (avd) thresholds , t a = -40 to 85c, unless otherwise specified note: 1. not tested in production. 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplie d by an internal rc oscillator and pll (selectable by option byte). symbol parameter conditions min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 3.60 1) 3.05 1) 2.45 1) 4.15 3.45 2.85 4.60 3.90 3.20 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.40 2.90 2.30 3.95 3.30 2.70 4.35 1) 3.70 1) 3.00 1) v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 200 mv vt por v dd rise time rate 2) 20 1) 100000 1) s/v t g(vdd) filtered glitch delay on v dd not detected by the lvd 150 ns i dd(lvd ) lvd/avd current consumption 220 a symbol parameter conditions min typ max unit v it+ (avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 3.90 1) 3.45 1) 2.90 1) 4.45 3.90 3.30 4.85 4.30 3.65 v v it- (avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 3.85 3.35 2.75 4.40 3.85 3.15 4.80 1) 4.20 1) 3.50 1) v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 150 mv ? v it- voltage drop between avd flag set and lvd reset activation v dd fall 0.45 v symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage refer to operating range of v dd with t a, section 13.3.1 on page 131 2.7 5.5 v v dd(x4pll) x4 pll operating voltage 2.7 3.3 v dd(x8pll) x8 pll operating voltage 3.3 5.5 ST7LITE3 138/167 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera - ture range does not take into account the clock source current consumption. to get the total de - vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 supply current t a = -40 to +85c unless otherwise specified notes: 1. cpu running with memory access, all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driv en by external square wave, lvd disabled. 2. all i/o pins in input m ode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external square wave, lvd disabled. 3. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in in put mode with a static value at v dd or v ss (no load), all peripher als in reset state; clock input (clkin) dr iven by external square wave, lvd disabled. 5. all i/o pins in output m ode with a static value at v ss (no load), lvd disabl ed. data based on characterization results, tested in production at v dd max and f cpu max. 6. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 7. this consumption refers to the halt period only and not t he associated run period which is software dependent. figure 76. typical i dd in run vs. f cpu figure 77. typical i dd in slow vs. f cpu symbol parameter conditions typ max unit i dd supply current in run mode v dd =5.5v f cpu =8mhz 1) 6.0 9.0 ma f cpu =4mhz 2.6 5.6 f cpu =1mhz 0.8 2.5 supply current in wait mode f cpu =8mhz 2) 2.4 4.0 supply current in slow mode f cpu =250khz 3) 0.7 1.1 supply current in slow wait mode f cpu =250khz 4) 0.6 1.0 supply current in halt mode 5) -40c t a +85c 0.5 10 a supply current in awufh mode 6)7) t a = +25c 20 50 tb d 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 2.4 2.7 3.3 4 5 6 vdd (v) idd (ma) 8mhz 4mhz 1mhz tb d 0.00 200.00 400.00 600.00 800.00 1000.00 2.4 2.7 3.3 4 5 6 vdd (v) idd (a) 8mhz 4mhz 1mhz ST7LITE3 139/167 supply current characteristics (cont?d) figure 78. typical i dd in wait vs. f cpu figure 79. typical i dd in slow-wait vs. f cpu figure 80. typical i dd vs. temperature at v dd = 5v and f osc = 16mhz figure 81. typical i dd vs. temperature and v dd at f osc = 16mhz 13.4.2 on-chip peripherals 1. data based on a differential i dd measurement between reset configuration (timer stopped) and a timer running in pwm mode at f cpu =8mhz. 2. data based on a differential i dd measurement between reset configurat ion and a permanent spi master communica - tion (data sent equal to 55h). 3. data based on a differential i dd measurement between reset configur ation and continuous a/d conversions. 4. data based on a differential i dd measurement between linsci running at maximum speed configuration (500 kbaud, continuous transmission of aa +re enabl ed and linsci off. this measurement includes the pad toggling consump - tion. 0.0 0.5 1.0 1.5 2.0 2.5 2.42.73.3456 vdd (v) idd (ma) 8mhz 4mhz 1mhz 0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 2.4 2.7 3.3 4 5 6 vdd (v) idd (a) 8mhz 4mhz 1mhz 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 130 temperature (c) idd (ma) run wait slow slow wait 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 130 temperature (c) idd run (ma) 5 3.3 2.7 symbol parameter conditions typ unit i dd(at) 12-bit auto-reload timer supply current 1) f cpu =4mhz v dd = 3.0v 150 a f cpu =8mhz v dd = 5.0v 1000 i dd(spi) spi supply current 2) f cpu =4mhz v dd = 3.0v 50 f cpu =8mhz v dd = 5.0v 200 i dd(adc) adc supply current when converting 3) f adc =4mhz v dd = 3.0v 250 v dd = 5.0v 1100 i dd(linsci) linsci supply current when transmitting 4) f cpu =8mhz v dd = 5.0v 650 ST7LITE3 140/167 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 13.5.1 general timings notes: 1. guaranteed by design. not tested in production. 2. data based on typical application software. 3. time measured between interrupt ev ent and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to fin - ish the current inst ruction execution. symbol parameter 1) conditions min typ 2) max unit t c(inst) instruction cycle time f cpu =8mhz 2 3 12 t cpu 250 375 1500 ns t v(it) interrupt reaction time 3) t v(it) = ? t c(inst) + 10 f cpu =8mhz 10 22 t cpu 1.25 2.75 s ST7LITE3 141/167 13.6 memory characteristics t a = -40c to 85c, unless otherwise specified 13.6.1 ram and hardware registers 13.6.2 flash program memory 13.6.3 eeprom data memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg - isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. data based on characterization results, not tested in production. 6. guaranteed by design. not tested in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase refer to operating range of v dd with t a, section 13.3.1 on page 131 2.7 5.5 v t prog programming time for 1~32 bytes 2) t a =? 40 to +85c 5 10 ms programming time for 1.5 kbytes t a = +25c 0.24 0.48 s t ret data retention 4) t a = +55c 3) 20 years n rw write erase cycles t a = +25c 10k cycles i dd supply current read / write / erase modes f cpu = 8mhz, v dd = 5.5v 2.6 6) ma no read/no write mode 100 a power down mode / halt 0 0.1 a symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/erase refer to operating range of v dd with t a, section 13.3.1 on page 131 2.7 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +85c 5 10 ms t ret data retention 4) t a =+55c 3) 20 years n rw write erase cycles t a = +25c 300k cycles ST7LITE3 142/167 13.7 emc characteristics susceptibility tests are pe rformed on a sample ba - sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbanc e occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re - sumed. the test results are given in the table be - low based on the ems levels and classes defined in application note an1709. 13.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per - formed at component level with a typical applica - tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage - ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro - duced by manually forcing a low state on the re - set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap - plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre - vent unrecoverable errors occurring (see applica - tion note an1015). 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 3b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func - tional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 3b symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25c, so20 package, conforming to sae j 1752/3 0.1mhz to 30mhz 16 17 db v 30mhz to 130mhz 20 25 130mhz to 1ghz 15 16 sae emi level 3 3.5 - ST7LITE3 143/167 emc characteristics (cont?d) 13.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensit ivity. for more details, re - fer to the application note an1181. 13.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega - tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test con - forms to the jesd22-a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 13.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec - ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 4000 v symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a ST7LITE3 144/167 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using t he output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 82 ). data based on design simulation and/or technology characteristics, not tested in production. 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de - scribed in figure 83 ). 4. to generate an external interrupt, a mi nimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 82. two typical applications with unused i/o pin symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption 2) floating input mode 200 r pu weak pull-up equivalent resistor 3) v in = v ss v dd =5v t a 85c 50 100 170 k ? v dd =3v 200 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 1) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 1) 25 t w(it)in external interrupt pulse time 4) 1 t cpu 10k ? unused i/o port st7xxx 10k ? unused i/o port st7xxx v dd caution : during normal operation the iccclk pin m ust be pulled- up, internally or externa lly (external pull-up of 10k mandatory in this is to avoid entering icc mode unexpectedly during a reset. noisy environment). robustness and lower cost. note : i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc ST7LITE3 145/167 figure 83. typical i pu vs. v dd with v in =v ss l to be characterized 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) ipu(ua) ta=140c ta=95c ta=25c ta=-45c ST7LITE3 146/167 i/o port pin characteristics (cont?d) 13.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . 3. not tested in production, based on characterization results. symbol parameter conditions min typ max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 86 ) v dd =5v i io =+5ma t a 85c 0.65 1.0 v i io =+2ma t a 85c 0.25 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 89 ) i io =+20ma,t a 85c 1.05 1.3 i io =+8ma t a 85c 0.4 0.75 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 92 ) i io = -5ma, t a 85c v dd -1.5 4.30 i io = -2ma t a 85c v dd -0.8 4.70 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 85 ) v dd =4v i io =+2ma t a 85c 0.25 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 88 ) i io =+8ma t a 85c 0.35 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 91 ) i io = -2ma t a 85c 3.70 v ol 1)3) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 84 ) v dd =3v i io =+2ma t a 85c 0.30 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 87 ) i io =+8ma t a 85c 0.40 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 90 ) i io = -2ma t a 85c 2.60 ST7LITE3 147/167 figure 84. typical v ol at v dd =3v figure 85. typical v ol at v dd =4v figure 86. typical v ol at v dd =5v figure 87. typical v ol at v dd =3v (high-sink) figure 88. typical v ol at v dd =4v (high-sink) figure 89. typical v ol at v dd =5v (high-sink) figure 90. typical v dd -v oh at v dd =3.0v figure 91. typical v dd -v oh at v dd =4.0v tbd 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.01123456 lio (m a) vol (v) at vdd = 3v -45c 25c 90c 110c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01123456 lio (m a) vol (v) at vdd = 4v -45c 25c 90c 110c tbd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.01123456 lio (m a) vol (v) at vdd = 5v -45c 25c 90c 110c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 5 8 10 15 lio (m a) vol(v) at vdd = 3v (hs) -45c 25c 90c 110c tbd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 581015 lio (m a) vol(v) at vdd = 4v (hs) -45c 25c 90c 110c tbd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 5 8 10 15 lio (m a) vol (v) at vdd = 5v (hs) -45c 25c 90c 110c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -0.01-1-2-3-4 lio (m a) vdd - voh at vdd = 3 v -45c 25c 90c 110c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -0.01-1-2-3-4-5-6 lio (m a) vdd - voh at vdd = 4 v -45c 25c 90c 110c ST7LITE3 148/167 figure 92. typical v dd -v oh at v dd =5v figure 93. typical v ol vs. v dd (standard i/os) figure 94. typical v ol vs. v dd (high-sink i/os) figure 95. typical v dd -v oh vs. v dd tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -0.01-1-2-3-4-5-6 lio (m a) vdd - voh at vdd = 5 v -45c 25c 90c 110c t bd 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 345 vdd (v) vol (v) at llo = 2ma -45c 25c 90c 110 c tbd 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 345 v dd ( v ) vol (v) at llo = 5ma (hs) -45c 25c 90c 110c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 345 v dd ( v ) vol (v) at llo = 15ma (hs) -45c 25c 90c 110c tbd 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 345 v dd ( v ) vdd - voh (v) at llo = -5ma -45c 25c 90c 110c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 345 v dd ( v ) vdd - voh (v) at llo = -2ma -45c 25c 90c 110c ST7LITE3 149/167 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40c to 85c, unless otherwise specified notes: 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 on page 130 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resi stive transistor. spec ified for voltages on reset pin between v ilmax and v dd 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 1 v v ol output low level voltage 2) v dd =5v i io =+5ma t a 85c t a 85c 0.5 - 1.0 1.2 v i io =+2ma t a 85c t a 85c 0.45 - 0.7 0.9 r on pull-up equivalent resistor 3) 1) v dd =5v t a 85c 10 46 70 k ? v dd =3v 91 k ? t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time 4) 20 s t g(rstl)in filtered glitch duration 200 ns ST7LITE3 150/167 control pin characteristics (cont?d) figure 96. reset pin protection when lvd is enabled. 1)2)3)4) figure 97. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (i nternal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 149 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allo w the internal reset to be output in the reset pin, the user must en - sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 130 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to i ccclk and reset circuit have been applied (see caution in table 1 on page 6 and notes above) ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the pow er supply are key to avoid any start-up ma rginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? note 5: please refer to ?illegal opcode reset? on page 126 for more details on ill egal opcode reset conditions 0.01 f st72xxx pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode 5) 0.01 f 0.01 f v dd external reset circuit user v dd 4.7k ? required recommended for emc st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode 5) ST7LITE3 151/167 13.10 communication interface characteristics 13.10.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics ( ss , sck, mosi, miso). figure 98. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or charac terisation results, not tested in production. 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck = 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave f cpu =8mhz 0 f cpu /2 = 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su( ss ) ss setup time slave 120 ns t h( ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in ST7LITE3 152/167 communication interface characteristics (cont?d) figure 99. spi slave timing diagram with cpha=1 1) figure 100. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) ST7LITE3 153/167 13.11 10-bit adc characteristics subject to general operating condition for v dd , f osc , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide - lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (espec ially for resistance g(reater than10k ? ). data based on characterization results, not tested in production. 4. the stabilization time of the ad c onverter is masked by the first t load . the first conversion af ter the enable is then always valid. figure 101. typical a pplication with adc symbol parameter conditions min typ 1) max unit f adc adc clock frequency 0.5 4 mhz v ain conversion voltage range 2) v ssa v dda v r ain external input resistor 10 3) k ? c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion ST7LITE3 154/167 adc characteristics (cont?d) adc accuracy with 3v v dd 5.5v notes: 1) data based on characterization results over t he whole temperature range, monitored in production. figure 102. adc accura cy characteristics symbol parameter conditions typ max unit |e t | total unadjusted error f cpu =8mhz, f adc =4mhz 1) 1.5 4 lsb |e o | offset error 0.5 1.5 |e g | gain error 1 1.5 |e d | differential li nearity error 1.5 3 |e l | integral linearity error 1.5 3 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss ST7LITE3 155/167 14 package characteristics 14.1 package mechanical data figure 103. 20-pin plastic small outline package, 300-mil width figure 104. 20-pin plastic dual in-line package, 300-mil width dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 20 eh a a1 b e d c h x 45 l a dim. mm inches min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.16 26.92 0.980 1.030 1.060 d1 0.13 0.005 e 2.54 0.100 eb 10.92 0.430 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 20 e1 d d1 b e a a1 l a2 c eb 11 10 1 20 b2 ST7LITE3 156/167 14.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipati on determined by the user. 2. the average chip-junction temperatur e can be obtained from the formula t j = t a + p d x r thja . symbol ratings value unit r thja package thermal resistance (junction to ambient) tbd c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c ST7LITE3 157/167 14.3 soldering and glueability information recommended soldering information gi ven only as design guidelines. figure 105. recommended wave soldering profile (with 37% sn and 63% pb) figure 106. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages: heraeus: pd945, pd955 loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec ST7LITE3 158/167 15 device configuration each device is available for production in user pro - grammable versions (flash) as well as in factory coded versions (rom/fastrom). st7plite3 devices are factory advanced serv - ice technique rom (fastrom) versions: they are factory programmed flash devices. st7flite3 devices are shipped to customers with a default program memory content (ffh), while fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer us - ing the option bytes. 15.1 flash option bytes the two option bytes allow the hardware configu - ration of the microcontroller to be selected. option byte 0 opt7 = awuck auto wake up clock selection 0: 32-khz oscillator (vlp ) selected as awu clock . 1: awu rc oscillator selected as awu clock. note: if this bit is reset, internal rc oscillator must be selected (option osc=0). opt6:4 = oscrange[2:0] oscillator range when the internal rc osc illator is not selected (option osc=1), these option bits select the range of the resonator oscillator current source or the ex - ternal clock source. note: oscrange[2:0] has no effect when awuck option is set to 0. in this case, the vlp os - cillator range is automatically selected as awu clock. opt 3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 ac - cording to the following table. opt1 = fmp_r read-out protection readout protection, when selected provides a pro - tection against program memory content extrac - tion and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5 on page 13 for more de - tails 0: read-out protection off 1: read-out protection on opt 0 = fmp_w flash write protection this option indicates if the flash program mem - ory is write protected. warning: when this option is selected, the pro - gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program - ming tool). the default content of the flash is fixed to ffh. oscrange 2 1 0 typ. frequency range with resonator lp 1~2mhz 0 0 0 mp 2~4mhz 0 0 1 ms 4~8mhz 0 1 0 hs 8~16mhz 0 1 1 vlp 32.768khz 1 0 0 external clock on osc1 1 0 1 reserved 1 1 0 external clock on pb4 1 1 1 sector 0 size sec1 sec0 0.5k 0 0 1k 0 1 2 1 0 4k 1 1 ST7LITE3 159/167 option bytes (cont?d) option byte 1 opt 7 = pllx4x8 pll factor selection . 0: pllx4 1: pllx8 opt 6 = plloff pll disable this option bit enables or disables the pll. 0: pll enabled 1: pll disabled (bypassed) opt 5 = reserved. must always be set to 1. opt 4 = osc rc oscillator selection this option bit enables to select the internal rc oscillator. 0: rc oscillator on 1: rc oscillator off opt 3:2 = lvd[1:0] low voltage selection these option bits enable the voltage detection block (lvd and avd) with a selected threshold to the lvd and avd. opt 1 = wdgsw hardware or so ftware watch - dog 0: hardware (watch dog always enabled) 1: software (watchdog to be enabled by software) opt 0 = wdg halt watchdog reset on halt 0: no reset generation when entering halt mode 1: reset generation when entering halt mode option byte 0 7 0 option byte 1 7 0 awu ck oscrange 2:0 sec1 sec0 fmpr fmpw pll x4x8 pll off res. osc lvd 1:0 wdg sw wdg halt default value 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 configuration vd1 vd0 lvd off 1 1 highest voltage threshold 1 0 medium voltage threshold 0 1 lowest voltage threshold 0 0 ST7LITE3 160/167 15.2 device ordering informat ion and transfer of customer code customer code is made up of the fastrom con - tents and the list of the selected options (if any). the fastrom contents are to be sent on dis - kette, or by electronic means, with the s19 hexa - decimal file generated by the development tool. all unused bytes must be set to ffh. the selected op - tions are communicated to stmicroelectronics us - ing the correctly completed option list append - ed on page 161 . refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con - tractual points. table 24. supported part numbers part number program memory (bytes) data eeprom (bytes) ram (bytes) internal rc temp. range package st7flite30f2b6 8k flash - 384 - -40c +85c dip20 st7flite30f2m6 - - so20 st7flite35f2b6 - yes dip20 st7flite35f2m6 - yes so20 st7flite39f2b6 256 yes dip20 st7flite39f2m6 256 yes so20 contact st sales office for product availability ST7LITE3 161/167 ST7LITE3 fastrom microcontroller option list (last update: july 2005) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference fastrom code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *fastrom code name is assigned by stmicroelectronics. fastrom code must be sent in .s19 format . .hex extension cannot be processed. device type/memory size/pac kage (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ " authorized characters are letters, di gits, '.', '-', '/ ' and spaces only. maximum character count: pdip20/so20 (8 char. max) : _ _ _ _ _ _ _ _ awuck selection [ ] 32-khz oscillator [ ] awu rc oscillator clock source selection: [ ] resonator: [ ] vlp: very low power resonator (32 to 100 khz) [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] external clock [ ] on pb4 [ ] on osc1 [ ] internal rc oscillator sector 0 size: [ ] 0.5k [ ] 1k [ ] 2k [ ] 4k readout protection: [ ] disabled [ ] enabled flash write protection [ ] disabled [ ] enabled pll [ ] disabled [ ] pllx4 [ ] pllx8 lvd reset [ ] disabled [ ] highest threshold [ ] medium threshold [ ] lowest threshold watchdog selection: [ ] software ac tivation [ ] hard ware activation watchdog reset on halt: [ ] disabled [ ] enabled comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the applic ation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . important note: not all configurations are available. see section 15.1 on page 158 for authorized option byte combinations. please download the latest versi on of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list --------------------------------- fastrom device: --------------------------------- | | | | ----------------------------------------- 8k fastrom ----------------------------------------- pdip20: || [ ] so20: || [ ] -------------------------------------------------------------------------- packaged product (do not specify for dip package) -------------------------------------------------------------------------- - | | [ ] tape & reel [ ] tube | ST7LITE3 162/167 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro - controller family. full details of tools available for the st7 from third party manufacturers can be ob - tained from the stmicroelectronics internet site: http//www.st.com. tools from these manufacturers include c compli - ers, evaluation tools, in-circuit debuggers, emula - tors and programmers. in-circuit debugging tools two types of debuggers are available for the ST7LITE3 family: st7flite-sk/rais low-cost in-circuit debugging/programming tool from raisonance. stxf-indart/usb low-cost in-circuit debugging tool from softec microsytem. emulators two types of emulators are available from st for the ST7LITE3 family: st7 dvp3 entry-level emulator offers a flexible and modular debugging and programming solution. st7 emu3 high-end emulator is delivered with everything (probes, teb, adapters etc.) needed to start emulating the ST7LITE3 . to configure it to emulate other st7 subfamily devices, the active probe for the st7emu3 can be changed and the st7emu3 probe is designed for easy interchange of tebs (target emulation board). see table 25 . flash programming tools st7-stick st7 in-circuit communication kit, a complete software/hardware package for programming st7 flash devices. it connects to a host pc parallel port and to the target board or socket board via st7 icc connector. icc socket boards provide an easy to use and flexible means of programming st7 flash devices. they can be connected to any tool that supports the st7 icc interface, such as st7 emu3, st7-dvp3, indart , rlink, st7-stick, or many third-party development tools. table 25. stmicroelectronics development tools note 1: add suffix /eu, /uk, /us for the power supply of your region. supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe & t.e.b. st7flite30 st7flite35 st7flite39 st7mdt10-dvp3 st7mdt10-20/dvp st7mdt10-emu3 st7mdt10-teb st7sb10-123 1) ST7LITE3 163/167 16 known limitations 16.1 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: ? the interrupt request is cleared (flag reset or in - terrupt mask) within its own interrupt routine ? the interrupt request is cleared (flag reset or in - terrupt mask) within any interrupt routine ? the interrupt request is cleared (flag reset or in - terrupt mask) in any part of the code while this in - terrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se - quence: perform sim and rim operation before and after resetting an active interrupt request ex: sim reset flag or interrupt mask rim 16.2 linsci limitations 16.2.1 linsci wrong break duration sci mode a single break character is sent by setting and re - setting the sbk bit in the scicr2 register. in some cases, the break ch aracter may have a long - er duration than expected: - 20 bits instead of 10 bits if m=0 - 22 bits instead of 11 bits if m=1. in the same way, as long as the sbk bit is set, break characters are sent to the tdo pin. this may lead to generate one break more than expect - ed. occurrence the occurrence of the problem is random and pro - portional to the baudrate. with a transmit frequen - cy of 19200 baud (f cpu =8mhz and sci - brr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with the communication protocol in the application, soft - ware can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the applica - tion is not doing anything between the idle and the ST7LITE3 164/167 important notes (cont?d) break. this can be ensured by temporarily disa - bling interrupts. the exact sequence is: - disable interrupts - reset and set te (idle request) - set and reset sbk (break request) - re-enable interrupts lin mode if the line bit in the scicr3 is set and the m bit in the scicr1 register is reset, the linsci is in lin master mode. a single break character is sent by setting and rese tting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: - 24 bits instead of 13 bits occurrence the occurrence of the problem is random and pro - portional to the baudrate. with a transmit frequen - cy of 19200 baud (fcpu=8mhz and sci - brr=0xc9), the wrong break duration occurrence is around 1%. analysis the lin protocol specifies a minimum of 13 bits for the break duration, but there is no maximum value. nevertheless, the maximum length of the header is specified as (14+10+10+ 1)x1.4=49 bits. this is composed of: - the synch break field (14 bits), - the synch field (10 bits), - the identifier field (10 bits). every lin frame starts with a break character. adding an idle character increases the length of each header by 10 bits. when the problem occurs, the header length is increased by 11 bits and be - comes ((14+11)+10+10+1)=45 bits. to conclude, the problem is not always critical for lin communication if the software keeps the time between the sync field and the id smaller than 4 bits, i.e. 208us at 19200 baud. the workaround is the same as for sci mode but considering the low probab ility of occurrence (1%), it may be better to keep the break generation se - quence as it is. 16.2.2 header time-out does not prevent wake- up from mute mode normally, when linsci is configured in lin slave mode, if a header time-out occurs during a lin header reception (i.e. header length > 57 bits), the lin header error bit (lhe) is set, an interrupt oc - curs to inform the application but the linsci should stay in mute mode, waiting for the next header reception. problem description the linsci sampling period is tbit / 16. if a lin header time-out occurs between the 9th and the 15th sample of the identifier field stop bit (refer to figure 107 ), the linsci wakes up from mute mode. nevertheless, lhe is set and lin header detection flag (lhdf) is kept cleared. in addition, if lhe is reset by software before this 15th sample (by accessing the scisr register and reading the scidr register in the linsci interrupt routine), the linsci will generate anoth er linsci interrupt (due to the rdrf flag setting). figure 107. header reception event sequence lin synch lin synch identifier field field break t header active mode is set rdrf flag is set critical window id field stop bit (rwu is cleared) ST7LITE3 165/167 important notes (cont?d) impact on application software may execute the interrupt routine twice after header reception. moreover, in reception mode, as the receiver is no longer in mute mode, an interrupt will be generat - ed on each data byte reception. workaround the problem can be detected in the linsci inter - rupt routine. in case of timeout error (lhe is set and lhlr is loaded with 00h), the software can check the rwu bit in the scicr2 register. if rwu is cleared, it can be set by software. refer to fig - ure 108 . workaround is shown in bold characters. figure 108 . linsci interrupt routine @interrupt void linsci_it ( void ) /* linsci interrupt routine */ { /* clear flags */ scisr_buffer = scisr; scidr_buffer = scidr; if ( scisr_buffer & lhe )/* header error ? */ { if (!lhlr)/* header time-out? */ { if ( !(scicr2 & rwu) )/* active mode ? */ { _asm("sim");/* disable interrupts */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ _asm("rim");/* enable interrupts */ } } } } example using cosmic compiler syntax ST7LITE3 166/167 17 revision history date revision main changes 29-jul-05 4.0 first release on internet main changes (versus rev. 3.0): ? changed status of the document: datas heet instead of preliminary data ? changed number of timers on first page ? changed i dd(pll) and added note 4 to i dd(rc) in section 13.3.1.1 on page 132 and section 13.3.1.2 on page 134 ? removed section 13.3.2 (general oper ating conditions: suffix 3 devices) ? removed note 7 to section 13.6 on page 141 ? added v hys typical value to section 13.8.1 on page 144 and changed r pu typ value at v dd =3v ? added figure 69 on page 133 and figure 71 on page 135 ? added figure 70 on page 133 and figure 72 on page 135 ? added figure 73 , figure 74 and figure 75 on page 136 ? added note to figure 82 on page 144 ? added figure 83 on page 145 ? removed min and max values for v dd =3v and v dd =4v in section 13.8.2 on page 146 ? added r on typ value for v dd =3v in section 13.9.1 on page 149 and changed r on typ value for vdd=5v ? in section 13.11 on page 153 , added f adc min value, c adc and r ain values and removed i adc row ? changed section 15.3 on page 162 (removed note 1 to dvp3 and added in-circuit debug - ging tools) ST7LITE3 167/167 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - 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