publication# 21046 rev: a amendment/ 0 issue date: september 1996 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. making the most of the am186 ? er or am188 ? er microcontroller application note by melanie typaldos the amd ? am186 ? er and am188 ? er microcontrollers provide a major advancement in systems integration by bringing 32 kbyte of zero-wait-state ram onto the microcontroller. this incorporation of system-level ram onto the controller brings the advantages of reduced system cost, reduced power consumption, and smaller board size. with these advantages comes the challenge of utilizing this new resource to the greatest advantage in a given system. this application note describes how to use an internal chip select to access the internal ram of the am186er controller, and the de- bugging support provided by the processor for code or data located in this internal ram. all refer- ences in the document to the am186er apply equally to the am188er microcontroller. overview of am186er controller the 80186 microcontroller and its derivative parts con- tinue to be popular in embedded applications. amd has been a leader in the continuing development of the 186 with its am186 product line. amds most recent addition to the am186 family is the am186er micro- controller. the am186er microcontroller is a direct de- scendent of the popular am186em microcontroller, which was introduced in 1994. like the am186em microcontroller, the am186er mi- crocontroller provides 12 external chip-selects signals, a demultiplexed address bus, 3 timers and a watchdog timer, an asynchronous serial port, a synchronous se- rial interface, 5 external interrupt pins, 2 dma chan- nels, and 32 programmable input/output pins. in addition, the am186er provides 32 kbyte of internal, zero-wait-state ram, and a 4x clock mode. the am186er microcontroller is available in speeds up to 40 mhz in a 100-pin pqfp or tqfp package at 3 v with 5-v tolerant i/o. memory and chip select configurations the internal ram of the am186er microcontroller is accessed via an internal chip select. the function of this chip select is similar to the function of traditional 186 external chip selects. the use and configuration of the internal ram must take place within the context of the total system. the final system configuration will be heavily dependent on the need for external memory or memory-mapped peripherals, and on the allocation of the external chip selects to access these devices. the chip select signals available on the am186er micro- controller are summarized in table 1. table 1. am186er microcontroller chip select signals chip select name normal usage number of signals size (total for all associated signals) wait states external ready comments ucs (upper chip select) rom boot code 1 64 kbyte to 512 kbyte from 0 to 3 configurable to use or ignore external ready ending address is always at the top of memory (0xfffff) lcs (lower chip select) ram data 1 64 kbyte to 512 kbyte from 0 to 3 configurable to use or ignore external ready starting address is always at the bottom of memory (0x00000) mcs (middle chip selects) slow memory or memory mapped peripherals 4 8 kbyte to 512 kbyte from 0 to 3 configurable to use or ignore external ready base address must be multiple of total block size pcs (peripheral chip selects) i/o or memory mapped peripherals 6 1536 byte pcs 3-0 from 0 to 15 pcs 6-5 from 0 to 3 configurable to use or ignore external ready may be mapped to memory or i/o space; pcs 4 is not available ics internal ram 1 32 kbyte 0 does not use external ready base address must be multiple of 32 kbyte; not visible externally
making the most of the am186 ? er or am188 ? er microcontroller 2 figure i shows the most common type of memory con- figuration used with the am186er microcontroller. in this configuration, the ucs chip select is used to ad- dress flash or rom memory which contains the ap- plication code. the internal ram is placed at address 0x00000 and is used for data storage, including the in- terrupt vector table and the stack. the peripheral con- trol block, pcb, is a 256-byte block through which the on-chip peripheral registers are accessed. the pcb can be memory mapped or i/o mapped. in figure 1, the pcb is memory-mapped to the memory addresses directly above the internal memory. other peripheral devices are also memory-mapped using the peripheral chip select (pcs ) signals. figure 1. 32 kbyte ram configuration figure 2 shows a system where 64 kbyte of ram is re- quired. the fast internal memory is configured at ad- dress 0x00000 to support the interrupt vector table and probably the stack segment. less frequently used data can be accessed via a slower ram device enabled via the middle chip select (mcs ) signals. this configura- tion also demonstrates the ability to map the pcb and off-chip peripherals to i/o space. both configurations allow the data segment registers (ds and es) to be set to address all data without need- ing to be reprogrammed. if set to 0, ds and es can ac- cess from 0x00000 to 0x0ffff without modification. this allows quick access to all system data. in figure 2, ds and es cannot be used to access either the pcb or the i/o-mapped peripherals. these would need to ac- cessed using the am186er i/o instructions in and out and their variants, and the dx,ax register pair. figure 2. 64 kbyte ram configuration setting up the internal chip select in general, the internal chip select used to access the 32 kbyte of internal ram on the am186er microcon- troller behaves much the same way as the traditional external chip selects. the internal ram can be config- ured to be addressed anywhere within the am186er microcontrollers 1 mbyte address space, but the base address must be a multiple of the 32-kbyte block size. since the memory being addressed is always guaran- teed to respond with zero-wait-states, no wait-state or ready programming is required or provided. figure 3 shows the internal memory chip select (imcs) regis- ter and its fields. the ba , or base address , field specifies bits 19-15 of the 20-bit base address of the internal memory space. bits 14-0 of the 20-bit base address are zero. this al- lows the ics space to be moved to any 32 kbyte boundary throughout memory. a typical location for the ics is at address 0x00000 so that it can be used to hold the interrupt vector table. overlap of the ics with other chip selects is only sup- ported if the overlapped chip select is programmed to zero wait-states and to ignore external ready. overlap- ping the ics with any chip select that does not meet these requirements results in unpredictable behavior of the part. if the ics is overlapped with an external chip select, both chip-select signals will assert for cycles where they overlap. since the write signals provided during an ics cycle are exactly the same as those for an external cycle, the write will occur to both devices. on a read, only the data provided by the internal mem- ory will be used by the processor. figure 3. the imcs register 256k flash ucs no memory memory-mapped peripherals pcs pcb 32k internal ram ics 0x00000 0x08000 0x09000 0xc0000 0xfffff 0x09800 256k flash ucs no memory 32k internal ram ics 0x00000 0x08000 0x10000 0xc0000 0xfffff 32k 2-wait state ram mcs memory space i/o space pcb available space for pcs i/o-mapped peripherals 0x00100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba sr re reserved
3 making the most of the am186 ? er or am188 ? er microcontroller the sr , or show reads , field can be used for debug- ging a system using the internal memory. when show reads is enabled, the sr bit is set, and the processor drives the data bus with the data read from the internal memory on read cycles. in this way, an emulator or logic analyzer can monitor the data read from the inter- nal memory. if the ics is overlapped with another chip select, as dis- cussed above, the external device must not drive data on the bus during read cycles if show reads is en- abled. this would result in multiple devices driving the data bus. for this reason it is impractical to use the show read function with overlapping chip selects. the re , or ram enable , field actually enables the in- ternal memory and the associated chip select. when re is set, the ics signal is enabled. unlike the external chip selects, the ics can be both enabled and disabled during the course of execution. this may be useful in the debug stage of the design. debug support the am186er microcontroller provides support for de- bugging code or data located in the internal ram. writes to the internal ram appear as normal am186er write cycles which can be viewed using a logic analyzer. the address being written to appears on the multiplexed address/data (ad) bus during the t1 clock cycle and on the non-multiplexed address (a) bus during the second half of t4 through the first half of the following t4 cycle. the data being written into the inter- nal ram will be present on the ad bus during t2 through t4. this behavior is identical to writes to exter- nal zero-wait-state memory, although no external chip select will assert for internal memory writes. a typical write cycle is shown in figure 4. reads from the internal ram appear as normal am186er read cycles. no external chip select will as- sert for internal memory reads. however, with external memory reads, the external device drives the data onto the ad bus late in t3. for the internal ram, no external device is placing the data on the bus for the read. the processor drives the data on the internal bus but, in normal operation, the data is not visible externally. this reduces power consumption and noise generation. however, the internal chip select can be configured to drive the data read from the internal ram out on the address/data bus late during t3 via the show reads feature discussed above. a normal external memory read cycle is shown in figure 5. figure 6 shows a read cycle to the internal memory, and figure 7 shows a read cycle to internal memory with the show reads function enabled. the show reads function allows the use of a logic an- alyzer for debugging, allowing the viewing of data read from the ics address range. it also allows emulators to monitor the values written to and read from the internal memory. the show reads mode can be entered via software by setting the show read bit in the imcs reg- ister. some emulators may force the processor into show read mode by holding the sren pin low during reset. further support for emulators is provided through the imdis pin. when this pin is held low during reset, the internal memory is disabled regardless of the setting of the ram enable (re) bit in the imcs register. this al- lows the use of emulator overlay memory for the pro- grammed ics accesses without any modification to existing code. an additional debug mode is available on the am186er microcontroller by overlapping the ics ad- dress range with that of a programmed chip select, for example lcs . this allows ics accesses to be signaled externally by the lcs chip select. when used with the show reads feature, this allows a logic analyzer to show all data transfers to and from the internal mem- ory. when using this mode, there must be no external memory device attached to the overlapped chip select, or bus contention can result. in addition, the over- lapped chip select must be programmed to zero wait- states and to ignore external ready. summary the am186 family continues to expand, providing new functionality and solutions relevant to the changing na- ture of embedded applications. the am186er micro- controller builds on the popularity of the am186em microcontroller by providing the same peripherals and the same pin-out as that part but with the addition of 32 kbyte of zero-wait-state internal ram. the am186er microcontroller allows many systems to function without any external ram. due to the highly in- tegrated nature of the device, it is possible to have a complete system consisting of nothing more than an am186er microcontroller and a single external flash device.
4 making the most of the am186 ? er or am188 ? er microcontroller figure 4. ics write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w address data ad15Cad0 1 , ad7Cad0 2 wr address a19Ca0 ale ao15Cao8 2 address notes: 1 C am186er microcontroller only 2 C am188er microcontroller only 3 C external chip selects will only assert for internal ram accesses if they are programmed to overlap with the ics address space. lcs , ucs , mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 (see note 3)
5 making the most of the am186 ? er or am188 ? er microcontroller figure 5. external memory read cycle waveforms clkouta t 1 t 2 t 3 t 4 t w ad15Cad0 1 , ad7Cad0 2 rd address a19Ca0 ale ao15Cao8 2 notes: 1 C am186er microcontroller only 2C am188er microcontroller only data address address lcs , ucs mcs 1Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0
making the most of the am186 ? er or am188 ? er microcontroller 6 figure 6. internal memory read cycle waveforms clkouta t 1 t 2 t 3 t 4 ad15Cad0 rd address a19Ca0 ale address lcs, ucs mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 (see note 1) notes: 1 C external chip selects will only assert for internal ram accesses if they are programmed to overlap with the ics address space.
7 making the most of the am186 ? er or am188 ? er microcontroller figure 7. internal ram show read cycle waveforms trademarks copyright ? 1996 advanced micro devices, inc. all rights reserved. amd and the amd logo are registered trademarks of advanced micro devices, inc. the combination of amd and the amd logo, am186, and am188 are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. clkouta t 1 t 2 t 3 t 4 ad15Cad0 rd address a19Ca0 ale data address lcs, ucs mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 (see note 1) notes: 1 C external chip selects will only assert for internal ram accesses if they are programmed to overlap with the ics address space.
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