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2.7 v to 5.5 v, <100 a, 8/10/12 bit d/a with i 2 c compatible interface, tiny sc70 package preliminary technical data ad5602/12/22 rev. prb 18-feb-05 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2005 analog devices, inc. all rights reserved. features single 8/10/12-bit dac, 2 lsb inl 6-lead sc70 package micropower operation: max 100 a @ 5 v power-down to <100 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on-reset to 0 v with brownout detection 3 power-down functions i 2 c r compatible serial interface supports: standard (100khz), fast (400khz) and high-speed (3.4mhz) modes on-chip output buffer amplifier, rail-to-rail operation applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram power-on reset dac register 8/10/12-bit dac input control logic power-down control logic ad5602/12/22 v dd gnd ref(+) resistor network v out scl sda output buffer addr figure 1 related devices part no. description ad5601/11/21 2.7v to 5.5 v, <100a, 8/10/12 bit nano dac tm d/a with spi interface in a tiny sc70 package general description the ad5602/12/22, a member of the nano dac tm d/a family is a single, 8/10/12-bit buffered voltage out dac that operates from a single +2.7 v to +5.5 v supply consuming <100 a at 5 v, and comes in a tiny sc70 package. its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the ad5602/12/22 utilizes a 2-wire i 2 c compatible serial interface that operates in standard (100 khz), fast (400 khz) and high-speed (3.4 mhz) modes. the reference for ad5602/12/22 is derived from the power supply inputs and thus gives the widest dynamic output range. the part incorporates a power-on-reset circuit that ensures the dac output powers up to 0 v and remains there until a valid write takes place to the device. the part contains a power-down feature that reduces the current consumption of the device to <100 na at 3 v and provides software selectable output loads while in power-down mode. the part is put into power-down mode over the serial interface. the low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment. the power consumption is 0.5 mw at 5 v. product highlights 1. available in 6-lead sc70. 2. max 100a power consumption, single-supply operation. this part operates from a single 2.7 v to 5.5 v supply and typically consumes 0.2 mw at 3 v and 0.5 mw at 5 v, making it ideal for battery-powered applications. 3. the on-chip output buffer amplifier allows the output of the dac to swing rail-to-rail with a typical slew rate of 0.5 v/s. 4. reference derived from the power supply. 5. standard, fast and high-speed mode i 2 c interface. 6. designed for very low power consumption. 7. power-down capability. when powered down, the dac typically consumes <100 na at 3 v. 8. brown out detection on power-on-reset. .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 2 of 22 table of contents ad5602/12/22?specifications ...................................................... 3 i 2 c timing specifications ................................................................ 5 absolute maximum ratings............................................................ 7 ordering guide.............................................................................. 7 esd caution.................................................................................. 7 pin configuration and function description .............................. 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 general description ....................................................................... 13 d/a section................................................................................. 13 resistor string ............................................................................. 13 output amplifier........................................................................ 13 serial interface ............................................................................ 14 input register.............................................................................. 14 power-on-reset ......................................................................... 15 power-down modes .................................................................. 15 write operation ............................................................... 15 read operation ..................................................................... 17 placing the ad5602/12/22 -1 into high-speed mode........... 19 applications..................................................................................... 20 choosing a reference as power supply for ad5602/12/22.. 20 bipolar operation using the ad5602/12/22.......................... 20 power supply bypassing and grounding................................ 21 outline dimensions ....................................................................... 22 revision history revision prb 18-feb-05 : preliminary version .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 3 of 22 ad5602/12/22?specifications table 1. v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max unless otherwise noted a,,, version 1 parameter min typ ma unit test conditions/comments static performance resolution ad5602 ad5612 AD5622 10 12 its relative accuracy 2 ad5602 ad5612 AD5622 1 0.5 4 2 6 ls ls ls ls ls , versions , versions a version , versions a, versions differential nonlinearity 2 1 ls guaranteed monotonic by design. zero code error td ls all 0s loaded to dac register. full-scale error td ls all 1s loaded to dac register. gain error td of fsr zero code error drift td v/c gain temperature coefficient td ppm of fsr/c output characteristics 3 output voltage range 0 v dd v output voltage settling time 1 s code to slew rate 0.5 v/s capacitive load stability 470 pf r l = ? 1000 pf rl = 2 k output noise spectral density 120 nv/hz dac code=td , 10 khz noise td dac code=td 0.1-10hz andwidth digital-to-analog glitch impulse 10 nv -s 1 ls change around major carry. digital feedthrough 0.5 nv-s dc output impedance 1 ? .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 4 of 22 a,b,w,y version 1 parameter min typ max unit test conditions/comments i dd (all power-down modes) v dd = +4.5 v to +5.5 v 0.2 1 a v ih = v dd and v il = gnd v dd = +2.7 v to +3.6 v 0.05 1 a v ih = v dd and v il = gnd power efficiency i out /i dd tbd % i load = 2 ma. v dd = +5 v .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 5 of 22 i 2 c timing specifications 4 table 2. v dd = 2.7 v to 5.5 v; all specifications t min to t max , f scl = 3.4 mhz unless otherwise noted. see figure 2. parameter conditions limit at t min , t max unit description min max f scl 5 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf 100 400 3.4 1.7 hz hz mhz mhz serial clock freuency t 1 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf 4 0.6 60 120 s s s s t high , scl high time t 2 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf 4.7 1.3 160 320 s s ns ns t lo , scl low time t 3 standard mode fast mode high-speed mode 250 100 10 ns ns ns t su;dat , data setup time t 4 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf 0 0 0 0 3.45 0. 70 150 s s ns ns t hd;dat , data hold time t 5 standard mode fast mode high-speed mode 4.7 0.6 160 s s ns t su;sta , set-up time for a repeated start condition t 6 standard mode fast mode high-speed mode 4 0.6 160 s s ns t hd;sta , hold time repeated start condition t 7 standard mode fast mode 4.7 1.3 s s t uf , us free time etween a stop and a start condition t standard mode fast mode high-speed mode 4 0.6 160 s s ns t su;sto , set-up time for a stop condition t standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf - 200.1c 10 20 1000 300 0 160 ns ns ns ns t rda , rise time of sda signal t 10 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf - 200.1c 10 20 300 300 0 160 ns ns ns ns t fda , fall time of sda signal t 11 standard mode fast mode high-speed mode, c = 100pf high-speed mode, c = 400pf - 200.1c 10 20 1000 300 40 0 ns ns ns ns t rcl , rise time of scl signal 4 see figure 2. hs-mode timing specificatio n applies to the ad5602/12/22-1 only. standard and fast-mode timing specifications ap ply to both the ad5602/12/22-1 and ad5602/12/22-2. c refers to the capacitance load on the bus line. 5 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on emc behavior of the part. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 6 of 22 parameter conditions limit at tmin, tmax unit description min max t 11a standard mode fast mode high-speed mode, c b = 100pf high-speed mode, c b = 400pf - 20+0.1c b 10 20 1000 300 80 160 ns ns ns ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit t 12 standard mode fast mode high-speed mode, c b = 100pf high-speed mode, c b = 400pf - 20+0.1c b 10 20 300 300 40 80 ns ns ns ns t fcl , fall time of scl signal t sp 6 fast mode high-speed mode 0 0 50 10 ns ns pulsewidth of spike suppressed p s s p t 6 t 4 t 1 t 3 t 5 t 8 t 2 t 11 t 12 t 6 scl sda t 7 t 9 t 10 s = start condition p = stop condition figure 2. two-wire serial interface timing diagram 6 input filtering on both the scl and sda inputs suppress noise spikes that are less than 50ns or 10ns for fast mode or high-spe ed mode respectively specifications subject to change without notice. .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 7 of 22 absolute maximum ratings table 3. t a = 25c, unless otherwise noted parameter rating v dd to gnd 0.3 v to 7.0 v digital input voltage to gnd 0.3 v to v dd 0.3 v v out to gnd 0.3 v to v dd 0.3 v operating temperature range etended automotive , ve rsion 40c to 125c etended industrial a, version -40c to 5c storage temperature range 65c to 160c maimum unction temperature 150c sc70 package a thermal impedance 332c/ c thermal impedance 120c/ lead temperature, soldering vapor phase 60 sec 215c infrared 15 sec 220c esd 2.0 kv ordering guide stresses above those listed under absolute maimum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. eposure to absolute maimum rating conditions for etended periods may affect device reliability. model inl i 2 c interface modes supported temperature range power supply range package option package description randing ad5602sz-1 1 ls ma standard , fast and high speed mo des -40c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5 ad5602sz-2 1 ls ma standard, fast modes -40 c to 5c 2.7 v to 5.5v s-6 6-lead sc-70 d5x ad5602sz-2 1 ls ma standard , fast modes -40 c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5 ad5612sz-1 0.5 ls ma standard , fa st and high speed modes -40c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5t ad5612sz-2 0.5 ls ma standard, fast modes -40 c to 5c 2.7 v to 5.5v s-6 6-lead sc-70 d5u ad5612asz-2 4 ls ma standard , fast modes -40 c to 5c 2.7 v to 5.5v s-6 6-lead sc-70 d5v ad5612sz-2 0.5 ls ma standard, fast modes -40 c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5s AD5622sz-1 2 ls ma standard , fast and high speed mo des -40c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5m AD5622sz-2 2 ls ma standard, fast modes -40 c to 5c 2.7 v to 5.5v s-6 6-lead sc-70 d5n AD5622sz-2 2 ls ma standard , fast modes -40 c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5p AD5622sz-1 6 ls ma standard , fast and high speed mo des -40c to 125c 2.7 v to 5.5v s-6 6-lead sc-70 d5 AD5622asz-2 6 ls ma standard, fast modes -40 c to 5c 2.7 v to 5.5v s-6 6-lead sc-70 d5r esd caution esd electrostatic discharge sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test euipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 8 of 22 pin configuration and function description top view (not to scale) v dd gnd ad5602/12/22 v ou t 1 2 3 6 5 4 a dd r scl sda figure 3. ad5602/12/22 sc70 (top view) table 4. pin function descriptions mnemonic function v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and v dd should be decoupled to gnd. v out analog output voltage from the dac. the output amplifier has rail-to-rail operation. addr tri-state address input. sets the two least significan t bits a1,a0 of the 7-bit slave address. see table 5. scl serial clock line. this is used in co njunction with the sda line to clock data into or out of the 16-bit input register. sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input register. it is a bidirectional open-drain data line that should be pu lled to the supply with an eternal pull-up resistor. gnd ground reference point for all circuitry on the part. .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 9 of 22 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity inl is a measure of the maimum deviation, in lss, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 2. differential nonlinearity differential nonlinearity dnl is the difference between the measured change and the ideal 1 ls change between any two adjacent codes. a specified differential nonlinearity of 1 ls maimum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 7. zero-code error zero-code error is a measure of the output error when zero code 0000he is loaded to the dac register. ideally the output should be 0 v. the zero-code error is always positive in the ad5602/12/22 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is epressed in mv. a plot of zero-code error vs. temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full-scale code ffff he is loaded to the dac register. ideally the output should be vdd 1 ls. full-scale error is epressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure 6. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal epressed as a percent of the full-scale range. total unadjusted error total unadjusted error tue is a measure of the output error taking all the various errors into account. a typical tue vs. code plot can be seen in figure 5. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is epressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is epressed in ppm of full-scale range/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is changed by 1 ls at the major carry transition 7fff he to 000 he. see figure 1. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 10 of 22 typical performance characteristics figure 4. typical inl plot figure 5. total unadjusted error plot.. figure 6. zero scale error and full scale error vs. temperature figure 7. typical dnl plot figure 8. inl and dnl vs supply figure 9. i dd histogram @ v dd = 3 v/5 v .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 11 of 22 figure 10. source and sink current capability figure 11. supply current vs. temperature figure 12. full scale settling time figure 13. supply current vs code. figure 14. supply current vs. supply voltage figure 15. half scale settling time .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 12 of 22 figure 16. power on reset to 0 v figure 17. digital to analog glitch impulse figure 18. output spectral density 100k bandwidth figure 19. exiting power-down figure 20. figure 21. 0.1 hz to 10 hz noise plot .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 13 of 22 general description d/a section the ad5602/12/22 dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 22 shows a block diagram of the dac architecture. v dd v out gnd resistor network ref (+) ref (?) [ output amplifier dac register 04611-a-022 figure 22. dac architecture since the input coding to the dac is straight binary, the ideal output voltage is given by; ? ? ? ? ? ? = n dd out d v v 2 where; d = decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 255 (ad5602), 0 to 1023 (ad5612) or 0 to 4095 (AD5622). and; n = bit resolution of the dac. resistor string the resistor string section is shown in figure 23. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier figure 23 resistor string structure output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 v to v dd . it is capable of driving a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 10. the slew rate is 0.5 v/s with a half- scale settling time of 8 s with the output unloaded. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 14 of 22 serial interface the ad5602/12/22 has a two-wire i 2 c compatible serial interface (refer to i 2 c-bus specification, version 2.1, january 2000, available from philips semiconductor). the ad5602/12/22 can be connected to an i 2 c bus as a slave device, under the control of a master device. see figure 2 for a timing diagram of a typical write sequence. the ad5602/12/22 supports standard (100khz), fast (400 khz) and high speed (3.4 mhz) data transfer modes. support is not provided for ten bit addressing and general call address. the ad5602/12/22 have a 7-bit slave address. the 5 msbs are 00011 and the two lsbs are determined by the state of the addr pin. the facility to make hardwired changes to addr allows the user to use up to three of these devices on one bus as outlined in table 5. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address. the slave whose address corre sponds to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have be en read or written, a stop condition is established. in write mode, the master will pull the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master wi ll then bring the sda line low before the 10th clock pulse and then high during the 10 th clock pulse to establish a stop condition. table. 5 device address selection addr a1 a0 gnd 1 1 v dd 0 0 nc 1 0 input register the input register is 16 bits wide. figure 23 illustrates the contents of the input register for each part. data is loaded into the device as a 16 bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 2. the 16 bit word consists of four control bits followed by , 10 or 12 bits of data depending on the device type. ms d15 is loaded first. the first two bits are reserved bits that must be set to zero, the net two are control bits that control the mode of operation of the device normal mode or any one of three power-down modes. see power down modes section for a complete description.the remaining bits are left-justified dac data bits, starting with the ms and ending with the ls. data its d15 ms d0 ls pd1 pd0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 0 0 figure 24a. ad5602 input register contents data its d15 ms d0 ls pd1 pd0 d d d7 d6 d5 d4 d3 d2 d1 d0 x x 0 0 figure 24b ad5612 input register contents data its d15 ms d0 ls pd1 pd0 d11 d10 d d d7 d6 d5 d4 d3 d2 d1 d0 0 0 figure 24c AD5622 input register contents .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 15 of 22 power-on-reset the ad5602/12/22 contains a power-on-reset circuit that controls the output voltage during power-up. the dac register is filled with zeros and the output voltage is 0 v. it remains there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. power-down modes the ad5602/12/22 contains four separate modes of operation. these modes are software-programmable by setting two bits (pd1 and pd0) in the control register. table 6 shows how the state of the bits corresponds to the mode of operation of the device. table 6. modes of operation for the ad5602/12/22 pd1 pd0 operating mode 0 0 normal operation 0 1 power-down 1 k load to gnd 1 0 power-down 100 k load to gnd 1 1 power-down three-state output hen both bits are set to 0, the part works normally with its normal power consumption of 100 a ma at 5 v. however, for the three power-down modes, the supply current falls to 100 na at 3 v. not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through a 1 k? resistor or a 100 k? resistor, or is left open-circuited three-state. figure 25 shows the output stage. poer-don circuitr resistor netor v out resistor string dac amplifier 04611-a-025 figure 25 output stage during power-down the bias generator, the output amplifier, the resistor string and other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to eit power-down is typically 14 s for v dd = 5 v and 17 s for v dd = 3 v. see figure 1 for a plot. rite operation hen writing to the ad5602/12/22, the user must begin with a star t command followed by an address byte r/ = 0, after which t he dac will acknowledge that it is prepared to receive data by pulling sda low. two bytes of data are then written to the dac, the most significant byte followed by the least significant byte as shown in figure 25, both data bytes will be acknowledged by the ad56 02/12/22. a stop condition then follows. the write operations for the three dacs is shown in figure 25. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 16 of 22 sda ack. by ad560 2 start by master frame 1 serial bus address byte frame 2 most significant data byte ack. by ad560 2 191 9 r/ a0 a1 1 1 0 0 scl 0 91 9 d3 d2 d1 x d0 x stop by master ack. by ad560 2 frame 3 least significant data byte scl (continued) sda (continued) 0 0 pd1 pd0 d7 d6 d5 d4 x x figure 26a ad5602 write sequence sda ack. by ad561 2 start by master frame 1 serial bus address byte frame 2 most significant data byte ack. by ad561 2 191 9 r/ a0 a1 1 1 0 0 scl 0 91 9 d5 d4 d3 d0 d2 d1 stop by master ack. by ad561 2 frame 3 least significant data byte scl (continued) sda (continued) 0 0 pd1 pd0 d9 d8 d7 d6 x x figure 26b ad5612 write sequence .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 17 of 22 sda ack. by ad562 2 start by master frame 1 serial bus address byte frame 2 most significant data byte ack. by ad562 2 191 9 r/ a0 a1 1 1 0 0 scl 0 91 9 d7 d6 d5 d2 d4 d3 stop by master ack. by ad562 2 frame 3 least significant data byte scl (continued) sda (continued) 0 0 pd1 pd0 d11 d10 d9 d8 d1 d0 figure 26c AD5622 write sequence read operation when reading data back from the ad5602/12/22, the user begins wi th a start command followed by an address byte (r/w = 1), after which the dac will acknowledge that it is prepared to transmit data by pulling sda low. two bytes of data are then read from th e dac which are both acknowledged by the master as shown in figure 26. a stop condition follows. sda ack. by master start by master frame 1 serial bus address byte frame 2 most significant data byte from ad5602 ack. by ad56202 191 9 r/ a0 a1 1 1 0 0 scl 0 d5 master frame 3 least significant data byte from ad5602 19 stop b y master 0 0 scl (continued) sda (continued) pd1 pd0 d7 d6 d4 d3 d2 0 0 0 d1 d0 0 noack b y figure 27a ad5602 read sequence .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 18 of 22 sda ack. by master start by master frame 1 serial bus address byte frame 2 most significant data byte from ad5612 ack. by ad5612 191 9 r/ a0 a1 1 1 0 0 scl 0 d7 master frame 3 least significant data byte from ad5612 19 stop b y master d0 0 scl (continued) sda (continued) pd1 pd0 d9 d8 d6 d5 d4 0 0 0 d3 d2 d1 noack b y figure 27b ad5612 read sequence sda ack. by master start by master frame 1 serial bus address byte frame 2 most significant data byte from AD5622 ack. by AD5622 191 9 r/ a0 a1 1 1 0 0 scl 0 d9 master frame 3 least significant data byte from AD5622 19 stop b y master d2 d1 scl (continued) sda (continued) pd1 pd0 d11 d10 d8 d7 d6 0 0 d0 d5 d4 d3 noack b y figure 27c AD5622 read sequence .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 19 of 22 placing the ad5602/12/22 -1 into high-speed mode hs-mode communication commences after the master addresses all devices connected to the bus with the master code, 00001xxx, to indicate that a high-speed mode transfer is to begin. no device connected to the bus is permitted to acknowledge the high-speed master code, therefore the code is followed by a not-acknowledge. the master must then issue a repeated start followed by the device a ddress. the selected device will then acknowledge its address. all devices continue to operate in hs-mode until such time as the master issues a stop condition. when the stop condition is issued the devices all return to f/s mode. sda ack. by ad56x2 start by master hs-mode master code serial bus address byte nack. 191 9 x x 1 0 0 0 scl 0 0 1 x sr fast mode high-speed mode 0 1a1 0 a0 r/w figure 28 placing the ad5602/12/22 into high speed mode .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 20 of 22 applications choosing a reference as power supply for ad5602/12/22 the ad5602/12/22 comes in a tiny sc70 package with less than 100 a supply current. because of this, the choice of reference depends on the application requirement. for space saving applications, the adr425 is available in an sc70 package and has excellent drift at 3ppm/c. it also provides very good noise performance at 3.4 v p-p in the 0.1 hz to 10 hz range. because the supply current required by the ad5602/12/22 is extremely low, it is ideal for low supply applications. the adr293 voltage reference is recommended in this case. this requires 15 a of quiescent current and can therefore drive multiple dacs in the one system if required. ad5602/12/22 scl sda 7v 5v v out = 0v to 5v adr425 figure 29. adr425 as power supply to ad5602/12/22 examples of some recommended precision references for use as supply to the ad5602/12/22 are shown in table 7. table 7. precision referenc es for use with ad5602/12/22 part no. initial accuracy mv ma temperature drift ppm/c ma 0.110 hz noise v p-p typ adr435 6 3 3.4 adr425 6 3 3.4 adr02 5 3 15 adr35 6 25 5 ipolar operation using the ad5602/12/22 the ad5602/12/22 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 30. the circuit in figure 30 will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad20 or an op25 as the output amplifier. the output voltage for any input code can be calculated as follows ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = 1 1 2 1 2 r r v r r r d v v dd n dd o 2 where d represents the input code in decimal (0?16384) and n represents the bit resolution of the dac. with v dd = 5 v, r1 = r2 = 10 k: v 5 2 10 ? ? ? ? ? ? ? = n o d v this is an output voltage range of 5 v with 000 hex corresponding to a ?5 v output and fff hex corresponding to a +5 v output. r2 = 10k ? ? .com .com .com .com 4 .com u datasheet
preliminary technical data ad5602/12/22 rev. prb 18-feb-05| page 21 of 22 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5602/12/22 should have separate analog and digital sections, each having its own area of the board. if the ad5602/12/22 is in a system where other devices require an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5602/12/22. the power supply to the ad5602/12/22 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), e.g., common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board. .com .com .com .com 4 .com u datasheet
ad5602/12/22 preliminary technical data rev. prb 18-feb-05| page 22 of 22 outline dimensions 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 3 5 4 2 6 1 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203ab figure 31. 6-lead plastic surface mount package [sc70] (ks-6) dimensions shown in millimeters purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05447-0-2/05(prb) .com .com .com 4 .com u datasheet

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