1/8 october 2001 STS11NF3LL n-channel 30v - 0.008 w - 11a so-8 low gate charge stripfet? ii power mosfet (*)value limited by wires bonding n typical r ds (on) = 0.011 w @ 4.5v n optimal r ds(on) q g trade-off @4.5v n conduction losses reduced n switching losses reduced description this application specific power mosfet is the third genaration of stmicroelectronics unique single feature size strip-based pro- cess. the resulting transistor shows the best trade-off between on-resistance and gate charge. when used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. this is extremely important for mother- boards where fast switching and high efficien- cy are of paramount importance. applications n specifically designed and optimised for high efficiency cpu core dc/dc converters for mobile pcs absolute maximum ratings ( l ) pulse width limited by safe operating area type v dss r ds(on) i d STS11NF3LL 30 v < 0.011 w 11 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v dgr drain-gate voltage (r gs = 20 k w ) 30 v v gs gate- source voltage 16 v i d drain current (continuos) at t c = 25c (*) drain current (continuos) at t c = 100c 11 7 a a i dm ( l ) drain current (pulsed) 44 a p tot total dissipation at t c = 25c 2.5 w so-8 internal schematic diagram
STS11NF3LL 2/8 thermal data (#) when mounted on a 1inch 2 pad electrical characteristics (t case = 25 c unless otherwise specified) off on (1) dynamic rthj-amb thermal resistance junction-ambient max (#) 50 c/w t j max. operating junction temperature 150 c t stg storage temperature C65 to 150 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 16v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 1v r ds(on) static drain-source on resistance v gs = 10 v, i d = 5.5 a 0.008 0.011 w v gs = 4.5 v, i d = 5.5 a 0.011 0.013 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d = 5.5 a 15 s c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 1700 pf c oss output capacitance 505 pf c rss reverse transfer capacitance 115 pf
3/8 STS11NF3LL electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 15 v, i d = 5.5 a r g = 4.7 w v gs = 4.5 v (resistive load, see fig. 3) 20 ns t r rise time 70 ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 15 v, i d = 11 a, v gs = 4.5 v 21 9.5 10 28 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off-delay time fall time v dd = 15 v, i d = 5.5 a, r g =4.7 w, v gs = 4.5 v (resistive load see, fig. 3) 40 20 ns ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 11 a i sdm (1) source-drain current (pulsed) 44 a v sd (2) forward on voltage i sd = 11 a, v gs = 0 1.2 v t rr q rr i rrm reverse recovery time reverse recovery chargereverse recovery current i sd = 11 a, di/dt = 100a/s, v dd = 20 v, t j = 150c (see test circuit, figure 5) 45 52 2.3 ns nc a thermal impedance safe operating area
STS11NF3LL 4/8 gate charge vs gate-source voltage transconductance capacitance variations output characteristics static drain-source on resistance transfer characteristics
5/8 STS11NF3LL normalized on resistance vs temperature normalized gate thereshold voltage vs temp. source-drain diode forward characteristics
STS11NF3LL 6/8 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
7/8 STS11NF3LL dim. mm inch min. typ. max. min. typ. max. a1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m0.60.023 s 8 (max.) 0016023 so-8 mechanical data
STS11NF3LL 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectroni cs. specifi cation mentio ned in this publication are subject to change without notice. this publication supersedes and replaces all in formation previou sly supplied. stmicroel ectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a trademark of stmicroelectronics ? 2001 stmicroelectronics C pr inted in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malay sia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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